Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of sub-pixels, each of the sub-pixels comprising at least a pixel driving circuit, a scan signal line with a main body part extending along a first direction, a first power supply line with a main body part extending along a second direction, and two data signal lines with main body parts extending along the second direction, the first power supply line and the two data signal lines being arranged in sequence along the first direction, and the pixel driving circuit being connected to the first power supply line; the pixel driving circuit comprises at least a driving transistor and a power supply connection electrode, the driving transistor comprising a second gate electrode and a second active layer, the second gate electrode extending along the second direction; in at least one of the sub-pixels, a first end of the power supply connection electrode is connected to the first power supply line through a power supply via, a second end of the power supply connection electrode is connected to a first region of the second active layer through an active via across the two data signal lines, and the second gate electrode and the power supply connection electrode are located in the same conductive layer.

Description

[0001] This case is a divisional application of patent application 202380010079.3. The original application was filed on August 10, 2023, with the application number 202380010079.3 and the invention title being: Display substrate and its preparation method, and display device. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate including a plurality of sub-pixels. At least one sub-pixel includes a pixel driving circuit, a scan signal line extending along a first direction on the main body portion, a first power line extending along a second direction on the main body portion, and two data signal lines extending along the second direction on the main body portion. The first power line and the two data signal lines are arranged sequentially along the first direction, which intersects the second direction. The pixel driving circuit is connected to the first power line, and the first power line is configured to provide a first power signal to the pixel driving circuit. The pixel driving circuit includes at least a driving transistor and a power connection electrode. The driving transistor includes at least a second gate electrode and a second active layer. The second gate electrode extends along the second direction. In at least one sub-pixel, a first end of the power connection electrode is connected to the first power line through a power via, and a second end of the power connection electrode crosses the two data signal lines and is connected to a first region of the second active layer through an active via.

[0006] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate, wherein the orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane; in at least one sub-pixel, the second gate electrode is connected to the second electrode plate through a sixth via.

[0007] In an exemplary embodiment, in at least one sub-pixel, the orthogonal projection of the sixth via on the substrate is located within the range of the orthogonal projection of the second electrode plate on the substrate.

[0008] In an exemplary embodiment, in at least one sub-pixel, the size of the sixth via in the second direction is larger than the size of the sixth via in the first direction.

[0009] In an exemplary embodiment, in at least one sub-pixel, the second gate electrode includes a first portion and a second portion, wherein the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate, and the first portion is connected to the second electrode plate through the sixth via.

[0010] In an exemplary embodiment, in at least one sub-pixel, the sixth via is partially covered by the first portion.

[0011] In an exemplary embodiment, in the first direction, the width of the first portion is smaller than the width of the second portion.

[0012] In an exemplary embodiment, in the second direction, the length of the first portion is greater than the length of the second portion.

[0013] In an exemplary embodiment, in at least one sub-pixel, in the second direction, the edge of the active via on the side away from the sixth via is located on the side of the second gate electrode away from the sixth via.

[0014] In an exemplary embodiment, in the second direction, a distance is provided between the edge of the power connection electrode near the sixth via and the edge of the active via near the sixth via, and the power connection electrode does not completely cover the active via, with the uncovered active via located on the side of the power connection electrode near the sixth via.

[0015] In an exemplary embodiment, at least one sub-pixel further includes a fifth connection electrode, which is connected to a second region of the second active layer via a third via, wherein the size of the third via in the first direction is larger than the size of the third via in the second direction.

[0016] In an exemplary embodiment, in at least one sub-pixel, the second active layer includes at least a main body and a protrusion, the protrusion being disposed on the side of the main body away from the sixth via and connected to the main body, and the power connection electrode being connected to the protrusion through an active via.

[0017] In an exemplary embodiment, in at least one sub-pixel, the protrusion has a first width in the first direction and a second width in the channel region of the second transistor in the second direction, wherein the first width is smaller than the second width.

[0018] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the second gate electrode onto the display substrate plane and the orthographic projection of the second active layer onto the display substrate plane has a third width, and the first width is smaller than the third width.

[0019] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit further includes a switching transistor and a compensation transistor, the gate electrode of the switching transistor and the gate electrode of the compensation transistor being connected to the scan signal line; in the second direction, the switching transistor and the compensation transistor are disposed on the side of the second electrode plate close to the scan signal line, and the driving transistor is disposed on the side of the second electrode plate away from the scan signal line.

[0020] In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel arranged periodically along the first direction. The first sub-pixel includes a first data signal line and a second data signal line, and the second sub-pixel includes a third data signal line and a fourth data signal line. The two power connection electrodes in the first sub-pixel and the second sub-pixel are an integral structure that is interconnected. The orthographic projection of the two power connection electrodes of the integral structure on the display substrate plane at least partially overlaps with the orthographic projection of the first data signal line, the second data signal line, the third data signal line and the fourth data signal line on the display substrate plane.

[0021] In an exemplary embodiment, in at least one sub-pixel, the size of the active via in the second direction is larger than the size of the active via in the first direction.

[0022] In an exemplary embodiment, at least a portion of the active via near the driving transistor is not covered by the power connection electrode.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of a display device; Figure 2 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure. Figure 3 An equivalent circuit diagram of a pixel driving circuit in a repeating unit is provided in an exemplary embodiment of this disclosure. Figure 4 This is a schematic diagram of the structure of a display substrate according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure; Figure 6A and Figure 6B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to the present disclosure; Figure 7A and Figure 7B This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed. Figure 8 This is a schematic diagram of a display substrate after the formation of a second insulating layer pattern according to the present disclosure; Figure 9A and Figure 9B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure; Figure 9C for Figure 9A Sectional view along the AA direction; Figures 9D to 9F for Figure 9A Sectional view along the BB direction; Figure 10 This is a schematic diagram of a display substrate after the formation of a third insulating layer and a planarization layer pattern according to the present disclosure; Figure 11A and Figure 11B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure; Figure 12This is a schematic diagram of a display substrate after a pixel definition layer pattern has been formed; Figure 13 This is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure; Figure 14A and Figure 14B This is a schematic diagram of another display substrate after a semiconductor layer pattern has been formed; Figure 15 This is a schematic diagram of another display substrate after the formation of the second insulating layer pattern according to the present disclosure; Figure 16A and Figure 16B This is a schematic diagram of another display substrate after the formation of the third conductive layer pattern according to the present disclosure; Figure 17 This is a schematic diagram of the structure of another display substrate according to an embodiment of the present disclosure; Figure 18A and Figure 18B This is a schematic diagram of another display substrate after a semiconductor layer pattern has been formed; Figure 19 This is a schematic diagram of a display substrate after the formation of a second insulating layer pattern according to another embodiment of the present disclosure; Figure 20A and Figure 20B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern, according to another embodiment of this disclosure.

[0027] Explanation of reference numerals in the attached figures: 10—Substrate; 11—First connecting electrode; 12—Second connecting electrode; 13—Third connecting electrode; 14—Fourth connecting electrode; 15—Fifth connecting electrode; 16—Sixth connecting electrode; 17—Seventh connecting electrode; 18—Eighth connecting electrode; 20—Power supply connection electrode; 21—First active layer; 22—Second active layer; 23—Third active layer; 24—Active connection electrode; 30—Scan signal line; 31—First gate electrode; 32—Second gate electrode; 33—Third gate electrode; 51—First power supply line; 52—Data signal line; 53—Compensation signal line; 60—Storage capacitor; 61—First plate; 62—Second plate; 63—First electrode; 64—Anode connection electrode; 71—First insulating layer; 72—Second insulating layer; 81—First connecting block; 82—Second connecting block; 91—Depression; 92—Groove; 100—Repeating unit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0029] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0030] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0031] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0032] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0033] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0034] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0035] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0036] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0037] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0038] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0039] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0040] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to both the data driver and the scan driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the scan driver is connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit, which is connected to both the scan signal line and the data signal line. The display unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. A sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0041] An exemplary embodiment of this disclosure provides a display substrate including a plurality of repeating units. At least one repeating unit includes a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns. At least one sub-pixel includes a pixel driving circuit connected to a first power line configured to provide a first power signal to the pixel driving circuit. The pixel driving circuit includes at least a driving transistor and a power connection electrode. The driving transistor includes at least a driving active layer. In at least one sub-pixel, a first end of the power connection electrode is connected to the first power line through a power via, and a second end of the power connection electrode is connected to a first region of the driving active layer through an active via. Two adjacent sub-pixels in two repeating units adjacent in the pixel row direction share the power via, and two adjacent sub-pixels in two repeating units adjacent in the pixel column direction share the power via.

[0042] In an exemplary embodiment, the first region of the driving active layer of two adjacent sub-pixels in two repeating units adjacent in the pixel column direction is interconnected.

[0043] In an exemplary embodiment, two adjacent sub-pixels in two repeating units adjacent in the pixel column direction share the active via.

[0044] In an exemplary embodiment, the pixel driving circuit further includes an active connection electrode, the first end of which is connected to the first region of the driving active layer, and the power connection electrode is connected to both the first power line and the second end of the active connection electrode via a transition via. The transition via includes a shallow half-hole and a deep half-hole, the shallow half-hole being an active via that exposes the second end of the active connection electrode, and the deep half-hole being a power via that exposes the first power line.

[0045] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the transition via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the transition via.

[0046] In an exemplary embodiment, the first ends of the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other, and the first ends of the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are connected to each other.

[0047] In an exemplary embodiment, the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are an integral structure that is interconnected, and the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are an integral structure that is interconnected.

[0048] In an exemplary embodiment, the two adjacent sub-pixels in two repeating units adjacent in the pixel row direction refer to the following: one repeating unit includes sub-pixel A, and the other repeating unit includes sub-pixel B, with sub-pixels A and B being adjacent in the pixel row direction. Similarly, the two adjacent sub-pixels in two repeating units adjacent in the pixel column direction refer to the following: one repeating unit includes sub-pixel C, and the other repeating unit includes sub-pixel D, with sub-pixels C and D being adjacent in the pixel column direction.

[0049] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0050] Figure 2 This is a schematic diagram of a planar structure of a display substrate, as an exemplary embodiment of this disclosure. Figure 2 As shown, in an exemplary embodiment, the display substrate may include a plurality of repeating units 100 in a direction parallel to the display substrate, and at least one repeating unit 100 may include a plurality of subpixels forming at least two pixel rows and at least two pixel columns. In the exemplary embodiment, the repeating unit is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging it along at least one direction, that is, the display substrate is spliced ​​together from a plurality of repeating units.

[0051] In an exemplary embodiment, a repeating unit 100 may include four sub-pixels. The four sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. The four sub-pixels may be arranged in a square manner, which can effectively increase the aperture ratio and the area of ​​the light-transmitting region.

[0052] In an exemplary embodiment, in at least one repeating unit 100, the second sub-pixel P2 may be disposed on one side of the first sub-pixel P1 extending in the first direction X, the third sub-pixel P3 may be disposed on one side of the first sub-pixel P1 extending in the second direction Y, and the fourth sub-pixel P4 may be disposed on one side of the third sub-pixel P3 extending in the first direction X. The plurality of sub-pixels arranged sequentially along the first direction X may be referred to as a pixel row, and the plurality of sub-pixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array, wherein the first direction X and the second direction Y intersect.

[0053] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, the third sub-pixel P3 can be a white sub-pixel (W) that emits white light, and the fourth sub-pixel P4 can be a green sub-pixel (G) that emits green light. In some possible embodiments, the arrangement of RBWG can be adjusted according to actual needs, and this disclosure does not specifically limit it.

[0054] In one exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each circuit unit may include at least a pixel driving circuit, which is connected to scan signal lines and data signal lines, etc., respectively. The pixel driving circuit is configured to receive data voltage transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting structure layer may include multiple light-emitting units, each light-emitting unit may include at least a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0055] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate, a color filter structure layer disposed on the side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on the side of the color filter structure layer away from the substrate. In at least one repeating unit, the color filter structure layer may include a plurality of color filter units, and the color filter unit may include at least a color filter layer configured to cause the corresponding sub-pixel to emit light of the desired color.

[0056] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit. The color filter unit referred to in this disclosure refers to a region divided according to a color filter layer. The light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. The positions of the circuit unit projected onto the substrate, the color filter layer projected onto the substrate, and the light-emitting unit projected onto the substrate may be corresponding or non-corresponding.

[0057] In the exemplary embodiments disclosed herein, the positions of the circuit unit projected onto the substrate, the color filter layer projected onto the substrate, and the light-emitting unit projected onto the substrate are substantially corresponding. The circuit unit, the color filter unit, and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, sub-pixel is used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0058] Figure 3This disclosure provides an exemplary embodiment of an equivalent circuit diagram of a pixel driving circuit in a repeating unit. (See diagram below.) Figure 3 As shown, at least one repeating unit may include four pixel driving circuits, which may be arranged in a square manner, and the pixel driving circuit may be a 3T1C structure.

[0059] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (first transistor T1, second transistor T2 and third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to the scan signal line 30, the first power supply line 51, the data signal line 52 and the compensation signal line 53, respectively.

[0060] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively.

[0061] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0062] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0063] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line 30, the first electrode of the first transistor T1 is connected to the data signal line 52, and the second electrode of the first transistor T1 is connected to the first node N1. When a conduction signal is applied to the scan signal line 30, the first transistor T1 inputs the data signal from the data signal line 52 to the gate electrode of the second transistor T2.

[0064] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first node N1, the first terminal of the second transistor T2 is connected to the first power line 51, and the second terminal of the second transistor T2 is connected to the second node N2. Under the control of the data signal received at its gate electrode, the second transistor T2 generates a corresponding current at its second terminal.

[0065] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the scan signal line 30, the first electrode of the third transistor T3 is connected to the compensation signal line 53, and the second electrode of the third transistor T3 is connected to the second node N2. When a conduction signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0066] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30.

[0067] In an exemplary embodiment, in a plurality of pixel driving circuits for at least one pixel row, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 30.

[0068] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 30.

[0069] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL emits light of corresponding brightness in response to the current at the second electrode of the second transistor T2. In an exemplary embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0070] In an exemplary embodiment, the signal of the first power line 51 is a continuously supplied high-level signal, and the signal of the second power line VSS is a continuously supplied low-level signal.

[0071] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the third transistor T3 may include both P-type and N-type transistors.

[0072] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon (LTPS) thin-film transistors, or oxide thin-film transistors, or a combination of both. The active layer of the LTPS thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0073] Figure 4 This is a schematic diagram of a display substrate structure according to an exemplary embodiment of the present disclosure, illustrating the structure of four repeating units (sixteen sub-pixels) in a bottom-emitting display substrate. In an exemplary embodiment, the four repeating units may include a first repeating unit Q1, a second repeating unit Q2, a third repeating unit Q3, and a fourth repeating unit Q4. The second repeating unit Q2 may be disposed on one side of the first repeating unit Q1 extending in a first direction X, the third repeating unit Q3 may be disposed on one side of the first repeating unit Q1 extending in a second direction Y, and the fourth repeating unit Q4 may be disposed on one side of the third repeating unit Q3 extending in a first direction X. At least one repeating unit may include four sub-pixels forming two pixel rows and two pixel columns. The four sub-pixels may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The second sub-pixel P2 may be disposed on one side of the first sub-pixel P1 extending in a first direction X, the third sub-pixel P3 may be disposed on one side of the first sub-pixel P1 extending in a second direction Y, and the fourth sub-pixel P4 may be disposed on one side of the third sub-pixel P3 extending in a first direction X. The first direction X intersects with the second direction Y. Multiple sub-pixels arranged sequentially along the first direction X can be called a pixel row, and multiple sub-pixels arranged sequentially along the second direction Y can be called a pixel column. Multiple pixel rows and multiple pixel columns constitute a pixel array with an array arrangement.

[0074] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, two first power lines 51, four data signal lines 52, and a compensation signal line 53. The signal lines are respectively connected to the pixel driving circuit in the corresponding sub-pixel. The scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power lines 51 are configured to provide a first power signal to the pixel driving circuit, the data signal lines 52 are configured to provide a data signal to the pixel driving circuit, and the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit.

[0075] In an exemplary embodiment, the scan signal line 30 can be a line shape in which the main body extends along the first direction X (pixel row direction), and the first power line 51, data signal line 52, and compensation signal line 53 can be a line shape in which the main body extends along the second direction Y (pixel column direction). In an exemplary embodiment, the scan signal line 30 can be disposed between adjacent pixel rows, for example, in the middle of the repeating unit in the second direction Y; one compensation signal line 53 can be located between adjacent pixel columns, for example, in the middle of the repeating unit in the first direction X; two first power lines 51 can be located on both sides of the repeating unit in the first direction X; four data signal lines 52 and compensation signal lines 53 can be located between two adjacent first power lines 51, two of the four data signal lines 52 can be located on the side of one first power line 51 near the compensation signal line 53, the other two of the four data signal lines 52 can be located on the side of another first power line 51 near the compensation signal line 53, and the storage capacitor 60 can be located between the data signal lines 52 and the compensation signal lines 53. Thus, a scan signal line 30 extending along the first direction X defines two pixel rows, and a compensation signal line 53 extending along the second direction Y can define two pixel columns, forming a repeating unit of first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4.

[0076] In an exemplary embodiment, each sub-pixel includes a pixel driving circuit, which may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor 60. Each transistor may include a gate electrode, an active layer, a first electrode, and a second electrode. The storage capacitor 60 may include a first electrode plate and a second electrode plate.

[0077] In an exemplary embodiment, the first electrode of the first transistor T1 is connected to the data signal line 52, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2 and the second plate of the storage capacitor 60, the first electrode of the second transistor T2 is connected to the first power supply line 51, the first electrode of the third transistor T3 is connected to the compensation signal line 53, and the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2 and the first plate of the storage capacitor 60.

[0078] In an exemplary embodiment, the pixel driving circuit further includes a power connection electrode 20, and the second transistor T2, which serves as a driving transistor, includes at least a second active layer 22, which serves as a driving active layer. In at least one sub-pixel, the first power line 51 is connected to the first region of the second active layer 22 via the power connection electrode 20.

[0079] In an exemplary embodiment, the power connection electrode 20 may be a strip shape extending along the first direction X. In at least one sub-pixel, the first end of the power connection electrode 20 is connected to the first power line 51 through a power via K1, and the second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through an active via K2.

[0080] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X (pixel row direction) share the same power via K1, and two adjacent sub-pixels in two adjacent repeating units in the second direction Y (pixel column direction) share the same power via K1.

[0081] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X refer to the following: in the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first repeating unit Q1 includes a fourth sub-pixel, and the second repeating unit Q2 includes a third sub-pixel; the fourth sub-pixel of the first repeating unit Q1 and the third sub-pixel of the second repeating unit Q2 are adjacent in the first direction X. Similarly, two adjacent sub-pixels in two adjacent repeating units in the second direction Y refer to the following: in the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the first repeating unit Q1 includes a fourth sub-pixel, and the third repeating unit Q3 includes a second sub-pixel; the fourth sub-pixel of the first repeating unit Q1 and the second sub-pixel of the third repeating unit Q3 are adjacent in the second direction Y.

[0082] In an exemplary embodiment, adjacent sub-pixels in repeating units adjacent to each other in the first direction X and the second direction Y share the same power via K1.

[0083] In an exemplary embodiment, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are two adjacent sub-pixels. For the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels. For the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are two adjacent sub-pixels. For the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels. Therefore, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 are adjacent sub-pixels in repeating units adjacent in the first direction X and the second direction Y, and the above sub-pixels share the same power via K1.

[0084] In an exemplary embodiment, the first regions of the second active layers 22 of two adjacent sub-pixels in two repeating units adjacent in the second direction Y are interconnected. For example, for first repeating units Q1 and third repeating units Q3 adjacent in the second direction Y, the first regions of the two second active layers 22 in the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 are interconnected, and the first regions of the two second active layers 22 in the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are interconnected. Similarly, for second repeating units Q2 and fourth repeating units Q4 adjacent in the second direction Y, the first regions of the two second active layers 22 in the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are interconnected, and the first regions of the two second active layers 22 in the fourth sub-pixel P4 of the second repeating unit Q4 are interconnected.

[0085] In an exemplary embodiment, the second active layer 22 of two adjacent sub-pixels in two repeating units adjacent to each other in the second direction Y is an integral structure that is interconnected.

[0086] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same active via K2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same active via K2. Similarly, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same active via K2.

[0087] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. As another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0088] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure that is interconnected.

[0089] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same power connection electrode 20. As another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same power connection electrode 20.

[0090] In an exemplary embodiment, the widths of the second active layer 22 in adjacent sub-pixels in the first direction X are different, and the widths of the second active layer 22 in adjacent sub-pixels in the second direction Y are different. The width can be the minimum size of the second active layer 22 in the second direction Y.

[0091] In an exemplary embodiment, in the first direction X, the first sub-pixel P1 and the second sub-pixel P2 are alternately arranged, and the width of the second active layer 22 in the first sub-pixel P1 is greater than the width of the second active layer 22 in the second sub-pixel P2; or, in the first direction X, the third sub-pixel P3 and the fourth sub-pixel P4 are alternately arranged, and the width of the second active layer 22 in the third sub-pixel P3 is less than the width of the second active layer 22 in the fourth sub-pixel P4.

[0092] In an exemplary embodiment, in the second direction Y, the first sub-pixel P1 and the third sub-pixel P3 are alternately arranged, and the width of the second active layer 22 in the first sub-pixel P1 is greater than the width of the second active layer 22 in the third sub-pixel P3; or, in the second direction Y, the second sub-pixel P2 and the fourth sub-pixel P4 are alternately arranged, and the width of the second active layer 22 in the second sub-pixel P2 is less than the width of the second active layer 22 in the fourth sub-pixel P4.

[0093] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer sequentially disposed on the substrate. The first electrode of the storage capacitor 60 may be disposed in the first conductive layer. The first power line 51, the data signal line 52, and the compensation signal line 53 may be disposed in the second conductive layer. The second electrode of the storage capacitor 60 and the second active layer 22 may be disposed in the semiconductor layer. The power connection electrode 20 and the scan signal line 30 may be disposed in the third conductive layer.

[0094] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0095] In an exemplary embodiment, taking four repeating units (first repeating unit Q1, second repeating unit Q2, third repeating unit Q3 and fourth repeating unit Q4) as an example, the substrate fabrication process of this embodiment may include the following operations.

[0096] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive thin film on a substrate, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on the substrate, such as... Figure 5 As shown.

[0097] In an exemplary embodiment, the first conductive layer of each sub-pixel in each repeating unit may include at least a first connecting electrode 11, a second connecting electrode 12, and a first plate 61 of a storage capacitor.

[0098] In an exemplary embodiment, the first electrode plate 61 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first electrode plate 61 may serve as a transparent electrode plate of a transparent storage capacitor, and the first electrode plate 61 is configured to form a transparent storage capacitor with the subsequently formed second electrode plate.

[0099] In an exemplary embodiment, the first connecting electrode 11 and the second connecting electrode 12 may be located on both sides of the first electrode plate 61 in the second direction Y, respectively.

[0100] In an exemplary embodiment, in the first sub-pixel P1 and the second sub-pixel P2, the first connecting electrode 11 can be disposed on the side opposite to the second direction Y-extension direction of the first electrode plate 61, and the second connecting electrode 12 can be disposed on the side of the second direction Y-extension direction of the first electrode plate 61. In the third sub-pixel P3 and the fourth sub-pixel P4, the first connecting electrode 11 can be disposed on the side of the second direction Y-extension direction of the first electrode plate 61, and the second connecting electrode 12 can be disposed on the side opposite to the second direction Y-extension direction of the first electrode plate 61.

[0101] In an exemplary embodiment, the first connecting electrode 11 may be a strip shape in which the main body extends along the second direction Y. The first end of the first connecting electrode 11 is connected to the first electrode plate 61, and the second end of the first connecting electrode 11 extends in a direction away from the second connecting electrode 12. The first connecting electrode 11 is configured to be connected to a third connecting electrode that is subsequently formed.

[0102] In an exemplary embodiment, the second connecting electrode 12 may be a strip shape in which the main body extends along the second direction Y. The first end of the second connecting electrode 12 is connected to the first electrode plate 61, and the second end of the second connecting electrode 12 extends away from the first connecting electrode 11. The second connecting electrode 12 is configured to be connected to the fourth connecting electrode that is subsequently formed.

[0103] In an exemplary embodiment, in the first pixel column, the edge of the first connecting electrode 11 near the second pixel column can be substantially flush with the edge of the first electrode plate 61 near the second pixel column. In the second pixel column, the edge of the first connecting electrode 11 near the first pixel column can be substantially flush with the edge of the first electrode plate 61 near the first pixel column.

[0104] In an exemplary embodiment, the first connection electrode 11, the second connection electrode 12, and the first electrode plate 61 of each sub-pixel can be an integral structure that is interconnected.

[0105] In an exemplary embodiment, in at least one sub-pixel, the width of the first connecting electrode 11 may be smaller than the width of the second connecting electrode 12, and the width may be the dimension of the first direction X.

[0106] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer pattern may further include a first connecting block 81. The first connecting block 81 may be block-shaped (e.g., rectangular) and may be disposed at the corner where the first connecting electrode 11 connects to the first electrode plate 61. The two adjacent sides of the first connecting block 81 are respectively connected to the first connecting electrode 11 and the first electrode plate 61 to form a first corner structure. For example, a first sub-pixel may include the first connecting block 81. Similarly, a second sub-pixel may include the first connecting block 81. Furthermore, a third sub-pixel may include the first connecting block 81.

[0107] In an exemplary embodiment, in at least one sub-pixel, the first corner structure may have a first convex angle β1, which may be a right angle.

[0108] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer pattern may further include a second connecting block 82. The second connecting block 82 may be block-shaped and may be disposed at the corner where the second connecting electrode 12 connects to the first electrode plate 61. The two adjacent sides of the second connecting block 82 are respectively connected to the second connecting electrode 12 and the first electrode plate 61 to form a second corner structure. For example, the first sub-pixel may include the second connecting block 82.

[0109] In an exemplary embodiment, the second corner structure may have a second convex angle β2, which may be an obtuse angle.

[0110] In an exemplary embodiment, in at least one sub-pixel, the first electrode plate 61 may be provided with a recess 91. The shape of the recess 91 may be block-shaped (such as rectangular), and it may be located on the side of the first electrode plate 61 away from the second connecting electrode 12. The recess 91 may have a recess width and a recess depth. The recess width may be greater than the recess depth. The recess width may be the dimension of the first direction X, and the recess depth may be the dimension of the second direction Y.

[0111] In an exemplary embodiment, in at least one repeating unit, the positions of the patterns in the first conductive layer of the first sub-pixel P1 and the positions of the patterns in the first conductive layer of the third sub-pixel P3 are substantially mirror-symmetrical with respect to a horizontal reference line; the positions of the patterns in the first conductive layer of the second sub-pixel P2 and the positions of the patterns in the first conductive layer of the fourth sub-pixel P4 are substantially mirror-symmetrical with respect to a horizontal reference line; the positions of the patterns in the first conductive layer of the first sub-pixel P1 and the positions of the patterns in the first conductive layer of the second sub-pixel P2 are substantially mirror-symmetrical with respect to a vertical reference line; and the positions of the patterns in the first conductive layer of the third sub-pixel P3 and the positions of the patterns in the first conductive layer of the fourth sub-pixel P4 are substantially mirror-symmetrical with respect to a vertical reference line. The horizontal reference line can be a straight line extending along a first direction X and bisecting the repeating unit in a second direction Y; the vertical reference line can be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0112] In an exemplary embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0113] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second conductive layer, such as... Figure 6A and Figure 6B As shown, Figure 6B for Figure 6A A schematic diagram of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as a shielding layer.

[0114] In an exemplary embodiment, the second conductive layer of each sub-pixel in each repeating unit may include at least a third connecting electrode 13 and a fourth connecting electrode 14.

[0115] In an exemplary embodiment, the third connecting electrode 13 may be block-shaped (e.g., rectangular) and located on the side of the first electrode plate 61 away from the second connecting electrode 12. The orthographic projection of the third connecting electrode 13 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 11 on the substrate, and the third connecting electrode 13 is directly connected to the first connecting electrode 11. In an exemplary embodiment, the third connecting electrode 13 is configured, on the one hand, to connect to the subsequently formed fifth connecting electrode, and on the other hand, to shield the second transistor from light, reducing the light intensity irradiated onto the second transistor, reducing the leakage current of the second transistor, thereby reducing the impact of light on the characteristics of the second transistor.

[0116] In an exemplary embodiment, the fourth connecting electrode 14 may be in the shape of a block (such as a rectangle) and may be located on the side of the first electrode plate 61 away from the first connecting electrode 11. The orthographic projection of the fourth connecting electrode 14 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 12 on the substrate, and the fourth connecting electrode 14 is directly connected to the second connecting electrode 12. The fourth connecting electrode 14 is configured to be connected to the sixth connecting electrode that is subsequently formed.

[0117] In an exemplary embodiment, in at least one sub-pixel, the area of ​​the third connecting electrode 13 projected onto the substrate can be greater than the area of ​​the fourth connecting electrode 14 projected onto the substrate. In an exemplary embodiment, in at least one repeating unit, the area of ​​the third connecting electrode 13 projected onto the substrate in the first sub-pixel can be larger than the area of ​​the third connecting electrode 13 projected onto the substrate in other sub-pixels.

[0118] In an exemplary embodiment, in at least one repeating unit, the area of ​​the fourth connecting electrode 14 projected onto the substrate in each sub-pixel can be substantially equal.

[0119] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may include at least two first power lines 51, four data signal lines 52, and one compensation signal line 53.

[0120] In an exemplary embodiment, the first power line 51, data signal line 52, and compensation signal line 53 can be in the shape of a straight line or a broken line extending along the second direction Y of the main body. The compensation signal line 53 can be located between adjacent sub-pixel columns of the repeating unit, for example, in the middle of the repeating unit in the first direction X. The first power line 51 can be located on the side opposite to the direction of extension of the repeating unit in the first direction X. The second power line 51 can be located on the side of the direction of extension of the repeating unit in the first direction X. Two of the four data signal lines 52 can be located between the first power line 51 and the compensation signal line 53. The other two data signal lines 52 can be located between the second power line 51 and the compensation signal line 53.

[0121] In an exemplary embodiment, a first power line 51 and a compensation signal line 53 may define a first pixel column, and two data signal lines 52 may be disposed in the first pixel column. A second power line 51 and a compensation signal line 53 may define a second pixel column, and two data signal lines 52 may be disposed in the second pixel column.

[0122] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line and a second data signal line disposed in the first pixel column, and a third and a fourth data signal line disposed in the second pixel column. Extending along the first direction X, they are sequentially a first power line, a first data signal line, a second data signal line, a compensation signal line, a third data signal line, a fourth data signal line, and a second first power line. The first electrode plate 61 may be located between the second data signal line and the compensation signal line 53, or between the compensation signal line 53 and the third data signal line.

[0123] In an exemplary embodiment, in at least one repeating unit, the positions of the two first power lines 51 can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the compensation signal line 53 and the two data signal lines 52 located on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0124] In an exemplary embodiment, in at least one repeating unit, the positions of the third connecting electrode 13 and the fourth connecting electrode 14 in the first sub-pixel P1 are substantially mirror-symmetrical with respect to the vertical reference line as are the positions of the third connecting electrode 13 and the fourth connecting electrode 14 in the second sub-pixel P2. Similarly, the positions of the third connecting electrode 13 and the fourth connecting electrode 14 in the third sub-pixel P3 are substantially mirror-symmetrical with respect to the vertical reference line. The positions of the third connecting electrode 13 and the fourth connecting electrode 14 in the first sub-pixel P1 and the third connecting electrode 13 and the fourth connecting electrode 14 in the third sub-pixel P3 are also substantially mirror-symmetrical with respect to the horizontal reference line, as are the positions of the third connecting electrode 13 and the fourth connecting electrode 14 in the second sub-pixel P2 and the fourth connecting electrode 14 in the fourth sub-pixel P4.

[0125] In an exemplary embodiment, two adjacent repeating units in the first direction X can share the same first power line 51. For example, the first repeating unit Q1 and the second repeating unit Q2 can share the same first power line 51. Similarly, the third repeating unit Q3 and the fourth repeating unit Q4 can share the same first power line 51. By setting adjacent repeating units to share the same first power line, this disclosure can effectively reduce the number of signal lines and vias, reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution.

[0126] In an exemplary embodiment, the first power line 51, the data signal line 52, and the compensation signal line 53 can be non-uniform width polygonal lines. Using polygonal lines with variable widths not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0127] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor film using a patterning process to form a first insulating layer covering a first conductive layer and a second conductive layer; and a semiconductor layer disposed on the first insulating layer, such as... Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A A schematic diagram of the semiconductor layer.

[0128] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode 62 of a storage capacitor. The first active layer 21 may serve as the active layer of a first transistor T1, the second active layer 22 may serve as the active layer of a second transistor T2, the third active layer 23 may serve as the active layer of a third transistor T3, and the second electrode 62 may serve as another transparent electrode of a transparent storage capacitor. The second electrode 62 is configured to form a transparent storage capacitor with the first electrode 61.

[0129] In an exemplary embodiment, for the first sub-pixel P1 and the second sub-pixel P2, the first active layer 21 and the third active layer 23 may be disposed on one side of the second direction Y extension direction of the first electrode plate 61 of the sub-pixel, and the second active layer 22 may be disposed on the side opposite to the second direction Y extension direction of the first electrode plate 61 of the sub-pixel.

[0130] In an exemplary embodiment, for the first sub-pixel P1, the first active layer 21 may be disposed on the side of the sub-pixel away from the second sub-pixel P2, and the third active layer 23 may be disposed on the side of the sub-pixel closer to the second sub-pixel P2. For the second sub-pixel P2, the first active layer 21 may be disposed on the side of the sub-pixel away from the first sub-pixel P1, and the third active layer 23 may be disposed on the side of the sub-pixel closer to the first sub-pixel P1.

[0131] In an exemplary embodiment, for the third sub-pixel P3 and the fourth sub-pixel P4, the first active layer 21 and the third active layer 23 can be disposed on the side opposite to the second direction Y extension direction of the first electrode plate 61 of the sub-pixel, and the second active layer 22 can be disposed on the side of the second direction Y extension direction of the first electrode plate 61 of the sub-pixel.

[0132] In an exemplary embodiment, for the third sub-pixel P3, the first active layer 21 can be disposed on the side of the sub-pixel away from the fourth sub-pixel P4, and the third active layer 23 can be disposed on the side of the sub-pixel closer to the fourth sub-pixel P4. For the fourth sub-pixel P4, the first active layer 21 can be disposed on the side of the sub-pixel away from the third sub-pixel P3, and the third active layer 23 can be disposed on the side of the sub-pixel closer to the third sub-pixel P3.

[0133] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0134] In an exemplary embodiment, the orthographic projection of the first region of the first active layer 21 of each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the corresponding data signal line 52 onto the substrate, and the second region of the first active layer 21 is connected to the second electrode plate 62.

[0135] In an exemplary embodiment, the orthographic projection of the first region of the second active layer 22 of each sub-pixel onto the substrate does not overlap with the orthographic projection of the third connection electrode 13 of the same sub-pixel onto the substrate. The orthographic projections of the second region and the channel region of the second active layer 22 onto the substrate at least partially overlap with the orthographic projection of the third connection electrode 13 onto the substrate, so that the third connection electrode 13, as a shielding layer, can shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0136] In an exemplary embodiment, in each sub-pixel, the distance between the first region of the second active layer 22 and the first power line 51 can be smaller than the distance between the second region of the second active layer 22 and the first power line 51, that is, the first region of the second active layer 22 is closer to the first power line 51 than the channel region of the second active layer 22.

[0137] In an exemplary embodiment, the first regions of the second active layer 22 of two adjacent sub-pixels in two repeating units adjacent in the second direction Y can be interconnected, so the second transistors of two adjacent sub-pixels in two repeating units adjacent in the second direction Y share the first region of the second active layer. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the first repeating unit Q1 and the first region of the second active layer 22 of the first sub-pixel P1 in the third repeating unit Q3 can be interconnected, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3 can be interconnected. For example, for the second repeating unit Q2 and the fourth repeating unit Q4 that are adjacent in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 can be connected to each other, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the second repeating unit Q2 and the first region of the second active layer 22 of the second sub-pixel P2 in the fourth repeating unit Q4 can be connected to each other.

[0138] In an exemplary embodiment, the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y can be an integrally connected structure. The integral structure of the second active layer 22 has a groove 92, and the openings of adjacent grooves 92 in at least one repeating unit are arranged opposite to each other. The groove 92 can have a groove width and a groove depth. The groove width can be less than the groove depth. The groove width can be the dimension in the second direction Y, and the groove depth can be the dimension in the first direction X. By setting the second transistors of two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the first region of the second active layer, this disclosure can not only effectively reduce the number of vias and reduce the occupied area of ​​the pixel driving circuit, but also increase the pixel aperture ratio and improve the display resolution. Furthermore, reducing vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0139] In an exemplary embodiment, the width of the second active layer in adjacent sub-pixels in the first direction X may be different, and the width of the second active layer in adjacent sub-pixels in the second direction Y may be different, with the width being the minimum size of the second active layer in the second direction Y.

[0140] In an exemplary embodiment, multiple sub-pixels of a second active layer with a larger width and multiple sub-pixels of a second active layer with a smaller width can be alternately arranged in the first direction X. For example, first sub-pixel P1 and second sub-pixel P2 are alternately arranged in the first direction X, and the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the second width L2 of the second active layer 22 in the second sub-pixel P2. As another example, third sub-pixel P3 and fourth sub-pixel P4 are alternately arranged in the first direction X, and the third width L3 of the second active layer 22 in the third sub-pixel P3 can be less than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0141] In an exemplary embodiment, in the second direction Y, multiple sub-pixels of a second active layer with a larger width and multiple sub-pixels of a second active layer with a smaller width can be alternately arranged. For example, a first sub-pixel P1 and a third sub-pixel P3 are alternately arranged in the second direction Y, and the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3. As another example, a second sub-pixel P2 and a fourth sub-pixel P4 are alternately arranged in the second direction Y, and the second width L2 of the second active layer 22 in the second sub-pixel P2 can be less than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0142] In an exemplary embodiment, the widths of the second active layer 22 of the four sub-pixels in at least one repeating unit may be different. For example, the first width L1 of the second active layer 22 in the first sub-pixel P1 may be greater than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4. Similarly, the second width L2 of the second active layer 22 in the second sub-pixel P2 may be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3.

[0143] In an exemplary embodiment, this disclosure, by alternately setting a second active layer with a larger width and a second active layer with a smaller width in the first direction X and the second direction Y, can not only effectively match the requirements of a single scan signal line structure, but also effectively increase the uniformity of the layout of the four pixel driving circuits in the repeating unit, and effectively increase the uniformity of the pixel openings of the four sub-pixels in the repeating unit.

[0144] In an exemplary embodiment, the orthographic projection of the first region of the third active layer 23 of each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 onto the substrate, and the orthographic projection of the second region of the third active layer 23 onto the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode 14 of the sub-pixel onto the substrate.

[0145] In an exemplary embodiment, in at least one repeating unit, the first region of the third active layer 23 in the first sub-pixel P1 and the first region of the third active layer 23 in the second sub-pixel P2 can be interconnected, and the first region of the third active layer 23 in the third sub-pixel P3 and the first region of the third active layer 23 in the fourth sub-pixel P4 can be interconnected.

[0146] In an exemplary embodiment, the third active layer 23 in the first sub-pixel P1 and the third active layer 23 in the second sub-pixel P2 can be an interconnected integral structure, and the third active layer 23 in the third sub-pixel P3 and the third active layer 23 in the fourth sub-pixel P4 can be an interconnected integral structure. Therefore, the third transistors of two adjacent sub-pixels in a pixel row share the first region of the third active layer. By setting the third transistors of two adjacent sub-pixels in a pixel row to share the first region of the third active layer, this disclosure can not only effectively reduce the number of vias and the area occupied by the pixel driving circuit, but also increase the pixel aperture ratio and improve the display resolution. Furthermore, reducing vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0147] In an exemplary embodiment, the second electrode plate 62 can be rectangular in shape, with chamfered corners. It can be disposed between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second electrode plate 62 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 61 on the substrate. The second electrode plate 62 can serve as another transparent electrode plate of a transparent storage capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent storage capacitor.

[0148] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 of each sub-pixel can be an interconnected integral structure.

[0149] In an exemplary embodiment, the areas of the overlapping regions of the first electrode 61 and the second electrode 62 projected onto the substrate in each sub-pixel can be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0150] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0151] In an exemplary embodiment, in at least one repeating unit, the positions of the patterns in the semiconductor layer of the first sub-pixel P1 and the positions of the patterns in the semiconductor layer of the third sub-pixel P3 are substantially mirror-symmetrical with respect to the horizontal reference line; the positions of the patterns in the semiconductor layer of the second sub-pixel P2 and the positions of the patterns in the semiconductor layer of the fourth sub-pixel P4 are substantially mirror-symmetrical with respect to the horizontal reference line; the positions of the patterns in the semiconductor layer of the first sub-pixel P1 and the positions of the patterns in the semiconductor layer of the second sub-pixel P2 are substantially mirror-symmetrical with respect to the vertical reference line; and the positions of the patterns in the semiconductor layer of the third sub-pixel P3 and the positions of the patterns in the semiconductor layer of the fourth sub-pixel P4 are substantially mirror-symmetrical with respect to the vertical reference line.

[0152] (14) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer pattern covering a semiconductor layer, wherein a plurality of vias are provided on the second insulating layer, such as... Figure 8 As shown.

[0153] In an exemplary embodiment, the plurality of vias for each sub-pixel in each repeating unit includes at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0154] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the range of the first region of the first active layer 21 and the orthographic projection of the data signal line 52 onto the substrate. The first via V1 is a via of a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the first region of the first active layer 21. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the data signal line 52. This allows the via of the transition structure composed of the two half-holes to simultaneously expose the first region of the first active layer 21 and the data signal line 52. The first via V1 is configured to allow the subsequently formed seventh connection electrode to be connected to both the first region of the first active layer 21 and the data signal line 52 through this via.

[0155] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the first region of the second active layer 22 onto the substrate. The second insulating layer within the second via V2 is etched away, exposing the surface of the first region of the second active layer 22. The second via V2 is configured to allow subsequently formed power connection electrodes to connect to the first region of the second active layer 22 through this via. In this exemplary embodiment, the second via V2 serves as the active via in this embodiment.

[0156] In an exemplary embodiment, since the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are interconnected, two adjacent sub-pixels in two adjacent repeating units in the second direction Y can share the same second via V2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same second via V2. Similarly, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same second via V2. By setting two adjacent sub-pixels in two adjacent repeating units to share the same second via V2, this disclosure can not only effectively reduce the number of vias and the occupied area of ​​the pixel driving circuit, increasing the pixel aperture ratio and improving the display resolution, but also simplify the manufacturing process, reduce production costs, and improve product yield.

[0157] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the range of the second region of the second active layer 22 and the orthographic projection of the third connecting electrode 13 onto the substrate. The third via V3 is a via of a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the second active layer 22. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the third connecting electrode 13. This allows the via of the transition structure composed of the two half-holes to simultaneously expose the second region of the second active layer 22 and the third connecting electrode 13. The third via V3 is configured to allow the subsequently formed fifth connecting electrode to be connected to both the second region of the second active layer 22 and the third connecting electrode 13 through this via.

[0158] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the range of the first region of the third active layer 23 and the orthographic projection of the compensation signal line 53 onto the substrate. The fourth via V4 is a via of a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the first region of the third active layer 23. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the compensation signal line 53. This allows the via of the transition structure composed of the two half-holes to simultaneously expose the first region of the third active layer 23 and the compensation signal line 53. The fourth via V4 is configured to allow the subsequently formed eighth connection electrode to be connected to both the first region of the third active layer 23 and the compensation signal line 53 through this via.

[0159] In an exemplary embodiment, since the first regions of the third active layer in the first sub-pixel P1 and the second sub-pixel P2 in the repeating unit are interconnected, and the first regions of the third active layer in the third sub-pixel P3 and the fourth sub-pixel P4 are interconnected, the first sub-pixel P1 and the second sub-pixel P2 in the repeating unit can share the same fourth via V4, and the third sub-pixel P3 and the fourth sub-pixel P4 can share the same fourth via V4. This disclosure, by setting adjacent sub-pixels to share the same fourth via V4, can not only effectively reduce the number of vias and the occupied area of ​​the pixel driving circuit, increasing the pixel aperture ratio and improving the display resolution, but also simplify the manufacturing process, reduce production costs, and improve product yield.

[0160] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the range of the orthographic projections of the second region of the third active layer 23 and the fourth connecting electrode 14 onto the substrate. The fifth via V5 is a via of a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the third active layer 23. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the fourth connecting electrode 14. This allows the via of the transition structure composed of the two half-holes to simultaneously expose the second region of the third active layer 23 and the fourth connecting electrode 14. The fifth via V5 is configured to allow the subsequently formed sixth connecting electrode to simultaneously connect to the second region of the third active layer 23 and the fourth connecting electrode 14 through this via.

[0161] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the second electrode plate 62 on the substrate. The second insulating layer within the sixth via V6 is etched away, exposing the surface of the second electrode plate 62. The sixth via V6 is configured to allow the subsequently formed second gate electrode to be connected to the second electrode plate 62 through the via.

[0162] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the range of the orthographic projection of the first power line 51 onto the substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first power line 51. The seventh via V7 is configured to allow subsequently formed power connection electrodes to connect to the first power line 51 through this via. In this exemplary embodiment, the seventh via V7 serves as the power via in this embodiment.

[0163] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same seventh via V7. For example, the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 share the same seventh via V7. Similarly, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 share the same seventh via V7. By setting two adjacent sub-pixels in two adjacent repeating units in the first direction X to share the same seventh via V7, this disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0164] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same seventh via V7. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same seventh via V7. Similarly, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same seventh via V7. By setting two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the same seventh via V7, this disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0165] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same seventh via V7, that is, four adjacent sub-pixels in adjacent repeating units share the same seventh via V7. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are two adjacent sub-pixels. For the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels. For the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are two adjacent sub-pixels. For the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels. The fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 share the same seventh via V7. This disclosure, by setting four adjacent sub-pixels in adjacent repeating units to share the same seventh via V7, can not only effectively reduce the number of vias and the area occupied by the pixel driving circuit, but also increase the pixel aperture ratio and improve the display resolution. Furthermore, reducing vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0166] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a plurality of vias are formed using a dry etching process. Simultaneously, the semiconductor layer exposed within the vias undergoes a first conductive treatment, creating a first conductive region in the exposed semiconductor layer. During this first conductive treatment, the portion of the semiconductor layer covered by the second insulating layer near the edge of the via is also conductive; that is, the first conductive semiconductor layer extends away from the via.

[0167] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern on a second insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the gate metal (GT) layer.

[0168] In an exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a power connection electrode 20, a scan signal line 30, a first gate electrode 31, a second gate electrode 32, and a third gate electrode 33.

[0169] In an exemplary embodiment, the shape of the scan signal line 30 can be the shape of the main body extending along the first direction X, and can be located in the middle of the repeating unit in the second direction Y, that is, between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4. The scan signal line 30 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0170] In an exemplary embodiment, the orthographic projection of the scan signal line 30 on the substrate does not overlap with the orthographic projections of the first active layer 21 and the third active layer 23 on the substrate.

[0171] In an exemplary embodiment, the first gate electrode 31 can be a strip extending along the second direction Y, and can be disposed on the side of the scan signal line 30 near the first active layer 21. The first end of the first gate electrode 31 is connected to the scan signal line 30, and the second end of the first gate electrode 31 extends toward the first active layer 21. The orthographic projection of the first gate electrode 31 onto the substrate at least partially overlaps with the orthographic projection of the first active layer 21 onto the substrate. In an exemplary embodiment, the first gate electrode 31 can serve as the gate electrode of the first transistor T1, allowing the scan signal line 30 to control the conduction or disconnection of the first transistor T1.

[0172] In an exemplary embodiment, the second gate electrode 32 can be a strip extending along the second direction Y. The first end of the second gate electrode 32 is connected to the second electrode plate 62 through a sixth via V6, and the second end of the second gate electrode 32 extends towards the second active layer 22. The orthographic projection of the second gate electrode 32 onto the substrate at least partially overlaps with the orthographic projection of the second active layer 22 onto the substrate. In an exemplary embodiment, the second gate electrode 32 can serve as the gate electrode of the second transistor T2, controlling the conduction or disconnection of the second transistor T2.

[0173] In an exemplary embodiment, since the second gate electrode 32 is connected to the second electrode plate 62 and the second electrode plate 62 is connected to the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 (the first end of the storage capacitor) have the same potential, forming the first node in the pixel driving circuit, and the second electrode plate 62 has the potential of the first node in the pixel driving circuit.

[0174] In an exemplary embodiment, the third gate electrode 33 can be a strip extending along the second direction Y, and can be disposed on the side of the scan signal line 30 near the third active layer 23. The first end of the third gate electrode 33 is connected to the scan signal line 30, and the second end of the third gate electrode 33 extends toward the third active layer 23. The orthographic projection of the third gate electrode 33 onto the substrate at least partially overlaps with the orthographic projection of the third active layer 23 onto the substrate. In an exemplary embodiment, the third gate electrode 33 can serve as the gate electrode of the third transistor T3, allowing the scan signal line 30 to control the conduction or disconnection of the third transistor T3.

[0175] In an exemplary embodiment, in a sub-pixel, a scan signal line 30 is simultaneously connected to the first gate electrode 31 and the third gate electrode 33, so that the scan signal line 30 can control the conduction or disconnection of the first transistor T1 and the third transistor T3 in a sub-pixel.

[0176] In an exemplary embodiment, in a pixel row, a scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, such that the scan signal line 30 can control the on or off of all first transistors T1 and all third transistors T3 in a pixel row.

[0177] In an exemplary embodiment, in a repeating unit, a scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, such that the scan signal line 30 can simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the repeating unit.

[0178] In an exemplary embodiment, the fifth connecting electrode 15 can be block-shaped (such as rectangular) and can be disposed on the side of the second electrode plate 62 away from the scan signal line 30. The fifth connecting electrode 15 is connected to the second region of the second active layer 22 and the third connecting electrode 13 through the third via V3.

[0179] In an exemplary embodiment, since the fifth connection electrode 15 is simultaneously connected to the second region of the second active layer 22 and the third connection electrode 13, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode plate 61, the fifth connection electrode 15 causes the second electrode of the second transistor and the first electrode plate 61 to have the same potential. In an exemplary embodiment, the fifth connection electrode 15 is configured to be connected to the subsequently formed anode connection electrode.

[0180] In an exemplary embodiment, the sixth connecting electrode 16 can be block-shaped (such as rectangular) and can be disposed on the side of the second electrode plate 62 near the scan signal line 30. The sixth connecting electrode 16 is connected to the second region of the third active layer 23 and the fourth connecting electrode 14 through the fifth via V5.

[0181] In an exemplary embodiment, since the sixth connection electrode 16 is connected to both the second region of the third active layer 23 and the fourth connection electrode 14, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first electrode plate 61, the sixth connection electrode 16 causes the second electrode of the third transistor and the first electrode plate 61 to have the same potential.

[0182] In an exemplary embodiment, the fifth connection electrode 15 and the sixth connection electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor and the first electrode plate 61 (the second end of the storage capacitor), forming a second node in the pixel driving circuit, so the first electrode plate 61 has the potential of the second node in the pixel driving circuit.

[0183] In an exemplary embodiment, since the first electrode plate 61 has the potential of the second node in the pixel driving circuit and the second electrode plate 62 has the potential of the first node in the pixel driving circuit, the first electrode plate 61 having the potential of the second node and the second electrode plate 62 having the potential of the first node form a storage capacitor.

[0184] In an exemplary embodiment, since the first electrode 61 is made of a transparent conductive material and the second electrode 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0185] In an exemplary embodiment, the seventh connection electrode 17 can be block-shaped (e.g., rectangular) and can be disposed between the first gate electrode 31 and the first power line 51. The seventh connection electrode 17 is connected to both the first region of the first active layer 21 and the data signal line 52 through the first via V1, thus enabling the data signal line 52 to write data signals to the first electrode of the first transistor T1. In an exemplary embodiment, each data signal line 52 can be connected to the first region of the first active layer in a sub-pixel through the first via V1, thus enabling four data signal lines 52 to write data signals to the first electrode of the first transistor T1 in a plurality of repeating units arranged along the second direction Y.

[0186] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. In each repeating unit, the first data signal line can be connected to the first region of the first active layer of the first sub-pixel P1 via the seventh connection electrode 17, the second data signal line can be connected to the first region of the first active layer of the third sub-pixel P3 via the seventh connection electrode 17, the third data signal line can be connected to the first region of the first active layer of the second sub-pixel P2 via the seventh connection electrode 17, and the fourth data signal line can be connected to the first region of the first active layer of the fourth sub-pixel P4 via the seventh connection electrode 17.

[0187] In an exemplary embodiment, the shape of the eighth connection electrode 18 can be a block shape (such as a rectangle), and it can be disposed between the third gate electrode 33 of two adjacent sub-pixels in the first direction X. The eighth connection electrode 18 is connected to the first region of the third active layer 23 and the compensation signal line 53 through the fourth via V4, thereby realizing that the compensation signal line 53 writes the compensation signal into the first pole of the third transistor T3.

[0188] In an exemplary embodiment, since the first regions of the third active layers in the first sub-pixel P1 and the second sub-pixel P2 in the repeating unit are interconnected, the first sub-pixel P1 and the second sub-pixel P2 share the same fourth via V4, and therefore the first sub-pixel P1 and the second sub-pixel P2 share the same eighth connecting electrode 18. Since the first regions of the third active layers in the third sub-pixel P3 and the fourth sub-pixel P4 are interconnected, the third sub-pixel P3 and the fourth sub-pixel P4 share the same fourth via V4, and therefore the third sub-pixel P3 and the fourth sub-pixel P4 share the same eighth connecting electrode 18. This disclosure, by setting adjacent sub-pixels in the first X direction of the repeating unit to share the same eighth connecting electrode, can not only effectively reduce the number of connecting electrodes, reduce the occupied area of ​​the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution, but also simplify the manufacturing process, reduce production costs, and improve product yield by reducing the number of connecting electrodes.

[0189] In an exemplary embodiment, in one repeating unit, the compensation signal line 53 can simultaneously provide compensation signals to the pixel driving circuits in four sub-pixels. Therefore, the four pixel driving circuits in one repeating unit can share one compensation signal line 53, i.e., the compensation signal line 53 in one repeating unit is a one-to-four structure. This disclosure's display substrate, by designing the compensation signal line as a one-to-four structure, saves the number of signal lines, reduces the space occupied, has a simple structure, a reasonable layout, makes full use of the layout space, improves space utilization, increases the pixel aperture ratio, and improves the display resolution.

[0190] In an exemplary embodiment, the compensation signal line 53 is disposed between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically disposed with respect to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the RC delay of the compensation signal written to the third transistor T3 is substantially the same, thus guaranteeing display uniformity.

[0191] In an exemplary embodiment, the power connection electrode 20 can be a strip shape extending along the first direction X, and can be disposed on the side of the second electrode plate 62 away from the scan signal line 30. The first end of the power connection electrode 20 is connected to the first power line 51 through the seventh via V7, and the second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through the second via V2, thereby realizing that the first power line 51 writes the first power signal into the first electrode of the second transistor T2.

[0192] In an exemplary embodiment, in each repeating unit, the first power line 51 of the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first sub-pixel P1 and the third sub-pixel P3, and the first power line 51 of the second pixel column can simultaneously provide a first power signal to the pixel driving circuits in the second sub-pixel P2 and the fourth sub-pixel P4. Therefore, the first power line 51 in one repeating unit is a one-to-two structure. By designing the first power line as a one-to-two structure, the display substrate of this disclosure saves the number of signal lines, reduces the space occupied, has a simple structure, a reasonable layout, makes full use of the layout space, improves space utilization, increases the pixel aperture ratio, and improves the display resolution.

[0193] In an exemplary embodiment, two first power lines 51 in a repeating unit are symmetrically arranged with respect to the compensation signal line 53, and the second transistor T2 of the first pixel column and the second transistor T2 of the second pixel column are symmetrically arranged with respect to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the voltage drop of the first power line written to the second transistor T2 is substantially the same, thus ensuring display uniformity.

[0194] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X can be connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 can be connected to each other. As another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 can be connected to each other.

[0195] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X can be an integral structure that is interconnected.

[0196] In an exemplary embodiment, since the second transistors of two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the first region of the second active layer, and the two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same second via V2, the two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same power connection electrode 20. Similarly, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same power connection electrode 20. By setting two sub-pixels in adjacent repeating units in the second direction Y to share the same power connection electrode, this disclosure can not only effectively reduce the number of connection electrodes, reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution, but also simplify the manufacturing process, reduce production costs, and improve product yield by reducing the number of connection electrodes.

[0197] In an exemplary embodiment, in at least one repeating unit, the positions of the patterns in the third conductive layer of the first sub-pixel P1 and the positions of the patterns in the third conductive layer of the third sub-pixel P3 are substantially mirror-symmetrical with respect to the horizontal baseline; the positions of the patterns in the third conductive layer of the second sub-pixel P2 and the positions of the patterns in the third conductive layer of the fourth sub-pixel P4 are substantially mirror-symmetrical with respect to the horizontal baseline; the positions of the patterns in the third conductive layer of the first sub-pixel P1 and the positions of the patterns in the third conductive layer of the second sub-pixel P2 are substantially mirror-symmetrical with respect to the vertical baseline; and the positions of the patterns in the third conductive layer of the third sub-pixel P3 and the positions of the patterns in the third conductive layer of the fourth sub-pixel P4 are substantially mirror-symmetrical with respect to the vertical baseline.

[0198] In an exemplary embodiment, during the process of forming the third conductive layer pattern, a wet etching process is first used to form the third conductive layer pattern, enabling at least one connection electrode to be simultaneously connected to the second conductive layer and the semiconductor layer through a via of the transition structure. The via of the transition structure may include at least two half-holes: a shallow half-hole and a deep half-hole. In the shallow half-hole, the second insulating layer is removed, exposing the surface of the semiconductor layer; in the deep half-hole, both the second and first insulating layers are removed, exposing the surface of the second conductive layer. This achieves the simultaneous connection of the connection electrode to the semiconductor layer and the second conductive layer through the shallow and deep half-holes. In an exemplary embodiment, a distance is provided between the end of the connection electrode located in the shallow half-hole region and the edge of the shallow half-hole, meaning the connection electrode does not completely cover the shallow half-hole.

[0199] In an exemplary embodiment, after the wet etching process forms the pattern of the third conductive layer, a self-aligned process using the third conductive layer as a mask is employed to etch the second insulating layer outside the third conductive layer using a dry etching process. While etching away the second insulating layer, the exposed semiconductor layer is subjected to a second conductorization to form a second conductorization region.

[0200] In an exemplary embodiment, during the second conductorization process, the edge portion of the semiconductor layer covered by the third conductive layer is also conductorized. That is, the semiconductor layer that is conductorized for the second time extends to the region that is conductorized for the first time, forming a double conductorization region in the overlapping area of ​​the first conductorization region and the second conductorization region, which can ensure a reliable connection between the third conductive layer and the semiconductor layer.

[0201] In an exemplary embodiment, for the power connection electrode 20 connected to the first region of the second active layer 22 through the second via V2, and the second gate electrode 32 connected to the second electrode plate 62 through the sixth via V6, the power connection electrode 20 and the second gate electrode 32 do not completely cover the via, and a distance is provided between the edge of the connection electrode and the edge of the via.

[0202] Figure 9C for Figure 9A Sectional view along the AA direction. Figures 9D to 9F for Figure 9A A cross-sectional view along the BB direction. In a direction perpendicular to the display substrate, the display substrate may include at least a second conductive layer, a first insulating layer 71, a semiconductor layer, a second insulating layer 72, and a third conductive layer sequentially disposed on the substrate 10. The second conductive layer may include at least a first power line 51 and a data signal line 52, the semiconductor layer may include at least a second active layer 22, and the third conductive layer may include at least a power connection electrode 20.

[0203] In an exemplary embodiment, the first end of the power connection electrode 20 is connected to the first power line 51 through a seventh via V7, and the second end of the power connection electrode 20 is connected to the second active layer 22 through a second via V2. Figure 9C As shown.

[0204] In an exemplary embodiment, during the process of forming the second insulating layer pattern, the second insulating layer within the second via V2 is etched away, exposing the surface of the second active layer 22. Simultaneously, the semiconductor layer exposed within the second via V2 undergoes a first conductor-enhancing process, forming a first conductor-enhanced region within the exposed semiconductor layer of the second via V2. Figure 9D As shown.

[0205] In an exemplary embodiment, in the process of forming the third conductive layer pattern, a third conductive layer including a power connection electrode 20 is first formed by a wet etching process. The power connection electrode 20 is connected to the second active layer 22 through a second via V2, such as... Figure 9E As shown. Subsequently, using a self-aligned process with the third conductive layer as a mask, a dry etching process is employed to etch the second insulating layer 72 outside the third conductive layer. Simultaneously, the exposed semiconductor layer 72 is subjected to a second conductorization, forming a second conductorized region, as shown. Figure 9F As shown.

[0206] (16) Forming a third insulating layer and a planarization layer pattern. In an exemplary embodiment, forming the third insulating layer and the planarization layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, then coating a planarization film, and patterning the planarization film and the third insulating film using a patterning process to form a third insulating layer covering a third conductive layer and a planarization layer pattern disposed on the third insulating layer, wherein the planarization layer is provided with a plurality of vias, such as... Figure 10 As shown.

[0207] In an exemplary embodiment, the via of each sub-pixel in each repeating unit includes at least an eleventh via V11.

[0208] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 15 onto the substrate. The third insulating layer and planarization layer within the eleventh via V11 are etched away, exposing the surface of the fifth connecting electrode 15. The eleventh via V11 is configured to allow the subsequently formed anode connecting electrode to be connected to the fifth connecting electrode 15 through the via.

[0209] In an exemplary embodiment, this process uses a single patterning process to simultaneously form vias on the third insulating layer and the planarization layer. That is, the third insulating layer and the planarization layer share a single halftone or gray-toned mask process, which effectively reduces the number of patterning processes.

[0210] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming a fourth conductive layer pattern on the color filter layer, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A A schematic diagram of the fourth conductive layer.

[0211] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in each repeating unit may include at least a first electrode 63 and an anode connection electrode 64.

[0212] In an exemplary embodiment, the first electrode 63 may be rectangular in shape, and the corners of the rectangle may be chamfered, grooved, or protruded. The orthographic projection of the first electrode 63 on the substrate and the orthographic projection of the second electrode plate 62 on the substrate at least partially overlap.

[0213] In an exemplary embodiment, the anode connection electrode 64 may be block-shaped (e.g., rectangular) and may be located on the side of the first electrode 63 away from the scan signal line 30. The first end of the anode connection electrode 64 is connected to the first electrode 63, and the second end of the anode connection electrode 64 extends in a direction away from the scan signal line 30 and is connected to the fifth connection electrode 15 through the eleventh via V11.

[0214] In an exemplary embodiment, in at least one sub-pixel, the anode connecting electrode 64 and the first electrode 63 can be an integral structure that is interconnected.

[0215] In an exemplary embodiment, in at least one repeating unit, the four first electrodes 63 can be arranged in a square. The upper left first electrode is connected to the pixel driving circuit in the first sub-pixel P1, the upper right first electrode is connected to the pixel driving circuit in the second sub-pixel P2, the lower left first electrode is connected to the pixel driving circuit in the third sub-pixel P3, and the lower right first electrode is connected to the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the first electrode can serve as the anode of the light-emitting device. The arrangement of the first electrodes can be adjusted according to actual needs, and this disclosure does not impose specific limitations here.

[0216] In an exemplary embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0217] In an exemplary embodiment, the first electrode 63 can also serve as an auxiliary capacitor for the storage capacitor. Since the first electrode 63 is connected to the anode connection electrode 64, and the anode connection electrode 64 is connected to the first electrode plate 61 via the fifth connection electrode 15, the third connection electrode 13, and the first connection electrode 11, the first electrode 63 possesses the potential of the second node in the pixel driving circuit. This allows the first electrode 63 with the second node potential and the second electrode plate 62 with the first node potential to form an auxiliary capacitor, which is connected in parallel with the storage capacitor. This disclosure utilizes the first electrode to form an auxiliary capacitor, and the auxiliary capacitor is connected in parallel with the storage capacitor. On the one hand, this effectively increases the capacitance value of the storage capacitor; on the other hand, it reduces the electrode plate area while maintaining the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0218] (18) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer covering the fourth conductive layer, such as... Figure 12 As shown.

[0219] In an exemplary embodiment, a pixel opening PK is provided on the pixel definition layer of each sub-pixel in each repeating unit. The pixel definition film inside the pixel opening PK is removed, exposing part of the surface of the first electrode 63. The orthographic projection of the pixel opening PK on the substrate is located within the range of the orthographic projection of the first electrode 63 on the substrate.

[0220] In an exemplary embodiment, the shape of the pixel opening PK can be similar to the shape of the first electrode 63 in a plane parallel to the substrate, and the cross-sectional shape of the pixel opening PK can be rectangular or trapezoidal in a plane perpendicular to the substrate.

[0221] In an exemplary embodiment, the shape of the pixel opening may include any one or more of the following: triangle, rectangle, trapezoid, parallelogram, pentagon, hexagon, circle, and ellipse.

[0222] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels in the repeating unit may be the same or different. The areas of the pixel openings of the four sub-pixels may be the same or different.

[0223] In an exemplary embodiment, the shape and area of ​​the pixel openings of the four sub-pixels in the repeating unit can be different to accommodate the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0224] In an exemplary embodiment, at least one partition groove M may be provided on the pixel definition layer of each repeating unit. The partition groove M may be a strip shape extending along the second direction Y of the main body and may be disposed between adjacent pixel openings PK in the first direction X. For example, the partition groove M may be disposed between the pixel opening PK of the first sub-pixel P1 and the pixel opening PK of the second sub-pixel P2. As another example, the partition groove M may be disposed between the pixel opening PK of the third sub-pixel P3 and the pixel opening PK of the fourth sub-pixel P4. In an exemplary embodiment, the partition groove M is configured to truncate the subsequently formed organic light-emitting layer, block the lateral propagation path of hole carriers, eliminate lateral leakage, and eliminate lateral crosstalk of sub-pixels.

[0225] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0226] (19) Forming an organic light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern may include: first forming an organic light-emitting layer pattern, wherein the organic light-emitting layer is connected to the first electrode 63 through a pixel opening PK. Subsequently, a second electrode is formed, wherein the second electrode is connected to the organic light-emitting layer. In an exemplary embodiment, the second electrode may serve as the cathode of the light-emitting device.

[0227] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0228] (20) Forming an encapsulation structure layer pattern. In an exemplary embodiment, forming an encapsulation structure layer pattern may include: firstly, depositing a first inorganic thin film using an open mask to form a first encapsulation layer. Subsequently, using an inkjet printing process, inkjet printing an organic material onto the first encapsulation layer, and curing it into a film to form a second encapsulation layer. Subsequently, depositing a second inorganic thin film using an open mask to form a third encapsulation layer, wherein the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer constitute an encapsulation structure layer. The first encapsulation layer and the third encapsulation layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The second encapsulation layer may be made of resin material, forming an inorganic material / organic material / inorganic material stacked structure. The organic material layer is disposed between the two inorganic material layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0229] This completes the fabrication of the display substrate according to the exemplary embodiments of this disclosure. The display substrate may include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a planarization layer sequentially disposed on the substrate. The light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.

[0230] In an exemplary embodiment, for a display substrate including a color filter structure layer, after forming the third conductive layer, a third insulating layer can be formed first, followed by the sequential formation of a red color filter layer, a green color filter layer, and a blue color filter layer, and then a planarization layer can be formed. This will not be elaborated further here.

[0231] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0232] In an exemplary embodiment, the second and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, and third insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The planarization layer can be made of organic materials, such as resin.

[0233] This disclosure provides a display substrate with a bottom-emitting structure. By placing the first electrode of the second transistor in a sub-pixel near a first power line, and by having adjacent sub-pixels in two adjacent repeating units in a first direction share a power via connecting the gate metal layer and the second conductive layer, and by having adjacent sub-pixels in two adjacent repeating units in a second direction share a power via connecting the gate metal layer and the second conductive layer, the number of vias is reduced. This effectively reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution. Furthermore, reducing vias simplifies the manufacturing process, reduces production costs, and improves product yield.

[0234] The present invention discloses a display substrate by setting the second active layers of two adjacent sub-pixels in two adjacent repeating units in the second direction into an integral structure that is interconnected. This allows two adjacent sub-pixels in two adjacent repeating units in the second direction to share an active via that connects the gate metal layer and the semiconductor layer, thereby further reducing the number of vias. This can effectively reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution.

[0235] The present invention discloses a display substrate by setting the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in a first direction to be interconnected as an integral structure, and by having two adjacent sub-pixels in two adjacent repeating units in a second direction share the power connection electrodes. This reduces the number of connection electrodes, effectively reducing the area occupied by the pixel driving circuit, increasing the pixel aperture ratio, and improving the display resolution. Furthermore, reducing the number of connection electrodes simplifies the manufacturing process, reduces production costs, and improves product yield.

[0236] The embodiments disclosed herein show that by alternately setting a second active layer with a larger width and a second active layer with a smaller width in the first direction X and the second direction Y, the substrate can not only effectively match the requirements of the single scan signal line structure, but also effectively increase the uniformity of the layout of the four pixel driving circuits in the repeating unit, and effectively increase the uniformity of the pixel openings of the four sub-pixels in the repeating unit.

[0237] The display substrate of this disclosure places the first power line, data signal line, and compensation signal line on the SHIELD layer, located on the side of the semiconductor layer close to the substrate, and the scan signal line and gate electrodes of multiple transistors on the GT layer, located on the side of the semiconductor layer away from the substrate. This not only reduces one conductive layer but also reduces the patterning process for the transition vias and the patterning process for the transition conductive layer, requiring only six patterning (MASK) processes to fabricate the driving structure layer. Compared to existing fabrication processes that require nine patterning processes, the display substrate of this disclosure reduces the number of patterning processes, effectively improving production efficiency, effectively reducing production costs, and maximizing product yield.

[0238] The display substrate of this disclosure employs a 3T1C pixel driving circuit with one scan signal line. This scan signal line is connected to the first and third transistors in the pixel driving circuit. By reducing the number of scan signal lines, the structure of the pixel driving circuit can be simplified, and the occupied area of ​​the pixel driving circuit can be reduced, which is beneficial for achieving high-resolution displays. Furthermore, since only one scan signal line is needed to drive a repeating unit, the number of its corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced significantly, effectively reducing the occupied area of ​​the gate driving circuit and clock signal line, which is beneficial for achieving narrow bezels and improving product advantages.

[0239] The present invention discloses a substrate that forms a transparent storage capacitor by means of a transparent conductive layer and a transparent semiconductor layer, so that light can pass through the transparent storage capacitor and be emitted. Therefore, the storage capacitor can be disposed in the pixel aperture, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture ratio.

[0240] The display substrate of this disclosure adopts a square arrangement of sub-pixels and a non-mesh first power line structure, which can effectively increase the pixel aperture ratio, improve the display effect, and is more suitable for display types of monitors.

[0241] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0242] Figure 13 This is a schematic diagram of another display substrate structure in an exemplary embodiment of the present disclosure, illustrating the structure of four repeating units (sixteen sub-pixels) in a bottom-emitting display substrate. In the exemplary embodiment, the main structure of the display substrate in this embodiment is basically the same as that in the previous embodiment, except that the pixel driving circuit further includes an active connection electrode 24, and the power connection electrode 20 is connected to both the first power line 51 and the active connection electrode 24 through a transition via.

[0243] In the exemplary embodiment, the structures of the scan signal line 30, the first power supply line 51, the data signal line 52, the compensation signal line 53, the storage capacitor 60, the first transistor T1, the second transistor T2, and the third transistor T3 are basically the same as those in the previous embodiment, and will not be described again here.

[0244] In an exemplary embodiment, the pixel driving circuit further includes an active connection electrode 24. The active connection electrode 24 may be a strip shape extending along a first direction X. The first end of the active connection electrode 24 is connected to a first region of the second active layer 22 of the integral structure, and the second end of the active connection electrode 24 extends in a direction away from the second active layer 22 to the region where the first power line 51 is located.

[0245] In an exemplary embodiment, the second active layer 22 and the active connection electrode 24 can be an integral structure that is interconnected.

[0246] In an exemplary embodiment, the orthographic projection of the second end of the active connection electrode 24 onto the substrate at least partially overlaps with the orthographic projection of the first power line 51 onto the substrate.

[0247] In an exemplary embodiment, the orthographic projection of the active connection electrode 24 on the substrate and the orthographic projection of the data signal line 52 on the substrate at least partially overlap, forming a structure in which the second active layer 22 spans the data signal line 52.

[0248] In an exemplary embodiment, the power connection electrode 20 can be block-shaped (such as rectangular), and the power connection electrode 20 is connected to the second end of the first power line 51 and the active connection electrode 24 simultaneously through the adapter via K3.

[0249] In an exemplary embodiment, the adapter via K3 may include a shallow half-hole and a deep half-hole. The shallow half-hole exposes the surface of the second end of the active connection electrode 24, and the deep half-hole exposes the surface of the first power line 51. The shallow half-hole can serve as an active via of this disclosure, and the deep half-hole can serve as a power via of this disclosure.

[0250] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same transition via K3. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same transition via K3. Similarly, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same transition via K3.

[0251] In an exemplary embodiment, two adjacent sub-pixels in two repeating units adjacent in the second direction Y share the same transition via K3. For example, for a first repeating unit Q1 and a third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same transition via K3, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same transition via K3. Similarly, for a second repeating unit Q2 and a fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same transition via K3, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same transition via K3.

[0252] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same transition via K3, that is, four adjacent sub-pixels in adjacent repeating units share the same transition via K3. For example, the fourth sub-pixel P4 in the first repeating unit Q1, the third sub-pixel P3 in the second repeating unit Q2, the second sub-pixel P2 in the third repeating unit Q3, and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same transition via K3.

[0253] In an exemplary embodiment, the second ends of the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X can be interconnected. Since the active connection electrode 24 of each sub-pixel is connected to the first region of the second active layer 22, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are interconnected through the active connection electrodes 24. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are interconnected through the active connection electrodes 24. As another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are interconnected through the active connection electrodes 24.

[0254] In an exemplary embodiment, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure that is interconnected.

[0255] In an exemplary embodiment, two adjacent sub-pixels in two repeating units adjacent in the second direction Y can share the same active connection electrode 24. For example, for a first repeating unit Q1 and a third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same active connection electrode 24. Similarly, for a second repeating unit Q2 and a fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same active connection electrode 24.

[0256] In an exemplary embodiment, the first region of the second active layer 22 of adjacent sub-pixels in the repeating units adjacent in the first direction X and the second direction Y can be interconnected by an active connection electrode 24.

[0257] In an exemplary embodiment, two adjacent sub-pixels in two repeating units adjacent in the first direction X share the same power connection electrode 20. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same power connection electrode 20. Similarly, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same power connection electrode 20.

[0258] In an exemplary embodiment, two adjacent sub-pixels in two repeating units adjacent in the second direction Y share the same power connection electrode 20. For example, for a first repeating unit Q1 and a third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same power connection electrode 20. Similarly, for a second repeating unit Q2 and a fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same power connection electrode 20.

[0259] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same power connection electrode 20, that is, four adjacent sub-pixels in adjacent repeating units share the same power connection electrode 20. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share the same power connection electrode 20.

[0260] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0261] (21) Forming a first conductive layer pattern, the process and the structure of the first conductive layer formed are basically the same as step (11) of the aforementioned embodiment.

[0262] (22) Forming a second conductive layer pattern, the process and the structure of the formed second conductive layer are basically the same as step (12) of the aforementioned embodiment.

[0263] (23) Forming a semiconductor layer pattern, the process and the structure of the formed semiconductor layer are basically the same as step (13) in the aforementioned embodiment, except that the semiconductor layer also includes an active connection electrode 24, such as Figure 14A and Figure 14B As shown, Figure 14B for Figure 14A A schematic diagram of the semiconductor layer.

[0264] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode plate 62 of a storage capacitor, and the structure is substantially the same as that in the foregoing embodiments.

[0265] In an exemplary embodiment, the semiconductor layer of each sub-pixel may further include an active connection electrode 24. The active connection electrode 24 may be a strip shape extending along the first direction X. The first end of the active connection electrode 24 is connected to the first region of the second active layer 22 of the integral structure. The second end of the active connection electrode 24 extends in a direction away from the second active layer 22 to the region where the first power line 51 is located. The second end of the active connection electrode 24 is configured to be connected to the first power line 51 through a subsequently formed power connection electrode.

[0266] In an exemplary embodiment, the second active layer 22 and the active connection electrode 24 can be an integral structure that is interconnected.

[0267] In an exemplary embodiment, the orthographic projection of the second end of the active connection electrode 24 onto the substrate at least partially overlaps with the orthographic projection of the first power line 51 onto the substrate.

[0268] In an exemplary embodiment, the orthographic projection of the active connection electrode 24 on the substrate and the orthographic projection of the data signal line 52 on the substrate at least partially overlap, forming a structure in which the second active layer 22 spans the data signal line 52.

[0269] In an exemplary embodiment, the second active layer 22 of two adjacent sub-pixels in two repeating units adjacent in the second direction Y can be an integral structure interconnected, thus allowing two adjacent sub-pixels in two repeating units adjacent in the second direction Y to share the same active connection electrode 24. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same active connection electrode 24. Similarly, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same active connection electrode 24.

[0270] In an exemplary embodiment, the active connection electrodes 24 of two adjacent sub-pixels in two repeating units adjacent in the first direction X can be interconnected. Since the active connection electrode 24 of each sub-pixel is connected to the first region of the second active layer 22, the first regions of the second active layer 22 of two adjacent sub-pixels in two repeating units adjacent in the first direction X are interconnected through the active connection electrodes 24. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are interconnected through the active connection electrodes 24. As another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are interconnected through the active connection electrodes 24.

[0271] In an exemplary embodiment, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure that is interconnected.

[0272] In an exemplary embodiment, the first regions of the second active layer 22 of adjacent sub-pixels in repeating units adjacent in the first direction X and the second direction Y can be interconnected by active connection electrodes 24. For example, the first regions of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1, the first regions of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2, the first regions of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3, and the first regions of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 can be interconnected by active connection electrodes 24. By setting the second transistors of four adjacent sub-pixels in adjacent repeating units to share the first region of the second active layer, this disclosure can not only effectively reduce the number of vias and the occupied area of ​​the pixel driving circuit, but also increase the pixel aperture ratio and improve the display resolution. Furthermore, reducing vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0273] In an exemplary embodiment, the widths of the second active layers in adjacent sub-pixels in the first direction X are different, and the widths of the second active layers in adjacent sub-pixels in the second direction Y are different.

[0274] (24) Forming the second insulating layer pattern, the process and the structure of the formed second insulating layer are basically the same as step (14) of the aforementioned embodiment, except that the eighth via V8 is a via with a transition structure, such as Figure 15 As shown.

[0275] In an exemplary embodiment, a plurality of vias are provided on the second insulating layer. The plurality of vias in each sub-pixel of each repeating unit include at least a first via V1, a third via V3 to a sixth via V6. The structure of the vias is substantially the same as that in the aforementioned embodiment.

[0276] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the range of the orthographic projections of the second end of the active connection electrode 24 and the first power line 51 onto the substrate. The eighth via V8, as a transition via of this disclosure, includes a shallow half-hole and a deep half-hole. The second insulating layer within the shallow half-hole is etched away, exposing the surface of the second end of the active connection electrode 24. The first and second insulating layers within the deep half-hole are etched away, exposing the surface of the first power line 51. This allows the via of the transition structure composed of the two half-holes to simultaneously expose the second end of the active connection electrode 24 and the first power line 51. The eighth via V8 is configured to allow a subsequently formed power connection electrode to simultaneously connect to the second end of the active connection electrode 24 and the first power line 51 through this via. In an exemplary embodiment, the eighth via V8 serves as a transition via of this disclosure, the shallow half-hole can serve as an active via of this disclosure, and the deep half-hole can serve as a power via of this disclosure.

[0277] In an exemplary embodiment, since the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are interconnected as a single integrated structure, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same eighth via V8. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same eighth via V8. Similarly, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same eighth via V8. By setting the two adjacent sub-pixels in two adjacent repeating units in the first direction X to share the same eighth via V8, this disclosure can not only effectively reduce the number of vias, reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution, but also simplify the manufacturing process, reduce production costs, and improve product yield.

[0278] In an exemplary embodiment, since two adjacent sub-pixels in two repeating units adjacent in the second direction Y can share the same active connection electrode 24, two adjacent sub-pixels in two repeating units adjacent in the second direction Y can share the same eighth via V8. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same eighth via V8, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same eighth via V8. Similarly, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same eighth via V8, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same eighth via V8. This disclosure, by setting two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the same eighth via V8, can not only effectively reduce the number of vias and the area occupied by the pixel driving circuit, but also increase the pixel aperture ratio and improve the display resolution. Furthermore, reducing vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0279] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same transition via K3, that is, four adjacent sub-pixels in adjacent repeating units share the same eighth via V8. For example, the fourth sub-pixel P4 in the first repeating unit Q1, the third sub-pixel P3 in the second repeating unit Q2, the second sub-pixel P2 in the third repeating unit Q3, and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same eighth via V8.

[0280] (25) Forming the third conductive layer pattern, the process and the structure of the formed third conductive layer are basically the same as step (15) of the aforementioned embodiment, except that the power connection electrode 20 is connected to the second end of the active connection electrode 24 and the first power line 51 simultaneously through the eighth via V8 of the adapter structure, as shown in the figure. Figure 16A and Figure 16B As shown, Figure 16B for Figure 16A A schematic diagram of the third conductive layer.

[0281] In an exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a power connection electrode 20, a scan signal line 30, a first gate electrode 31, a second gate electrode 32, and a third gate electrode 33. Except for the power connection electrode 20, the other structures are basically the same as those in the foregoing embodiments.

[0282] In an exemplary embodiment, the power connection electrode 20 can be block-shaped (e.g., rectangular). The power connection electrode 20 is connected to both the second end of the active connection electrode 24 and the first power line 51 through the eighth via V8 of the adapter structure. Since the active connection electrode 24 is connected to the first region of the second active layer, the first power line 51 writes the first power signal into the first terminal of the second transistor T2.

[0283] In an exemplary embodiment, since two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same eighth via V8, they also share the same power connection electrode 20. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same power connection electrode 20. Similarly, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same power connection electrode 20. By setting two adjacent sub-pixels in two adjacent repeating units in the first direction X to share the same power connection electrode 20, this disclosure not only effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0284] In an exemplary embodiment, since two adjacent sub-pixels in two repeating units adjacent in the second direction Y share the same eighth via V8, they also share the same power connection electrode 20. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same power connection electrode 20. Similarly, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same power connection electrode 20. This disclosure, by setting two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the same power supply connection electrode 20, can not only effectively reduce the number of connection electrodes and reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio and improve the display resolution, but also simplify the manufacturing process, reduce production costs and improve product yield by reducing the number of connection electrodes.

[0285] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same power connection electrode 20, that is, four adjacent sub-pixels in adjacent repeating units share the same power connection electrode 20. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share the same power connection electrode 20. By setting four adjacent sub-pixels in adjacent repeating units to share the same power connection electrode 20, this disclosure can not only effectively reduce the number of connection electrodes, reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution, but also simplify the manufacturing process, reduce production costs, and improve product yield by reducing the number of connection electrodes.

[0286] In the exemplary embodiment, the subsequent process of forming the third insulating layer, planarization layer, fourth conductive layer, pixel definition layer, organic light-emitting layer, cathode and encapsulation structure layer, as well as the resulting structure, are basically the same as in the foregoing embodiments, and will not be repeated here.

[0287] This disclosure provides a display substrate with a bottom-emitting structure. By providing active connection electrodes, adjacent sub-pixels in adjacent repeating units in the first and second directions share transition vias and connection electrodes that connect the gate metal layer to the semiconductor layer and the SHIELD layer. This effectively reduces the number of transition vias and connection electrodes, thereby reducing the area occupied by the pixel driving circuit, increasing the pixel aperture ratio, and improving the display resolution. Furthermore, reducing the number of transition vias and connection electrodes simplifies the manufacturing process, reduces production costs, and improves product yield.

[0288] The embodiments disclosed herein also demonstrate that the substrate has the technical effects of reducing the number of patterning processes, reducing the number of scanning signal lines, and increasing the pixel aperture ratio.

[0289] Figure 17 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of four repeating units (sixteen sub-pixels) in a bottom-emitting display substrate. In the exemplary embodiment, the main structure of the display substrate in this embodiment is basically the same as that in the previous embodiment, except that the first region of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y is not connected, and the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X and the second direction Y are connected to each other.

[0290] In the exemplary embodiment, the structures of the scan signal line 30, the first power supply line 51, the data signal line 52, the compensation signal line 53, the storage capacitor 60, the first transistor T1, the second transistor T2, and the third transistor T3 are basically the same as those in the previous embodiment, and will not be described again here.

[0291] In an exemplary embodiment, in at least one repeating unit, the first regions of the second active layer 22 of two adjacent sub-pixels in two repeating units adjacent in the second direction Y are not connected, and the first power line 51 is connected to the first region of the second active layer 22 in each sub-pixel through the power connection electrode 20.

[0292] In an exemplary embodiment, the power connection electrode 20 can be a strip shape extending along the first direction X. The first end of the power connection electrode 20 is connected to the first power line 51 through a power via K1, and the second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through an active via K2.

[0293] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same power via K1, and two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same power via K1.

[0294] In an exemplary embodiment, four adjacent sub-pixels in repeating units adjacent in the first direction X and the second direction Y share the same power via K1. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share the same power via K1.

[0295] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. As another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0296] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure that is interconnected.

[0297] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are connected to each other. For example, the first ends of the power connection electrodes 20 of the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 are connected to each other. As another example, the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 are connected to each other.

[0298] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two repeating units adjacent to each other in the second direction Y are an integral structure that is interconnected.

[0299] In an exemplary embodiment, the power connection electrodes 20 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y are interconnected as a single structure, that is, the power connection electrodes 20 of four adjacent sub-pixels in adjacent repeating units are interconnected as a single structure. For example, the four power connection electrodes 20 of the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 are interconnected as a single structure.

[0300] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0301] (31) Forming a first conductive layer pattern, the process and the structure of the first conductive layer formed are basically the same as step (11) of the aforementioned embodiment.

[0302] (32) Forming a second conductive layer pattern, the process and the structure of the formed second conductive layer are basically the same as step (12) of the aforementioned embodiment.

[0303] (33) Forming a semiconductor layer pattern, the process and the structure of the formed semiconductor layer are basically the same as step (13) of the aforementioned embodiment, except that the second active layer 22 of each sub-pixel is set separately, that is, the first region of the second active layer 22 of adjacent sub-pixels is not connected, such as Figure 18A and Figure 18B As shown, Figure 18B for Figure 18A A schematic diagram of the semiconductor layer.

[0304] In an exemplary embodiment, the orthographic projection of the second region and the channel region of the second active layer 22 of each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the third connection electrode 13 onto the substrate, so that the third connection electrode 13, as a shielding layer, can shield the channel region of the second transistor T2, prevent light from affecting the channel, and ensure the electrical performance of the second transistor T2.

[0305] In an exemplary embodiment, the first region of the second active layer 22 is set separately in each sub-pixel, meaning that the first regions of the second active layer 22 are not connected in adjacent sub-pixels. In at least one sub-pixel, the distance between the first region of the second active layer 22 and the first power line 51 can be less than the distance between the second region of the second active layer 22 and the first power line 51, that is, the first region of the second active layer 22 is closer to the first power line 51 than the second region of the second active layer 22.

[0306] In an exemplary embodiment, the widths of the second active layers in adjacent sub-pixels along the first direction X are different, and the widths of the second active layers in adjacent sub-pixels along the second direction Y are also different. Along the first direction X, multiple larger-width second active layers and multiple smaller-width second active layers are alternately arranged, and along the second direction Y, multiple larger-width second active layers and multiple smaller-width second active layers are alternately arranged.

[0307] In an exemplary embodiment, a first sub-pixel P1 and a second sub-pixel P2 are alternately arranged in the first direction X. The first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the second width L2 of the second active layer 22 in the second sub-pixel P2. A third sub-pixel P3 and a fourth sub-pixel P4 are alternately arranged in the first direction X. The third width L3 of the second active layer 22 in the third sub-pixel P3 can be less than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0308] In an exemplary embodiment, a first sub-pixel P1 and a third sub-pixel P3 are alternately arranged in the second direction Y. The first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3. A second sub-pixel P2 and a fourth sub-pixel P4 are alternately arranged in the second direction Y. The second width L2 of the second active layer 22 in the second sub-pixel P2 can be less than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0309] In an exemplary embodiment, the widths of the second active layer 22 of the four sub-pixels in at least one repeating unit may be different. For example, the first width L1 of the second active layer 22 in the first sub-pixel P1 may be greater than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4. Similarly, the second width L2 of the second active layer 22 in the second sub-pixel P2 may be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3.

[0310] In an exemplary embodiment, this disclosure, by alternately setting a second active layer with a larger width and a second active layer with a smaller width in the first direction X and the second direction Y, can not only effectively match the requirements of a single scan signal line structure, but also effectively increase the uniformity of the layout of the four pixel driving circuits in the repeating unit, and effectively increase the uniformity of the pixel openings of the four sub-pixels in the repeating unit.

[0311] (34) Forming the second insulating layer pattern, the process and the structure of the formed second insulating layer are basically the same as step (14) of the aforementioned embodiment, except that the second via V2 of each sub-pixel is set separately, that is, adjacent sub-pixels do not share the second via V2, such as Figure 19 As shown.

[0312] In an exemplary embodiment, a plurality of vias are provided on the second insulating layer, and the plurality of vias of each sub-pixel in each repeating unit include at least the first via V1 to the seventh via V7, and the structure of the vias is substantially the same as that in the foregoing embodiment.

[0313] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same seventh via V7, and two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same seventh via V7.

[0314] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same seventh via V7, that is, four adjacent sub-pixels in adjacent repeating units share the same seventh via V7.

[0315] (35) Forming the third conductive layer pattern, the process and the structure of the formed third conductive layer are basically the same as step (15) of the aforementioned embodiment, except that the power connection electrode 20 is connected to the first region of the second active layer 22 of the two sub-pixels simultaneously through the second vias V2 of the two sub-pixels, as shown in the figure. Figure 20A and Figure 20B As shown, Figure 20B for Figure 20A A schematic diagram of the third conductive layer.

[0316] In an exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a power connection electrode 20, a scan signal line 30, a first gate electrode 31, a second gate electrode 32, and a third gate electrode 33. Except for the power connection electrode 20, the other structures are basically the same as those in the foregoing embodiments.

[0317] In an exemplary embodiment, the power connection electrode 20 can be a strip shape extending along the first direction X. The first end of the power connection electrode 20 is connected to the first power line 51 through the seventh via V7, and the second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through the second via V2. Thus, the first power line 51 writes the first power signal into the first electrode of the second transistor T2.

[0318] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X can be connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. As another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0319] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure that is interconnected.

[0320] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two repeating units adjacent in the second direction Y can be connected to each other. For example, for a first repeating unit Q1 and a third repeating unit Q3 adjacent in the second direction Y, the first ends of the power connection electrodes 20 of the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can be connected to each other, and the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can be connected to each other. Similarly, for a second repeating unit Q2 and a fourth repeating unit Q4 adjacent in the second direction Y, the first ends of the power connection electrodes 20 of the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can be connected to each other, and the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can be connected to each other.

[0321] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two repeating units adjacent to each other in the second direction Y are an integral structure that is interconnected.

[0322] In an exemplary embodiment, the power connection electrodes 20 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y are interconnected as a single structure, that is, the power connection electrodes 20 of four adjacent sub-pixels in adjacent repeating units are interconnected as a single structure. For example, the power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 are interconnected as a single structure. By setting the power connection electrodes 20 of four adjacent sub-pixels in adjacent repeating units as an interconnected single structure, this disclosure can not only effectively reduce the number of vias and the area occupied by the pixel driving circuit, but also increase the pixel aperture ratio and improve the display resolution. Furthermore, reducing vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0323] In the exemplary embodiment, the subsequent process of forming the third insulating layer, planarization layer, fourth conductive layer, pixel definition layer, organic light-emitting layer, cathode and encapsulation structure layer, as well as the resulting structure, are basically the same as in the foregoing embodiments, and will not be repeated here.

[0324] This disclosure provides a display substrate with a bottom-emitting structure. In a first direction, the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units are interconnected in a single, integrated structure. Similarly, in a second direction, the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units are interconnected in a single, integrated structure. This effectively reduces the number of vias, thereby reducing the area occupied by the pixel driving circuit, increasing the pixel aperture ratio, and improving display resolution. Furthermore, reducing the number of vias simplifies the manufacturing process, lowers production costs, and improves product yield.

[0325] The embodiments disclosed herein also demonstrate that the substrate has the technical effects of reducing the number of patterning processes, reducing the number of scanning signal lines, and increasing the pixel aperture ratio.

[0326] The structure and its preparation process shown in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs. This disclosure does not limit these aspects.

[0327] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0328] This exemplary embodiment also provides a method for fabricating a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of repeating units, at least one repeating unit including a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the fabrication method includes: A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit being connected to a first power line configured to provide a first power signal to the pixel driving circuit; the pixel driving circuit includes at least a driving transistor and a power connection electrode, the driving transistor including at least a driving active layer; in at least one sub-pixel, a first end of the power connection electrode is connected to the first power line through a power via, and a second end of the power connection electrode is connected to a first region of the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

[0329] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0330] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit, a scan signal line extending along a first direction of a main body portion, a first power line extending along a second direction of a main body portion, and two data signal lines extending along the second direction of a main body portion, wherein the first power line and the two data signal lines are arranged sequentially along the first direction, the first direction intersecting the second direction, the pixel driving circuit being connected to the first power line, and the first power line being configured to provide a first power signal to the pixel driving circuit; The pixel driving circuit includes at least a driving transistor and a power connection electrode. The driving transistor includes at least a second gate electrode and a second active layer. The second gate electrode extends along the second direction. In at least one sub-pixel, the first end of the power connection electrode is connected to the first power line through a power via, and the second end of the power connection electrode crosses the two data signal lines and is connected to the first region of the second active layer through an active via. The second gate electrode and the power connection electrode are located in the same conductive layer.

2. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a storage capacitor, which includes a first electrode plate and a second electrode plate, wherein the orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. In at least one sub-pixel, the second gate electrode is connected to the second electrode plate through a sixth via.

3. The display substrate according to claim 2, wherein, In at least one sub-pixel, the orthographic projection of the sixth via on the substrate lies within the range of the orthographic projection of the second electrode plate on the substrate.

4. The display substrate according to claim 2, wherein, In at least one sub-pixel, the size of the sixth via in the second direction is larger than the size of the sixth via in the first direction.

5. The display substrate according to claim 2, wherein, In at least one sub-pixel, the second gate electrode includes a first portion and a second portion, wherein the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate, and the first portion is connected to the second electrode plate through the sixth via.

6. The display substrate according to claim 5, wherein, In at least one sub-pixel, the sixth via is partially covered by the first portion.

7. The display substrate according to claim 5, wherein, In the first direction, the width of the first portion is smaller than the width of the second portion.

8. The display substrate according to claim 5, wherein, In the second direction, the length of the first part is greater than the length of the second part.

9. The display substrate according to claim 2, wherein, In at least one sub-pixel, in the second direction, the edge of the active via on the side away from the sixth via is located on the side of the second gate electrode away from the sixth via.

10. The display substrate according to claim 2, wherein, In at least one sub-pixel, in the second direction, there is a distance between the edge of the power connection electrode near the sixth via and the edge of the active via near the sixth via, the power connection electrode does not completely cover the active via, and the uncovered active via is located on the side of the power connection electrode near the sixth via.

11. The display substrate according to claim 2, wherein, At least one sub-pixel also includes a fifth connection electrode, which is connected to the second region of the second active layer through a third via, wherein the size of the third via in the first direction is larger than the size of the third via in the second direction.

12. The display substrate according to claim 2, wherein, In at least one sub-pixel, the second active layer includes at least a main body and a protrusion, the protrusion being disposed on the side of the main body away from the sixth via and connected to the main body, and the power connection electrode being connected to the protrusion through an active via.

13. The display substrate according to claim 12, wherein, In at least one sub-pixel, the protrusion has a first width in the first direction and a second width in the channel region of the second transistor in the second direction, wherein the first width is smaller than the second width.

14. The display substrate according to claim 13, wherein, The overlapping area of ​​the second gate electrode projected onto the display substrate plane and the second active layer projected onto the display substrate plane has a third width, and the first width is smaller than the third width.

15. The display substrate according to claim 2, wherein, In at least one sub-pixel, the pixel driving circuit further includes a switching transistor and a compensation transistor, the gate electrode of the switching transistor and the gate electrode of the compensation transistor being connected to the scan signal line; in the second direction, the switching transistor and the compensation transistor are disposed on the side of the second plate close to the scan signal line, and the driving transistor is disposed on the side of the second plate away from the scan signal line.

16. The display substrate according to any one of claims 1 to 15, wherein, The plurality of sub-pixels includes a first sub-pixel and a second sub-pixel arranged periodically along the first direction. The first sub-pixel includes a first data signal line and a second data signal line. The second sub-pixel includes a third data signal line and a fourth data signal line. The two power connection electrodes in the first sub-pixel and the second sub-pixel are an integral structure that is interconnected. The orthographic projection of the two power connection electrodes of the integral structure on the display substrate plane overlaps at least partially with the orthographic projection of the first data signal line, the second data signal line, the third data signal line and the fourth data signal line on the display substrate plane.

17. The display substrate according to any one of claims 1 to 15, wherein, In at least one sub-pixel, the size of the active via in the second direction is larger than the size of the active via in the first direction.

18. The display substrate according to any one of claims 1 to 15, wherein, At least a portion of the active via near the driving transistor is not covered by the power connection electrode.

19. A display device comprising a display substrate as described in any one of claims 1 to 18.

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