A semiconductor device and a method of fabricating the same
By oxidizing the molybdenum layer between the insulating layers in a semiconductor device to form a molybdenum oxide layer, and then etching it away, the problem of uneven etching rate is solved, thereby improving the electrical performance and manufacturing yield of the device.
Patent Information
- Application Number
- CN202611131753.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-29
- Publication Date
- 2026-08-25
AI Technical Summary
In the prior art, the etching process of the molybdenum layer is subject to a depth loading effect, which leads to uneven etching rates at different depths, affecting the uniformity of the electrical performance of semiconductor devices and the manufacturing yield.
An oxidation-then-etching method is used to oxidize the molybdenum layer between the insulating layers to form a molybdenum oxide layer, which is then etched away to ensure that the molybdenum layers at different depths have equal or approximately equal lateral etching distances.
This solves the problem of uneven etching rates, improves the consistency of electrical performance and manufacturing yield of semiconductor devices, and avoids etching lag in deep areas and over-etching in surface areas.
Smart Images
Figure CN122641273A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor device and a method for preparing the same. Background Technology
[0002] Molybdenum, due to its low resistivity, high filling capacity, and excellent chemical stability, plays a crucial role in the metal wiring and interconnect structures of semiconductor devices such as advanced logic chips and 3D NAND flash memory, and is gradually replacing traditional tungsten materials. In existing semiconductor manufacturing processes, patterning of molybdenum primarily employs wet etching or dry etching techniques. Wet etching typically relies on chemical solutions such as phosphate groups for reaction, while dry etching often utilizes plasma equipment to bombard and remove molybdenum through specific gas combinations. For complex structures containing alternating layers of dielectric and molybdenum, current technologies typically involve directly introducing etching gases or using chemical solutions to contact the exposed metal surface to achieve pattern transfer and structure shaping.
[0003] However, in existing technologies, as the feature size of semiconductor devices shrinks and the aspect ratio of trenches increases, inconsistent etching rates between upper and lower layers (also known as depth loading) can easily occur during the etching of the molybdenum layer. Particularly in stacked structures with high aspect ratio trenches, limited gas transport and differences in reaction kinetics lead to significant deviations in the removal rates of the molybdenum layer between the deep and surface regions, thus affecting the uniformity of the device's electrical performance and overall manufacturing yield. Summary of the Invention
[0004] In view of the above problems, this application provides a semiconductor device and a method for fabricating the same, the specific solution of which is as follows:
[0005] The first aspect of this application provides a method for fabricating a semiconductor device, comprising:
[0006] A semiconductor structure is provided, comprising a semiconductor substrate and a stacked structure located on one side surface of the semiconductor substrate; the stacked structure comprises multiple layers of molybdenum metal stacked sequentially along the thickness direction of the semiconductor substrate; an insulating layer is provided between the semiconductor substrate and adjacent molybdenum metal layers, and between adjacent molybdenum metal layers; wherein the semiconductor structure has a trench penetrating the stacked structure; the molybdenum metal layer at the top of the stacked structure also covers the sidewalls of the trench.
[0007] Remove the molybdenum layer from the top of the laminated structure and the sidewalls of the trench;
[0008] By introducing an oxidizing gas into the trench, the molybdenum metal layer between the insulating layers is oxidized to form a molybdenum oxide layer. After the molybdenum oxide layer is formed, it is etched away to ensure that there is a set lateral etching distance between the molybdenum metal layer between adjacent insulating layers and the trench sidewall. Under the set oxidation conditions, the molybdenum metal layer between adjacent insulating layers is oxidized to ensure that the lateral etching distances corresponding to different molybdenum metal layers meet the condition of equality.
[0009] Optionally, in the above preparation method, after oxidizing the molybdenum layer between the insulating layers by introducing an oxidizing gas into the trench to form a molybdenum oxide layer, the molybdenum oxide layer is removed, including:
[0010] The molybdenum metal layer located between the insulating layers is etched away through multiple etching stages. Each etching stage includes: oxidizing the molybdenum metal layer under set oxidation conditions, and then etching away the molybdenum oxide layer formed by the oxidation process. The sum of the lateral etching removal amounts of the molybdenum metal layer by the multiple etching stages is the lateral etching distance.
[0011] Optionally, in the above preparation method, the oxidation conditions include:
[0012] The oxidation time for the oxidation treatment shall not be less than 70 seconds;
[0013] During the oxidation process, the pressure in the reaction chamber shall not be less than 8 Torr;
[0014] During the oxidation process, the flow rate of the oxidizing gas shall not be less than 1250 sccm.
[0015] Optionally, in the above preparation method, the oxidation time does not exceed 100 s;
[0016] The cavity pressure should not exceed 15 Torr;
[0017] The flow rate of oxidizing gas shall not exceed 3250 sccm.
[0018] Optionally, in the above preparation method, the chamber pressure and the flow rate of the oxidizing gas are constant during the same etching stage.
[0019] Optionally, in the above preparation method, the oxidation time of the multiple etching stages increases sequentially, the chamber pressure of the reaction chamber increases sequentially, and the flow rate of the oxidizing gas increases sequentially.
[0020] Optionally, in the above preparation method, the condition that the lateral etching distances are equal includes: the difference between the lateral etching distances of each molybdenum layer located between the insulating layers and the target etching size does not exceed 3 nm.
[0021] Optionally, in the above preparation method, removing the molybdenum layer on the top of the laminated structure and the sidewalls of the trench includes:
[0022] The metallic molybdenum layer on the top of the stacked structure and the sidewalls of the trench is oxidized to a molybdenum oxide layer, and then the molybdenum oxide layer is removed.
[0023] A second aspect of this application provides a semiconductor device prepared by any of the above-described methods, comprising:
[0024] A semiconductor structure includes a semiconductor substrate and a stacked structure located on one side surface of the semiconductor substrate; along the thickness direction of the semiconductor substrate, the stacked structure includes multiple layers of molybdenum metal stacked sequentially; an insulating layer is provided between the semiconductor substrate and adjacent molybdenum metal layers, and between adjacent molybdenum metal layers.
[0025] A trench that penetrates the stacked structure;
[0026] There is a lateral etching distance between the molybdenum layer between adjacent insulating layers and the sidewall of the trench, and the lateral etching distances corresponding to different molybdenum layers satisfy the condition of equality.
[0027] Optionally, in the above-mentioned semiconductor device, the thickness of each molybdenum layer increases sequentially in the direction from the opening of the trench to the bottom of the trench.
[0028] In the semiconductor device fabrication method described in this application, when removing the molybdenum layer between insulating layers in a stacked structure, the molybdenum layer between the insulating layers is first oxidized to form a molybdenum oxide layer, and then the molybdenum oxide layer is etched away. Based on the high correlation between the thickness of the molybdenum oxide layer and the subsequent etching rate, this controlled oxidation-then-etching mechanism ensures that molybdenum layers at different depths in the trench can form molybdenum oxide layers that meet the etching requirements. The molybdenum oxide layers formed from different molybdenum layers can achieve a consistent removal rate in the subsequent etching process, allowing the molybdenum layers between the insulating layers to form equal or approximately equal lateral etching distances.
[0029] The semiconductor device formed by this preparation method effectively solves the problems of uneven etching rate of molybdenum layer at different depths of trench and uneven lateral etching distance in traditional processes. It avoids the problems of lag etching of molybdenum layer in deep trench area and over-etching of molybdenum layer in trench surface area, thereby improving the consistency of electrical performance and overall manufacturing yield of semiconductor device. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0031] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.
[0032] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;
[0033] Figures 2-15 A schematic diagram of the device structure at different process stages of a semiconductor device fabrication method provided in this application embodiment;
[0034] Figure 16 A schematic diagram illustrating the principle of etching and removing a molybdenum layer for the implementation of this application;
[0035] Figure 17 A graph showing oxidation time versus molybdenum oxide layer thickness and etching rate provided for embodiments of this application;
[0036] Figure 18 This is a schematic diagram illustrating the relationship between the etching rate of a molybdenum metal layer and the thickness of a molybdenum oxide layer, provided in an embodiment of this application.
[0037] Figure 19 A schematic diagram illustrating the relationship between the etching rate of a molybdenum metal layer and the thickness of a molybdenum oxide layer, provided as an embodiment of this application.
[0038] Figure 20 A schematic diagram illustrating the relationship between gas flow rate and the thickness of the molybdenum oxide layer and the etching rate of the metallic molybdenum layer, provided in an embodiment of this application;
[0039] Figure 21 A schematic diagram illustrating the relationship between cavity pressure and the etching rate of the molybdenum layer is provided for an embodiment of this application.
[0040] Figure 22 This is a graph showing the relationship between the spacing between the upper and lower substrates inside the cavity and the etching rate of the molybdenum layer.
[0041] Figure 23A schematic diagram illustrating the relationship between oxidation time, etching deviation, and etching rate, provided for embodiments of this application;
[0042] Figure 24 This is a morphology diagram of the device when the molybdenum layer is unsaturated with oxidation.
[0043] Figure 25 This is a topographic image of the device after etching away the molybdenum oxide layer under unsaturated oxidation conditions.
[0044] The annotations in the attached figures are explained as follows:
[0045] 100 Semiconductor substrate; 101 Stacked structure; 102 Insulating layer; 103 Sacrificial layer; 1031 Top sacrificial layer; 1032 Bottom sacrificial layer; 104 Trench; 105 Gap; 106 Molybdenum layer; 1061 Top molybdenum layer; 1062 Bottom molybdenum layer; 107 Molybdenum oxide layer; d Lateral etching removal amount; D Lateral etching distance; 108 Semiconductor material. Detailed Implementation
[0046] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.
[0047] Molybdenum (Mo) is gradually replacing traditional tungsten (W) due to its low resistivity and high filler capacity, playing a crucial role in the metal wiring and interconnect structures of logic chips and 3D NAND. Furthermore, molybdenum is commonly used in multilayer structures such as Mo / Al / Mo / MoOx, especially in optoelectronic devices and integrated circuits, where it is also used in stacked metal films to optimize conductivity and corrosion resistance.
[0048] The key advantages of molybdenum in semiconductor devices include:
[0049] Low resistivity: Molybdenum has a significantly lower resistivity than tungsten, making it suitable for high-density integrated circuits, reducing signal delay and power consumption;
[0050] High fill capacity: Atomic layer deposition (ALD) technology enables uniform deposition of molybdenum in trenches with high aspect ratios, meeting the requirements of advanced processes;
[0051] Chemical stability: Molybdenum has strong resistance to oxidation and corrosion, making it suitable for complex process environments.
[0052] Conventional etching techniques for molybdenum mainly include wet etching, dry etching, and composite layer processing. Wet etching suffers from uneven etching rates and insufficient etching precision. Traditional etching solutions exhibit significant differences in etching rates for different metal layers (such as Mo and Al), resulting in low yields for multilayer structures. Furthermore, wet etching often requires strong acids (such as nitric acid and phosphoric acid), generating harmful waste liquids that contradict green manufacturing trends and cause environmental problems. Moreover, it easily leaves impurities or rough surfaces after etching, requiring additional polishing steps and causing surface quality issues. Dry etching can achieve high-precision 3D structure processing using plasma etching equipment, but the equipment is expensive and the process is complex. Composite layer processing technology, specifically for multilayer structures such as Mo / Al, requires the development of multi-metal compatible etching solutions. Current research on dry etching technology for molybdenum in semiconductors focuses on combining plasma etching with ALD technology to optimize etching selectivity and uniformity, achieving nanometer-level precision suitable for 4F layers. 2 DRAM and advanced logic chips.
[0053] In conventional etching methods, dry etching of molybdenum layers in multilayer structures typically involves directly etching the metal film using an etching gas. However, due to limited gas transport and differences in reaction kinetics, the etching capability of the etching gas is affected by the trench depth in the multilayer structure. Near the top of the trench, the molybdenum layer is etched at a faster rate, while near the bottom, the rate is slower, resulting in a significant difference in the removal rate of the molybdenum layer between the deeper and surface regions.
[0054] In view of this, embodiments of this application provide a method for fabricating a semiconductor device, comprising:
[0055] A semiconductor structure is provided, comprising a semiconductor substrate and a stacked structure located on one side surface of the semiconductor substrate; the stacked structure comprises multiple layers of molybdenum metal stacked sequentially along the thickness direction of the semiconductor substrate; an insulating layer is provided between the semiconductor substrate and adjacent molybdenum metal layers, and between adjacent molybdenum metal layers; wherein the semiconductor structure has a trench penetrating the stacked structure; the molybdenum metal layer at the top of the stacked structure also covers the sidewalls of the trench.
[0056] Remove the molybdenum layer from the top of the laminated structure and the sidewalls of the trench;
[0057] By introducing an oxidizing gas into the trench, the molybdenum metal layer between the insulating layers is oxidized to form a molybdenum oxide layer. After the molybdenum oxide layer is formed, it is etched away to ensure that there is a set lateral etching distance between the molybdenum metal layer between adjacent insulating layers and the trench sidewall. Under the set oxidation conditions, the molybdenum metal layer between adjacent insulating layers is oxidized to ensure that the lateral etching distances corresponding to different molybdenum metal layers meet the condition of equality.
[0058] In the semiconductor device fabrication method provided in this application, when removing the molybdenum layer between insulating layers in a stacked structure, the molybdenum layer between the insulating layers is first oxidized to form a molybdenum oxide layer, and then etched away. Based on the high correlation between the thickness of the molybdenum oxide layer and the subsequent etching rate, this controlled oxidation-then-etching mechanism ensures that molybdenum layers at different depths in the trench can form molybdenum oxide layers that meet etching requirements. The molybdenum oxide layers formed from different molybdenum layers can achieve a consistent removal rate in the subsequent etching process, allowing the molybdenum layers between insulating layers to form equal or approximately equal lateral etching distances. The semiconductor device fabricated using this method effectively solves the problems of uneven etching rates and uneven lateral etching distances of molybdenum layers at different depths in the trench in traditional processes. It avoids etching lag in the deep trench regions and over-etching of the molybdenum layer in the trench surface regions, improving the consistency of the electrical performance of the semiconductor device and the overall manufacturing yield.
[0059] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments described in this application are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The terminology used in the embodiments of this application is only used to explain the specific embodiments of this application and is not intended to limit this application.
[0060] refer to Figures 1-15 , Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figures 2-15 This application provides a method for fabricating a semiconductor device, illustrating the device structure at different process stages. The method includes:
[0061] Step S11: As Figures 2-5 A semiconductor structure is provided, comprising a semiconductor substrate 100 and a stacked structure 101 located on one side surface of the semiconductor substrate 100; along the thickness direction of the semiconductor substrate 100, the stacked structure 101 comprises multiple layers of molybdenum metal layers 106 stacked sequentially; an insulating layer 102 is provided between the semiconductor substrate 100 and adjacent molybdenum metal layers 106 (bottom molybdenum metal layer 1062), and between adjacent molybdenum metal layers 106; wherein, the semiconductor structure has a trench 104 penetrating the stacked structure 101; the top molybdenum metal layer 106 of the stacked structure 101 also covers the sidewalls of the trench 104.
[0062] In step S11, as Figures 2-5As shown, the method for fabricating a semiconductor structure may include:
[0063] First, such as Figure 2 As shown, multiple layers of sacrificial layers 103 are formed sequentially on the surface of the semiconductor substrate 100. An insulating layer 102 is present between adjacent sacrificial layers 103 and between the semiconductor substrate 100 and adjacent sacrificial layers 103 (bottom sacrificial layer 1032). The alternating arrangement of sacrificial layers 103 and insulating layers 102 constitutes a stacked structure 101. In this case, the upper surface of the stacked structure 101 can be the top sacrificial layer 1031.
[0064] Then, as Figure 3 As shown, a trench 104 is formed through the stacked structure 101, the trench 104 extends from the top sacrificial layer 1031 to the semiconductor substrate 100, and the bottom of the trench 104 exposes the semiconductor substrate 100.
[0065] Furthermore, such as Figure 4 As shown, based on the trench 104, each sacrificial layer 103 is etched away. After the sacrificial layer 103 is removed, a gap 105 is formed between adjacent insulating layers 102.
[0066] Furthermore, such as Figure 5 As shown, a molybdenum layer 106 is formed. In this embodiment, the molybdenum layer 106 can be filled into each gap 105 using a deposition or sputtering process. The top molybdenum layer 1061 covers the uppermost insulating layer 102 and the sidewalls of the trench 104, forming a layer as shown. Figure 5 The semiconductor structure shown.
[0067] Step S12: As Figure 6 and Figure 7 As shown, the molybdenum layer 106 on the top of the stacked structure 101 and the sidewall of the trench 104 is removed.
[0068] In step S12, it is possible to first... Figure 6 As shown, the top molybdenum layer 1061 covering the uppermost insulating layer 102 and the sidewalls of the trench 104 is oxidized to a molybdenum oxide layer 107. Then, as... Figure 7 As shown, the molybdenum oxide layer 107 is etched away. This process can be divided into multiple etching stages to remove the top metallic molybdenum layer 1061. Each etching stage first oxidizes a portion of the metallic molybdenum layer 106, and then removes the molybdenum oxide layer 107.
[0069] Step S13: As Figures 8-13As shown, based on the introduction of oxidizing gas into the trench 104, the molybdenum layer 106 between the insulating layers 102 is oxidized to form a molybdenum oxide layer 107. Then, the molybdenum oxide layer 107 is etched away to ensure that there is a set lateral etching distance between the molybdenum layer 106 between adjacent insulating layers 102 and the sidewall of the trench 104. Under the set oxidation conditions, the molybdenum layer 106 between adjacent insulating layers 102 is oxidized to ensure that the lateral etching distances corresponding to different molybdenum layers 106 meet the condition of equality.
[0070] This application first oxidizes the molybdenum metal layer 106 into a molybdenum oxide layer 107, and then etches away the molybdenum oxide layer 107 to achieve the etching removal of the molybdenum metal layer 106. By precisely setting the oxidation conditions, the lateral distance of the etching removal of the molybdenum metal layer 106 can be precisely controlled, so that each layer of molybdenum metal layer 106 located between the insulating layers 102 has an equal or approximately equal lateral etching distance.
[0071] In step S13, after oxidizing the molybdenum layer 106 between the insulating layers 102 to form a molybdenum oxide layer 107 by introducing an oxidizing gas through the trench 104, the molybdenum oxide layer 107 is removed. This includes etching the molybdenum layer 106 between the insulating layers 102 through multiple etching stages. Each etching stage includes oxidizing the molybdenum layer 106 under set oxidation conditions, followed by etching to remove the molybdenum oxide layer 107 formed by the oxidation process. The sum of the lateral etching removal amounts d of the molybdenum layer 106 in the multiple etching stages is the lateral etching distance D. In this method, each layer of molybdenum layer 106 between the insulating layers 102 is etched through multiple etching stages to form the required lateral etching distance D. Figures 8-13 The method shown is illustrated using three etching stages as an example.
[0072] In the first etching stage, firstly as... Figure 8 As shown, the molybdenum metal layers 106 located between the insulating layers 102 undergo a first oxidation treatment, and then as follows: Figure 9 As shown, the molybdenum oxide layer 107 formed by the first oxidation treatment is removed by etching.
[0073] In the second etching stage, firstly as Figure 10 As shown, the molybdenum metal layers 106 located between the insulating layers 102 undergo a second oxidation treatment, and then as follows: Figure 11 As shown, the molybdenum oxide layer 107 formed by the second oxidation process is removed by etching.
[0074] In the third etching stage, firstly as Figure 12 As shown, the molybdenum metal layers 106 located between the insulating layers 102 undergo a third oxidation treatment, and then as follows: Figure 13As shown, the molybdenum oxide layer 107 formed by the third oxidation process is removed by etching.
[0075] It should be noted that, in this embodiment, the number of etching stages in the entire etching process of the molybdenum layer 106 can be set according to the required lateral etching distance D and the oxidation depth of the molybdenum layer 106 in a single etching stage, and is not limited to... Figures 8-13 The three etching stages are shown.
[0076] In this embodiment, the molybdenum metal layer 106 located between the insulating layers 102 is etched away in multiple etching stages. The lateral oxidation size of the molybdenum metal layer 106 in each etching stage can be precisely controlled by a set oxidation adjustment. Thus, in the same etching stage, the molybdenum metal layers 106 at different depths have equal or approximately equal lateral oxidation sizes. When the molybdenum oxide layer 107 formed in the etching stage is completely removed, the lateral etching removal amount d of each molybdenum metal layer 106 is equal or approximately equal. Therefore, after multiple etching stages, the sum of the lateral etching removal amount d of each molybdenum metal layer 106 in all etching stages (i.e., the lateral etching distance D) is equal or approximately equal.
[0077] Optionally, the thickness of the molybdenum layer 106 can be 20nm to 40nm, specifically, the thickness of the molybdenum layer 106 is 26nm.
[0078] In some embodiments of this application, the preparation method further includes: Figure 14 and Figure 15 As shown, semiconductor material 108 is filled within the gaps 105 formed by the lateral etching distance D corresponding to each molybdenum layer 106. In this method, firstly, as... Figure 14 As shown, semiconductor material 108 is deposited on the stacked structure 101. The semiconductor material 108 fills the gaps 105 formed by the lateral etching distance D and also covers the sidewalls of the trench 104 and the uppermost insulating layer 102; then, as... Figure 15 As shown, the semiconductor material 108 covering the sidewalls of the trench 104 and the uppermost insulating layer 102 is removed, leaving the semiconductor material 108 within the gap 105. The semiconductor material 108 can serve as the channel layer of a semiconductor device. Optionally, the semiconductor material 108 can be a semiconductor material such as SiGe; however, this embodiment does not limit the semiconductor material 108 used.
[0079] refer to Figure 16 , Figure 16 A schematic diagram illustrating the principle of etching removal of a molybdenum layer 106 provided for the implementation of this application. In one etching stage, the etching removal process of the molybdenum layer 106 includes:
[0080] First, a portion of the metallic molybdenum is oxidized using an oxidizing gas (such as O2) to form a molybdenum oxide layer 107 (MoO2 / MoO3). The reaction equation for this step is:
[0081] nMo + O2 → MoO2 / MoO3;
[0082] Then, a specific etching gas (such as WF6) reacts with the formed MoO2 / MoO3 to generate volatile byproducts, which are then discharged from the cavity. This step converts the generated MoO2 / MoO3 into gaseous substances (such as MoF6), thereby achieving material removal. The reaction equation is:
[0083] MoO3+WF6→MoF6+WO3F2;
[0084] Finally, residual byproducts were further removed by purging with BCl3. The reaction equation for this step is:
[0085] WO3F2+ BCl3→MoCl x +BOCl x / BOF x .
[0086] When etching the molybdenum layer 106 located between the insulating layers 102, if the molybdenum is directly etched away, gas transport is restricted due to the different depth positions of each molybdenum layer 106 in the stacked structure 101 corresponding to the trench 104. This results in differences in reaction kinetics and different etching rates for the molybdenum layers 106. The molybdenum layer 106 near the top of the trench 104 has a higher etching rate, while the molybdenum layer 106 near the bottom of the trench 104 has a lower etching rate. This leads to significant differences in the lateral etching distance D of each molybdenum layer 106. The lateral etching distance D of each molybdenum layer 106 increases from the bottom to the top of the trench 104, which in turn affects the uniformity of the electrical performance of the device and the overall manufacturing yield.
[0087] The inventors discovered that for a given semiconductor structure, with a fixed thickness for each film layer, the lateral oxidation size of the molybdenum layer 106 located between the insulating layers 102 in an etching stage (equal to the lateral etching removal amount d of the molybdenum layer 106 in that etching stage) has a maximum value. This is because the oxidizing gas needs to oxidize the molybdenum layer 106 between the insulating layers 102 based on the trench 104, and the resulting molybdenum oxide layer 107 isolates the oxidizing gas from the molybdenum layer 106 located between the insulating layers 102. In the same oxidation stage, as the lateral oxidation size increases, the molybdenum oxide layer 107 acts as a barrier to oxidation, and the larger the lateral oxidation size, the stronger the barrier effect. When the lateral oxidation size reaches a maximum value, the molybdenum oxide layer 107 will completely block the reaction between the oxidizing gas and the molybdenum layer 106. Based on this characteristic, in some embodiments of the technical solution of this application, in each etching stage, when the molybdenum layers 106 located between the insulating layers 102 are oxidized under the set oxidation conditions, the lateral oxidation size of each molybdenum layer 106 reaches its maximum value. The horizontal direction is perpendicular to the depth direction of the trench 104, and the vertical direction is parallel to the depth direction of the trench 104.
[0088] In each etching stage, when the molybdenum metal layers 106 located between the insulating layers 102 are oxidized under the set oxidation conditions, the lateral oxidation size of each molybdenum metal layer 106 reaches its maximum value. Thus, in the same etching stage, even if there are differences in the oxidation rate of the molybdenum metal layers 106 at different depths of the corresponding grooves, the final lateral oxidation size of each molybdenum metal layer 106 is the same. After completely removing the molybdenum oxide layers 107 formed by each molybdenum metal layer 106, the lateral etching removal amount d of each molybdenum metal layer 106 in this etching stage is the same. Furthermore, since the molybdenum metal layer 106 is converted into a molybdenum oxide layer 107 for etching removal, the etching gas acts on the molybdenum oxide layer 107 in the same etching stage. When the molybdenum oxide layer 107 is completely etched away, the unoxidized molybdenum metal layer 106 will not be etched away. Therefore, the lateral etching removal amount d in the same etching stage can be precisely controlled by the lateral oxidation size. Over-etching will not affect the lateral etching removal amount d, and it can be ensured that the final lateral etching distance D of each molybdenum metal layer 106 meets the same conditions.
[0089] In this embodiment, the oxidation conditions include: an oxidation time of not less than 70 seconds; a chamber pressure of not less than 8 Torr during the oxidation process; and a flow rate of not less than 1250 sccm during the oxidation process. When these oxidation conditions are met, during the oxidation of the molybdenum layer 106, in the same etching stage, each molybdenum layer 106 located between the insulating layers 102 can form a molybdenum layer 106 with the largest lateral oxidation size, so that the molybdenum layers 106 at different depths of the trench 104 can form equal or approximately equal lateral etching removal amounts d in the same etching stage.
[0090] Optionally, the oxidation time should not exceed 100s; the chamber pressure should not exceed 15Torr; and the flow rate of the oxidizing gas should not exceed 3250sccm. When the oxidation time is 70s~100s, the chamber pressure is 8Torr~15Torr, and the flow rate of the oxidizing gas is 1250sccm~3250sccm, the molybdenum metal layers 106 between the insulating layers 102 can be fully oxidized to achieve the maximum lateral oxidation size, and the process parameter requirements during the oxidation process can also be reduced.
[0091] In the semiconductor device fabrication method provided in this application embodiment, the chamber pressure and oxidizing gas flow rate are constant during the same etching stage. Maintaining constant chamber pressure and oxidizing gas flow rate during the same etching stage ensures the stability of the chamber reaction environment, preventing fluctuations in the reaction environment from affecting the oxidation effect and lateral etching removal amount d of each molybdenum layer 106. This allows for a more consistent lateral etching removal amount d for each molybdenum layer 106 during the same etching stage.
[0092] In the semiconductor device fabrication method provided in this application embodiment, the oxidation time of multiple etching stages increases sequentially, the chamber pressure of the reaction chamber increases sequentially, and the flow rate of the oxidizing gas increases sequentially. For example... Figure 8 , Figure 10 and Figure 12 As shown, compared to the previous etching stage, the lateral oxidation depth of the subsequent etching stage increases. The oxidizing gas needs to travel a greater lateral distance in the gap 105 between the two insulating layers 102 to oxidize the molybdenum layer 106. By setting the oxidation time, chamber pressure, and flow rate of the oxidizing gas in each etching stage to increase the gradient, the problem of insufficient oxidation in the subsequent etching stage caused by the difference in lateral oxidation depth can be avoided. This ensures that the molybdenum layer 106 can achieve the maximum lateral oxidation size in each etching stage, thereby ensuring that each metal layer has an equal or approximately equal lateral etching distance D.
[0093] Optionally, the lateral etching distance D satisfies the condition that the difference between the lateral etching distance D of each molybdenum layer 106 located between the insulating layers 102 and the target etching size (this difference is the etching deviation mentioned below) does not exceed 3 nm. For example, when the target etching size is 90 nm, the lateral etching distance D of each molybdenum layer 106 located between the insulating layers 102 is 90 nm ± 3 nm. For semiconductor devices with defined design parameters, the target etching size required for the molybdenum layer 106 located between the insulating layers 102 is a pre-set known process parameter. This target etching size can be set according to the design parameters of the required semiconductor device, and this embodiment does not limit this.
[0094] In the semiconductor device fabrication method provided in this application embodiment, removing the metal molybdenum layer 106 on the top of the stacked structure 101 and the sidewall of the trench 104 includes: oxidizing the metal molybdenum layer 106 on the top of the stacked structure 101 and the sidewall of the trench 104 into a molybdenum oxide layer 107, and removing the molybdenum oxide layer 107. Similar to the method of etching away the molybdenum layer 106 between the insulating layers 102, when removing the molybdenum layer 106 on the top of the stacked structure 101 and the sidewall of the trench 104, the molybdenum layer 106 is first oxidized to a molybdenum oxide layer 107, and then the molybdenum oxide layer 107 is etched away. This allows for precise control of the etching thickness and precise etching away of the molybdenum layer 106 covering the sidewall of the trench 104. This ensures that each molybdenum layer 106 between the insulating layers 102 is flush with the sidewall of the trench 104 before etching away, so that the lateral etching distance D of each molybdenum layer 106 between the insulating layers 102 can be precisely controlled to meet the condition of equality.
[0095] Under experimental conditions of 300W RF power, 350℃ cavity temperature, 10Torr cavity pressure, 2250sccm gas flow rate, and 50mm spacing between the upper and lower substrates within the cavity, experimental data analysis was conducted to investigate the factors affecting the etching rate of the molybdenum layer 106. The results demonstrate a strong correlation between the actual etching rate of the molybdenum layer 106 and the resulting molybdenum oxide layer 107. Therefore, in scenarios involving the etching of metal layers in the stacked structure 101, the present application's technical solution can optimize oxidation conditions by adjusting oxidation time, cavity pressure, and oxidizing gas flow rate. This results in a more uniform etching effect for each molybdenum layer 106 located between the insulating layers 102 in each etching stage. This solves the problem of uneven etching rates of the molybdenum layer 106 at different depths of the trench 104 in conventional molybdenum etching processes. The present application's technical solution can improve device electrical properties and yield, and can be widely applied to advanced semiconductor processes.
[0096] refer to Figure 17 , Figure 17A graph showing the relationship between oxidation time, molybdenum oxide layer 107 thickness, and etching rate, provided for an embodiment of this application. Figure 17 Curves 1 and 2 represent the oxidation time versus etching rate, and curves 3 and 4 represent the oxidation time versus the thickness of the molybdenum oxide layer 107. The oxidation time is in seconds, the thickness of the molybdenum oxide layer 107 is in angstroms, and the etching rate is in angstroms per second. In the scenario of etching the metallic molybdenum layer 106 between the insulating layers 102, the thickness of the molybdenum oxide layer 107 is the lateral oxidation dimension of the metallic molybdenum layer 106.
[0097] exist Figure 17 In the illustrated method, two wafers with different thicknesses of molybdenum metal layers 106 are used for experimental verification. Curves 1 and 3 represent the experimental test curves corresponding to one wafer, and curves 2 and 4 represent the experimental test curves corresponding to the other wafer. Based on Figure 17 The results show that the thickness of the molybdenum oxide layer 107 is correlated with the oxidation time.
[0098] During the same etching stage, as the oxidation time increases, the lateral oxidation size of the molybdenum layer 106 increases linearly until it reaches the maximum lateral oxidation size. The etching time of the molybdenum oxide is a fixed value. Under certain etching conditions, the etching rate of the molybdenum layer 106 is equal to the etching rate of the molybdenum oxide layer 107 with the maximum lateral oxidation size. At this time, the etching rate of the molybdenum oxide layer 107 is constant.
[0099] Under a given etching time, if the molybdenum layer 106 has not reached its maximum lateral oxidation size, the thickness of the molybdenum oxide layer 107 has a linear relationship with the etching rate of the molybdenum layer 106; the longer the oxidation time, the greater the thickness of the molybdenum oxide layer. In this case, because the maximum lateral oxidation size has not been reached, the set etching time exceeds the actual etching time required to oxidize the molybdenum layer 107, resulting in etching time redundancy. The actual etching rate of the molybdenum layer 106 is equal to the quotient of the current thickness of the molybdenum oxide layer 107 and the etching time; therefore, the actual etching rate of the molybdenum layer 106 is less than the etching rate of the molybdenum oxide layer 107. Thus, when the molybdenum layer 106 has not reached its maximum lateral oxidation size, the actual etching rate of the molybdenum layer 106 has a positive linear relationship with the oxidation time; the longer the oxidation time, the shorter the redundancy in the etching time, and the greater the actual etching rate of the molybdenum layer 106, until the maximum lateral oxidation rate is reached, at which point the etching rate of the molybdenum layer 106 equals the etching rate of the molybdenum oxide layer 107.
[0100] like Figure 17As shown, when the oxidation time is less than 50 s, the thickness of the molybdenum oxide layer 107 has a linear relationship with the oxidation time; as the oxidation time increases, the thickness of the molybdenum oxide layer 107 increases linearly. When the etching time is set, the actual etching rate of the molybdenum metal layer 106 is equal to the quotient of the thickness of the molybdenum oxide layer 107 and the etching time. Therefore, at this time, the thickness of the molybdenum oxide layer 107 and the actual etching rate of the molybdenum metal layer 106 have a linear relationship; as the thickness of the molybdenum oxide layer 107 increases, the actual etching rate of the molybdenum metal layer 106 increases linearly. When the oxidation time increases to 70 s, the oxidation reaction of the molybdenum metal layer 106 tends to be sufficient, and the molybdenum metal layer 106 located between the insulating layers 102 can reach the maximum lateral oxidation size. This allows the molybdenum metal layer 106 at different depths of the groove to form a relatively uniform lateral oxidation size, thus laying the foundation for the uniform removal of each layer of molybdenum metal layer 106.
[0101] refer to Figure 18 , Figure 18 This is a schematic diagram illustrating the relationship between the etching rate of the molybdenum layer 106 and the thickness of the molybdenum oxide layer 107, provided as an embodiment of this application. Based on Figure 18 The results show that as the thickness of the molybdenum oxide layer 107 increases, the etching rate of the molybdenum metal layer 106 exhibits a significant upward trend, and the linear correlation coefficient R between the two is high. 2 The value is greater than 0.99, indicating that the final etching effect of the molybdenum metal layer 106 can be directly controlled by adjusting the amount of molybdenum oxide layer 107 formed. In other words, there is a strong positive correlation between the thickness of the molybdenum oxide layer 107 and the etching rate of the molybdenum metal layer 106.
[0102] refer to Figure 19 , Figure 19 This diagram illustrates the relationship between the etching rate of the molybdenum oxide layer 107 and the etching rate of the molybdenum oxide layer 107, as provided in another embodiment of this application. When the oxidation time is less than 50 seconds, the oxidizing gas cannot achieve the maximum oxidation thickness of the molybdenum oxide layer 106, and the molybdenum oxide layer 106 cannot reach oxidation saturation. At this time, the linear correlation coefficient R between the thickness of the molybdenum oxide layer 107 and the etching rate of the molybdenum oxide layer 106 is... 2 The linear correlation coefficient R is only 0.513. 2 The etching rate is low, the molybdenum oxide layer 107 cannot achieve saturated oxidation, the etching rate of the molybdenum metal layers 106 at different depths of the trench 104 has a large difference, and the molybdenum metal layers 106 cannot achieve a uniform lateral etching distance D.
[0103] refer to Figure 20 , Figure 20 This is a schematic diagram illustrating the relationship between gas flow rate and the thickness of the molybdenum oxide layer and the etching rate of the molybdenum metal layer 106, as provided in an embodiment of this application. Figure 20Curves 5 and 6 represent the gas flow rate versus the etching rate of the molybdenum layer 106, and curves 7 and 8 represent the gas flow rate versus the thickness of the molybdenum oxide layer 107. The gas flow rate is expressed in sccm, the thickness of the molybdenum oxide layer 107 in angstroms, and the etching rate of the molybdenum layer 106 in angstroms per second.
[0104] exist Figure 20 In the illustrated method, two wafers with different thicknesses of molybdenum metal layers 106 were used for experimental verification. Curves 5 and 7 represent the curves corresponding to one of the wafers to be processed, while curves 6 and 8 represent the curves corresponding to the other wafer. Based on Figure 20 The results show that, with the increase of the oxidizing gas flow rate, the thickness of the molybdenum oxide layer 107 and the etching rate of the molybdenum metal layer 106 generally increase, indicating a positive correlation between the thickness of the molybdenum oxide layer 107 and the gas flow rate; and the etching rate of the molybdenum metal layer 106 is also correlated with the gas flow rate. Figure 20 The correlation of the curves shows that when the flow rate of the oxidizing gas is 1250 sccm to 3250 sccm, the molybdenum layers 106 at different depths can achieve a consistent oxidation effect, thereby enabling each molybdenum layer 106 to achieve a relatively uniform etching removal rate.
[0105] refer to Figure 21 , Figure 21 This is a schematic diagram illustrating the relationship between cavity pressure and the etching rate of the molybdenum layer 106, provided as an embodiment of this application. Based on Figure 21 The results show that when the molybdenum oxide layer 106 is not saturated with oxidation, the thickness of the molybdenum oxide layer 107 increases continuously with the increase of the chamber pressure, and the etching rate of the molybdenum oxide layer 106 increases accordingly. When the chamber pressure increases to 8 Torr, the oxidation effect tends to stabilize, and the molybdenum oxide layer 106 forms saturated oxidation. When the chamber pressure reaches 10 Torr, further increases in pressure have no significant effect on improving the thickness of the molybdenum oxide layer or the etching rate of the molybdenum oxide layer 106.
[0106] refer to Figure 22 , Figure 22 This is a graph showing the relationship between the spacing between the upper and lower substrates within the cavity and the etching rate of the molybdenum layer 106. The horizontal axis represents the spacing between the upper and lower substrates in millimeters, and the vertical axis represents the etching rate of the molybdenum layer 106 in angstroms per second. Experiments were conducted using two wafers with molybdenum layers 106 of different thicknesses to verify this. Figure 22 The two curves represent the test curves of the spacing between the upper and lower substrates and the etching rate of the molybdenum layer 106 corresponding to a wafer, respectively. Based on Figure 22 It can be seen that the vertical spacing of the substrate has little effect on the oxidation thickness and etching rate of the molybdenum layer 106.
[0107] refer to Figure 23 , Figure 23 This is a schematic diagram illustrating the relationship between oxidation time, etching deviation, and etching rate, provided for an embodiment of this application. Figure 23 Curve 9 represents the relationship between oxidation time and etching deviation, and curve 10 represents the relationship between oxidation time and etching rate. The unit of oxidation time is seconds, the unit of etching deviation is nm, and the unit of etching rate of molybdenum layer 106 is nm / s.
[0108] based on Figure 23 As shown in curve 9, when the oxidation time is no more than 50s, the molybdenum layers 106 located between the insulating layers 102 have a large etching deviation relative to the target etching size. When the oxidation time is not less than 70s, the etching deviation of each molybdenum layer 106 does not exceed 1nm. Meeting the above equal conditions, each molybdenum layer 106 has a relatively consistent lateral etching distance D. Based on... Figure 23 As shown in curve 10, when the etching rate of the molybdenum layer 106 does not exceed 70s, the etching rate of the molybdenum layer 106 has a large linear increase with the increase of oxidation time, but when it exceeds 70s, the increase in etching rate is very small.
[0109] refer to Figure 24 and Figure 25 , Figure 24 This is a morphology image of the device when the 106 molybdenum layer is unsaturated with oxide. Figure 25 This is a topographic image of the device after etching away the molybdenum oxide layer 107 under unsaturated oxidation of the molybdenum layer 106.
[0110] like Figure 24 As shown, with the increase of the aspect ratio of trench 104, it becomes more difficult for oxidizing gas to be transported to the bottom of trench 104. Therefore, there are differences in the concentration of oxidizing gas at different depths of trench 104, and the oxidation rate of the molybdenum layer 106 at different depths of trench 104 varies. In the same etching stage, the molybdenum layer 106 near the bottom of trench 104 has a smaller lateral oxidation size, while the molybdenum layer 106 near the top of trench 104 has a larger lateral oxidation size.
[0111] like Figure 25 As shown, during the etching removal of the molybdenum oxide layer 107, as the aspect ratio of the trench 104 increases, the concentration of etching gas at different depths of the trench 104 varies, resulting in different etching rates for the molybdenum layer 106 at different depths of the trench 104. Figure 23The lateral oxidation dimensions of each molybdenum layer 106 increase from bottom to top, therefore the lateral etching removal amount d of each molybdenum layer 106 in the same etching stage also increases from bottom to top. After multiple etching processes, the lateral etching distance D of each molybdenum layer 106 varies significantly. Therefore, if the molybdenum layer 106 is not saturated during the oxidation process, such as... Figure 25 As shown, the lateral etching distance D of each molybdenum layer 106 located between the insulating layers 102 varies considerably.
[0112] In the technical solution of this application, as described above, by setting oxidation conditions, saturated oxidation of each molybdenum layer 106 can be achieved in each etching stage, thereby enabling each molybdenum layer 106 to have a relatively consistent lateral etching distance D. As described above, in this embodiment, the adjusted cavity pressure, gas flow rate, and oxidation time constitute the oxidation conditions suitable for saturated oxidation. Key oxidation parameters can be specifically optimized according to the aspect ratio or lateral etching distance D, ensuring that even in complex semiconductor structures with high aspect ratio trenches 104, the oxygen free radical concentration at the bottom of the trench 104 can be maintained at an effective reaction level to achieve saturated oxidation of the molybdenum layer 106. For example, by adopting a strategy of increasing gas flow rate, more oxygen molecules are transported to the depth of the trench 104, ensuring that the bottom molybdenum layer 106 can achieve the expected saturated oxidation effect synchronously with the top molybdenum layer 106.
[0113] Based on the fabrication methods provided in the above embodiments, another embodiment of this application provides a semiconductor device, which can be fabricated using any of the above-described fabrication method embodiments. The structure of the semiconductor device can be as follows: Figure 13 As shown, it includes:
[0114] The semiconductor structure includes a semiconductor substrate 100 and a stacked structure 101 located on one side surface of the semiconductor substrate 100; along the thickness direction of the semiconductor substrate 100, the stacked structure 101 includes multiple layers of molybdenum metal layers 106 stacked sequentially; an insulating layer 102 is provided between the semiconductor substrate 100 and adjacent molybdenum metal layers 106, and between adjacent molybdenum metal layers 106.
[0115] A trench 104 penetrating the laminated structure 101;
[0116] There is a lateral etching distance D between the molybdenum layer 106 between adjacent insulating layers 102 and the sidewall of the trench 104, and the lateral etching distance D corresponding to different molybdenum layers 106 satisfies the condition of equality.
[0117] Optionally, in Figure 13 Based on the method shown, semiconductor devices can also be used as follows: Figure 15It also includes semiconductor material 108 located in the gap 105 formed by etching away part of the molybdenum layer 106 in the insulating layer 102.
[0118] In one embodiment, as described above, the molybdenum metal layers 106 located between the insulating layers 102 can have equal or approximately equal thicknesses by setting oxidation conditions.
[0119] In another approach, the thickness of each molybdenum layer 106 increases sequentially from the opening to the bottom of the trench 104. This results in a larger lateral surface area for the bottom molybdenum layer 1062, allowing for a wider gap 105. This facilitates the saturation oxidation of the molybdenum layer 106 and the etching removal of the molybdenum oxide layer 107, thereby compensating for the difference in lateral etching distance D of the molybdenum layers 106 at different depths due to the depth of the trench 104. In this case, the impedance difference caused by the different thicknesses of the molybdenum layers 106 can be compensated for by using interconnects with different impedances external to the semiconductor device.
[0120] The semiconductor devices and fabrication methods disclosed in the above embodiments have the same or corresponding beneficial effects, and will not be repeated here to avoid repetition.
[0121] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.
[0122] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for understanding and ease of description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.
[0123] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.
[0124] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.
[0125] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a semiconductor substrate and a stacked structure located on one surface of the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the stacked structure includes multiple layers of molybdenum metal layers stacked sequentially; an insulating layer is provided between the semiconductor substrate and adjacent molybdenum metal layers, and between adjacent molybdenum metal layers; wherein, the semiconductor structure has a trench penetrating the stacked structure; the molybdenum metal layer at the top of the stacked structure also covers the sidewalls of the trench; Remove the molybdenum layer from the top and trench sidewalls of the stacked structure; An oxidizing gas is introduced into the trench to oxidize the molybdenum layer between the insulating layers, forming a molybdenum oxide layer. The molybdenum oxide layer is then etched away to ensure that there is a predetermined lateral etching distance between the molybdenum layer between adjacent insulating layers and the trench sidewall. Under predetermined oxidation conditions, the molybdenum layer between adjacent insulating layers is oxidized to ensure that the lateral etching distances corresponding to different molybdenum layers are equal.
2. The preparation method according to claim 1, characterized in that, After introducing an oxidizing gas into the trench to oxidize the molybdenum layer between the insulating layers to form a molybdenum oxide layer, removing the molybdenum oxide layer includes: The molybdenum metal layer located between the insulating layers is etched away through multiple etching stages; wherein each etching stage includes: after oxidizing the molybdenum metal layer under the set oxidation conditions, etching away the molybdenum oxide layer formed by the oxidation treatment; the sum of the lateral etching removal amount of the molybdenum metal layer by the multiple etching stages is the lateral etching distance.
3. The preparation method according to claim 2, characterized in that, The oxidation conditions include: The oxidation time of the oxidation treatment shall not be less than 70 seconds; During the oxidation process, the chamber pressure in the reaction chamber is not less than 8 Torr; During the oxidation process, the flow rate of the oxidizing gas is not less than 1250 sccm.
4. The preparation method according to claim 3, characterized in that, The oxidation time shall not exceed 100 seconds; The pressure in the cavity does not exceed 15 Torr; The flow rate of the oxidizing gas does not exceed 3250 sccm.
5. The preparation method according to claim 2, characterized in that, During the same etching stage, the chamber pressure in the reaction chamber is constant, and the flow rate of the oxidizing gas is constant.
6. The preparation method according to claim 2, characterized in that, The oxidation time of the multiple etching stages increases sequentially, the chamber pressure of the reaction chamber increases sequentially, and the flow rate of the oxidizing gas increases sequentially.
7. The preparation method according to claim 1, characterized in that, The condition that the lateral etching distances are equal includes: the difference between the lateral etching distances of the molybdenum metal layers located between the insulating layers and the target etching size does not exceed 3 nm.
8. The preparation method according to any one of claims 1-7, characterized in that, Removing the molybdenum layer from the top and trench sidewalls of the stacked structure includes: The molybdenum layer on the top of the stacked structure and on the sidewalls of the trench is oxidized to a molybdenum oxide layer, and then the molybdenum oxide layer is removed.
9. A semiconductor device prepared by the method of any one of claims 1-8, characterized in that, include: A semiconductor structure, the semiconductor structure including a semiconductor substrate and a stacked structure located on one side surface of the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the stacked structure includes multiple layers of molybdenum metal stacked sequentially; an insulating layer is provided between the semiconductor substrate and adjacent molybdenum metal layers, and between adjacent molybdenum metal layers; A trench penetrating the stacked structure; There is a lateral etching distance between the molybdenum layer between adjacent insulating layers and the sidewall of the trench, and the lateral etching distances corresponding to different molybdenum layers satisfy the condition of equality.
10. The semiconductor device according to claim 9, characterized in that, The thickness of each layer of molybdenum increases sequentially from the opening of the trench to the bottom of the trench.