A power semiconductor die electro-optical fusion health screening and matching method

Abstract

The application discloses a power semiconductor die electro-optical fusion health degree screening and matching method, and relates to the technical field of power semiconductor die testing, die screening and power module packaging reliability. The method binds the die identity and position information, respectively performs electrical testing and LF-OCT line field optical coherence tomography, extracts electrical testing parameters and structural characteristic parameters, and then generates electrical robustness indexes and optical structural integrity indexes. A two-dimensional electro-optical evaluation plane is constructed, each die is mapped as a unique coordinate point in the plane, and health degree grading screening is performed accordingly, and high consistency matching before power module packaging is realized according to the coordinate point spacing. The application is suitable for various power semiconductor dies such as Si, SiC, GaN and IGBT, realizes fusion evaluation of electrical and structural defects, and effectively improves the reliability and consistency of the power module.

Description

Technical Field

[0001] This invention relates to the fields of power semiconductor die testing, die screening, and power module packaging reliability technology, and more specifically to a method for electro-optical fusion health screening and grouping of power semiconductor dies. Background Technology

[0002] Power semiconductor dies are core components in new energy vehicles, photovoltaic energy storage, rail transit, and various power conversion equipment. Their performance and reliability directly determine the efficiency and lifespan of the entire system. With the continuous development of power devices towards higher frequencies and higher power densities, multi-die parallel packaging technology has become the mainstream solution to meet high current demands. However, parallel packaging places extremely stringent requirements on the parameter consistency between the dies. If there are significant differences in on-resistance, leakage current, switching losses, or internal structural integrity among the dies, it can easily lead to uneven current distribution, localized overheating, and thermal stress concentration during module operation, thereby causing premature failure.

[0003] Currently, the industry commonly uses electrical parameter-based screening methods (KGD testing) to ensure die quality. This method mainly uses a probe station to perform static or dynamic electrical tests on the die, collecting key indicators such as on-state voltage drop, threshold voltage, and breakdown voltage, and rejecting dies with electrical anomalies based on preset thresholds. However, simple electrical testing can only reflect the electrical state of the device at the time of testing and cannot effectively identify subsurface structural defects such as microcracks, edge chipping, grinding damage layers, or uneven metal layer thickness introduced by wafer thinning, dicing, and handling processes. These structural defects often do not cause significant drift in electrical parameters in the early stages, but they can evolve into fatal failures under subsequent packaging stress or long-term thermal cycling, becoming a major bottleneck restricting module reliability.

[0004] To compensate for the shortcomings of electrical testing, existing technologies have incorporated microscopic inspection, infrared imaging, or traditional point-scan optical coherence tomography (OCT). However, surface optical inspection struggles to penetrate opaque materials to observe internal structures, while traditional point-scan OCT, although possessing micrometer-level resolution, relies on a point-by-point mechanical scanning mechanism, resulting in slow imaging speeds that are ill-suited to the high-throughput, near-real-time screening requirements of semiconductor production lines. Furthermore, existing technologies typically separate electrical testing from optical inspection, lacking an effective means to unify and comprehensively evaluate the data from both, leading to screening results that are merely simple "pass / fail," lacking quantitative assessment of wafer health and a basis for consistent grouping.

[0005] Therefore, existing power semiconductor die screening technologies face three major technical challenges: difficulty in detecting structural defects, difficulty in improving detection efficiency, and difficulty in integrating multi-dimensional data. To address these shortcomings, a novel screening and grouping method is urgently needed that can balance detection accuracy and efficiency, and can quantify both electrical performance and internal structural integrity in a unified manner. This would solve the problem of dies that are "electrically qualified but structurally flawed" flowing into the packaging stage, thereby improving the overall reliability and consistency of power modules. Summary of the Invention

[0006] In view of the above problems, this invention is proposed to provide a power semiconductor die electro-optic fusion health screening and grouping method that overcomes or at least partially solves the above problems. It not only evaluates the electrical performance of the die, but also uses LF-OCT to quickly obtain structural information of the die edge, metal layer, passivation layer, termination structure and subsurface region, and converts the electrical parameters and LF-OCT structural parameters into unified and comparable indicators. Finally, it achieves high consistency grouping of die health classification and module packaging. This invention can be applied to Si, SiC, GaN, IGBT, MOSFET, diode, thyristor or other power semiconductor dies.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, embodiments of the present invention provide a method for electro-optical fusion health screening and grouping of power semiconductor dies, comprising: Obtain the identity information and spatial location information of the semiconductor die under test, and bind the identity information and spatial location information; Electrical tests are performed on the bonded power semiconductor die to obtain electrical test parameters, and electrical robustness indices are generated based on the electrical test parameters. LF-OCT line-field optical coherence tomography was performed on the same power semiconductor die under test to obtain LF-OCT tomographic structure data, and structural feature parameters were extracted from the LF-OCT tomographic structure data. Based on the structural feature parameters, an optical structure integrity index was generated. The electrical robustness index and the optical structural integrity index are respectively used as the two coordinate dimensions of the two-dimensional electro-optic evaluation plane to construct the two-dimensional electro-optic evaluation plane, and each power semiconductor die under test is associated with the corresponding coordinate point in the two-dimensional electro-optic evaluation plane. Based on the position of the coordinate points in the two-dimensional electro-optic evaluation plane, the health level of the power semiconductor dies under test is graded and screened, and the power module is grouped before packaging based on the distance between the corresponding coordinate points of multiple candidate dies.

[0009] Preferably, the identity information and spatial location information include wafer number, die number, batch number, test time, wafer coordinates, stage coordinates, LF-OCT scan area coordinates, and packaging target location; The electrical testing of the bonded power semiconductor die to obtain electrical test parameters specifically includes: The test obtains one or more of the following parameters: on-state voltage drop, on-resistance, leakage current, breakdown voltage, threshold voltage, gate charge, turn-on loss, turn-off loss, short-circuit withstand capability, dynamic on-resistance, and dynamic switching response.

[0010] Preferably, the step of performing LF-OCT line-field optical coherence tomography on the same power semiconductor die under test specifically includes: The LF-OCT system's line field illumination optical system forms a linear illumination area on the surface of the bare die, and interference signals are acquired in parallel. The LF-OCT scan covers one or more of the following areas: the edge area of ​​the die, the area near the scribe line, the front metal layer area, the back metallized area, the passivation layer area, the junction terminal extension area, the polishing and thinning area, and the local suspected damage area.

[0011] Preferably, the extraction of structural feature parameters from the LF-OCT tomographic data specifically includes: Extract one or more of the following from LF-OCT tomographic images: chipping depth, chipping area, crack depth, crack length, crack propagation direction, distance between crack and active region, grinding damage layer thickness, metal layer thickness distribution, metal layer thickness uniformity, passivation layer integrity, mesa etching residue, junction terminal extension structure integrity, interlayer continuity, local void or delamination area, and subsurface anomalous reflection intensity.

[0012] Preferably, the step of generating electrical robustness indicators based on the electrical test parameters specifically includes: The measured values ​​of each electrical test parameter are compared with the preset reference values, the upper limit of allowable and / or the lower limit of allowable to obtain the normalized deviation of each electrical test parameter. The normalized deviation is limited to a preset range to obtain the normalized risk value; Based on the weights of each electrical parameter, a weighted sum is calculated on the normalized risk values ​​after restrictions to obtain a comprehensive electrical risk score. The electrical robustness index is generated by reverse transformation based on the comprehensive electrical risk score.

[0013] Preferably, generating the optical structure integrity index based on the structural feature parameters specifically includes: The measured values ​​of each structural characteristic parameter are compared with the allowable thresholds to calculate the normalized risk value of structural defects for each structural characteristic parameter. For structural defects that are location-sensitive, the normalized risk value of the structural defect is corrected according to the amplification factor of the defect location on the reliability risk, so as to obtain the corrected structural risk value. Based on the weights of each structural feature parameter, a weighted sum is calculated on the corrected structural risk value to generate a structural risk score for the bare wafer. Based on the structural risk score, the optical structure integrity index is generated.

[0014] Preferably, it further includes: When any structural feature parameter exceeds the corresponding fatality threshold, the fatal defect flag of the p-th die is set. Set the value to 1 and directly classify the bare wafer into the structural risk category or the exclusion category; when none of the structural defects in all categories meet the corresponding fatality criteria, set the fatality defect flag bit. The value is set to 0, and the p-th bare die is graded and evaluated based on the optical structure integrity index.

[0015] Preferably, the step of screening for health grading based on the position of the coordinate point in the two-dimensional electro-optical assessment plane specifically includes: By setting electrical robustness thresholds and optical structural integrity thresholds, the two-dimensional electro-optic evaluation plane is divided into multiple regions; Dies whose coordinates fall within the high reliability region are classified as high reliability application dies; those falling within the derating region are classified as derating use dies; those falling within the risk region are classified as potential reliability risk dies; and those falling within the rejection region are classified as rejection dies.

[0016] Preferably, the assembly of the power module before packaging based on the coordinate distance between multiple bare dies specifically includes: Calculate the weighted distance between any two candidate wafers in the two-dimensional electro-optic evaluation plane; With minimizing the average dispersion within a group as the objective function, and under the conditions of package quantity, package location, electrical threshold, structural threshold, and fatal defect rejection, the die with the closer weighted coordinate point is selected to enter the same power module.

[0017] Preferably, the weighted coordinate point distance is:

[0018] in, Indicates the first nude film and the first The overall difference distance between bare wafers; Indicates the weight of the electrical dimension; Represents the weights of optical structure dimensions, and satisfies:

[0019] and Indicates the first nude film and the first The coordinates of a bare wafer; The objective function is:

[0020]

[0021] The constraints are:

[0022]

[0023]

[0024]

[0025] in, Represents the optimal set of bare die pairings; This indicates the minimum electrical robustness requirement that allows entry into the grouping process; This indicates the minimum optical structural integrity index that allows entry into the grouping process; This indicates that each power module needs to be selected. A bare film.

[0026] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a method for electro-optical fusion health screening and grouping of power semiconductor dies, which has the following effects: First, the present invention enables the joint evaluation of the electrical performance and subsurface structural integrity of power semiconductor dies.

[0027] Compared with screening methods that rely solely on electrical parameters, this invention considers electrical parameters such as on-state voltage drop, on-state resistance, leakage current, breakdown voltage, threshold voltage, and switching losses, as well as structural parameters such as edge chipping, cracks, grinding damage layer, metal layer thickness distribution, passivation layer integrity, and terminal structure integrity obtained by LF-OCT.

[0028] Second, the present invention can improve the efficiency of optical structure detection.

[0029] Because LF-OCT uses line-focused illumination and parallel acquisition along the line direction, compared with traditional point-scan OCT, it can reduce the point-by-point scanning time within the same lateral sampling range, improve the efficiency of structural detection in key areas of the die, and is suitable for integration with KGD or pre-packaging screening processes.

[0030] Third, the present invention can identify bare wafers with qualified electrical parameters but potential structural defects.

[0031] For bare dies with normal electrical test results but low LF-OCT optical structure integrity index, this invention can identify them as bare dies with potential reliability risks, thereby reducing the probability of them entering the high-reliability power module packaging process.

[0032] Fourth, the present invention can reduce the phase instability caused by mechanical scanning.

[0033] LF-OCT acquires information from multiple lateral positions in parallel using a single illumination line, reducing reliance on one-dimensional high-speed mechanical scanning. In scenarios requiring phase stability or high repeatability of structure detection, this approach helps reduce image distortion, phase drift, and detection errors caused by mechanical scanning.

[0034] Fifth, this invention enables the quantitative classification of the health of bare films.

[0035] By constructing a two-dimensional electro-optic evaluation plane, each die can be mapped to a coordinate point, so that the die status is no longer just a simple "qualified / unqualified", but can be divided into high-reliability application dies, derating dies, dies with potential reliability risks, and rejected dies.

[0036] Sixth, the present invention can improve the internal consistency of multi-die power modules.

[0037] By calculating the distance between coordinate points of different dies in the two-dimensional electro-optic evaluation plane, dies with closer electrical performance and structural health status can be selected for use in the same module, reducing the risk of uneven current distribution, local overheating, and early failure.

[0038] Seventh, the present invention can improve the traceability of the die screening and packaging process.

[0039] Because each die is bound to a wafer number, die number, batch number, test time, wafer coordinates, stage coordinates, LF-OCT scan area, and packaging target location, if a module failure occurs later, the electrical and structural state of the die before packaging can be traced. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a flowchart of a power semiconductor die electro-optic fusion health screening and grouping method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the LF-OCT line field scanning system provided in an embodiment of the present invention; Figure 3 This is a comparison diagram of point scanning OCT and LF-OCT scanning methods provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of LF-OCT structural feature extraction provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a two-dimensional electro-optic evaluation plane provided in an embodiment of the present invention; Figure 6 This is a structural fatal defect rejection logic diagram provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the die assembly provided in an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] This invention discloses a method for electro-optical fusion health screening and grouping of power semiconductor dies, such as... Figure 1 As shown, it includes: Obtain the identity information and spatial location information of the power semiconductor die under test, and bind the identity information and spatial location information; Electrical tests are performed on the bonded die under test to obtain electrical test parameters, and electrical robustness indicators are generated based on the electrical test parameters. LF-OCT line-field optical coherence tomography was performed on the same bare wafer to obtain LF-OCT tomographic structural data, and structural feature parameters were extracted from it. Based on the structural feature parameters, an optical structural integrity index was generated. A two-dimensional electro-optic evaluation plane is constructed with electrical robustness index as the abscissa and optical structural integrity index as the ordinate, and each bare die is mapped as a unique coordinate point in the two-dimensional electro-optic evaluation plane; Health grading and screening are performed based on the position of coordinate points in the two-dimensional electro-optic evaluation plane, and power module grouping is performed before packaging based on the distance between coordinate points of multiple bare dies.

[0044] The specific implementation process of each step of the present invention is described in detail below.

[0045] Step 1: Obtain the identification and spatial location information of the power semiconductor die under test. The system first acquires the identity information and spatial location information of the die to be tested, including: wafer number, die number, batch number, test time, wafer coordinates, stage coordinates, LF-OCT scan area coordinates, and packaging target location.

[0046] This step ensures that each wafer has a unique traceable identifier. This identifier is used to link subsequent electrical test parameters, LF-OCT tomographic images, structural characteristic parameters, health grading results, and grouping results.

[0047] Step 2: Perform electrical tests on the bare die to be tested and obtain the electrical test parameters. The system performs static and dynamic electrical tests on the power semiconductor die under test. The electrical test parameters include one or more of the following: on-state voltage drop, on-resistance, leakage current, breakdown voltage, threshold voltage, gate charge, turn-on loss, turn-off loss, short-circuit withstand capability, dynamic on-resistance, and dynamic switching response parameters.

[0048] Among them, on-state voltage drop and on-resistance characterize the loss level of the die in the on-state; leakage current and breakdown voltage characterize the die's withstand voltage and insulation capability; threshold voltage characterizes the device's turn-on characteristics; turn-on loss and turn-off loss characterize dynamic switching performance; short-circuit withstand capability characterizes the die's ability to withstand abnormal operating conditions. Gate charge characterizes the amount of charge required for gate driving of the die, which is related to gate drive loss, switching speed, and drive circuit design; dynamic on-resistance characterizes the change in on-resistance of the die after switching stress or high-voltage bias, and can reflect interface traps, charge trapping, and dynamic conduction performance degradation; dynamic switching response parameters include one or more of the following: turn-on delay time, turn-off delay time, rise time, fall time, voltage change rate, current change rate, voltage overshoot, current overshoot, and oscillation characteristics, used to characterize the die's response speed, transient stability, and switching stress level during dynamic switching.

[0049] For the A bare die can have its electrical test parameters represented as an electrical parameter vector:

[0050] in, Indicates the first A set of electrical test parameters for a bare die. Indicates the first The first piece of nude film Electrical test parameters, This indicates the number of electrical parameters involved in the evaluation.

[0051] Electrical robustness indices are generated based on electrical test parameters: The system unifies multiple electrical test parameters into a single electrical robustness index.

[0052] For the The first piece of nude film The electrical test parameters are given, and their measured values ​​are assumed to be... The reference value is The lower limit is allowed to be The maximum allowed is Then the normalized deviation of the electrical test parameter can be expressed as:

[0053] in, Indicates the first nude film number Normalized deviation of electrical test parameters.

[0054] For electrical parameters that are better the smaller they are, such as leakage current, on-resistance, or switching losses, the following normalized risk expression can also be used:

[0055] For electrical parameters where a larger value is always better, such as breakdown voltage or short-circuit withstand capability, the following normalized risk expression can also be used:

[0056] To ensure the stability of the normalization result, it can be restricted to the interval [0,1]:

[0057] in, Indicates the first nude film number The normalized risk value of the electrical test parameters after interval restriction, and satisfying the following:

[0058] Let the first The weights of the electrical parameters are And satisfy:

[0059] Based on the weights of each electrical parameter, the normalized risk values ​​after restrictions are weighted and summed to obtain the first... Comprehensive electrical risk score for each bare die:

[0060] in, Show the first Comprehensive electrical risk score for each bare die; Indicates the first nude film number Normalized risk values ​​of electrical test parameters after range limitation; Indicates the first The weights of the electrical test parameters; This indicates the number of electrical test parameters involved in the evaluation.

[0061] Since all normalized risk values ​​are within the range [0,1], and the sum of the weights is 1, therefore:

[0062] when The closer the value is to 1, the higher the overall electrical risk of the wafer; when... The closer the value is to 0, the lower the overall electrical risk of the wafer.

[0063] To ensure that a higher index value indicates a more stable electrical state of the bare chip, the comprehensive electrical risk score is reverse-converted. The electrical robustness index of the bare die is:

[0064] Furthermore, after substituting the comprehensive electrical risk score, it can be expressed as:

[0065] in, .when The closer the value is to 1, the further the electrical performance of the bare die is from the failure boundary, and the more stable the electrical state is; when... The closer it is to 0, the closer the electrical parameters of the bare die are to or beyond the preset boundary.

[0066] In addition to weighted normalization, electrical robustness indices can also be calculated using threshold scoring, fuzzy evaluation, principal component analysis, machine learning models, anomaly detection models, or reliability prediction models.

[0067] Step 3: Perform LF-OCT line-field optical coherence tomography on the same wafer under test. After obtaining the electrical test parameters, or before and after the electrical test, the system performs LF-OCT line-field optical coherence tomography on the same die under test. LF-OCT scanning can cover one or more of the following areas: die edge region; region near the scribe line; front metal layer region; back metallization region; passivation layer region; junction termination extension region; polishing thinning region; and local suspected damage region.

[0068] The actual imaging area and imaging depth of LF-OCT depend on the optical transmittance of the wafer material, the detection wavelength, the surface roughness, the metal obstruction state, and the incident direction. For areas completely obscured by the metal layer or with strong optical attenuation, scanning can be performed from the back of the wafer, the edge area, or a preset optically accessible area, or only the visible interface, the anomalous scattering layer, and structural features within the detectable depth range below the surface can be extracted.

[0069] like Figure 2 As shown, the LF-OCT system includes a low-coherence light source, a beam splitting structure, a reference arm, a sample arm, a line field illumination optical system, a linear array detector or a planar array detector, a data acquisition unit, a tomographic image reconstruction unit, and a high-precision motion stage.

[0070] The specific scanning process is as follows: The low-coherence light source is used to output low-coherence measurement light with a preset center wavelength and spectral bandwidth. After entering the beam splitter, the low-coherence measurement light is split into reference light propagating along the reference arm and sample light propagating along the sample arm. The beam splitter is also used to receive the reference arm return light and the sample arm return light, and to recombine the two return lights to form an interference signal.

[0071] After the reference light enters the reference arm, it is collimated or focused by the reference arm's optical components and then illuminates the reference mirror. The reference mirror reflects the reference light back to the beam splitter along the original optical path. The reference arm provides a reference optical path that matches the sample arm and provides an interference reference for the light signals returning from different depths within the sample. By adjusting the position of the reference mirror, the optical path difference between the reference arm and the sample arm can be adjusted, ensuring that the target detection depth is within the effective imaging range of the LF-OCT system.

[0072] After the sample light enters the sample arm, it is shaped by the line field illumination optics system. This system expands the incident beam into a linear illumination beam along a lateral direction and projects the linear illumination area onto the surface of the power semiconductor die under test via scanning optics. As a result, multiple lateral positions within the linear illumination area can be simultaneously illuminated and acquired in parallel by the detector, thus reducing the time required for point-by-point scanning in traditional point-scan OCT.

[0073] The semiconductor die under test is fixed on a high-precision motion stage. This stage can move along the X, Y, and Z directions and can be adjusted at an angle around a preset axis. The X direction corresponds to the length of the linear illumination area, the Y direction corresponds to the scanning direction perpendicular to the linear illumination area, the Z direction is used to adjust the working distance between the die surface and the scanning optical components, and the angle adjustment is used to correct the die surface tilt, ensuring that the linear illumination area and the target detection area maintain a preset relative position.

[0074] During a single acquisition, the line-field illumination optics system forms a linear illumination area on the surface of the wafer. After the sample light enters the wafer, reflected or backscattered light is generated at the wafer surface, metal layers, passivation layers, junction termination structures, crack interfaces, grinding damage layers, and other interfaces where the refractive index changes. The reflected or backscattered light returns along the sample arm to the beam splitter and interferes with the reference light returning from the reference arm.

[0075] The combined interference light is guided to a linear or area array detector. The detector simultaneously acquires spectral interference signals corresponding to multiple lateral positions along the linear illumination direction. Unlike point scanning, which acquires only one lateral position at a time, LF-OCT can acquire depth information for multiple lateral positions within an illumination line range in parallel during a single exposure, such as... Figure 3 As shown.

[0076] The data acquisition unit receives the interference signal output by the detector and performs signal amplification, analog-to-digital conversion, acquisition triggering, background signal recording, and raw data storage. The tomographic image reconstruction unit performs background subtraction, wavenumber domain resampling, dispersion compensation, Fourier transform, depth reconstruction, phase processing, and image enhancement on the raw interference signal to obtain a two-dimensional depth tomographic image corresponding to the linear illumination region.

[0077] After acquiring data for a linear region, the high-precision motion stage moves a preset distance along the Y-direction perpendicular to the linear illumination region, or the scanning optics drive the linear illumination region to move a preset distance along the Y-direction. The system repeats illumination, interference signal acquisition, and depth reconstruction at the new scanning position, thereby continuously obtaining multiple adjacent two-dimensional tomographic images. By arranging and fusing the two-dimensional tomographic images corresponding to different Y-direction positions according to their spatial coordinates, three-dimensional LF-OCT tomographic structural data of the sample under test can be obtained.

[0078] By controlling a high-precision motion stage or scanning optical components, the LF-OCT system can perform full-area or selective scanning of the edge region of the bare die, the metal layer region, the passivation layer region, the junction terminal region, the polishing and thinning region, and the local suspected damage region. It also provides tomographic image data for the subsequent extraction of edge chipping, cracks, polishing damage layer, metal layer thickness, interlayer continuity, and subsurface abnormal structural features.

[0079] The light emitted from the low-coherence source is split into reference light and sample light. After passing through the line-field illumination optical system, the sample light forms a linear illumination area on the surface of the wafer under test. The lateral position along the line is denoted as... The wavenumber of the light source is denoted as :

[0080] Where λ represents the wavelength of the light source. Indicates wave number.

[0081] For any lateral position x along the line, the spectral interference intensity signal acquired by the detector can be expressed as:

[0082] in: Indicates the wave number at the lateral position x. The interference light intensity signal below; Indicates the light intensity returned by the reference arm; This represents the reflected light intensity at the lateral position x of the sample arm; This indicates the depth position corresponding to the internal reflective interface of the sample. This represents the phase term caused by system dispersion, sample scattering, and optical path perturbation.

[0083] If we consider the background and noise terms, the original interference signal can be further expressed as:

[0084] In the formula, This represents the raw spectral interference signal acquired by the detector; Indicates the system's DC background term; This indicates the detection noise term.

[0085] Effective interference signals can be obtained through background subtraction.

[0086] in, This indicates the background reference signal.

[0087] By performing a Fourier transform from the wavenumber domain to the depth domain on the effective interference signal, the complex reflection signal in the depth direction can be obtained:

[0088] Where Γ(x,z) represents the lateral position. Depth position Complex reflection signal at the location; This represents the Fourier transform from the wavenumber domain to the depth domain.

[0089] The corresponding two-dimensional fault structure intensity image can be represented as:

[0090] When the system moves the stage or scanning beam along the y-direction perpendicular to the line direction, LF-OCT tomographic structural data can be obtained:

[0091] in, Indicates the first LF-OCT three-dimensional tomographic data of the bare wafer. Indicates the coordinates of the line direction. Indicates the scan direction coordinates. Represents the coordinates in the depth direction.

[0092] It should be noted that the LF-OCT light source is not limited to a single type. It can employ swept-frequency light sources, broadband low-coherence light sources, supercontinuum light sources, near-infrared light sources, or other light sources capable of achieving low-coherence tomographic imaging. The LF-OCT detector is not limited to a linear array detector; it can employ a linear array detector, an area array detector, a line-direction pixel region in a 2D camera, or other detection structures capable of parallel line field detection. The LF-OCT scanning method is interchangeable, and can employ sample stage movement, beam scanning, probe movement, die array movement, multi-line parallel scanning, or multi-region selective scanning.

[0093] Extracting structural feature parameters from LF-OCT tomographic images, such as Figure 4 As shown, it includes one or more of the following: chipping depth; chipping area; crack depth; crack length; crack propagation direction; distance between crack and active region; grinding damage layer thickness; metal layer thickness distribution; metal layer thickness uniformity; passivation layer integrity; mesa etching residue; junction terminal extension structure integrity; interlayer continuity; area of ​​local voids or delamination; and subsurface anomalous reflection intensity.

[0094] For the A bare wafer can be represented by its structural characteristic parameters as follows:

[0095] in, Indicates the first The set of structural feature parameters of a bare wafer. Indicates the first The first piece of nude film Item structure characteristic parameters, This indicates the number of structural parameters involved in the evaluation.

[0096] Among them, the chipping depth is used to characterize the extent to which edge defects of the die penetrate into the die interior along the thickness direction. The greater the chipping depth, the more likely it is to affect the mechanical strength of the die edge and may invade the junction terminal region or active region. The chipping area is used to characterize the lateral extension range of edge defects on the die surface or edge region, and can be used to evaluate the overall edge damage caused during dicing, handling or clamping.

[0097] Crack depth characterizes the extent to which a crack extends along the thickness of the die, and can be used to determine whether the crack is only located on the surface or has extended to the metal layer, passivation layer, junction termination structure, or active region. Crack length characterizes the extent of crack extension in the die plane or in a tomographic image. The longer the crack length, the wider the crack propagation range, and the higher the risk of continued propagation under encapsulation stress or thermal cycling. Crack extension direction is used to determine whether the crack is propagating towards the active region, junction termination region, electrode region, or high electric field region. The distance between the crack and the active region is used to quantify the spatial distance between the crack and the core functional area of ​​the die. The smaller this distance, the greater the potential impact of the crack on the device's conductive channels, withstand voltage structure, and long-term reliability.

[0098] The thickness of the grinding damage layer is used to characterize the thickness of the subsurface damage layer formed during wafer thinning, back-side grinding, or polishing. It can reflect the severity of microcracks, residual stress, and material lattice damage inside the die. The thicker the grinding damage layer, the higher the risk of crack propagation or warping of the die during subsequent sintering, welding, packaging, and thermal cycling.

[0099] Metal layer thickness distribution characterizes the spatial variation of metal layer thickness at different locations on the die, and can be used to identify areas where the metal layer is too thin, too thick, missing, or has abnormal deposition. Metal layer thickness uniformity evaluates the consistency of the overall metal layer thickness and can be quantified based on maximum thickness, minimum thickness, average thickness, standard deviation, or coefficient of variation. Abnormal or insufficient metal layer thickness distribution may cause uneven local contact resistance, current density, and heat flux density, thereby increasing the risk of local overheating, metal fatigue, or electromigration.

[0100] Passivation layer integrity is used to determine whether the passivation layer has cracks, damage, gaps, local missing parts, abnormal thickness, or discontinuity. Insufficient passivation layer integrity may weaken the insulation, moisture protection, and electric field protection capabilities of the bare die surface and edge areas, and may cause increased leakage current, local electric field concentration, or decreased withstand voltage performance.

[0101] Mesa etching residue is used to characterize the presence of incomplete etching, residual material, localized protrusions, or abnormal deposits in the mesa etching area. Mesa etching residue may alter local structural dimensions, surface morphology, and electric field distribution, and may affect device isolation performance, surface leakage characteristics, and the withstand voltage capability of the junction termination region.

[0102] Junction terminal extension structural integrity is used to evaluate the geometric profile, structural continuity, edge integrity, and interlayer interface state of the junction terminal extension region. It can be used to determine whether there are cracks, edge chipping, etching anomalies, local missing parts, or structural interruptions in the junction terminal region. When the junction terminal extension structural integrity is reduced, it may cause uneven edge electric field distribution or local electric field concentration, thereby increasing the risk of premature breakdown.

[0103] Interlayer continuity characterizes whether metal layers, passivation layers, semiconductor layers, back metallization layers, and other adjacent material layers maintain continuous connectivity. It can be used to identify interlayer fractures, interface delamination, local missing layers, or structural abrupt changes. Insufficient interlayer continuity may lead to abnormal current transport, heat transfer, or mechanical stress transfer paths, and increase the risk of delamination or interface failure.

[0104] Local void or delamination area is used to quantify the spatial extent of voids, delamination, and separation regions within the die or at interlayer interfaces. Larger void or delamination areas are more likely to reduce effective contact area, thermal conductivity, and interfacial mechanical strength, and may further expand under subsequent encapsulation stress and thermal cycling.

[0105] Subsurface anomalous reflection intensity is used to characterize abnormal optical reflection or scattering changes in the region below the surface of a bare wafer relative to the normal structural region. It can be used to assist in the identification of microcracks, material density changes, interface anomalies, residues, local voids, delamination, and other hidden structural defects that are difficult to identify directly through surface images. Subsurface anomalous reflection intensity can be used in conjunction with the depth, area, shape, and spatial location of the anomalous region to improve the accuracy of structural defect identification and risk assessment.

[0106] The above structural feature parameters can be used to quantitatively describe the structural health status of the wafer under test from multiple dimensions such as defect size, defect depth, defect location, structural continuity, and interface state. This provides a data foundation for subsequent structural defect normalization risk calculation, critical defect determination, optical structural integrity index generation, and wafer health grading.

[0107] The system unifies multiple LF-OCT structural feature parameters into a single optical structural integrity index.

[0108] For the The first piece of nude film Item structural characteristic parameters, let their measured values ​​be... The allowed threshold is Then the normalized risk value of structural defects can be expressed as:

[0109] in, Indicates the first nude film number Normalized defect risk value of the structural parameters.

[0110] To ensure numerical stability, it can be restricted to the interval [0,1]:

[0111] For location-sensitive structural defects, such as cracks near the active region, edge chipping near the junction termination region, or passivation layer damage located in a high electric field region, a location risk factor can be introduced. The corrected structural risk value is obtained as follows:

[0112] in, , which represents the amplification factor of the defect location on the reliability risk.

[0113] Let the first The weights of the structural feature parameters of the terms are And satisfy:

[0114] Then the first The structural risk score of the bare wafer is:

[0115] No. The optical structural integrity index of the bare wafer is:

[0116] in, .when The closer the value is to 1, the better the structural integrity of the die; when... The closer the value is to 0, the more severe the structural defects in the die.

[0117] In addition to the deduction evaluation method, the calculation of optical structural integrity index can also be carried out by defect area ratio, defect depth score, defect location risk coefficient, structural integrity scoring model, image segmentation model or deep learning image recognition model.

[0118] Furthermore, such as Figure 6 As shown, the system uses structural feature parameters extracted from LF-OCT tomographic data to make a step-by-step judgment on through cracks, deep edge chipping, severe terminal structural damage, severe discontinuity of metal layers, and interlayer structural discontinuity. Regarding the first... The first piece of nude film For critical structural defects, set corresponding defect determination flags. :

[0119] Where r = 1, 2, ..., q, and q represents the number of structural defect categories involved in the fatal defect veto judgment.

[0120] (1) Determination of through cracks Through-cracks are identified based on crack depth, crack length, crack propagation direction, distance between the crack and the active region, and the spatial connectivity of the crack in continuous fault images.

[0121] A crack marker will penetrate when any of the following conditions are met. Set to 1:

[0122] Alternatively, the crack may span two or more pre-defined structural layers in continuous LF-OCT tomographic images or three-dimensional tomographic structural data, and form a continuous connected path with the surface, back, metal layer, passivation layer, active region, or junction terminal region of the bare sheet.

[0123] in, Indicates the first The maximum crack depth detected on a bare wafer; This indicates the lethal depth threshold corresponding to a through-crack.

[0124] When the crack propagation direction points towards the active region or the junction terminal region, and the minimum distance between the crack and the active region or the junction terminal region satisfies:

[0125] In such cases, the crack can also be classified as a fatal crack. This represents the minimum distance between the crack and the active region or the junction terminal region; This indicates the preset safe distance threshold.

[0126] (2) Deep edge collapse determination Deep edge collapse is determined based on the edge collapse depth, edge collapse area, and distance between the edge collapse and the active region or junction terminal region.

[0127] The deep edge collapse flag will be set when any of the following conditions are met. Set to 1:

[0128]

[0129] or:

[0130] in, Indicates the first Maximum chipping depth of a bare die; Indicates the area of ​​the chipped edge; This represents the minimum distance between the collapsed edge region and the active region or the junction terminal region. , and These represent the corresponding fatality thresholds.

[0131] (3) Determination of severe damage to terminal structure Severe damage to the terminal structure is determined based on the integrity of the terminal extension structure, the residual etching on the mesa, the integrity of the passivation layer, the location of cracks, and the location of edge breakage.

[0132] When the terminal extension structure integrity index is satisfied:

[0133] Alternatively, the residual area of ​​the etched surface meets the following requirements:

[0134] Alternatively, if cracks, chipping, or passivation layer damage are detected extending into the junction terminal propagation region or high electric field region, this will indicate severe damage to the terminal structure. Set to 1.

[0135] in, Indicates the first Integrity index of the terminal extension structure of a bare die; Indicates the area of ​​residual etching on the platform; and These represent the corresponding fatality thresholds.

[0136] (4) Determination of severe discontinuity in the metal layer Severe discontinuity of the metal layer is determined based on the metal layer thickness distribution, metal layer thickness uniformity, minimum metal layer thickness, area of ​​local voids or delamination, and continuity of the metal layer structure.

[0137] The severe discontinuity flag of the metal layer will be set when any of the following conditions are met. Set to 1:

[0138]

[0139] or:

[0140] in, Indicates the minimum thickness of the metal layer; Indicator of metal layer thickness uniformity; Indicates the area of ​​local voids or delaminations within the metal layer region; , and These represent the corresponding fatality thresholds.

[0141] When a metal layer reflection interface interruption, local missing metal layer, or sudden change in metal layer thickness exceeding a preset range is detected in continuous LF-OCT tomographic images, it can also be determined as a severe discontinuity of the metal layer.

[0142] (5) Determination of discontinuity in interlayer structure Discontinuity in interlayer structure is determined based on interlayer continuity, local voids or layer area, and subsurface anomalous reflection intensity.

[0143] The interlayer discontinuity flag will be set when any of the following conditions are met. Set to 1:

[0144]

[0145] or:

[0146] in, Indicates interlayer continuity; Indicates the area of ​​a local cavity or layer; Indicates the intensity of subsurface anomalous reflection; , and These represent the corresponding fatality thresholds.

[0147] When continuous interface separation, void connectivity, or reflection interface interruption is detected between adjacent structural layers in LF-OCT three-dimensional tomographic data, it can also be determined as interlayer structural discontinuity.

[0148] Fatal defect total flag After completing the identification of various fatal structural defects, the first The total critical defect flag of a bare die Represented as:

[0149] Right now:

[0150] when When, it indicates the first If a blank wafer has at least one type of fatal structural defect, it will no longer be included in the ordinary optical structural integrity scoring process, but will be directly classified into the structural risk category or the rejection category.

[0151] when If no structural defects exceeding the fatal threshold are detected, the system continues to calculate the optical structure integrity index based on characteristic parameters such as edge chipping, cracks, abrasion damage layer, metal layer, passivation layer, junction terminal, and interlayer structure, and then proceeds to the subsequent health grading process.

[0152] This invention utilizes the line illumination and parallel acquisition characteristics of LF-OCT to acquire two-dimensional tomographic images or three-dimensional structural data of key areas of a bare wafer in a short time, and extracts structural feature parameters such as edge chipping depth, crack depth, grinding damage layer thickness, metal layer thickness distribution, passivation layer integrity, and terminal structure integrity.

[0153] Step 4: Construct a two-dimensional electro-optic evaluation plane with electrical robustness index as the x-axis and optical structural integrity index as the y-axis.

[0154] For the The two-dimensional electro-optic evaluation coordinates of a single power semiconductor die are represented as follows:

[0155] in, Indicates the first The coordinates of a bare wafer in the two-dimensional electro-optic evaluation plane; Indicates the first Electrical robustness indicators of a bare die; Indicates the first The LF-OCT optical structure integrity index of a bare die.

[0156] Using this method, each wafer is no longer just a simple pass or fail result, but has a unique coordinate point in the two-dimensional evaluation space.

[0157] Step 5: Classify the health of each wafer based on its coordinate position in the two-dimensional electro-optic evaluation plane.

[0158] like Figure 5 As shown, let the electrical robustness threshold be... The optical structure integrity threshold is Then, nude films can be divided into four categories.

[0159] Category 1: High-reliability application bare dies.

[0160] when:

[0161] and:

[0162] and:

[0163] This indicates that the electrical performance and structural integrity of the bare die meet the requirements and it can be used for high-reliability power module packaging.

[0164] Category 2: Using bare film with reduced cost.

[0165] when:

[0166] and:

[0167] and:

[0168] If the condition is good, it indicates that the structure of the bare chip is in good condition, but the electrical performance margin is insufficient. It can be used under derated conditions or undergo re-inspection according to actual needs.

[0169] Category 3: Bare wafers with potential reliability risks.

[0170] when:

[0171] and:

[0172] If the electrical parameters of the die are temporarily met, but LF-OCT testing shows that its structural integrity is insufficient, which may lead to failure risks during packaging stress, thermal cycling, or long-term service.

[0173] Category 4: Removal of uncut films.

[0174] when:

[0175] and:

[0176] or:

[0177] At that time, the bare film is determined to be a discarded bare film.

[0178] For multi-die power modules, the system groups candidates based on the distance between their coordinate points in the two-dimensional electro-optic evaluation plane.

[0179] For any two candidate wafers and Their coordinates are as follows:

[0180]

[0181] The weighted distance between the two coordinate points can be expressed as:

[0182] in, Indicates the first nude film and the first The overall difference distance between bare wafers; Indicates the weight of the electrical dimension; Represents the weights of optical structure dimensions, and satisfies:

[0183] For the same power module's set of bare dies If the set contains For a given set of bare wafers, the average dispersion within the group is defined as:

[0184] The grouping objective is:

[0185] The constraints are:

[0186]

[0187]

[0188]

[0189] in, Represents the optimal set of bare die pairings; This indicates the minimum electrical robustness requirement that allows entry into the grouping process; This indicates the minimum optical structural integrity index that allows entry into the grouping process; This indicates that each power module needs to be selected. A bare film.

[0190] In other words, provided that the requirements for package quantity, package location, electrical threshold, structural threshold, and fatal defect rejection are met, dies with closer two-dimensional coordinate distances are preferentially selected for inclusion in the same power module, such as... Figure 7 As shown.

[0191] This method can reduce the differences in electrical performance and structural health of dies within the same power module to a preset threshold, thereby improving the consistency of current distribution, heat distribution, and service life within the module.

[0192] It should be noted that the objective function for grouping can be adjusted. In addition to minimizing the distance between coordinate points within the group, it can also be used to minimize the maximum distance, minimize the variance, minimize the weighted sum of electrical and structural differences, or maximize the overall reliability score of the module.

[0193] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0194] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for electro-optical fusion health screening and grouping of power semiconductor dies, characterized in that, include: Obtain the identity information and spatial location information of the semiconductor die under test, and bind the identity information and spatial location information; Electrical tests are performed on the bonded power semiconductor die to obtain electrical test parameters, and electrical robustness indices are generated based on the electrical test parameters. LF-OCT line-field optical coherence tomography was performed on the same power semiconductor die under test to obtain LF-OCT tomographic structure data, and structural feature parameters were extracted from the LF-OCT tomographic structure data. Based on the structural feature parameters, an optical structure integrity index was generated. The electrical robustness index and the optical structural integrity index are respectively used as the two coordinate dimensions of the two-dimensional electro-optic evaluation plane to construct the two-dimensional electro-optic evaluation plane, and each power semiconductor die under test is associated with the corresponding coordinate point in the two-dimensional electro-optic evaluation plane. Based on the position of the coordinate points in the two-dimensional electro-optic evaluation plane, the health level of the power semiconductor dies under test is graded and screened, and the power module is grouped before packaging based on the distance between the corresponding coordinate points of multiple candidate dies.

2. The method as described in claim 1, characterized in that, The identity information and spatial location information include wafer number, die number, batch number, test time, wafer coordinates, stage coordinates, LF-OCT scan area coordinates, and packaging target location; The electrical testing of the bonded power semiconductor die to obtain electrical test parameters specifically includes: The test obtains one or more of the following parameters: on-state voltage drop, on-resistance, leakage current, breakdown voltage, threshold voltage, gate charge, turn-on loss, turn-off loss, short-circuit withstand capability, dynamic on-resistance, and dynamic switching response.

3. The method as described in claim 1, characterized in that, The LF-OCT line-field optical coherence tomography scan of the same power semiconductor die under test specifically includes: The LF-OCT system's line field illumination optical system forms a linear illumination area on the surface of the bare die, and interference signals are acquired in parallel. The LF-OCT scan covers one or more of the following areas: the edge area of ​​the die, the area near the scribe line, the front metal layer area, the back metallized area, the passivation layer area, the junction terminal extension area, the polishing and thinning area, and the local suspected damage area.

4. The method as described in claim 1, characterized in that, The extraction of structural feature parameters from the LF-OCT tomographic data specifically includes: Extract one or more of the following from LF-OCT tomographic images: edge chipping depth, edge chipping area, crack depth, crack length, crack propagation direction, distance between crack and active region, grinding damage layer thickness, metal layer thickness distribution, metal layer thickness uniformity, passivation layer integrity, mesa etching residue, junction terminal extension structure integrity, interlayer continuity, local void or delamination area, and subsurface anomalous reflection intensity.

5. The method as described in claim 1, characterized in that, The specific steps of generating electrical robustness indicators based on the electrical test parameters include: The measured values ​​of each electrical test parameter are compared with the preset reference values, the upper limit of allowable and / or the lower limit of allowable to obtain the normalized deviation of each electrical test parameter. The normalized deviation is limited to a preset range to obtain the normalized risk value; Based on the weights of each electrical parameter, the normalized risk values ​​after restrictions are summed in a weighted manner to obtain a comprehensive electrical risk score. The comprehensive electrical risk score is reverse-converted to generate the electrical robustness index.

6. The method as described in claim 1, characterized in that, The specific steps of generating the optical structure integrity index based on the structural feature parameters include: The measured values ​​of each structural characteristic parameter are compared with the allowable thresholds to calculate the normalized risk value of structural defects for each structural characteristic parameter. For structural defects that are location-sensitive, the normalized risk value of the structural defect is corrected according to the amplification factor of the defect location on the reliability risk, so as to obtain the corrected structural risk value. Based on the weights of each structural feature parameter, a weighted sum is calculated on the corrected structural risk value to generate a structural risk score for the bare wafer. Based on the structural risk score, the optical structure integrity index is generated.

7. The method as described in claim 6, characterized in that, Also includes: When any structural feature parameter exceeds the corresponding fatality threshold, the fatal defect flag of the p-th die is set. Set the value to 1 and directly classify the bare wafer into the structural risk category or the exclusion category; when none of the structural defects in all categories meet the corresponding fatality criteria, set the fatality defect flag bit. The value is set to 0, and the p-th bare die is graded and evaluated based on the optical structure integrity index.

8. The method as described in claim 1, characterized in that, The step of classifying and screening the health status of the power semiconductor die under test based on the position of the coordinate point in the two-dimensional electro-optic evaluation plane specifically includes: By setting electrical robustness thresholds and optical structural integrity thresholds, the two-dimensional electro-optic evaluation plane is divided into multiple regions; Dies whose coordinates fall into the high reliability region are classified as high reliability application dies; those falling into the derating region are classified as derating use dies; those falling into the risk region are classified as potential reliability risk dies; and those falling into the rejection region are classified as rejection dies.

9. The method as described in claim 8, characterized in that, The process of grouping power modules before packaging based on the distance between corresponding coordinate points of multiple candidate dies specifically includes: Calculate the weighted distance between any two candidate wafers in the two-dimensional electro-optic evaluation plane; With minimizing the average dispersion within a group as the objective function, and under the conditions of package quantity, package location, electrical threshold, structural threshold, and fatal defect rejection, the die with the closer weighted coordinate point is selected to enter the same power module.

10. The method as described in claim 9, characterized in that, The weighted coordinate point distance is: in, Indicates the first nude film and the first The overall difference distance between bare wafers; Indicates the weight of the electrical dimension; Represents the weights of optical structure dimensions, and satisfies: and Indicates the first nude film and the first The coordinates of a bare wafer; The objective function is: The constraints are: in, Represents the optimal set of bare die pairings; This indicates the minimum electrical robustness requirement that allows entry into the grouping process; This indicates the minimum optical structural integrity index that allows entry into the grouping process; This indicates that each power module needs to be selected. A bare film.

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