Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device. A second groove structure is covered on a shallow trench isolation structure. By using the relatively wide and slow topographic features of the shallow trench isolation structure, combining the high-precision etching and topographic control ability of a post-LOCOS (local oxidation of silicon) hard mask layer, the filling effect of conductive material is significantly optimized, and the early bridging of the conductive material on the side wall of the second groove is effectively inhibited, so that the generation of seams or voids in the conductive material is avoided, the film densification and structure uniformity of the conductive material are improved, the process stability is improved, and the early chip failure risk caused by incomplete filling is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device process technology, specifically relating to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] MTI (Middle Trench Isolation), DTI (Deep Trench Isolation), and STI (Shallow Trench Isolation) are trench isolation structure technologies used in semiconductor manufacturing for device isolation. In some semiconductor devices, MTI is used to connect the buried layer (NBL), DTI is used to connect to the substrate, and STI (Shallow Trench Isolation) is used to isolate different device regions.

[0003] In existing technologies, the formation sequence of isolation structures is typically as follows: first, MTI (Medium-to-Insulation Layer), then DTI (Digital-to-Insulation Layer), and finally STI (Solid-to-Insulation Layer). However, because the conductive material within the MTI undergoes high-temperature thermal processing during the subsequent DTI and STI processes, N-type dopants (such as phosphorus) within the MTI can easily diffuse and escape from the highly doped conductive material. This is particularly detrimental to the subsequent gate oxide (GOX) process, which has extremely high quality requirements, as the gate oxide process is highly sensitive to doping contamination. Any phosphorus escape and cross-contamination can severely damage the integrity of the gate oxide layer and the reliability of the device.

[0004] In the manufacturing process of isolation structures, by transferring the MTI fabrication process to the DTI and STI fabrication processes, the sides of the MTI are made to contact the STI region or the MTI is placed within the STI region, thus surrounding the apex of the MTI with STI oxide. This improves the integrity of the barrier layer at the top sidewall corner of the trench and alleviates the problem of N-type dopant diffusion. By transferring the MTI fabrication process to the Local Oxidation (LOCOS) process, the main DTI and STI (Shallow Trench Isolation) thermal processes are avoided, effectively improving the problem of N-type dopant diffusion in the MTI. However, since no annealing process is performed, the N-type dopant concentration in this MTI is extremely high, and there is still a risk of diffusion during the most critical gate oxide process in CMOS. This can lead to contamination risks on wafer devices in the same furnace tube, degrade the quality of the gate oxide layer, and may also cause contamination on the furnace tube itself, resulting in the risk of wafer scrap.

[0005] It is worth noting that the structural layout of MTI in the above scheme is prone to gaps or voids due to uneven filling of the high aspect ratio trenches during the subsequent conductive material filling process, which affects the process stability and device yield.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a method for manufacturing a semiconductor device and a semiconductor device in which the method optimizes the formation process of the second trench structure (MTI) to improve the filling quality of the conductive material, eliminate fine-slit defects, improve process stability and device yield while avoiding dopant diffusion and contamination.

[0008] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0009] A method for manufacturing a semiconductor device, comprising:

[0010] A semiconductor body is provided, the semiconductor body including a substrate, a buried layer on the substrate and an epitaxial layer on the buried layer;

[0011] A first trench is formed in the semiconductor body, and a first trench structure is formed in the first trench, the first trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer;

[0012] A device region is formed in the semiconductor body;

[0013] An oxide isolation structure is formed at least on a portion of the surface of the device region;

[0014] A shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure including a target shallow trench isolation structure;

[0015] A second trench is formed in the semiconductor body after the formation of the oxide isolation structure, which partially or completely covers the target shallow trench isolation structure, and the second trench extends from the top surface of the epitaxial layer to the buried layer.

[0016] A second trench structure is formed in the second trench, the second trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0017] In one or more embodiments of the present invention, the target shallow trench isolation structure is located on both sides of the second trench, and the second trench covers part or all of the target shallow trench isolation structure;

[0018] The step of forming the second trench includes:

[0019] A second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor body;

[0020] The second hard mask layer, the third nitride layer, the second nitride layer, and the semiconductor body are etched to form a second trench body extending to the buried layer, wherein the target shallow trench isolation structure is attached to both sides of the second trench body.

[0021] The third nitride layer and the second nitride layer on both sides of the second trench body are etched back;

[0022] The second trench is formed by removing the second hard mask layer and partially or completely removing the target shallow trench isolation structure that is attached to the second trench body.

[0023] In one or more embodiments of the present invention, the thickness of the third nitride layer and the second nitride layer etched back on both sides of the second trench body is not less than the width of the target shallow trench isolation structure that is in contact with the second trench body; and / or,

[0024] The thickness of the third nitride layer and the second nitride layer on both sides of the second trench is 2500 Å to 3000 Å.

[0025] In one or more embodiments of the present invention, the width of the second trench body is 0.3 μm to 0.7 μm; and / or,

[0026] The width of the target shallow trench isolation structure is not less than 0.28; and / or,

[0027] The width of the second groove is 0.5μm to 1.0μm.

[0028] In one or more embodiments of the present invention, the step of forming a second trench structure in the second trench includes:

[0029] A second barrier layer is formed on the sidewall of the second trench, and a second conductive material is deposited to fill the second trench;

[0030] Remove the second conductive material from the surface of the second nitride layer;

[0031] Remove a portion of the second conductive material within the second trench, ensuring that the surface of the remaining second conductive material is not lower than the surface of the semiconductor body.

[0032] Remove the third nitride layer and the second nitride layer.

[0033] In one or more embodiments of the present invention, after removing a portion of the second conductive material in the second trench, the method further includes the step of forming an oxide protective layer on the surface of the second conductive material.

[0034] In one or more embodiments of the present invention, the target shallow trench isolation structure is located in the middle of the second trench, and the second trench covers the entire target shallow trench isolation structure;

[0035] The step of forming the second trench includes:

[0036] A second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor body;

[0037] The second hard mask layer, the third nitride layer, the second nitride layer, and the target shallow trench isolation structure are etched to form the prototype of the second trench;

[0038] Based on the second trench prototype, the semiconductor body is etched to form a second trench extending to the buried layer.

[0039] In one or more embodiments of the present invention, the target shallow trench isolation structure is located in the middle of the second trench, and the second trench covers the entire target shallow trench isolation structure;

[0040] The step of forming the second trench includes:

[0041] A second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor body;

[0042] The second hard mask layer, the third nitride layer, the second nitride layer, and the target shallow trench isolation structure are etched to form the prototype of the second trench;

[0043] Based on the second trench prototype, the semiconductor body is etched for the first time to form a second trench opening extending to the epitaxial layer. The second trench opening includes an upper part with a first width and a lower part with a second width that is smaller than the first width.

[0044] An oxide sidewall is formed on the upper sidewall of the second trench opening;

[0045] Based on the second trench opening, the semiconductor body is etched again to form a second trench body extending to the buried layer;

[0046] The oxide sidewalls are removed to form the second trench.

[0047] In one or more embodiments of the present invention, the width of the target shallow trench isolation structure is 0.3 μm to 0.5 μm; and / or,

[0048] The width of the second groove is 0.5μm to 1.0μm.

[0049] In one or more embodiments of the present invention, the step of forming a second trench structure in the second trench includes:

[0050] A second barrier layer is formed on the sidewall of the second trench, and a second conductive material is deposited to fill the second trench;

[0051] Remove the second conductive material from the surface of the second hard mask layer;

[0052] Remove a portion of the second conductive material within the second trench, ensuring that the surface of the remaining second conductive material is not lower than the surface of the semiconductor body.

[0053] Remove the second hard mask layer, the third nitride layer, and the second nitride layer.

[0054] In one or more embodiments of the present invention, after removing a portion of the second conductive material in the second trench, the method further includes the step of forming an oxide protective layer on the surface of the second conductive material.

[0055] In one or more embodiments of the present invention, the step of forming an oxide protective layer on the surface of the second conductive material includes:

[0056] The second conductive material in the second trench is etched so that the surface of the second conductive material is higher than the surface of the semiconductor body.

[0057] Using the third nitride layer as a mask, a wet oxidation process is used to oxidize the top of the second conductive material to form an oxide protective layer;

[0058] Remove all nitride layers from the surface of the semiconductor substrate.

[0059] In one or more embodiments of the present invention, after forming an oxide protective layer on the surface of the second conductive material, the method further includes:

[0060] The gate oxidation process is performed under the condition that the second trench structure is protected by the oxide protective layer.

[0061] A semiconductor device, comprising:

[0062] A semiconductor body includes a substrate, a buried layer on the substrate, and an epitaxial layer on the buried layer. A device region is formed in the semiconductor body, and an oxide isolation structure is formed on a portion of the surface of the device region.

[0063] A first trench extends from the top surface of the epitaxial layer to the substrate;

[0064] A first trench structure is disposed within a first trench, the first trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer;

[0065] A shallow trench isolation structure is formed within the epitaxial layer of the semiconductor body, the shallow trench isolation structure being configured to isolate the device region, the shallow trench isolation structure including a target shallow trench isolation structure;

[0066] The second trench is formed within the semiconductor body and partially or completely covers the target shallow trench isolation structure. The second trench extends from the top surface of the epitaxial layer to the buried layer and is configured to be wider at the top and narrower at the bottom.

[0067] A second trench structure is disposed in the second trench, and the second trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0068] A semiconductor device is manufactured using the semiconductor device manufacturing method described above.

[0069] Compared with the prior art, the semiconductor device manufacturing method and semiconductor device of the present invention cover the shallow trench isolation structure with the second trench structure. By utilizing the relatively gentle morphological characteristics of the shallow trench isolation structure, combined with the high-precision etching and morphological control capabilities of the hard mask layer after the local oxidation (LOCOS) process, the filling effect of the conductive material is significantly optimized, effectively suppressing the premature bridging of the conductive material on the sidewall of the second trench. This avoids the generation of gaps or voids inside the conductive material, improves the film density and structural uniformity of the conductive material, enhances process stability, and reduces the risk of early chip failure due to incomplete filling.

[0070] The semiconductor device manufacturing method and semiconductor device of the present invention, while retaining the advantages of existing technologies in suppressing doping diffusion, further solve the problems of conductive material filling defects and process integration, and significantly improve the manufacturing yield and long-term reliability of the device. Attached Figure Description

[0071] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1 This is a process flow diagram of a semiconductor device manufacturing method according to an embodiment of the present invention;

[0073] Figures 2a to 2zfor Figure 1 A schematic diagram of the process steps of the semiconductor device manufacturing method in the illustrated embodiment;

[0074] Figure 3 This is a process flow diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention;

[0075] Figures 4a-4j for Figure 3 A schematic diagram of the process steps of the semiconductor device manufacturing method in the illustrated embodiment;

[0076] Figure 5 This is a process flow diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention;

[0077] Figures 6a-6f for Figure 5 A schematic diagram of the process steps for manufacturing a semiconductor device in the illustrated embodiment. Detailed Implementation

[0078] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0079] As mentioned in the background section, medium trench isolation (MTI), deep trench isolation (DTI), shallow trench isolation (STI), and localized oxidation (LOCOS) are mainstream device isolation technologies used to achieve electrical isolation between adjacent devices and prevent leakage and signal crosstalk. Among them, the location, formation timing, and doping control of MTI are key technical factors affecting device performance, yield, and reliability.

[0080] Existing technologies have disclosed various integration schemes for MTI and isolation structures.

[0081] Patent application number 202311059503.1 proposes a process for forming MTI after STI (Surface Mount Technology). It adjusts the traditional sequence "MTI→DTI→STI" to "DTI→STI→MTI," allowing the MTI sidewalls to contact or embed within the STI region, with the apex surrounded by STI oxide. This improves the integrity of the barrier layer at the top sidewall corners of the trench and alleviates the N+ polysilicon doping diffusion problem. However, this solution still relies on traditional hard mask technology, which is prone to creating gaps during polysilicon filling. There is still room for improvement in process stability and chip yield.

[0082] Patent application number 202511460916X discloses a process for forming MTI after LOCOS, which avoids the main DTI and STI (Shallow Trench Isolation) thermal processes and prevents N+ polysilicon from doping and diffusing on the sidewalls of the MTI.

[0083] The patent application number 202512056187.8 focuses on doping contamination control, pointing out that if the N-type doped polysilicon inside the MTI skips the DTI and STI heat treatment, phosphorus in the highly doped polysilicon is prone to escape and diffuse during the gate oxidation (GOX) process, causing cross-contamination. The GOX process is highly sensitive to doping contamination, which directly affects the reliability of the device.

[0084] In the second and third schemes mentioned above, the MTI is formed in the active region rather than the STI region, which does not make full use of the isolation advantage of the STI structure. In the subsequent conductive material filling process, gaps or voids are easily generated due to uneven filling of the high aspect ratio trench, which affects the process stability and device yield.

[0085] Based on this, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, wherein a second trench structure is covered with a shallow trench isolation structure. By utilizing the relatively gentle morphological characteristics of the shallow trench isolation structure, combined with the high-precision etching and morphological control capabilities of the hard mask layer after the local oxidation (LOCOS) process, the filling effect of the conductive material is significantly optimized, effectively suppressing premature bridging of the conductive material on the sidewall of the second trench, thereby avoiding the generation of seams or voids inside the conductive material, improving the film density and structural uniformity of the conductive material, improving process stability, and reducing the risk of early chip failure due to incomplete filling.

[0086] like Figure 1 As shown, a method for manufacturing a semiconductor device according to an embodiment of the present invention specifically includes the following steps:

[0087] S1 provides a semiconductor body. The semiconductor body includes a substrate, a buried layer on the substrate, and an epitaxial layer on the buried layer.

[0088] S2, a first trench is formed in the semiconductor body, and a first trench structure is formed in the first trench. The first trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0089] S3 forms the device region within the semiconductor body.

[0090] S4, an oxide isolation structure is formed at least on a portion of the surface of the device region.

[0091] S5, forming a shallow trench isolation structure in the semiconductor body, the shallow trench isolation structure including the target shallow trench isolation structure.

[0092] S6, forming a second trench in the semiconductor body after the oxide isolation structure is formed, partially or completely covering the target shallow trench isolation structure. The second trench extends from the top surface of the epitaxial layer to the buried layer.

[0093] S7, a second trench structure is formed in the second trench. The second trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0094] The target shallow trench isolation structure is located on both sides of the second trench, and the second trench covers part or all of the target shallow trench isolation structure.

[0095] Based on this, the steps for forming the second trench include:

[0096] S61, a second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor substrate.

[0097] S62, etch the second hard mask layer, the third nitride layer, the second nitride layer and the semiconductor body to form a second trench body extending to the buried layer, wherein target shallow trench isolation structures are attached to both sides of the second trench body.

[0098] S63, the third nitride layer and the second nitride layer on both sides of the second trench body are etched back.

[0099] S64, remove the second hard mask layer and partially or completely remove the target shallow trench isolation structure that is attached to the second trench body to form the second trench.

[0100] This embodiment forms a second trench body between two adjacent target shallow trench isolation structures. Utilizing existing trench etching process formulations, the etching rate of the semiconductor body is faster than that of the shallow trench isolation structure. This allows most of the target shallow trench isolation structures on both sides to be retained after the second trench body is formed. Finally, by removing part or all of the remaining shallow trench isolation structure, a second trench with a wide top and narrow bottom structure is formed. This significantly optimizes the subsequent filling of conductive materials, effectively suppresses premature bridging of conductive materials on the sidewalls of the second trench, avoids the generation of seams or voids inside the conductive material, improves the film density and structural uniformity of the conductive material, enhances process stability, and reduces the risk of early chip failure due to incomplete filling.

[0101] In this embodiment, before removing part or all of the remaining shallow trench isolation structure, the third nitride layer and the second nitride layer on both sides of the second trench body are first etched back to expand the width of the second trench body at the nitride layer, so that the remaining shallow trench isolation structure is partially or completely exposed, thereby facilitating the subsequent removal of the shallow trench isolation structure located below the nitride layer.

[0102] Figures 2a to 2z It shows Figure 1 The illustrated embodiment shows a schematic diagram of the process steps in the manufacturing method of the semiconductor device. This embodiment... Figures 2a to 2z The accompanying drawings are merely illustrative, showing a cross-section of a portion of the trench structure. The manufacturing method of the semiconductor device and the manufactured semiconductor device of this invention should not be affected by the illustrative drawings, thus lest they affect the scope of protection of this invention. The following description, in conjunction with... Figures 2a to 2z The manufacturing method of the semiconductor device according to the embodiments of the present invention will be described in detail.

[0103] like Figure 2a As shown, a semiconductor body 10 is provided. The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having a first doping type disposed on the buried layer 12.

[0104] The second doping type is the opposite of the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or combinations thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof.

[0105] In some embodiments, the thickness of the epitaxial layer 13 is, for example, 8 μm to 15 μm, and it can be used to form different device regions.

[0106] In some embodiments, the buried layer 12 may have a blanket structure having a horizontal extension substantially the same as that of the substrate 11, laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure.

[0107] In some embodiments, the semiconductor body 10 may be formed by the following steps: providing a substrate 11; forming a pad oxide layer on the surface of the substrate 11; implanting a buried layer 12; removing the pad oxide layer; growing a sacrificial oxide layer; removing the sacrificial oxide layer; and growing an epitaxial layer 13. The pad oxide layer may be removed, for example, by wet removal using diluted hydrofluoric acid (DHF). The sacrificial oxide layer may be removed, for example, by wet removal using buffer oxide etching (BOE) combined with diluted hydrofluoric acid (DHF). However, it should be understood that the semiconductor body 10 may be fabricated using any relevant process of the prior art, or a semiconductor body 10 having a substrate 11, a buried layer 12, and an epitaxial layer 13 may be purchased directly; the present invention does not impose excessive limitations.

[0108] like Figure 2b As shown, a first hard mask layer 14 is formed on the surface of the semiconductor body 10, i.e., the epitaxial layer 13. Specifically, this step may include growing or depositing a pad oxide layer 14a on the surface of the epitaxial layer 13, and depositing a first nitride layer 14b on the surface of the pad oxide layer 14a. The pad oxide layer 14a is, for example, formed of silicon dioxide with a thickness of 100 Å to 200 Å, and the first nitride layer 14b is, for example, formed of silicon nitride with a thickness of 1600 Å.

[0109] Understandably, the pad oxide layer 14a can be densified to achieve better performance of the first hard mask layer 14.

[0110] like Figure 2c As shown, a first trench 21a and an isolation trench 21b are formed. Specifically, a first soft mask layer 15 can be used to etch the first hard mask layer 14 and the semiconductor body 10 to form the first trench 21a and the isolation trench 21b in the first hard mask layer 14 and the semiconductor body 10, penetrating the first hard mask layer 14 and extending to the substrate 11. In some embodiments, the first soft mask layer 15 can be a photoresist. After the first trench 21a and the isolation trench 21b are etched and formed, the first soft mask layer 15 is stripped off.

[0111] The first trench 21a has a first width w1 and a first depth, and the isolation trench 21b has a second width w2, where w1 > w2. Both the first trench 21a and the isolation trench 21b extend from the top surface of the epitaxial layer 13 into the substrate 11, and the first depth is greater than the second depth.

[0112] like Figure 2d and Figure 2eAs shown, a first barrier layer is formed covering the sidewalls and bottom wall of the first trench 21a and the isolation trench 21b. The first barrier layer includes a first oxide layer 22 and a dielectric layer 23. The thickness of the first oxide layer 22 is, for example, 4000 Å. In some embodiments, the first oxide layer 22 may be formed by a thermal oxidation process. In other embodiments, a first portion 221 of the first oxide layer 22 may be formed at the bottom of the first trench 21a by a thermal oxidation process, and a second portion 222 of the first oxide layer 22 may be formed on the sidewall of the first trench 21a by a HARP (High Aspect Ratio Process). The thickness of the first portion 221 is less than the thickness of the second portion 222. The combination of thermal oxidation and HARP processes to create different thicknesses for the first portion 222 on the sidewall and the second portion 221 on the bottom wall of the first trench 21a is more conducive to reducing the structural stress of the first trench 21a. The same method can be used to form the first barrier layer on the sidewall and bottom wall of the isolation trench 21b.

[0113] exist Figure 2d The first oxide layer 22a in the first trench 21a and the first oxide layer 22b in the isolation trench 21b are illustrated by way of example. And for ease of understanding, the first portion 221 and the second portion 222 in the first oxide layer 22a are illustrated by way of example.

[0114] like Figure 2e As shown, a dielectric layer 23 is deposited to fill the first trench 21a and the isolation trench 21b. The dielectric layer 23a deposited in the first trench 21a belongs to the subsequently formed first trench structure 20a. The dielectric layer 23b deposited in the isolation trench 21b belongs to the subsequently formed isolation trench structure 20b.

[0115] Specifically, the dielectric layer 23 can be deposited using the HARP process. The thickness of the dielectric layer 23 can be 6000 Å, in which case the wider first trench 21a still has a space of, for example, 0.7 μm to 0.9 μm, and the narrower isolation trench 21b still has a space of, for example, about 0.1 μm.

[0116] like Figure 2f As shown, anisotropic etching is performed on the first trench 21a, forming a V-shaped notch at the top of the first trench 21a during the etching process. In some embodiments, anisotropic etching can be performed by ion bombardment. Because the first trench 21a has a relatively wide first width w1, more ions enter the first trench 21a, resulting in the complete removal of the dielectric layer 23a and the first oxide layer 22a at the bottom of the first trench 21a. That is, as... Figure 2fAs shown in region A, the bottom of the first trench 21a is opened. Since the isolation trench 21b has a narrower second width w2, fewer ions enter its interior, allowing the first oxide layer 22b at the bottom of the isolation trench 21b to be completely preserved, and the dielectric layer 23b at the bottom of the isolation trench 21b can still retain a thickness of about 1400 Å.

[0117] In some embodiments, after the dielectric layer 23 is formed, the dielectric layer 23 and the first oxide layer 22 can be densified by an annealing process to achieve a better isolation effect for the formed first trench structure and the isolation trench structure.

[0118] like Figure 2g As shown, a first conductive material 24 with a first doping type is deposited, filling the first trench 21a and the isolation trench 21b. The first conductive material 24a deposited in the first trench 21a belongs to the subsequently formed first trench structure 20a, and the first conductive material 24b deposited in the isolation trench 21b belongs to the subsequently formed isolation trench structure 20b. Since the bottom of the first trench 21a is open, the first conductive material 24a in the first trench 21a contacts the substrate 11 and achieves electrical connection. In some embodiments, since both the first trench 21a and the isolation trench 21b have a certain width, the deposition of the first conductive material 24 within the first trench 21a and the isolation trench 21b forms narrow gaps as shown in regions B1 and B2. Because these gaps are located deep within the first trench 21a and the isolation trench 21b, they will not be opened in subsequent processes; that is, these gaps will not affect the performance of the device.

[0119] In this embodiment, the first conductive material 24 is heavily doped P-type polycrystalline silicon (P+poly). The heavily doped P-type polycrystalline silicon can be prepared by ion implantation followed by annealing of intrinsic polycrystalline silicon, or by in-situ doping during polycrystalline silicon deposition. The preparation of heavily doped P-type polycrystalline silicon is a prior art and will not be described in detail in this invention.

[0120] like Figure 2h As shown, excess first conductive material 24 and dielectric layer 23 can be removed by chemical mechanical polishing (CMP). For example, the first nitride layer 14b can be used as a stop layer in the CMP process to remove the first conductive material 24 and dielectric layer 23 from its surface. The loss of the first nitride layer 14b depends on the selective rate of polishing. When the deposited first nitride layer 14b has a thickness of 1600 Å, this step can control the loss of the first nitride layer 14b to at most about 600 Å to retain sufficient first nitride layer 14b.

[0121] During the deposition of the first conductive material 24, a portion of the first conductive material 24 may also be deposited on the substrate 11 of the semiconductor body 10. In this step, it is also necessary to remove the first conductive material 24 from the substrate 11 to achieve better wafer warpage and lower stress. In some embodiments, the first conductive material 24 on the substrate 11 can be removed by a wet process.

[0122] like Figure 2i As shown, a first hard mask layer 14 is used as an etching protection layer to perform a back etching process on the first conductive material 24. Specifically, in this step, the etching depth of the first conductive material 24 in the first trench 21a and the isolation trench structure 21b can be adjusted according to the residual amount of the first nitride layer 14b (e.g., Figure 2i The etching depths of regions C1 and C2 are measured, ensuring that no excess first conductive material 24 remains on the surface of the first nitride layer 14b. In some embodiments, this step can be performed using an anisotropic plasma dry etching process. The normal loss of the first nitride layer 14b is less than 100 Å.

[0123] It should be noted that, in this step, the first conductive material 24 retained in the first trench 21a and the isolation trench structure 21b should be at least flush with the pad oxide layer 14a. In a preferred embodiment, such as Figure 2i and Figure 2j As shown, the retained first conductive material 24 may extend slightly beyond the surface of the pad oxide layer 14a to facilitate subsequent electrical extraction from the substrate 11.

[0124] In some embodiments, only the first trench 21a and the first trench structure 20a therein may be formed for electrical outtake from the substrate 11.

[0125] like Figure 2j As shown, the first nitride layer 14b on the surface of the semiconductor body 10 is removed. This step is achieved, for example, by a wet process using H3PO4 (phosphoric acid), retaining the first oxide layer 22a, dielectric layer 23a, and first conductive material 24a in the first trench 21a to form the first trench structure 20a; and retaining the first oxide layer 22b, dielectric layer 23b, and first conductive material 24b in the isolation trench 21b to form the isolation trench structure 20b.

[0126] It should be noted that, since the initial thickness of the first nitride layer 14b is small in this embodiment of the invention, and the thickness of the first nitride layer 14b is further reduced after the aforementioned steps, the time consumed by the phosphoric acid process in this step can be shortened.

[0127] like Figure 2k As shown, after forming the first trench structure 20a and the isolation trench structure 20b, the device region and the shallow trench isolation structure 30 / 30' are formed.

[0128] In some embodiments, the device region includes a first region AA and a second region HV. The first region AA and the second region HV can be electrically isolated by a trench isolation structure composed of a first trench structure 20a formed in the foregoing steps, an isolation trench structure 20b, and a second trench structure formed in subsequent steps. Figure 2k In the example shown, only the first trench structure 20c represents the trench isolation structure that isolates the first region AA and the second region HV.

[0129] The first region AA can be used to form the first device, and the second region HV can be used to form the second device. The operating voltage of the second device is higher than that of the first device. For example, the second device can be a medium-voltage device or a high-voltage device, and the first device can be a low-voltage device. For example, the operating voltage of the low-voltage device is less than 1.5V, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0130] The first region AA may include a first implantation region 41a with a second doping type and a second implantation region 41b with a first doping type. The second region HV may include a third implantation region 42a with a second doping type and a fourth implantation region 42b with a first doping type. It should be understood that, corresponding to the operating voltage of the second device being higher than that of the first device, the third implantation region 42a and the fourth implantation region 42b should have a deeper ion implantation depth than the first implantation region 41a and the second implantation region 41b. That is, the depth to which the first implantation region 41a and the second implantation region 41b extend from the surface of the semiconductor body 10 into the epitaxial layer 13 is less than the extension depth of the third implantation region 42a and the fourth implantation region 42b.

[0131] Different injection zones, as well as injection zones and first trench 21a and isolation trench 21b, can be electrically isolated by shallow trench isolation structure 30.

[0132] The device area and shallow trench isolation structure 30 can be formed with reference to any process of the prior art, and will not be described in detail in this invention.

[0133] like Figure 2l As shown, a second nitride layer 14b' is deposited on the surface of the pad oxide layer 14a. The thickness of the second nitride layer 14b' can be 1000 Å.

[0134] like Figure 2mAs shown, an oxide isolation structure 50 is formed. In some embodiments, multiple oxide isolation structures 50 may be formed that partially overlap with the surface of each implanted region. That is, on the surface of the semiconductor body 10, each implanted region is in contact with the oxide isolation structure 50 or the pad oxide layer 14a. The oxide isolation structure 50 may have a thickness of 1000 Å-3000 Å. Figure 2m The diagram illustrates, for example, the oxide isolation structure 50a on the surface of the first implantation region 41a, the oxide isolation structure 50b on the surface of the second implantation region 41b, the oxide isolation structure 50c on the surface of the third implantation region 42a, and the oxide isolation structure 50d on the surface of the fourth implantation region 42b. Electrical isolation between the implantation regions can be achieved through the oxide isolation structures 50.

[0135] In some embodiments, the formation of the oxide isolation structure 50 may include the following steps: forming openings in the second nitride layer 14b' and the pad oxide layer 14a to expose the surfaces of each implanted region portion; and forming the oxide isolation structure 50 at each opening using, for example, a local oxidation of silicon (LOCOS) process. Figure 2m As shown, the oxide isolation structure 50 is embedded in the surface of the semiconductor body 10, which improves the isolation effect.

[0136] like Figure 2n As shown, a third nitride layer 14b” is deposited to cover the oxide isolation structure 50, and a second hard mask layer 14'' is deposited. It should be noted that, in Figure 2n In the illustrated embodiment, the third nitride layer 14b” may be made of the same material as the second nitride layer 14b’. That is, after the third nitride layer 14b” is formed, the third nitride layer 14b” may be connected to the second nitride layer 14b’. The third nitride layer 14b” may have a thickness of at least 500 Å to provide reliable protection for the localized oxide structure 50 of silicon.

[0137] In some embodiments, before depositing the third nitride layer 14b", the silicon oxynitride film on the surface of the second nitride layer 14b' is cleaned by the DHF process to avoid it affecting the formation of the subsequent second trench structure.

[0138] In some embodiments, the second hard mask layer 14'' can be a TEOS hard mask layer, which can have a thickness of 2500 Å.

[0139] In some embodiments, only the third nitride layer 14b may be deposited to protect the oxide isolation structure 50.

[0140] like Figure 2oAs shown, the second trench 61 is etched between two adjacent target shallow trench isolation structures 30'. Specifically, the second hard mask layer 14'', the third nitride layer 14b", the second nitride layer 14b', and the pad oxide layer 14a are etched first to expose the semiconductor body 10 and the corresponding two target shallow trench isolation structures 30'.

[0141] like Figure 2p and Figure 2q As shown, since the second trench 61 initially etched is located between the two target shallow trench isolation structures 30', the etching rate of the semiconductor body 10 in the existing trench etching process formulation is faster than the etching rate of the target shallow trench isolation structures 30'. Therefore, during the etching of the semiconductor body 10 to form the second trench body 61' extending to the buried layer 12, the etching depth of the semiconductor body 10 between the two target shallow trench isolation structures 30' is deeper, while the etching depth of the target shallow trench isolation structures 30' is very shallow. In the initial stage of etching, such as Figure 2p As shown, the top of the target shallow trench isolation structures 30' on both sides of the second trench body 61' near the corner of the second trench body 61' will become rounded due to partial etching. Continue etching, as... Figure 2q As shown, the second trench body 61' extending to the buried layer 12 is finally formed.

[0142] In this embodiment, the width of the second trench body 61' is 0.3μm~0.7μm; the width of the target shallow trench isolation structure 30' is not less than 0.28μm.

[0143] In some embodiments, the bottom of the second trench body 61' may contact the buried layer 12 or partially penetrate into the interior of the buried layer 12. Preferably, the bottom of the second trench body 61' penetrates into the buried layer 12 to a depth of less than 1 μm to avoid excessive outward diffusion of dopants from the subsequently filled conductive material, which could lead to an increase in the doping concentration of the local buried layer 12.

[0144] In some embodiments, this step may be performed by etching using a second soft mask layer (not shown) to form the second trench body 61'. The second soft mask layer may also be photoresist, and is peeled off after the second trench body 61' is formed.

[0145] like Figure 2rAs shown, phosphoric acid (H3PO4) is used to etch back the third nitride layer 14b” and the second nitride layer 14b’ on both sides of the second trench body 61’. The etch back thickness is not less than the width of the target shallow trench isolation structure 30’ that is attached to the second trench body 61’. In this embodiment, the etch back thickness is 2500Å~3000Å, preferably 3000Å. The second hard mask layer 14’’ serves as an etching protection layer for the third nitride layer 14b” and the second nitride layer 14b’. This etch back process is the benchmark process for device manufacturing. Experiments have verified that the etch back of the nitride layer has good controllability.

[0146] like Figure 2s As shown, the second hard mask layer 14'' and the target shallow trench isolation structure 30' that is attached to the second trench body 61' are removed to form the second trench 61. The second trench 61 has a structure that is wider at the top and narrower at the bottom, and the width of the second trench 61 is 0.5μm~1.0μm.

[0147] For example, when the second hard mask layer 14'' is a TEOS hard mask layer, the TEOS hard mask layer and the target shallow trench isolation structure 30' can be removed using BOE solution (buffered oxide etchant) or diluted hydrofluoric acid (DHF).

[0148] Specifically, the TEOS hard mask layer is etched at 2800 Å using DHF or BOE wet etching. If the width (CD) of the side target shallow trench isolation structure 30' is much greater than 3000 Å, the remaining target shallow trench isolation structures 30' on both sides of the second trench body 61' are partially removed; if the width of the side target shallow trench isolation structure 30' is small (e.g., a minimum of 0.28 μm), the remaining target shallow trench isolation structures 30' on both sides of the second trench body 61' can be completely removed. Simultaneously, the top TEOS hard mask layer will be completely removed, thus the subsequent TEOS hard mask layer removal step can be omitted.

[0149] It is understood that in this embodiment, except for the two sides of the second trench body 61', all other shallow trench isolation structures 30 are protected by nitride layers.

[0150] In some embodiments, prior to DHF or BOE wet etching, a 110 Å sacrificial oxide layer may be grown on the sidewall of the second trench body 61' to smooth the trench sidewall and remove etching damage.

[0151] like Figure 2t As shown, a second barrier layer 62 is grown on the sidewall and bottom wall of the second trench 61.

[0152] In some embodiments, the second oxide layer may be grown directly on the sidewalls and bottomwalls of the second trench 61 to form the second barrier layer 62, in which case the second oxide layer may have a thickness of, for example, 500 Å.

[0153] In some other embodiments, a sacrificial oxide layer with a thickness of, for example, 110 Å is first formed on the sidewalls and bottom wall of the second trench 61 before the second oxide layer is formed, and the sacrificial oxide layer is removed by wet process to improve the flatness of the bottom wall and sidewall of the second trench 61.

[0154] In some other embodiments, a fourth nitride layer of, for example, 100 Å to 300 Å may be formed on the second oxide layer after growing, for example, a second oxide layer of 110 Å to 200 Å, thereby improving the isolation effect.

[0155] like Figure 2u As shown, the buried layer 12 is exposed by etching the second barrier layer 62 on at least part of the bottom wall of the second trench 61, which facilitates the subsequent electrical connection between the buried layer 12 and the surface of the semiconductor body 10.

[0156] It should be noted that the loss of the nitride layer should be as small as possible in this step. Typically, this loss is less than 100 Å. Since there will be a step in the second trench 61 due to the removal of the shallow trench isolation structures on both sides, the remaining thickness of the second barrier layer 62 may be lower than expected. However, given that the subsequent heat treatment processes are minimal, even if the thickness is thin, the outward diffusion of subsequent dopants can still be effectively controlled.

[0157] like Figure 2v As shown, a second conductive material 63 with a second doping type is deposited, such that the second conductive material 63 fills the second trench 61. For example, the thickness of the second conductive material 63 is, for instance, 8000 Å to fill the second trench 61. Because the upper portion of the second trench 61 is wider, good filling of the second conductive material 63 can be achieved, and the resulting gap depth can be controlled to a relatively deep position or be negligible.

[0158] In this embodiment, the second conductive material 63 is heavily doped N-type polycrystalline silicon (N+poly). The heavily doped N-type polycrystalline silicon can be prepared by ion implantation followed by annealing of intrinsic polycrystalline silicon, or by in-situ doping during polycrystalline silicon deposition. The preparation of heavily doped N-type polycrystalline silicon is a prior art and will not be described in detail in this invention.

[0159] In step 2w, excess second conductive material 63 on the surface of the third nitride layer 14b” is removed. Specifically, the third nitride layer 14b” can be used as a stop layer for this step, and the second conductive material 63 on the surface of the third nitride layer 14b” can be removed by CMP process. More specifically, in some embodiments, the thickness loss of the third nitride layer 14b” should be ensured to be less than 300 Å, so that a sufficiently thick mixed layer is retained on the surface of the oxide isolation structure 50.

[0160] Similar to the deposition of the first conductive material 24, a portion of the second conductive material 63 may also be deposited on the substrate 11 of the semiconductor body 10 during the deposition of the second conductive material 63. In some embodiments, it is also necessary to remove the second conductive material 63 from the substrate 11 of the semiconductor body 10. The second conductive material 63 on the substrate 11 is removed by wet etching, for example, using a diluted mixture of hydrofluoric acid and nitric acid.

[0161] like Figure 2x As shown, the second conductive material 63 is subjected to a dry etching back process, and the top of the second conductive material 63 is oxidized by a wet oxidation process using the third nitride layer 14b'' as a mask to form an oxide protective layer 64.

[0162] By etching back, the surface of the second conductive material 63 is maintained above the surface of the semiconductor body 10. This step ensures that no excess second conductive material 63 remains on the surface of the third nitride 14b''. In this step, the etch-back thickness is 1000 Å to 1400 Å, and the loss generated by the mixed nitride layer is less than 100 Å.

[0163] In some embodiments, the second conductive material 63 is heavily doped N-type polysilicon (N+poly). In the etch-back process, the amount of polysilicon etched back needs to be controlled so that the top surface of the second conductive material 63 is 300 Å to 600 Å higher than the surface of the semiconductor body 10. The polysilicon that is higher will be oxidized in subsequent steps to form an oxide protective layer 64, thereby preventing the dopants in the heavily doped N-type polysilicon from diffusing outward in the subsequent gate oxidation process.

[0164] In this embodiment, the second conductive material 63 is heavily doped N-type polycrystalline silicon. The polycrystalline silicon on the top of the second conductive material 63 can be oxidized by a low-temperature wet oxidation process to generate a silicon oxide layer at a temperature of 950°C. The oxidation rate of heavily doped N-type polycrystalline silicon is faster, 2 to 4 times faster than that of intrinsic polycrystalline silicon.

[0165] Considering the loss of the silicon oxide layer in subsequent processes, the polysilicon oxide depth at the top of the second conductive material 63 in this step needs to exceed the height of the top surface of the second conductive material 63 above the surface of the semiconductor body 10 during the etch-back process. This is to ensure the blocking effect of subsequent dopants. For example, if the top surface of the second conductive material 63 is 300 Å to 600 Å above the surface of the semiconductor body 10 during the etch-back process, the polysilicon oxide depth at the top of the second conductive material 63 in this step is 600 Å to 1000 Å, which means the original thickness of the oxide protective layer 64 is 600 Å to 1000 Å.

[0166] like Figure 2yAs shown, the second nitride layer 14b' and the third nitride layer 14b'' on the surface of the semiconductor body 10 are removed using H3PO4 (phosphoric acid), while the pad oxide layer 14a is retained.

[0167] like Figure 2z As shown, after forming the oxide protective layer 64, processes such as well as trap implantation, gate structure formation, contact formation, BEoL metal layer and passivation are performed to complete the fabrication of the semiconductor device.

[0168] Gate oxidation is one of the most critical processes in subsequent CMOS operations. Before gate oxidation, the thickness of the oxide protective layer on top of the second conductive material must be greater than or equal to 600 Å. This oxide protective layer can prevent dopant from diffusing outward during the gate oxidation process. Furthermore, this protective layer does not affect the formation of contact holes on the second conductive material.

[0169] like Figure 3 As shown, a method for manufacturing a semiconductor device according to another embodiment of the present invention specifically includes the following steps:

[0170] S10 provides a semiconductor body. The semiconductor body includes a substrate, a buried layer on the substrate, and an epitaxial layer on the buried layer.

[0171] S20, a first trench is formed in the semiconductor body, and a first trench structure is formed in the first trench. The first trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0172] S30 forms the device region within the semiconductor body.

[0173] S40, an oxide isolation structure is formed at least on a portion of the surface of the device region.

[0174] S50, a shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure including the target shallow trench isolation structure.

[0175] S60, forming a second trench in the semiconductor body after the formation of the oxide isolation structure, partially or completely covering the target shallow trench isolation structure. The second trench extends from the top surface of the epitaxial layer to the buried layer;

[0176] S70, a second trench structure is formed in the second trench. The second trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0177] The target shallow trench isolation structure is located in the middle of the second trench, and the second trench covers the entire target shallow trench isolation structure.

[0178] Based on this, the steps for forming the second trench include:

[0179] S610 forms a second nitride layer, a third nitride layer, and a second hard mask layer on a semiconductor substrate.

[0180] S620 etches the second hard mask layer, the third nitride layer, the second nitride layer, and the target shallow trench isolation structure to form the prototype of the second trench.

[0181] S630, based on the prototype of the second trench, etches the semiconductor body to form the second trench extending to the buried layer.

[0182] This embodiment utilizes existing trench etching process formulations to achieve a high selective etching ratio between the shallow trench isolation structure and the semiconductor substrate. During the initial etching, the target shallow trench isolation structure located in the middle region of the second trench is etched away while the semiconductor substrate in the second trench is completely preserved, forming a prototype of the second trench. Through further etching, the prototype of the second trench is deepened, forming a second trench with a structure that is wider at the top and narrower at the bottom. This significantly optimizes the subsequent filling of conductive materials, effectively suppresses premature bridging of conductive materials on the sidewalls of the second trench, avoids the generation of seams or voids inside the conductive materials, improves the film density and structural uniformity of the conductive materials, enhances process stability, and reduces the risk of early chip failure due to incomplete filling.

[0183] This embodiment differs from the one described above. Figure 1 The illustrated embodiment is as follows: Figures 2a to 2n The process steps are basically the same, the difference being that in the subsequent process steps, this embodiment selects to etch the second trench 61 on the target shallow trench isolation structure 30', which results in a different process step flow from the previous embodiment.

[0184] The following is combined Figures 4a to 4j The process steps in the semiconductor device manufacturing method of this embodiment that differ from those in the previous embodiments will be described in detail.

[0185] like Figure 4a As shown, the second trench 61 is etched on the target shallow trench isolation structure 30', which is located in the middle region of the second trench 61. Specifically, the second hard mask layer 14'', the third nitride layer 14b", the second nitride layer 14b', and the pad oxide layer 14a are etched first to expose the semiconductor body 10 and the corresponding target shallow trench isolation structure 30'.

[0186] like Figure 4b and Figure 4cAs shown, since the target shallow trench isolation structure 30' is located in the middle region of the second trench, during the initial etching, the existing trench etching process formula can achieve a high selective etching ratio between the shallow trench isolation structure and the semiconductor substrate. This allows for the removal of the target shallow trench isolation structure 30' located in the middle region of the second trench while completely preserving the semiconductor substrate 10 within the second trench, forming the second trench prototype 61''. Figure 4c As shown, the semiconductor body 10 is further etched using the mature Bosch etching process. Through multiple polymer deposition / etching cycles, the second trench prototype 61'' can be etched to the target depth to form a second trench 61 extending to the buried layer 12. The second trench 61 has a structure that is wider at the top and narrower at the bottom.

[0187] In this embodiment, the width of the second trench 61 is 0.5μm~1μm; the width of the target shallow trench isolation structure 30' is 0.3μm~0.5μm.

[0188] In some embodiments, the bottom of the second trench 61 may contact the buried layer 12 or partially penetrate into the interior of the buried layer 12. Preferably, the bottom of the second trench 61 penetrates into the buried layer 12 to a depth of less than 1 μm to avoid excessive outward diffusion of dopants from the subsequently filled conductive material, which could lead to an increase in the doping concentration of the local buried layer 12.

[0189] In some embodiments, this step may be performed by etching using a second soft mask layer (not shown) to form the second trench 61. The second soft mask layer may also be photoresist, and the second soft mask layer is peeled off after the second trench 61 is formed.

[0190] like Figure 4d As shown, a second barrier layer 62 is grown on the sidewalls and bottom wall of the second trench 61. In some embodiments, the second oxide layer can be grown directly on the sidewalls and bottom wall of the second trench 61 to form the second barrier layer 62, in which case the second oxide layer has a thickness of, for example, 500 Å. In other embodiments, a sacrificial oxide layer with a thickness of, for example, 110 Å is formed on the sidewalls and bottom wall of the second trench 61 before forming the second oxide layer, and the sacrificial oxide layer is removed by wet processing to improve the smoothness of the bottom wall and sidewall of the second trench 61. In other embodiments, a fourth nitride layer of, for example, 100 Å to 300 Å can be formed on the second oxide layer after growing, for example, a second oxide layer of 110 Å to 200 Å, thereby improving the isolation effect.

[0191] like Figure 4eAs shown, the buried layer 12 is exposed by etching at least part of the second barrier layer 62 on the bottom wall of the second trench 61, facilitating subsequent electrical connection between the buried layer 12 and the surface of the semiconductor body 10. That is, the second trench 61 is opened in region D as shown, exposing the buried layer 12. It should be noted that in this step, the loss to the second hard mask layer 14'' should be as small as possible. Typically, this loss is less than 100 Å.

[0192] like Figure 4f As shown, a second conductive material 63 having a second doping type is deposited, such that the second conductive material 63 fills the second trench 61. For example, the thickness of the second conductive material 63 is, for example, 8000 Å to fill the second trench 61.

[0193] In this embodiment, the second conductive material 63 is heavily doped N-type polycrystalline silicon (N+poly). The heavily doped N-type polycrystalline silicon can be prepared by ion implantation followed by annealing of intrinsic polycrystalline silicon, or by in-situ doping during polycrystalline silicon deposition. The preparation of heavily doped N-type polycrystalline silicon is a prior art and will not be described in detail in this invention.

[0194] In step 4g, excess second conductive material 63 on the surface of the second hard mask layer 14'' is removed. Specifically, the second hard mask layer 14'' can be used as a stop layer for this step, and the second conductive material 63 on the surface of the second hard mask layer 14'' can be removed by a CMP process. More specifically, in some embodiments, the thickness loss of the second hard mask layer 14'' should be ensured to be less than 200 Å, so that a sufficiently thick mixed layer is retained on the surface of the oxide isolation structure 50.

[0195] Similar to the deposition of the first conductive material 24, a portion of the second conductive material 63 may also be deposited on the substrate 11 of the semiconductor body 10 during the deposition of the second conductive material 63. In some embodiments, it is also necessary to remove the second conductive material 63 from the substrate 11 of the semiconductor body 10. The second conductive material 63 on the substrate 11 is removed by wet etching, for example, using a diluted mixture of hydrofluoric acid and nitric acid.

[0196] like Figure 4h As shown, a dry etching back process is performed on the second conductive material 63. Through this back etching, the surface of the second conductive material 63 is maintained above the surface of the semiconductor body 10. This step ensures that no excess second conductive material 63 remains on the surface of the second hard mask layer 14''. This step results in a loss of less than 100 Å in the second hard mask layer 14''.

[0197] In some embodiments, the second conductive material 63 is heavily doped N-type polysilicon (N+poly). In the etch-back process, the amount of polysilicon etched back needs to be controlled so that the top surface of the second conductive material 63 is 300 Å to 600 Å higher than the surface of the semiconductor body 10. The polysilicon that is higher will be oxidized in subsequent steps to form an oxide protective layer 64, thereby preventing the dopants in the heavily doped N-type polysilicon from diffusing outward in the subsequent gate oxidation process.

[0198] like Figure 4i As shown, the second hard mask layer 14'' is used as a mask, and the top of the second conductive material 63 is oxidized by a wet oxidation process to form an oxide protective layer 64.

[0199] In this embodiment, the second conductive material 63 is heavily doped N-type polycrystalline silicon. The polycrystalline silicon on the top of the second conductive material 63 can be oxidized by a low-temperature wet oxidation process to generate a silicon oxide layer. The oxidation rate of heavily doped N-type polycrystalline silicon is faster, 2 to 4 times faster than that of intrinsic polycrystalline silicon.

[0200] Considering the loss of the silicon oxide layer in subsequent processes, the polysilicon oxide depth at the top of the second conductive material 63 in this step needs to exceed the height of the top surface of the second conductive material 63 above the surface of the semiconductor body 10 during the etch-back process. This is to ensure the blocking effect of subsequent dopants. For example, if the top surface of the second conductive material 63 is 300 Å to 600 Å above the surface of the semiconductor body 10 during the etch-back process, the polysilicon oxide depth at the top of the second conductive material 63 in this step is 600 Å to 1000 Å, which means the original thickness of the oxide protective layer 64 is 600 Å to 1000 Å.

[0201] like Figure 4j As shown, the second hard mask layer 14'', the second nitride layer 14b', and the third nitride layer 14b'' are removed, leaving the pad oxide layer 14a.

[0202] For example, when the second hard mask layer 14'' is a TEOS hard mask layer, the TEOS hard mask layer can be removed using BOE solution (buffered oxide etchant) or diluted hydrofluoric acid (DHF). The second nitride layer 14b' and the third nitride layer 14b'' on the surface of the semiconductor body 10 are removed using H3PO4 (phosphoric acid).

[0203] After forming the oxide protective layer 64, processes such as well as well-drain implantation, gate structure formation, contact formation, BEoL metal layer formation, and passivation are performed to complete the fabrication of the semiconductor device.

[0204] Gate oxidation is one of the most critical processes in subsequent CMOS operations. Before gate oxidation, the thickness of the oxide protective layer on top of the second conductive material must be greater than or equal to 600 Å. This oxide protective layer can prevent dopant from diffusing outward during the gate oxidation process. Furthermore, this protective layer does not affect the formation of contact holes on the second conductive material.

[0205] like Figure 5 As shown, a method for manufacturing a semiconductor device in another embodiment of the present invention specifically includes the following steps:

[0206] S100 provides a semiconductor body. The semiconductor body includes a substrate, a buried layer on the substrate, and an epitaxial layer on the buried layer.

[0207] S200, a first trench is formed in the semiconductor body, and a first trench structure is formed in the first trench. The first trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0208] S300 forms the device region within the semiconductor body.

[0209] S400, an oxide isolation structure is formed at least on a portion of the surface of the device region.

[0210] S500, a shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure including the target shallow trench isolation structure.

[0211] S600, a second trench is formed in the semiconductor body after the oxide isolation structure is formed, partially or completely covering the target shallow trench isolation structure. The second trench extends from the top surface of the epitaxial layer to the buried layer;

[0212] S700, a second trench structure is formed in the second trench. The second trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0213] The target shallow trench isolation structure is located in the middle of the second trench, and the second trench covers the entire target shallow trench isolation structure.

[0214] Based on this, the steps for forming the second trench include:

[0215] S601 forms a second nitride layer, a third nitride layer, and a second hard mask layer on a semiconductor substrate.

[0216] S602, etching the second hard mask layer, the third nitride layer, the second nitride layer, and the target shallow trench isolation structure to form the prototype of the second trench.

[0217] S603, based on the second trench prototype, the semiconductor body is etched for the first time to form a second trench opening extending to the epitaxial layer. The second trench opening includes an upper part with a first width and a lower part with a second width that is smaller than the first width.

[0218] S604, an oxide sidewall is formed on the sidewall above the second trench opening.

[0219] S605, based on the second trench opening, the semiconductor body is etched again to form the second trench body extending to the buried layer.

[0220] S606, remove oxide sidewalls to form a second trench.

[0221] This embodiment utilizes existing trench etching process formulations to achieve a high selective etching ratio between the shallow trench isolation structure and the semiconductor substrate. During the initial etching, the target shallow trench isolation structure located in the central region of the second trench is removed while the semiconductor substrate within the second trench is completely preserved, forming a preliminary second trench shape. Through subsequent etching, the preliminary second trench shape is deepened, forming a second trench opening with a wider top and narrower bottom structure. Oxide sidewalls are formed on the wider sidewalls of the second trench opening to maintain a relatively wide upper portion of the opening throughout the final etching process. The final etching forms the second trench substrate, and after removing the oxide sidewalls, a second trench with a wider top and narrower bottom structure is formed. This significantly optimizes the subsequent filling of conductive materials, effectively suppresses premature bridging of the conductive material on the second trench sidewalls, avoids the formation of seams or voids within the conductive material, improves the film density and structural uniformity of the conductive material, enhances process stability, and reduces the risk of early chip failure due to incomplete filling.

[0222] This embodiment differs from the one described above. Figure 3 The illustrated embodiment shows the fabrication process steps for the first trench and the first trench structure (refer to the following). Figure 1 The illustrated embodiment Figures 2a to 2n (Steps) and subsequent Figures 4d to 4j The process steps shown are basically the same, the difference being that in the preparation process step of forming the second trench 61, this embodiment is different from the previous one. Figure 3 The embodiment shown has several additional process steps, resulting in a different process flow compared to the previous embodiment.

[0223] The following is combined Figures 6a to 6f The process steps in the semiconductor device manufacturing method of this embodiment that differ from those in the previous embodiments will be described in detail.

[0224] like Figure 6aAs shown, the second trench 61 is etched on the target shallow trench isolation structure 30', which is located in the middle region of the second trench 61. Specifically, the second hard mask layer 14'', the third nitride layer 14b", the second nitride layer 14b', and the pad oxide layer 14a are etched first to expose the semiconductor body 10 and the corresponding target shallow trench isolation structure 30'.

[0225] like Figure 6b and Figure 6c As shown, since the target shallow trench isolation structure 30' is located in the middle region of the second trench, during the initial etching, the existing trench etching process formula can achieve a high selective etching ratio between the shallow trench isolation structure and the semiconductor substrate. This allows for the removal of the target shallow trench isolation structure 30' located in the middle region of the second trench while completely preserving the semiconductor substrate 10 within the second trench, forming the second trench prototype 61''. Figure 6c As shown, the semiconductor body 10 is further etched using the mature Bosch etching process. By adjusting the polymer deposition and etching time in each cycle through multiple polymer deposition / etching cycles, the second trench prototype 61'' can be deepened. The deepening depth can be 0.5μm~2μm, forming the second trench opening 61''' with a structure that is wider at the top and narrower at the bottom.

[0226] like Figure 6d As shown, an oxide sidewall 611 is provided on the sidewall of the wider part of the second trench opening 61'''. For example, a sacrificial oxide layer of 100Å~500Å is grown, and then a thin oxide sidewall 611 is formed by dry etching to protect the top sidewall of the finally formed second trench 61, so that the top sidewalls always maintain a wide width during the final etching process.

[0227] like Figure 6e As shown, etching continues to deepen the second trench opening 61''' until a second trench body 61' that penetrates deep into the buried layer 12 is formed. In some embodiments, the bottom of the second trench body 61' may contact the buried layer 12 or partially penetrate into the interior of the buried layer 12. Preferably, the bottom of the second trench body 61' penetrates the buried layer 12 to a depth of less than 1 μm to avoid excessive outward diffusion of doping from the subsequently filled conductive material, which could lead to an increase in the doping concentration of the local buried layer 12.

[0228] like Figure 6f As shown, the oxide sidewall 611 is removed to form a second trench 61. The second trench 61 has a structure that is wider at the top and narrower at the bottom, and the width of the second trench 61 is 0.5 μm to 1.0 μm. For example, the oxide sidewall 611 can be removed by wet removal of the sacrificial oxide layer using diluted hydrofluoric acid (DHF).

[0229] In this embodiment, the width of the target shallow trench isolation structure 30' is 0.3μm~0.5μm.

[0230] In some embodiments, this step may be performed by etching using a second soft mask layer (not shown) to form the second trench 61. The second soft mask layer may also be photoresist, and the second soft mask layer is peeled off after the second trench 61 is formed.

[0231] The subsequent processes and preceding steps in this embodiment Figure 3 The process of the illustrated embodiment is the same, and can be referred to the description in the previous embodiment, which will not be elaborated in detail here.

[0232] refer to Figure 2z or Figure 4j As shown, the present invention also provides a semiconductor device, comprising:

[0233] The semiconductor body includes a substrate 11, a buried layer 12 on the substrate 11, and an epitaxial layer 13 on the buried layer 12. A device region is formed in the semiconductor body, and an oxide isolation structure is formed on a portion of the surface of the device region.

[0234] The first trench extends from the top surface of the epitaxial layer 13 to the substrate 11.

[0235] A first trench structure 20a is disposed within a first trench. The first trench structure 20a is configured to electrically connect the substrate 11 to the top surface of the epitaxial layer 13.

[0236] A shallow trench isolation structure 30 is formed within the epitaxial layer 13 of the semiconductor substrate. The shallow trench isolation structure 30 is configured to isolate a device region. The shallow trench isolation structure 30 includes a target shallow trench isolation structure.

[0237] The second trench is formed within the semiconductor body and partially or completely covers the target shallow trench isolation structure. The second trench extends from the top surface of the epitaxial layer 13 to the buried layer 12, and the second trench is configured with a structure that is wider at the top and narrower at the bottom.

[0238] A second trench structure is disposed in the second trench. The second trench structure is configured to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0239] Figures 2a to 2z The process shown or Figures 4a to 4j The process shown or Figures 6a to 6f The processes shown can all be used for manufacturing. Figure 2z or Figure 4j The semiconductor device shown is not described in detail here. The description of the manufacturing method of the semiconductor device in the foregoing can be incorporated herein.

[0240] It should be noted that the semiconductor device of the present invention is preferably manufactured using the semiconductor device manufacturing method described above.

[0241] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0242] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a substrate, a buried layer on the substrate and an epitaxial layer on the buried layer; A first trench is formed in the semiconductor body, and a first trench structure is formed in the first trench, the first trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer; A device region is formed in the semiconductor body; An oxide isolation structure is formed at least on a portion of the surface of the device region; A shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure including a target shallow trench isolation structure; A second trench is formed in the semiconductor body after the formation of the oxide isolation structure, which partially or completely covers the target shallow trench isolation structure, and the second trench extends from the top surface of the epitaxial layer to the buried layer. A second trench structure is formed in the second trench, the second trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The target shallow trench isolation structure is located on both sides of the second trench, and the second trench covers part or all of the target shallow trench isolation structure; The step of forming the second trench includes: A second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor body; The second hard mask layer, the third nitride layer, the second nitride layer, and the semiconductor body are etched to form a second trench body extending to the buried layer, wherein the target shallow trench isolation structure is attached to both sides of the second trench body. The third nitride layer and the second nitride layer on both sides of the second trench body are etched back; The second trench is formed by removing the second hard mask layer and partially or completely removing the target shallow trench isolation structure that is attached to the second trench body.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The thickness of the third nitride layer and the second nitride layer on both sides of the second trench body is not less than the width of the target shallow trench isolation structure that is attached to the second trench body; And / or, The thickness of the third nitride layer and the second nitride layer on both sides of the second trench is 2500 Å to 3000 Å.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The width of the second trench body is 0.3μm~0.7μm; and / or, The width of the target shallow trench isolation structure is not less than 0.28; and / or, The width of the second groove is 0.5μm to 1.0μm.

5. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The step of forming the second trench structure in the second trench includes: A second barrier layer is formed on the sidewall of the second trench, and a second conductive material is deposited to fill the second trench; Remove the second conductive material from the surface of the second nitride layer; Remove a portion of the second conductive material within the second trench, ensuring that the surface of the remaining second conductive material is not lower than the surface of the semiconductor body. Remove the third nitride layer and the second nitride layer.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, After removing a portion of the second conductive material within the second trench, the process further includes the step of forming an oxide protective layer on the surface of the second conductive material.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The target shallow trench isolation structure is located in the middle of the second trench, and the second trench covers the entire target shallow trench isolation structure; The step of forming the second trench includes: A second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor body; The second hard mask layer, the third nitride layer, the second nitride layer, and the target shallow trench isolation structure are etched to form the prototype of the second trench; Based on the second trench prototype, the semiconductor body is etched to form a second trench extending to the buried layer.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The target shallow trench isolation structure is located in the middle of the second trench, and the second trench covers the entire target shallow trench isolation structure; The step of forming the second trench includes: A second nitride layer, a third nitride layer, and a second hard mask layer are formed on the semiconductor body; The second hard mask layer, the third nitride layer, the second nitride layer, and the target shallow trench isolation structure are etched to form the prototype of the second trench; Based on the second trench prototype, the semiconductor body is etched for the first time to form a second trench opening extending to the epitaxial layer. The second trench opening includes an upper part with a first width and a lower part with a second width that is smaller than the first width. An oxide sidewall is formed on the upper sidewall of the second trench opening; Based on the second trench opening, the semiconductor body is etched again to form a second trench body extending to the buried layer; The oxide sidewalls are removed to form the second trench.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, characterized in that, The width of the target shallow trench isolation structure is 0.3μm~0.5μm; and / or, The width of the second groove is 0.5μm to 1.0μm.

10. The method for manufacturing a semiconductor device according to claim 7 or 8, characterized in that, The step of forming the second trench structure in the second trench includes: A second barrier layer is formed on the sidewall of the second trench, and a second conductive material is deposited to fill the second trench; Remove the second conductive material from the surface of the second hard mask layer; Remove a portion of the second conductive material within the second trench, ensuring that the surface of the remaining second conductive material is not lower than the surface of the semiconductor body. Remove the second hard mask layer, the third nitride layer, and the second nitride layer.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After removing a portion of the second conductive material within the second trench, the process further includes the step of forming an oxide protective layer on the surface of the second conductive material.

12. The method for manufacturing a semiconductor device according to claim 6 or 11, characterized in that, The step of forming an oxide protective layer on the surface of the second conductive material includes: The second conductive material in the second trench is etched so that the surface of the second conductive material is higher than the surface of the semiconductor body. Using the third nitride layer as a mask, a wet oxidation process is used to oxidize the top of the second conductive material to form an oxide protective layer; Remove all nitride layers from the surface of the semiconductor substrate.

13. The method for manufacturing a semiconductor device according to claim 6 or 11, characterized in that, After forming an oxide protective layer on the surface of the second conductive material, the method further includes: The gate oxidation process is performed under the condition that the second trench structure is protected by the oxide protective layer.

14. A semiconductor device, characterized in that, include: A semiconductor body includes a substrate, a buried layer on the substrate, and an epitaxial layer on the buried layer. A device region is formed in the semiconductor body, and an oxide isolation structure is formed on a portion of the surface of the device region. A first trench extends from the top surface of the epitaxial layer to the substrate; A first trench structure is disposed within a first trench, the first trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer; A shallow trench isolation structure is formed within the epitaxial layer of the semiconductor body, the shallow trench isolation structure being configured to isolate the device region, the shallow trench isolation structure including a target shallow trench isolation structure; The second trench is formed within the semiconductor body and partially or completely covers the target shallow trench isolation structure. The second trench extends from the top surface of the epitaxial layer to the buried layer and is configured to be wider at the top and narrower at the bottom. A second trench structure is disposed in the second trench, and the second trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer.

15. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 13.

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