Semiconductor device

Abstract

A semiconductor device includes a substrate; an insulating layer provided on the substrate, the insulating layer including an outer boundary; a passivation layer provided on the insulating layer, the passivation layer including an inner boundary located inside the outer boundary; a dummy pattern layer having a lower surface that forms a same plane as a lower surface of the passivation layer, overlapping at least a portion of an area provided between the outer boundary and the inner boundary, and having a side surface located inside the inner boundary; and a redistribution pattern layer provided on the dummy pattern layer.

Description

Cross-reference of related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0024013, filed on February 25, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure generally relate to semiconductor devices, and more specifically to semiconductor devices including redistribution layer (RDL) patterns. Background Technology

[0003] Semiconductor devices, due to their miniaturization, multifunctionality, and low manufacturing cost, have attracted much attention as crucial components in the electronics industry. With the development of the electronics industry, the demand for high integration in semiconductor devices is also increasing.

[0004] To meet the requirements of high integration, semiconductor devices may include redistribution layer (RDL) patterns. The redistribution layer pattern can be electrically connected to chip pads and can extend from one area where chip pads are located to another. Summary of the Invention

[0005] The advantages of the embodiments disclosed herein are not limited to those mentioned in this specification, and other advantages not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] The embodiments disclosed herein aim to provide a semiconductor device capable of preventing device characteristic degradation due to process defects.

[0007] In one embodiment of this disclosure, the semiconductor device may include: a substrate; an insulating layer disposed on the substrate and including an outer boundary; a passivation layer disposed on the insulating layer and including an inner boundary located inside the outer boundary; a dummy pattern layer having a lower surface coplanar with the lower surface of the passivation layer, overlapping at least a portion of the region between the outer and inner boundaries, and having a side surface located inside the inner boundary; and a redistribution pattern layer disposed on the dummy pattern layer.

[0008] In one embodiment of this disclosure, the semiconductor device may include: a substrate including a chip region and a scribe region; an insulating layer disposed on the substrate; a dummy pattern layer disposed on the insulating layer in the scribe region; a passivation layer located on the insulating layer and at least partially overlapping the dummy pattern layer; and a redistribution pattern layer disposed outside the passivation layer to overlap with the upper surface of the dummy pattern layer, wherein one side surface of the dummy pattern layer is located inside the side surface of the passivation layer.

[0009] According to embodiments of this disclosure, device characteristics degradation due to process defects can be prevented.

[0010] The beneficial effects of the embodiments disclosed herein are not limited to those mentioned above, and other advantages not mentioned will be clearly understood by those skilled in the art from the detailed description. Attached Figure Description

[0011] The embodiments of this disclosure will be more fully understood through the following detailed description and accompanying drawings, but these descriptions and drawings are for illustrative purposes only and are not intended to limit the embodiments.

[0012] Figure 1 This is a diagram showing a wafer incorporating semiconductor devices according to embodiments of the present disclosure.

[0013] Figure 2 yes Figure 1 A magnified view of region A.

[0014] Figure 3 It is shown Figure 2 The diagram shows the cross-sectional structure of the portion indicated by line I-I'.

[0015] Figures 4 to 6 It is shown Figure 2 The diagram shows other cross-sectional structures of the section indicated by line I-I'.

[0016] Figures 7 to 12 It shows the basis Figure 3 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0017] Figures 13 to 16 It shows the basis Figure 4 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0018] Figure 17 It shows the basis Figure 5 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0019] Figure 18 It shows the basis Figure 6 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment. Detailed Implementation

[0020] The embodiments of this disclosure will be described in detail with reference to the accompanying drawings. The specific structural and functional descriptions of these embodiments are intended to illustrate the technical concepts presented in this disclosure. The drawings illustrate possible embodiments, but the scope of this disclosure is not limited to the embodiments or examples described in this specification, and various variations are permitted.

[0021] All the crosshairs in the figure represent corresponding or similar areas between the figures, rather than representing the material related to these areas.

[0022] When one element is labeled "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between them. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0023] When one element is identified as being "above", "over", "below", or "below" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0024] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “below,” “under,” “on top,” “upper,” “side surface,” “above,” “topmost,” “below,” “lowest,” “front,” “back,” “left,” “right,” “column,” “row,” “layer,” and other terms that suggest relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings and are not intended to be limiting. Within the scope of this disclosure, other spatial relationships or directions may exist that are not shown in the accompanying drawings or described in the specification.

[0025] Terms such as “first” and “second” are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0026] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0027] Figure 1 This is a diagram showing a wafer 1 in which semiconductor devices according to embodiments of the present disclosure are integrated.

[0028] refer to Figure 1 Wafer 1 may include multiple chip regions (CHR) and scribe regions (SR).

[0029] A chip region (CHR) is the area formed after wafer 1 is diced to create a single semiconductor chip. Each chip region (CHR) may contain an integrated circuit used as a single semiconductor chip. A chip region (CHR) may include a cell region (CR) and a guard ring region (GR). The guard ring region (GR) may be continuous with the side surfaces of the cell region (CR). The guard ring region (GR) may form a continuous frame surrounding the chip region (CHR).

[0030] The scribing region SR can extend along a first direction FD and a second direction SD to surround the side surface of each chip region CHR. The first direction FD and the second direction SD can be substantially perpendicular to each other. The scribing region SR can be continuous with the chip region CHR. In the dicing process, the wafer 1 can be diced along the dicing lines in the scribing region SR using a laser, blade, etc.

[0031] The scribe area SR may include a redistribution alignment key area AR, which is defined as the region where redistribution alignment keys are set. In semiconductor device manufacturing, the redistribution alignment keys serve as alignment references during the redistribution pattern layer etching process.

[0032] The redistributed alignment key region (AR) can be located between adjacent chip regions (CHR). Although Figure 1 The diagram shows that the redistributed alignment key region AR is located between adjacent chip regions CHR on the first direction FD, but the location of the redistributed alignment key region AR is not limited to this.

[0033] refer to Figure 1 A portion of wafer 1 may include a first semiconductor device and an adjacent second semiconductor device. The region between the first semiconductor device and the second semiconductor device may be defined as region A.

[0034] Figure 2 yes Figure 1 A magnified view of region A in the middle.

[0035] A portion of the first semiconductor device and a portion of the second semiconductor device may be included in region A.

[0036] refer to Figure 2 The first semiconductor device may include a first chip region CHR1 and a portion of a first scribe region SR1 that is continuous therewith. The first chip region CHR1 may include a first cell region CR1 and a first guard ring region GR1. The first guard ring region GR1 may be continuous with the first cell region CR1. The first guard ring region GR1 may include a first guard ring 110. The first guard ring 110 may extend to surround the edge of the first cell region CR1.

[0037] although Figure 2 The illustration shows two first protection rings 110 in the first protection ring region GR1, but the embodiment is not necessarily limited to this. The first protection ring region GR1 may have one or more first protection rings 110, preferably two or more first protection rings 110.

[0038] refer to Figure 2The second semiconductor device may include a second chip region CHR2 and a portion of a second scribe region SR2 that is continuous with the second chip region CHR2. The second chip region CHR2 may include a second cell region CR2 and a second guard ring region GR2. The second guard ring region GR2 may be continuous with the second cell region CR2. The second guard ring region GR2 may include a second guard ring 210. The second guard ring 210 may extend to surround the edge of the second cell region CR2.

[0039] although Figure 2 The illustration shows two second protection rings 210 in the second protection ring region GR2, but the embodiment is not necessarily limited to this. The second protection ring region GR2 may have one or more second protection rings 210, preferably two or more second protection rings 210.

[0040] The redistribution alignment key region AR can be set in a portion of the first scribe region SR1 and the second scribe region SR2. A redistribution alignment key RK can be set in the redistribution alignment key region AR. The redistribution alignment key RK can be used for alignment during the etching of the redistribution patterned layer in semiconductor device manufacturing processes.

[0041] Despite Figure 2 In the example, three redistribution alignment keys RK are shown in the redistribution alignment key region AR, but the embodiment is not necessarily limited to this, and the redistribution alignment key region AR may have one or more redistribution alignment keys RK.

[0042] In one embodiment, the redistribution alignment key RK can be strip-shaped and positioned on the plane defined by the first direction FD and the second direction SD, such as... Figure 2 As shown, but the embodiments are not limited thereto.

[0043] Figure 3 It is shown Figure 2 The diagram shows the cross-sectional structure of the section indicated by line I-I'.

[0044] refer to Figure 3 The first semiconductor device may include a first substrate 101, a first guard ring 110, a first insulating layer 120, a first dummy pattern layer 130, a first passivation layer 140, a first redistribution insulating layer 150, and a first redistribution pattern layer 160.

[0045] The first semiconductor device may include a first outer boundary 124. In one embodiment, the first outer boundary 124 may be the outermost boundary of the first semiconductor device. In one embodiment, the outer boundary of the first insulating layer 120 may be the same as the first outer boundary 124. In one embodiment, the first outer boundary 124 may be located within the first scribe region SR1. The first passivation layer 140 may include a first inner boundary 143 located within the first scribe region SR1. The first inner boundary 143 may be a boundary of the first semiconductor device that is closer to the first guard ring region GR1 than the first outer boundary 124.

[0046] The first outer boundary 124 may extend along the third direction VD. The first inner boundary 143 may extend along the third direction VD. The first inner boundary 143 may be located at the interface between the first redistribution pattern layer 160 and the first passivation layer 140. The third direction VD may be substantially perpendicular to the first direction FD.

[0047] The first substrate 101 is located in the first chip region CHR1 and the first scribe region SR1. The first chip region CHR1 includes a first cell region CR1 and a first guard ring region GR1.

[0048] The first protective ring 110 and the first insulating layer 120 may be disposed on the first substrate 101. The first substrate 101 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The first substrate 101 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The first substrate 101 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or a combination thereof.

[0049] A first protective ring 110 may be disposed on a first substrate 101. The first protective ring 110 may be disposed within a first protective ring region GR1. The first protective ring 110 may be disposed inside a first inner boundary 143. The first protective ring 110 may include a plurality of first protective metal contacts 111 extending along a third direction VD and a plurality of first protective metal layers 112 extending along a first direction FD.

[0050] In one embodiment, the first protective metal contact 111 and the first protective metal layer 112 may comprise tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination of at least two of these. Although Figure 3 The first protective ring 110 is shown to include four first protective metal contacts 111 and four first protective metal layers 112, but the embodiments are not necessarily limited to this, and the first protective ring 110 may include various numbers of first protective metal contacts 111 and first protective metal layers 112.

[0051] Among the plurality of first protective metal layers 112, the first protective metal layer that is furthest from the first substrate 101 along the third direction VD can be defined as the first upper protective metal layer 113.

[0052] A first upper protective metal layer 113 may be disposed on a first upper metal interlayer insulating layer 123. The upper surface of the first upper protective metal layer 113 may be coplanar with the upper surface of the first dummy pattern layer 130. The first upper protective metal layer 113 may comprise the same material as the first dummy pattern layer 130. In one embodiment, the first upper protective metal layer 113 may comprise aluminum (Al).

[0053] The first insulating layer 120 may be disposed on the first substrate 101. The first insulating layer 120 may include a first interlayer insulating layer 121, a first lower intermetallic insulating layer 122, and a first upper intermetallic insulating layer 123.

[0054] The first interlayer insulating layer 121 may include at least two elements selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). The first interlayer insulating layer 121 may include an insulating material having excellent step coverage and gap-filling properties. In one embodiment, the first interlayer insulating layer 121 may include an oxide, such as tetraethyl orthosilicate (TEOS) or borosilicate glass (BPSG).

[0055] The first lower metal-to-metal insulating layer 122 may be disposed on the first interlayer insulating layer 121. The first lower metal-to-metal insulating layer 122 may include a first lower cover layer 124 and a first lower metal-to-metal dielectric layer 125.

[0056] although Figure 3 Two first lower metal-to-metal insulating layers 122 stacked along the third direction VD are shown, but embodiments are not necessarily limited thereto, and various numbers of first lower metal-to-metal insulating layers 122 may be provided. For example, in one embodiment, there may be one or more first lower metal-to-metal insulating layers 122.

[0057] A first lower intermetallic dielectric layer 125 may be disposed on a first lower capping layer 124. In one embodiment, the first lower capping layer 124 may include a nitride comprising silicon (Si), carbon (C), and nitrogen (N). In one embodiment, the first lower intermetallic dielectric layer 125 may include a low-k oxide.

[0058] The first upper intermetallic insulating layer 123 may be disposed on the first lower intermetallic insulating layer 122. The first upper intermetallic insulating layer 123 may include a first upper cover layer 126 and a first upper intermetallic dielectric layer 127.

[0059] In one embodiment, the first upper capping layer 126 may comprise a material substantially the same as the first lower capping layer 124. In one embodiment, the first upper intermetallic dielectric layer 127 may have a different structure than the first lower intermetallic dielectric layer 125. In one embodiment, the first upper intermetallic dielectric layer 127 may comprise an oxide having excellent step coverage and gap-filling properties. In one embodiment, the first upper intermetallic dielectric layer 127 may comprise an oxide layer such as tetraethyl orthosilicate (TEOS).

[0060] A first dummy pattern layer 130 may be disposed on a first upper intermetallic insulating layer 123. The lower surface of the first dummy pattern layer 130 may be coplanar with the lower surface of the first passivation layer 140 (i.e., forming the same plane). The first dummy pattern layer 130 may overlap with at least a portion of the region between the first outer boundary 124 and the first inner boundary 143. One side surface of the first dummy pattern layer 130 may be located inside the first inner boundary 143.

[0061] The first dummy pattern layer 130 may have a first width W1. The first dummy pattern layer 130 may be located in a first scribe area SR1. The first dummy pattern layer 130 may be disposed on the first insulating layer 120. In one embodiment, the first dummy pattern layer 130 may include aluminum (Al).

[0062] A first passivation layer 140 may be disposed on the first insulating layer 120. The first passivation layer 140 may be located inside the first outer boundary 124. The first passivation layer 140 may include a first inner boundary 143 located inside the first outer boundary 124.

[0063] The first passivation layer 140 may include a first passivation oxide layer 141 adjacent to the first upper intermetallic insulating layer 123 and a first passivation nitride layer 142 disposed on the first passivation oxide layer 141. In one embodiment, the first passivation layer 140 may include an oxide, a nitride, or a combination thereof. In one embodiment, the first passivation oxide layer 141 may include a high-density plasma (HDP) oxide.

[0064] A first redistribution insulating layer 150 may be disposed on a first passivation layer 140. In an embodiment, the first redistribution insulating layer 150 may include silicon oxide.

[0065] A first redistributed pattern layer 160 may be disposed on a first dummy pattern layer 130. The first redistributed pattern layer 160 may be located within a first scribbling region SR1. The lower surface of the first redistributed pattern layer 160 may form a coplanar plane with the upper surface of the first dummy pattern layer 130 and may have a second width W2. In one embodiment, the first width W1 of the first dummy pattern layer 130 may be greater than the second width W2 of the first redistributed pattern layer 160. In one embodiment, the lower surface (or bottom) of the first redistributed pattern layer 160 may be flat. The top surface of the first redistributed pattern layer 160 may have a flat central portion and two upwardly projecting leg ends, thereby giving the second redistributed pattern layer 160 an overall bracket shape, with the flat portion of the bracket extending parallel to the top surface of the first dummy pattern layer 130 and the legs extending perpendicular to the flat portion.

[0066] The distance from the upper surface of the first redistributed insulating layer 150 to the first dummy pattern layer 130 may be greater than the distance from the uppermost surface of the first redistributed pattern layer 160 to the first dummy pattern layer 130. The first redistributed pattern layer 160 may contact the upper surface of the first dummy pattern layer 130 between the first outer boundary 124 and the first inner boundary 143. The first redistributed pattern layer 160 may contact the side surface of the first passivation layer 140 between the first outer boundary 124 and the first inner boundary 143. The bottom surface of the first redistributed pattern layer 160 may be lower than the top surface of the first oxide passivation layer 141. In one embodiment, the top surface of the central portion of the top surface of the second redistributed pattern layer 160 may be coplanar with the top surface of the second passivation layer 140.

[0067] The first redistribution pattern layer 160 may be located outside the side surface of the first passivation layer 140. The first redistribution pattern layer 160 may be configured to overlap with the upper surface of the first dummy pattern layer 130.

[0068] Refer again Figure 3 The second semiconductor device may include a second substrate 201, a second guard ring 210, a second insulating layer 220, a second dummy pattern layer 230, a second passivation layer 240, a second redistribution insulating layer 250, and a second redistribution pattern layer 260.

[0069] The second semiconductor device may include a second outer boundary 224. In one embodiment, the second outer boundary 224 may be the outermost boundary of the second semiconductor device. In one embodiment, the outer boundary of the second insulating layer 220 may be the same as the second outer boundary 224. In one embodiment, the second outer boundary 224 may be located in the second scribe region SR2. The second passivation layer 240 may include a second inner boundary 243 located inside the second scribe region SR2. The second inner boundary 243 may be closer to the second guard ring region GR2 than the second outer boundary 224.

[0070] The second outer boundary 224 may extend along a third direction VD. The second inner boundary 243 may extend along a third direction VD. The second inner boundary 243 may be located at the interface between the second redistribution pattern layer 260 and the second passivation layer 240.

[0071] The second substrate 201 may be located in the second chip region CHR2 and the second scribe region SR2. The second chip region CHR2 may include the second cell region CR2 and the second guard ring region GR2.

[0072] The second protective ring 210 and the second insulating layer 220 may be disposed on the second substrate 201. The second substrate 201 may comprise a material substantially the same as that of the first substrate 101.

[0073] The second protective ring 210 may be disposed on the second substrate 201. The second protective ring 210 may be disposed in the second protective ring region GR2. The second protective ring 210 may be disposed inside the second inner boundary 243. The second protective ring 210 may include a plurality of second protective metal contacts 211 extending along a third direction VD and a plurality of second protective metal layers 212 extending along a first direction FD.

[0074] In one embodiment, the second protective metal contact 211 or the second protective metal layer 212 may comprise substantially the same material as the first protective metal contact 111 or the first protective metal layer 112. Although Figure 3 The second protective ring 210 is shown to include four second protective metal contacts 211 and four second protective metal layers 212, but the embodiments are not necessarily limited to this, and the second protective ring 210 may include various numbers of second protective metal contacts 211 and second protective metal layers 212.

[0075] Among the plurality of second protective metal layers 212, the second protective metal layer that is furthest from the second substrate 201 along the third direction VD can be defined as the second upper protective metal layer 213.

[0076] The second upper protective metal layer 213 may be disposed on the second upper metal interlayer insulating layer 223. The upper surface of the second upper protective metal layer 213 may form the same plane as the upper surface of the second dummy pattern layer 230. The second upper protective metal layer 213 may include the same material as the second dummy pattern layer 230. In one embodiment, the second upper protective metal layer 213 may include substantially the same material as the first upper protective metal layer 113.

[0077] The second insulating layer 220 may be disposed on the second substrate 201. The second insulating layer 220 may include a second interlayer insulating layer 221, a second lower intermetallic insulating layer 222, and a second upper intermetallic insulating layer 223.

[0078] The second interlayer insulation layer 221 may include a material substantially the same as that of the first interlayer insulation layer 121.

[0079] The second lower metal-to-metal insulating layer 222 may be disposed on the second inter-layer insulating layer 221. The second lower metal-to-metal insulating layer 222 may include a second lower cover layer 224 and a second lower metal-to-metal dielectric layer 225.

[0080] although Figure 3 Two second lower metal-to-metal insulating layers 222 stacked along the third direction VD are shown, but the embodiment is not necessarily limited to this, and various numbers of second lower metal-to-metal insulating layers 222 may be provided. For example, in one embodiment, there may be one or more second lower metal-to-metal insulating layers 222.

[0081] A second lower intermetallic dielectric layer 225 may be disposed on the second lower cover layer 224. In one embodiment, the second lower cover layer 224 may comprise a material substantially the same as that of the first lower cover layer 124. In one embodiment, the second lower intermetallic dielectric layer 225 may comprise a material substantially the same as that of the first lower intermetallic dielectric layer 125.

[0082] The second upper intermetallic insulating layer 223 may be disposed on the second lower intermetallic insulating layer 222. The second upper intermetallic insulating layer 223 may include a second upper cover layer 226 and a second upper intermetallic dielectric layer 227 disposed on the second upper cover layer 226.

[0083] In one embodiment, the second upper cover layer 226 may comprise a material substantially the same as the first upper cover layer 126. In one embodiment, the second upper intermetallic dielectric layer 227 may have a different structure than the second lower intermetallic dielectric layer 225. In one embodiment, the second upper intermetallic dielectric layer 227 may comprise a material substantially the same as the first upper intermetallic dielectric layer 127.

[0084] The second dummy pattern layer 230 may be disposed on the second upper metal-to-metal insulating layer 223. The lower surface of the second dummy pattern layer 230 may form a coplanar plane with the lower surface of the second passivation layer 240. The second dummy pattern layer 230 may overlap with at least a portion of the region between the second outer boundary 224 and the second inner boundary 243. One side surface of the second dummy pattern layer 230 may be located inside the second inner boundary 243.

[0085] The second dummy pattern layer 230 may have a third width W3. The second dummy pattern layer 230 may be located in the second scribbled area SR2. The second dummy pattern layer 230 may be disposed on the second insulating layer 220. In one embodiment, the second dummy pattern layer 230 may comprise a material substantially the same as the first dummy pattern layer 130.

[0086] The second passivation layer 240 may be disposed on the second insulating layer 220. The second passivation layer 240 may be located inside the second outer boundary 224. The second passivation layer 240 may include a second inner boundary 243 located inside the second outer boundary 224.

[0087] The second passivation layer 240 may include a second passivation oxide layer 241 and a second passivation nitride layer 242. In one embodiment, the second passivation layer 240 may include a material substantially the same as that of the first passivation layer 140. In one embodiment, the second passivation oxide layer 241 may include a material substantially the same as that of the first passivation oxide layer 141.

[0088] The second redistribution insulating layer 250 may be disposed on the second passivation layer 240. The second redistribution insulating layer 250 may include a material substantially the same as that of the first redistribution insulating layer 150.

[0089] The second redistribution pattern layer 260 may be disposed on the second dummy pattern layer 230. The second redistribution pattern layer 260 may be located in the second scribbling region SR2. The lower surface of the second redistribution pattern layer 260 (which forms the same plane as the upper surface of the second dummy pattern layer 230) may have a fourth width W4. In one embodiment, the third width W3 may be greater than the fourth width W4.

[0090] The distance from the upper surface of the second redistributed insulating layer 250 to the second dummy pattern layer 230 may be greater than the distance from the uppermost surface of the second redistributed pattern layer 260 to the second dummy pattern layer 230. The second redistributed pattern layer 260 may contact the upper surface of the second dummy pattern layer 230 located between the second outer boundary 224 and the second inner boundary 243. The second redistributed pattern layer 260 may contact the side surface of the second passivation layer 240 located between the second outer boundary 224 and the second inner boundary 243. The bottom surface of the second redistributed pattern layer 260 may be lower than the top surface of the second oxide passivation layer 241. In one embodiment, the top surface of the central portion of the top surface of the second redistributed pattern layer 260 may be coplanar with the top surface of the second passivation layer 240.

[0091] The second redistribution pattern layer 260 may be located outside the side surface of the second passivation layer 240. The second redistribution pattern layer 260 may be configured to overlap with the upper surface of the second dummy pattern layer 230. In one embodiment, the lower surface (or bottom surface) of the second redistribution pattern layer 260 may be flat, and the top surface of the second redistribution pattern layer 260 may have a flat central portion and two upwardly projecting leg ends, such that the second redistribution pattern layer 260 is generally bracket-shaped, wherein the flat portion of the bracket extends parallel to the top surface of the second dummy pattern layer 230, and the legs extend perpendicular to the flat portion.

[0092] Figure 4 It is shown Figure 2 The diagram shows another cross-sectional structure of the section shown by line I-I'.

[0093] In describing the following embodiments, descriptions of components that are substantially the same as those in the previous embodiment will be omitted.

[0094] refer to Figure 4 The first semiconductor device may include a first substrate 101, a first guard ring 110, a first insulating layer 120, a first dummy pattern layer 130, a first passivation layer 140, a first redistribution insulating layer 150, a first redistribution pattern layer 160, and a first lower dummy pattern layer 170.

[0095] The first lower dummy pattern layer 170 may include a plurality of first dummy metal contacts 171 and a plurality of first dummy metal layers 172 connected by the plurality of first dummy metal contacts 171. Each first dummy metal layer 172 may extend horizontally (i.e., parallel to the top surface of the substrate 101). Each first dummy metal contact 171 may extend perpendicularly to the top surface of the substrate 101. The uppermost first dummy metal contact 171 of the plurality of first dummy metal contacts 171 may be connected to the lower surface of the first dummy pattern layer 130.

[0096] In one embodiment, the first dummy metal contact 171 and the first dummy metal layer 172 may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination of at least two of these.

[0097] Refer again Figure 4 The second semiconductor device may include a second substrate 201, a second guard ring 210, a second insulating layer 220, a second dummy pattern layer 230, a second passivation layer 240, a second redistribution insulating layer 250, a second redistribution pattern layer 260, and a second lower dummy pattern layer 270.

[0098] The second lower dummy pattern layer 270 may include a plurality of second dummy metal contacts 271 and a plurality of second dummy metal layers 272 connected by the plurality of second dummy metal contacts 271. Each second dummy metal layer 272 may extend horizontally (i.e., parallel to the top surface of the substrate 201). Each second dummy metal contact 271 may extend perpendicularly to the top surface of the substrate 201. The uppermost second dummy metal contact 271 of the plurality of second dummy metal contacts 271 may be connected to the lower surface of the second dummy pattern layer 230.

[0099] In one embodiment, the second dummy metal contact 271 or the second dummy metal layer 272 may comprise a material substantially the same as the first dummy metal contact 171 or the first dummy metal layer 172.

[0100] Figure 5 It is shown Figure 2 The diagram shows another cross-sectional structure of the section shown by line I-I'.

[0101] refer to Figure 5 The first semiconductor device may include a first substrate 101, a first guard ring 110, a first insulating layer 120, a first dummy pattern layer 130, a first passivation layer 140, a first redistribution insulating layer 150, and a first redistribution pattern layer 160.

[0102] One side surface of the first dummy pattern layer 130 may be located inside the first inner boundary 143. Another side surface of the first dummy pattern layer 130 may be located inside the side surface of the first passivation layer 140. The other side surface of the first dummy pattern layer 130 may be located between the first outer boundary 124 and the first inner boundary 143. The other side surface of the first dummy pattern layer 130 may be located outside the side surface of the first passivation layer 140.

[0103] The first dummy pattern layer 130 may have a fifth width W5. In one embodiment, the fifth width W5 may be greater than the second width W2. Figure 5 In this embodiment, the side surface of the first dummy pattern layer 130 maintains a certain distance from the first outer boundary 124, for example, it may be located below the central portion of the first redistribution pattern layer 160. Therefore, a portion of the bottom surface of the first redistribution pattern layer 160 may contact the first passivation oxide layer 141.

[0104] Refer again Figure 5 The second semiconductor device may include a second substrate 201, a second guard ring 210, a second insulating layer 220, a second dummy pattern layer 230, a second passivation layer 240, a second redistribution insulating layer 250, and a second redistribution pattern layer 260.

[0105] One side surface of the second dummy pattern layer 230 may be located inside the second inner boundary 243. The said one side surface of the second dummy pattern layer 230 may be located inside the side surface of the second passivation layer 240. The other side surface of the second dummy pattern layer 230 may be located between the second outer boundary 224 and the second inner boundary 243. The said other side surface of the second dummy pattern layer 230 may be located outside the side surface of the second passivation layer 240.

[0106] The second dummy pattern layer 230 may have a sixth width W6. In one embodiment, the sixth width W6 may be greater than the fourth width W4. Figure 5In this embodiment, the side surface of the second dummy pattern layer 230 maintains a certain distance from the second outer boundary 224, for example, it may be located below the central portion of the second redistribution pattern layer 260. Therefore, a portion of the bottom surface of the second redistribution pattern layer 260 may contact the second passivation oxide layer 241.

[0107] Figure 6 It is shown Figure 2 The diagram shows another cross-sectional structure of the section shown by line I-I'.

[0108] refer to Figure 6 The first semiconductor device may include a first substrate 101, a first guard ring 110, a first insulating layer 120, a first dummy pattern layer 130, a first passivation layer 140, a first redistribution insulating layer 150, and a first redistribution pattern layer 160.

[0109] The first protective ring 110 may include a first upper protective metal layer 113 connected to a side surface of the first dummy pattern layer 130.

[0110] Refer again Figure 6 The second semiconductor device may include a second substrate 201, a second guard ring 210, a second insulating layer 220, a second dummy pattern layer 230, a second passivation layer 240, a second redistribution insulating layer 250, and a second redistribution pattern layer 260.

[0111] The second protective ring 210 may include a second upper protective metal layer 213 connected to a side surface of the second dummy pattern layer 230.

[0112] Figures 7 to 12 It shows the basis Figure 3 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0113] refer to Figure 7 A first protective metal contact 111 and a second protective metal contact 211 may be formed vertically on the substrate 10. The first protective metal contact 111 may be located in a first protective ring region GR1. The second protective metal contact 211 may be located in a second protective ring region GR2. A first protective metal layer 112 may be formed on the first protective metal contact 111. A second protective metal layer 212 may be formed on the second protective metal contact 211. Both the first protective metal layer 112 and the second protective metal layer 212 may extend in a horizontal direction parallel to the top surface of the substrate 10.

[0114] Refer again Figure 7 The first protective metal contact 111, the second protective metal contact 211, the first protective metal layer 112 and the second protective metal layer 212 may not be formed in the redistribution alignment key region AR.

[0115] refer to Figure 8 An interlayer insulating layer 21 may be formed on the substrate 10, and then a lower intermetallic insulating layer 22 may be formed on the interlayer insulating layer 21. The lower intermetallic insulating layer 22 may include a lower capping layer 23 and a lower intermetallic dielectric layer 24.

[0116] The first protective metal contact 111 and the second protective metal contact 211 can be formed by penetrating the lower cover layer 23 and the lower intermetallic dielectric layer 24. The first protective metal layer 112 can be formed on the first protective metal contact 111. The second protective metal layer 212 can be formed on the second protective metal contact 211.

[0117] refer to Figure 9 An upper intermetallic insulating layer 25 can be formed on the lower intermetallic insulating layer 22. The upper intermetallic insulating layer 25 may include an upper cover layer 26 and an upper intermetallic dielectric layer 27 formed on the upper intermetallic insulating layer 25. Thus, an insulating layer 20 can be formed on the substrate 10, which includes an interlayer insulating layer 21, a lower intermetallic insulating layer 22 and an upper intermetallic insulating layer 25.

[0118] The first protective metal contact 111 and the second protective metal contact 211 can be formed by penetrating the upper cover layer 26 and the upper intermetallic dielectric layer 27.

[0119] refer to Figure 10 A first upper protective metal layer 113 may be formed on the first protective metal contact 111. A second upper protective metal layer 213 may be formed on the second protective metal contact 211. A dummy pattern layer 30 may be formed on the insulating layer 20 in the scribing region SR. The dummy pattern layer 30 may include a first dummy pattern layer 130 and a second dummy pattern layer 230. The upper surface of the dummy pattern layer 30 may have a seventh width W7.

[0120] A passivation layer 40 may be formed on the insulating layer 20. The passivation layer 40 may include a passivation oxide layer 41 and a passivation nitride layer 42 formed on the passivation oxide layer 41.

[0121] refer to Figure 11 A redistributed insulating layer 50 may be formed on the passivation layer 40. The redistributed insulating layer 50 may include a first redistributed insulating layer 150 and a second redistributed insulating layer 250.

[0122] A redistributed via region VR can be formed through the redistributed insulating layer 50 and a portion of the passivation layer 40. The redistributed via region VR can be formed by anisotropic etching of the redistributed insulating layer 50 and the first passivation oxide layer 41 to expose a portion of the top surfaces of the first dummy pattern layer 130 and the second dummy pattern layer 230. In one embodiment, the redistributed via region VR may be strip-shaped, but embodiments are not limited thereto. The lower surface of the redistributed via region VR may contact a portion of the upper surface of the dummy pattern layer 30. The lower surface of the redistributed via region VR may have an eighth width W8.

[0123] Because the seventh width W7 of the upper surface of the dummy pattern layer 30 is greater than the eighth width W8 of the lower surface of the redistributed via region VR, the dummy pattern layer 30 can act as a buffer during the etching process. Therefore, the insulating layer 20 located below the dummy pattern layer 30 may not be etched. Thus, by preventing stress concentration in the redistributed via region VR, process defects such as cracks or delamination can be controlled, thereby preventing degradation of device characteristics.

[0124] refer to Figure 12 Conductive material 60 may be formed on the upper surface of the dummy pattern layer 30, the side surface of the passivation layer 40, and the side surface and part of the upper surface of the redistribution insulating layer 50. In one embodiment, conductive material 60 may include aluminum (Al).

[0125] Since the conductive material 60 is bonded to the dummy pattern layer 30, stress concentration in the redistributed via region VR can be reduced, thereby controlling process defects such as cracks or delamination at the bottom of the redistributed via region VR, thus preventing the deterioration of device characteristics.

[0126] Refer again Figure 3 A portion of the conductive material 60 can be removed by an etching process. This forms a first redistribution pattern layer 160 and a second redistribution pattern layer 260. The first redistribution pattern layer 160 can be located on the first dummy pattern layer 130. The second redistribution pattern layer 260 can be located on the second dummy pattern layer 230.

[0127] The distance from the upper surface of the first redistributed insulating layer 150 to the upper surface of the first dummy pattern layer 130 may be greater than the distance from the uppermost surface of the first redistributed pattern layer 160 to the upper surface of the first dummy pattern layer 130. The distance from the upper surface of the second redistributed insulating layer 250 to the upper surface of the second dummy pattern layer 230 may be greater than the distance from the uppermost surface of the second redistributed pattern layer 260 to the upper surface of the second dummy pattern layer 230.

[0128] Figures 13 to 16 It shows the basis Figure 4 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0129] refer to Figure 13 A first protective metal contact 111, a second protective metal contact 211, a first dummy metal contact 171, and a second dummy metal contact 271 can be formed on the substrate 10. The first protective metal contact 111 can be located in a first protective ring region GR1. The second protective metal contact 211 can be located in a second protective ring region GR2. The first dummy metal contact 171 can be located in a first scribe line region SR1. The second dummy metal contact 271 can be located in a second scribe line region SR2.

[0130] A first protective metal layer 112 may be formed on the first protective metal contact 111. A second protective metal layer 212 may be formed on the second protective metal contact 211. A first dummy metal layer 172 may be formed on the first dummy metal contact 171. A second dummy metal layer 272 may be formed on the second dummy metal contact 271.

[0131] refer to Figure 14 An interlayer insulating layer 21 may be formed on the substrate 10. A lower intermetallic insulating layer 22 may be formed on the interlayer insulating layer 21. The lower intermetallic insulating layer 22 may include a lower capping layer 23 and a lower intermetallic dielectric layer 24 formed on the lower capping layer 23.

[0132] The first protective metal contact 111, the second protective metal contact 211, the first dummy metal contact 171, and the second dummy metal contact 271 can be formed by penetrating the lower cover layer 23 and the lower intermetallic dielectric layer 24. The first protective metal layer 112 can be formed on the first protective metal contact 111. The second protective metal layer 212 can be formed on the second protective metal contact 211. The first dummy metal layer 172 can be formed on the first dummy metal contact 171. The second dummy metal layer 272 can be formed on the second dummy metal contact 271.

[0133] refer to Figure 15 An upper intermetallic insulating layer 25 can be formed on the lower intermetallic insulating layer 22. The upper intermetallic insulating layer 25 may include an upper cover layer 26 and an upper intermetallic dielectric layer 27 formed on the upper cover layer 26. In this way, an insulating layer 20 can be formed on the substrate 10, which includes an interlayer insulating layer 21, a lower intermetallic insulating layer 22 and an upper intermetallic insulating layer 25.

[0134] The first protective metal contact 111, the second protective metal contact 211, the first dummy metal contact 171, and the second dummy metal contact 271 can be formed by penetrating the upper cover layer 26 and the upper intermetallic dielectric layer 27.

[0135] refer to Figure 16A first upper protective metal layer 113 may be formed on the first protective metal contact 111. A second upper protective metal layer 213 may be formed on the second protective metal contact 211. A dummy pattern layer 30 may be formed on the insulating layer 20 in the scribing region SR. The dummy pattern layer 30 may include a first dummy pattern layer 130 and a second dummy pattern layer 230. The first dummy pattern layer 130 may be formed on the first dummy metal contact 171. The second dummy pattern layer 230 may be formed on the second dummy metal contact 271.

[0136] Refer again Figure 4 and Figure 11 A redistributed insulating layer 50 may be formed on the passivation layer 40. The redistributed insulating layer 50 may include a first redistributed insulating layer 150 and a second redistributed insulating layer 250.

[0137] A redistributed via region VR can be formed by passing through the redistributed insulating layer 50 and part of the passivation layer 40. The lower surface of the redistributed via region VR can contact part of the upper surface of the dummy pattern layer 30. The lower surface of the redistributed via region VR can have an eighth width W8.

[0138] refer to Figure 4 and Figure 12 Conductive material 60 can be formed on the upper surface of the dummy pattern layer 30, the side surface of the passivation layer 40, and the side surface and part of the upper surface of the redistribution insulating layer 50.

[0139] Refer again Figure 4 A portion of the conductive material 60 can be removed by an etching process. This forms a first redistribution pattern layer 160 and a second redistribution pattern layer 260. The first redistribution pattern layer 160 can be located on the first dummy pattern layer 130. The second redistribution pattern layer 260 can be located on the second dummy pattern layer 230.

[0140] Figure 17 It shows the basis Figure 5 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0141] Figure 17 The semiconductor device shown can be used in conjunction with the reference above. Figures 7 to 9 The semiconductor device described is formed using the same method as the manufacturing process.

[0142] refer to Figure 17 A first upper protective metal layer 113 may be formed on the first protective metal contact 111. A second upper protective metal layer 213 may be formed on the second protective metal contact 211. A first dummy pattern layer 130 and a second dummy pattern layer 230 may be formed on the insulating layer 20 in the scribing region SR.

[0143] Refer again Figure 5 and Figure 11 A redistributed insulating layer 50 may be formed on the passivation layer 40. The redistributed insulating layer 50 may include a first redistributed insulating layer 150 and a second redistributed insulating layer 250.

[0144] A redistributed via region VR can be formed by passing through the redistributed insulating layer 50 and part of the passivation layer 40. The lower surface of the redistributed via region VR can contact part of the upper surface of the dummy pattern layer 30. The lower surface of the redistributed via region VR can have an eighth width W8.

[0145] refer to Figure 5 and Figure 12 Conductive material 60 can be formed on the upper surface of the dummy pattern layer 30, the side surface of the passivation layer 40, and the side surface and part of the upper surface of the redistribution insulating layer 50.

[0146] Refer again Figure 5 A portion of the conductive material 60 can be removed by an etching process. This forms a first redistribution pattern layer 160 and a second redistribution pattern layer 260. The first redistribution pattern layer 160 may be located on a portion of the upper surface of the first dummy pattern layer 130. The second redistribution pattern layer 260 may be located on a portion of the upper surface of the second dummy pattern layer 230.

[0147] Figure 18 It shows the basis Figure 6 A diagram illustrating a method for forming a semiconductor device according to a disclosed embodiment.

[0148] Figure 18 The semiconductor device shown can be used in conjunction with the reference above. Figures 7 to 9 The semiconductor device described is formed using the same method as the manufacturing process.

[0149] refer to Figure 18 A first dummy pattern layer 130 and a second dummy pattern layer 230 can be formed on the insulating layer 20 in the marking area SR.

[0150] A first upper protective metal layer 113 may be formed on the uppermost of the plurality of first protective metal contacts 111. Figure 18 In the embodiment shown, the first upper protective metal layer 113 may be connected to a side surface of the first dummy pattern layer 130.

[0151] The second upper protective metal layer 213 may be formed on the uppermost of the plurality of second protective metal contacts 211. Figure 18 In the illustrated embodiment, the second upper protective metal layer 213 may be connected to a side surface of the second dummy pattern layer 230.

[0152] Refer again Figure 6 and Figure 11 A redistributed insulating layer 50 may be formed on the passivation layer 40. The redistributed insulating layer 50 may include a first redistributed insulating layer 150 and a second redistributed insulating layer 250.

[0153] A redistributed via region VR can be formed by passing through the redistributed insulating layer 50 and part of the passivation layer 40. The lower surface of the redistributed via region VR can contact part of the upper surface of the dummy pattern layer 30. The lower surface of the redistributed via region VR can have an eighth width W8.

[0154] refer to Figure 6 and Figure 12 Conductive material 60 can be formed on the upper surface of the dummy pattern layer 30, the side surface of the passivation layer 40, and the side surface and part of the upper surface of the redistribution insulating layer 50.

[0155] Refer again Figure 6 A portion of the conductive material 60 can be removed by an etching process. This forms a first redistribution pattern layer 160 and a second redistribution pattern layer 260. The first redistribution pattern layer 160 may be located on a portion of the upper surface of the first dummy pattern layer 130. The second redistribution pattern layer 260 may be located on a portion of the upper surface of the second dummy pattern layer 230.

[0156] While this disclosure has disclosed some detailed embodiments, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All changes within the equivalent meaning and scope of the claims are included within its scope. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: An insulating layer disposed on a substrate, the insulating layer including an outer boundary; A passivation layer is disposed on the insulating layer, the passivation layer including an inner boundary; A dummy pattern layer is provided, the lower surface of which is coplanar with the lower surface of the passivation layer. as well as A redistributed pattern layer is disposed on the dummy pattern layer. Wherein, the dummy pattern layer overlaps with at least a portion of the region extending between the outer boundary and the inner boundary, and One side surface of the dummy pattern layer is located inside the inner boundary.

2. The semiconductor device according to claim 1, wherein, The redistribution pattern layer contacts the upper surface of the dummy pattern layer and the side surface of the passivation layer, the passivation layer being disposed between the outer boundary and the inner boundary.

3. The semiconductor device according to claim 2, further comprising: A redistributed insulating layer is disposed on the passivation layer. Wherein, the distance from the upper surface of the redistributed insulating layer to the upper surface of the dummy pattern layer is greater than the distance from the uppermost surface of the redistributed pattern layer to the upper surface of the dummy pattern layer.

4. The semiconductor device according to claim 1, wherein, The passivation layer comprises high-density plasma HDP oxide, nitride, or a combination thereof.

5. The semiconductor device according to claim 1, further comprising: A dummy metal contact is provided, which is connected to the lower surface of the dummy pattern layer.

6. The semiconductor device according to claim 1, wherein, The other side surface of the dummy pattern layer is located between the outer boundary and the inner boundary.

7. The semiconductor device of claim 1 further includes a guard ring disposed on the substrate and located inside the inner boundary.

8. The semiconductor device according to claim 7, wherein: The protective ring includes an upper protective metal layer, and The upper surface of the upper protective metal layer is coplanar with the upper surface of the dummy pattern layer.

9. The semiconductor device according to claim 8, wherein, The upper protective metal layer comprises the same material as the dummy pattern layer.

10. The semiconductor device according to claim 8, wherein, The upper protective metal layer is connected to the dummy pattern layer.

11. A semiconductor device, comprising: The substrate includes the chip region and the scribe region; An insulating layer disposed on the substrate; A dummy pattern layer is disposed on the insulating layer in the scribed area; A passivation layer is disposed on the insulating layer; as well as A redistribution pattern layer is disposed outside the passivation layer to overlap with the dummy pattern layer. Wherein, the passivation layer at least partially overlaps with the dummy pattern layer, and In this case, one side surface of the dummy pattern layer is located inside the side surface of the passivation layer.

12. The semiconductor device according to claim 11, wherein, The redistribution pattern layer contacts the side surface of the passivation layer.

13. The semiconductor device of claim 11, further comprising a redistributed insulating layer disposed on the passivation layer, in, The distance from the upper surface of the redistributed insulating layer to the upper surface of the dummy pattern layer is greater than the distance from the uppermost surface of the redistributed pattern layer to the upper surface of the dummy pattern layer.

14. The semiconductor device according to claim 11, wherein, The passivation layer comprises high-density plasma HDP oxide, nitride, or a combination thereof.

15. The semiconductor device of claim 11, further comprising a dummy metal contact connected to the lower surface of the dummy pattern layer.

16. The semiconductor device according to claim 11, wherein, The other side surface of the dummy pattern layer is located outside the side surface of the passivation layer.

17. The semiconductor device of claim 11, further comprising a guard ring disposed on the substrate and inside the side surface of the passivation layer.

18. The semiconductor device according to claim 17, wherein: The protective ring includes an upper protective metal layer, and The upper surface of the upper protective metal layer is coplanar with the upper surface of the dummy pattern layer.

19. The semiconductor device according to claim 18, wherein, The upper protective metal layer comprises the same material as the dummy pattern layer.

20. The semiconductor device according to claim 18, wherein, The upper protective metal layer is connected to the dummy pattern layer.

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