Semiconductor device and method of controlling underfill overflow

Abstract

Semiconductor devices and methods of controlling underfill overflow. A semiconductor device has a substrate and an interconnect structure formed over a die attach region of the substrate. An insulating layer is formed over a surface of the substrate. A trench is formed in the insulating layer between the die attach region and the interconnect structure to extend around a perimeter of the die attach region. A semiconductor die is disposed over the die attach region. An underfill material is deposited under the semiconductor die. The trench prevents or impedes excess underfill material from reaching the interconnect structure. A T-bar structure is formed between the die attach region and the interconnect structure to extend around the perimeter of the die attach region. The trench and / or the T-bar structure operate as an overflow structure to impede flow of the underfill material. Multiple trenches and / or multiple T-bar structures can alternate around the perimeter of the die attach region.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more specifically to semiconductor devices and methods for controlling bottom fill overflow. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] For space efficiency, semiconductor dies and / or semiconductor wafers can be stacked. Figure 1 The illustration shows a conventional semiconductor wafer or die 50 with a conductive layer 52 and bumps 54. A semiconductor die 60 is mounted to the semiconductor wafer / die 50 in a die attachment region 62, where bumps 64 connect the conductive layer 62 and contact pads 68. In a stacked arrangement, the semiconductor wafer / die 50 may be referred to as the mother die, and the semiconductor die 60 may be referred to as the daughter die. Underfill material 70 is deposited beneath the semiconductor die 60 for structural support and environmental protection. Depending on the manufacturing process, the distribution of underfill material 70 is often difficult to control. Excess underfill material 70 may seep out from the die attachment region 62 or otherwise overflow and reach the bumps 54, resulting in electrical isolation or short-circuit conditions in the interconnect structure, depending on the underfill material and other inspection and manufacturing defects. Attached Figure Description

[0004] Figure 1 The illustration shows the traditional bottom fill overflow to the nearby bump; Figures 2a-2f The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw marks; Figures 3a-3l The illustration shows the process of forming an overflow structure as a trench between the die attachment region and the interconnect structure formed on the substrate. Figures 4a-4f The illustration shows another process for forming an overflow structure as a T-bar structure between the die attachment region and the interconnect structure formed on the substrate; Figure 5 An embodiment with a tall T-shaped strip structure is illustrated; Figure 6 An embodiment with a groove and T-strip structure is illustrated; Figures 7a-7bAn embodiment with alternating grooves and T-strip structures is illustrated; and Figure 8 The illustration shows a printed circuit board (PCB) with different types of packages arranged on its surface. Detailed Implementation

[0005] In the following description with reference to the figures, the invention is described in one or more embodiments, wherein the same numerals denote the same or similar elements. While the invention has been described in terms of the best mode for carrying out its objectives, those skilled in the art will appreciate that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, supported by the following disclosure and the accompanying drawings. The term “semiconductor die” as used herein refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between the voltage and current necessary for the circuit to function.

[0007] Back-end manufacturing refers to the process of dicing or isomerizing a finished wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To isomerize a semiconductor die, the wafer is scribed and broken along non-functional regions (called serrations or cuts). This is done using laser cutting tools or saw blades. After isomerization, the individual semiconductor dies are placed on a packaging substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor dies are then connected to contact pads within the package. Electrical connections can be achieved using conductive layers, bumps, column bumps, conductive paste, or wirebonding. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the functionality of the semiconductor device available to other system components.

[0008] Figure 2aA semiconductor wafer 100a with a base substrate material 102 is shown, which is, for example, silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material used for structural support. Multiple semiconductor dies or components 104a are formed on the wafer 100a, separated by non-active inter-die wafer regions or saw tracks 106a. The saw tracks 106a provide dicing areas to single-individualize the semiconductor wafer 100a into individual semiconductor dies 104a. In one embodiment, the semiconductor wafer 100a is circular with a diameter of 100-450 millimeters (mm). The semiconductor wafer 100a can be rectangular or any other geometry.

[0009] Figure 2b A cross-sectional view of a portion of a semiconductor wafer 100a is shown. Each semiconductor die 104a has a back surface or non-active surface 108a and an active layer 110a, the active layer 110a containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers, formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active layer 110a to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. The semiconductor die 104a may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed above or inside the active layer 110a using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads or a redistribution layer (RDL) electrically connected to circuitry within the active layer 110a. Depending on the design and function of the semiconductor die 104a and other electrical components within the semiconductor wafer 100a, portions of the conductive layer 112 can be electrically shared or electrically isolated.

[0011] An insulating or dielectric layer 114 is formed over the active surface 110a and the conductive layer 112 using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. The insulating layer 114 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties.

[0012] exist Figure 2c In this process, a semiconductor wafer 100a is monomerized into individual semiconductor dies 104a using a saw blade or laser cutting tool 118 through a saw path 106a. Individual semiconductor dies 104a can be inspected and electrically tested to identify known good dies or cells (KGD / KGU) after monomerization.

[0013] In another case, Figure 2d A semiconductor wafer 100b, similar in fabrication to semiconductor wafer 100a, is shown. Multiple semiconductor dies or components 104b are formed on the wafer 100b, separated by non-active inter-die regions or saw teeth 106b. The saw teeth 106b provide dicing areas to individualize the semiconductor wafer 100b into individual semiconductor dies 104b. In one embodiment, the semiconductor wafer 100b is circular with a diameter of 100-450 mm. The semiconductor wafer 100b can be rectangular or any other geometry.

[0014] Figure 2e A cross-sectional view of a portion of a semiconductor wafer 100b is shown. Each semiconductor die 104b has a back surface or non-active surface 108b and an active layer 110b, the active layer 110b containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers. This circuitry is formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active layer 110b to implement analog or digital circuitry, such as DSPs, ASICs, memory, or other signal processing circuitry. The semiconductor die 104b may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors. The semiconductor die 104b may have different electrical functions than the semiconductor die 104a.

[0015] A conductive layer 120 is formed above or inside the active layer 110b using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 120 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 120 functions as contact pads or RDLs electrically connected to circuitry in the active layer 110b.

[0016] Conductive bump material is deposited over conductive layer 120 using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 120 using suitable attachment or bonding processes. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 122. In one embodiment, bumps 122 are formed over under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 122 can also be compression bonded or thermo-pressed bonded to conductive layer 120. Bumps 122 represent a type of interconnect structure that can be formed over conductive layer 120. The interconnect structure can also use bonding wires, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0017] exist Figure 2f In this process, a saw blade or laser cutting tool 118 is used to monomerize a semiconductor wafer 100b into individual semiconductor dies 104b through a saw path 106b. The individual semiconductor dies 104b can be inspected and electrically tested to identify KGD / KGU after monomerization.

[0018] Figure 3a Further details are shown of a portion of a semiconductor wafer 100a before monomerization or a portion of a semiconductor die 104a after monomerization. In one embodiment, the insulating layer 114 has a thickness T1 of 10.0 micrometers (μm). A portion of the insulating layer 114 is removed using a laser 131 via an etching process or laser direct ablation (LDA) to form openings or trenches 130a-130f. Openings 130a, 130d, 130e, and 130f extend downwards into and expose the conductive layer 112. The locations of openings 130a, 130d, 130e, and 130f are selected to align with the conductive layer 112. Trenches 130b and 130c extend downwards into the insulating layer 114, reaching the active surface 110a, or reaching a level above the active surface. For example, Figure 3b Further details of trenches 130b and 130c in region 132 are shown, which extend into the insulating layer 114 above the active surface 110a, with a depth D1 less than 10.0 μm and a width W1 of at least 50.0 μm. Figure 3cThis is a top view of a semiconductor die 104a having openings 130a, 130d, 130e, and 130f exposing a conductive layer 112, and trenches 130b and 130c extending around the perimeter of the die attachment region 134. As will be shown, trenches 130b and 130c serve as overflow structures to absorb, block, prevent, or otherwise suppress any overflow of underfill material to other interconnect structures.

[0019] exist Figure 3d In this process, a photoresist layer 140 is deposited on top of the semiconductor wafer 100a or the semiconductor die 104a. Figure 3e In this process, the photoresist layer 140 is subjected to LDA or patterned and etched over the conductive layer 112 to form the opening 142. Figure 3f In the photoresist layer 140, the openings 142 are filled with conductive material, such as Al, Cu, Sn, Ni, Au, Ag or other suitable conductive material, to form conductive pillars 144.

[0020] exist Figure 3g In this process, conductive bump material is deposited on the conductive post 144 using evaporation, electrolytic plating, electroless plating, droplet coating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive post 144 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form a ball or bump 146. In one embodiment, the bump 146 is formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bump 146 can also be compression bonded or thermocompressed bonded to the conductive post 144. The bump 146 represents a type of interconnect structure that can be formed on the conductive post 144. The interconnect structure can also use bonding wires, conductive paste, cylindrical bumps, microbumps, or other electrical interconnects. The combination of conductive pillars 144 and bumps 146 constitutes a vertical interconnect structure 148.

[0021] exist Figure 3h In the process, the photoresist layer 140 is removed, leaving interconnect structures 148 over the conductive layer 112 of the semiconductor die 104a. One or more electrical components 150 are disposed over the die attachment region 134 using pick-and-place operations, with bumps 122 oriented toward the conductive layer 112. In one embodiment, the electrical component 150 may be from... Figure 2fThe semiconductor die 104b is the primary component. Alternatively, the electrical component 150 may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs. In this case, in the stacked semiconductor arrangement, semiconductor die 104a is considered the mother die, i.e., the larger semiconductor die, and semiconductor die 104b is considered the daughter die, i.e., smaller than semiconductor die 104a. Semiconductor die 104a may have a large size of approximately 2.0 × 2.0 mm, while semiconductor die 104b may be smaller than semiconductor die 104a, typically approximately 1.0 × 1.0 mm. Figure 3i An electrical component 150 is shown mounted to a semiconductor die 104a, wherein a bump 122 is electrically and mechanically bonded to a conductive layer 112 in a die attachment region 134.

[0022] exist Figure 3j In this process, underfill material 156 is deposited beneath electrical component 150. The distribution of underfill material 156 can be difficult to control. Any excess underfill material 156 may flow outwards from the perimeter of electrical component 150. Underfill material 156 should not be allowed to reach interconnect structure 148, as that could lead to defects. When underfill material 156 reaches trench 130c, the trench operates as an overflow structure to absorb, block, prevent, or otherwise inhibit further advance of the underfill material. That is, excess underfill material 156 flows into trench 130c and prevents outward flow of underfill material toward interconnect structure 148. Figure 3k A top view shows trenches 130b and 130c arranged around the perimeter of the electrical component 150 to surround all sides of the electrical component. The bottom fill material 156 is shown as being blocked by the trenches 130c in the stacked semiconductor package 158.

[0023] If the capacity of trench 130c is insufficient to prevent the outward flow of underfill material 156, trench 130b operates as a second overflow structure to provide a next layer of protection, thereby absorbing, blocking, preventing, or otherwise inhibiting the further advance of underfill material. When underfill material 156 reaches trench 130b, the trench operates as a second overflow structure to absorb, block, prevent, or otherwise inhibit the further advance of underfill material. That is, excess underfill material 156 flows into trench 130b and prevents the outward flow of underfill material toward interconnect structure 148. Figure 3l A top view of the bottom fill material 156 blocked by the groove 130b is shown.

[0024] Trench 130b and 130c control the overflow of excess underfill material 156 seeping from beneath semiconductor die 104b. This embodiment illustrates two trenches 103b and 130c. Only one trench may exist, or more than two trenches may exist. In any case, depending on the control of the underfill material 156, one or more trenches are provided around the perimeter of die attachment region 134 and electrical component 150 to prevent or block underfill material from reaching interconnect structure 148.

[0025] In another embodiment, from Figure 3h Continuing, trenches 130b and 130c are filled with a solid material, such as metal, polymer, or epoxy resin, to form T-shaped strip structures 160a and 160b, as shown below. Figure 4a As shown in the figure. Components with similar functions are given the same reference numerals. Grooves 130b and 130c may have a width W2 of at least 20.0 μm. T-shaped strip structures 160a-160b have a width W3 of approximately 30.0 μm.

[0026] One or more electrical components 150 are positioned over the die attachment region 134 using a pick-and-place operation, wherein the bumps 122 are oriented toward the conductive layer 112. In one embodiment, the electrical component 150 may be from... Figure 2f The semiconductor die 104b is the primary component. Alternatively, the electrical component 150 may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs. In this case, in a stacked arrangement, semiconductor die 104a is considered the mother die, i.e., the larger semiconductor die, and semiconductor die 104b is considered the daughter die, i.e., smaller than semiconductor die 104a. Figure 4b An electrical component 150 is shown mounted to a semiconductor die 104a, wherein bumps 122 are electrically and mechanically bonded to a conductive layer 112 in a die attachment region 134.

[0027] Figure 4c This is a top view of semiconductor die 104a, in which bumps 146 of interconnect structure 148 and T-shaped strip structures 160a and 160b extend around the perimeter of die attachment region 134. T-shaped strip structures 160a and 160b can be formed in the same photomask as conductive layer 112, i.e., prior to the formation of interconnect structure 148. As will be shown, T-shaped strip structures 160a and 160b serve as overflow structures to absorb, block, prevent, or otherwise suppress any overflow of underfill material to interconnect structure 148.

[0028] exist Figure 4dIn this configuration, underfill material 164 is deposited beneath electrical components 150. The distribution of underfill material 164 can be difficult to control. Any excess underfill material 164 may flow outwards from the perimeter of electrical components 150. Underfill material 164 should not be allowed to reach interconnect structures 148, as this could lead to defects. When underfill material 164 reaches T-bar structure 160a, the T-bar structure operates as an overflow structure to absorb, block, prevent, or otherwise inhibit further advance of the underfill material. That is, excess underfill material 164 flows upwards against T-bar structure 160a, and possibly over its top surface, to prevent outward flow of underfill material toward interconnect structures 148 in the stacked semiconductor package 166. Figure 4e A top view is shown of T-shaped strip structures 160a and 160b arranged around the perimeter of the electrical component 150 to surround all sides of the electrical component. The bottom filler material 164 is shown as being blocked by the T-shaped strip structure 160a in the stacked semiconductor package 166.

[0029] If the capacity of the T-shaped strip structure 160a is insufficient to prevent the outward flow of the bottom filler material 164, the T-shaped strip structure 160b operates as a second overflow structure to provide a next layer of protection, thereby absorbing, blocking, preventing, or otherwise inhibiting the further advance of the bottom filler material. When the bottom filler material 164 reaches the T-shaped strip structure 160b, the T-shaped strip structure operates as a second overflow structure to absorb, block, prevent, or otherwise inhibit the further advance of the bottom filler material. That is, excess bottom filler material 164 flows upward against the T-shaped strip structure 160a, and possibly above its top surface, to prevent the outward flow of bottom filler material toward the interconnect structure 148. Figure 4f The bottom fill material 164 is shown being blocked by the T-shaped strip structure 160b.

[0030] T-shaped strip structures 160a and 160b control the overflow of excess underfill material 164 seeping from beneath the semiconductor die 104b. This embodiment illustrates two T-shaped strip structures 160a and 160b. Only one T-shaped strip structure may be present, or more than two may be present. In any case, depending on the control of the underfill material 164, one or more T-shaped strip structures are disposed around the perimeter of the die attachment region 134 and the electrical component 150 to prevent or block underfill material from reaching the interconnect structure 148.

[0031] In another embodiment, from Figure 4d Continuing, trenches 130b and 130c are filled with a solid material, such as metal, polymer, or epoxy resin, to form T-shaped strip structures 160a and 160b, as shown below. Figure 5As shown in the diagram. In this case, the T-shaped strip structures 160a and 160a have a height H1 of at least 20.0 μm above surface 128, which is greater than... Figure 4d The height shown in the image. Similar to... Figures 4d-4f , Figure 5 The T-shaped strip structures 160a and 160b in the package operate as overflow structures to absorb, block, prevent, or otherwise inhibit the further advance of the underfill material in the stacked semiconductor package 168. The T-shaped strip structures 160a and 160b can be formed in the same photomask as the conductive layer 112, i.e., before the interconnect structure 148 is formed.

[0032] In another embodiment, from Figure 3i Continuing, trench 130b is filled with a solid material, such as metal, polymer, or epoxy resin, to form a T-shaped strip structure 170, such as... Figure 6 As shown in the diagram. Trench 130c remains open. Alternatively, trench 130c is filled with a solid material, such as metal, polymer, or epoxy resin, to form a T-bar structure 170, and trench 130b remains open. The T-bar structure 170 can be formed in the same photomask as the conductive layer 112, i.e., before the interconnect structure 148 is formed.

[0033] Similar to Figure 4d Underfill material 174 is deposited beneath electrical component 150. The distribution of underfill material 174 can be difficult to control. Any excess underfill material 174 may flow outwards from the perimeter of electrical component 150. Underfill material 174 should not be allowed to reach interconnect structure 148, as that could lead to defects. When underfill material 174 reaches trench 130c, the trench operates as an overflow structure to absorb, block, prevent, or otherwise inhibit further advance of the underfill material. That is, excess underfill material 174 flows into trench 130c and prevents outward flow of underfill material toward interconnect structure 148 in stacked semiconductor package 176.

[0034] If the capacity of trench 130c is insufficient to prevent the outward flow of bottom filler material 174, the T-shaped strip structure 170 operates as an overflow structure to provide a next layer of protection, thereby absorbing, blocking, preventing, or otherwise inhibiting the further advance of the bottom filler material. When the bottom filler material 174 reaches the T-shaped strip structure 170, the T-shaped strip structure operates as an overflow structure to absorb, block, prevent, or otherwise inhibit the further advance of the bottom filler material. That is, with Figure 3k-3lSimilar to 4e-4f, excess underfill material 164 flows upward against the T-shaped strip structure 170 and, possibly above its top surface, prevents the underfill material from flowing outward toward the interconnect structure 148 in the stacked semiconductor package 176.

[0035] The trench 130c and the T-bar structure 170 control the overflow of excess underfill material 174 seeping from beneath the semiconductor die 104b. This embodiment illustrates a trench 130c and a T-bar structure 170. Any combination of trench and T-bar structures can be present. For example, Figure 7a T-shaped stripe structures 180a, trenches 180b, T-shaped stripe structures 180c, and trenches 180d are shown alternating between the die attachment region 134 and the interconnect structure 148. T-shaped stripe structures 180a and 180c can be formed similarly to T-shaped stripe structures 160a-160b. T-shaped stripe structures 180a and 180c can be formed in the same photomask as the conductive layer 112, i.e., prior to the formation of the interconnect structure 148. In any case, depending on the control of the underfill material 174, one or more trenches and one or more T-shaped stripe structures are disposed around the perimeter of the die attachment region 134 and the electrical component 150, and may be alternated in arrangement to prevent the underfill material from reaching the interconnect structure 148 in the stacked semiconductor package 180. Figure 7b A top view is shown of excess underfill material 174 prevented between trench 180b and T-bar structure 180a in a stacked semiconductor package 180.

[0036] Figure 8 The illustration shows an electrical device 400 having a chip carrier substrate or PCB 402, wherein multiple semiconductor packages are disposed on the surface of the PCB 402, including stacked semiconductor packages 158, 166, 168, 176, and 180. Depending on the application, the electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages.

[0037] Electrical device 400 may be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electrical device 400 may be a sub-component of a larger system. For example, electrical device 400 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electrical device. Alternatively, electrical device 400 may be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for product market acceptance. The spacing between semiconductor devices can be reduced to achieve higher density.

[0038] exist Figure 8 In this PCB 402, a general-purpose substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on or within the surface of the PCB 402 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each semiconductor package, mounted components, and other external system components. Trace 404 also provides power and ground connections to each semiconductor package.

[0039] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first-level package in which the die is mechanically and electrically disposed directly on the PCB.

[0040] For illustrative purposes, several types of first-level packages, including wire bond packages 406 and flip chips 408, are shown on PCB 402. Additionally, several types of second-level packages, including ball grid arrays (BGAs) 410, bump chip carriers (BCCs) 412, pad gate arrays (LGAs) 416, multi-chip modules (MCMs) or SIP modules 418, square flat no-lead packages (QFNs) 420, square flat packages 422, embedded wafer-level ball grid arrays (eWLBs) 424, and wafer-level chip-level packages (WLCSPs) 426, are shown disposed on PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer-level package (Fo-WLP), and the WLCSP 426 is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured with any combination of first and second-level package styles, along with other electrical components, can be connected to PCB 402. In some embodiments, electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, leading to lower costs for consumers.

[0041] Although one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: The substrate including the die attachment area; Interconnect structures formed above the substrate; Trenches are formed between the die attachment area and the interconnect structure; A semiconductor die positioned above the die attachment area; and Underfill material deposited beneath the semiconductor die, with trenches preventing excessive underfill material from reaching the interconnect structure.

2. The semiconductor device of claim 1, further comprising an insulating layer formed above the surface of the substrate, wherein the trench is formed in the insulating layer.

3. The semiconductor device of claim 1 further includes a T-shaped strip structure formed between the die attachment region and the interconnect structure.

4. The semiconductor device of claim 3, wherein the T-shaped strip structure extends around the perimeter of the die attachment region.

5. The semiconductor device of claim 1, further comprising a plurality of alternating trenches and a plurality of T-shaped strip structures surrounding the periphery of the die attachment region.

6. A semiconductor device, comprising: Substrate; Overflow structures are formed around the die attachment area of ​​the substrate; A semiconductor die positioned above the die attachment area; and Underfill material deposited beneath the semiconductor die, with overflow structures preventing the underfill material from being deposited.

7. The semiconductor device of claim 6 further includes an insulating layer formed above the surface of the substrate.

8. The semiconductor device of claim 7, wherein the overflow structure comprises a trench formed in an insulating layer surrounding the die attachment region.

9. The semiconductor device of claim 6, wherein the overflow structure further comprises a T-shaped strip structure formed around the die attachment region.

10. The semiconductor device of claim 6, further comprising an interconnect structure formed above the substrate, wherein the overflow structure prevents excessive underfill material from reaching the interconnect structure.

11. A method for manufacturing a semiconductor device, comprising: Provide a substrate including a die attachment area; An interconnect structure is formed over the substrate; An overflow structure is formed between the die attachment area and the interconnect structure; The semiconductor die is positioned above the die attachment area; and An underfill material is deposited beneath the semiconductor die, where an overflow structure prevents excessive underfill material from reaching the interconnect structure.

12. The method of claim 11, further comprising forming an insulating layer over the surface of the substrate.

13. The method of claim 12, wherein forming the overflow structure comprises forming a trench in an insulating layer surrounding the die attachment region.

14. The method of claim 11, wherein forming the overflow structure further comprises forming a T-shaped strip structure around the die attachment region.

15. The method of claim 11, wherein forming the overflow structure further comprises forming a plurality of alternating grooves and a plurality of T-shaped strip structures around the perimeter of the die attachment region.

Images