A method of manufacturing a semiconductor chip

Abstract

The application belongs to the technical field of semiconductor manufacturing process, and discloses a manufacturing method of a semiconductor chip, which comprises the following steps: setting a solder pad at a preset pin soldering position of a substrate of the semiconductor chip and forming an electrical connection with a functional layer of the chip; then forming a green oil layer covering the functional layer of the chip and avoiding the solder pad; then adhering pins on a lead frame to the solder pad and performing reflow soldering treatment; then pouring plastic sealing material to cover the functional layer of the chip, the solder pad and the pin connection part, and the free end of the pin extends outward; then performing first heating treatment to make the plastic sealing material semi-solidified, and then performing cutting treatment; then performing second heating treatment to make the plastic sealing material completely solidified, and the manufacturing of the semiconductor chip is completed. The application breaks the process and structure limitations of traditional semiconductor pin packaging, realizes the universal layout and flexible adaptation of the lead frame, reduces the mold development cost and shortens the product development and production cycle from the source, and effectively improves the compatible adaptation capability of the packaging product in different application scenarios.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing process technology, and specifically relates to a method for manufacturing a semiconductor chip. Background Technology

[0002] Semiconductor device packaging is a key step in ensuring the electrical performance and structural stability of chips. The rationality of pin design and packaging process directly determines the product's compatibility, reliability, and overall production cost.

[0003] In traditional semiconductor device packaging processes, pins need to be pre-defined as functional pins and dummy pins (non-functional pins) during the design phase based on specific application schemes. Different application schemes correspond to different pin definitions and lead frame structures. This design approach requires the targeted development of lead frames, stamping dies, molding dies, and lead trimming dies, which not only significantly increases the cost of mold development but also extends the product R&D and production cycle, resulting in poor versatility of packaged products. Furthermore, the pre-differentiation of functional and dummy pins necessitates the manual or mechanical removal of dummy pins that are not yet soldered during subsequent production. This process is not only cumbersome and complex but also prone to causing mechanical damage to the product during removal, reducing production efficiency and product yield. Furthermore, traditional packaging processes set lead cutting and molding as two independent steps. The order of these two steps has obvious defects. When molding is performed before lead cutting, the fully cured molded body has high hardness. The mechanical stress generated during lead cutting can easily be transmitted to the soldering position between the pin and the pad, causing quality problems such as pad cracking and cold solder joints. When lead cutting is performed before molding, the pin will lose the support of the frame connecting ribs and deform, which will affect the subsequent soldering accuracy and molding effect. Summary of the Invention

[0004] This application aims to improve at least one technical problem in the background art.

[0005] This application provides a method for manufacturing a semiconductor chip, comprising the following steps: Semiconductor chip semi-finished product A is obtained. Semiconductor chip semi-finished product A includes a substrate and a chip functional layer disposed on one side of the substrate. Pads are disposed at preset pin soldering positions on the edge of the substrate so that the pads are electrically connected to the chip functional layer to obtain semiconductor chip semi-finished product B. A green solder mask layer is formed on the semiconductor chip semi-finished product B, such that the green solder mask layer covers the chip functional layer and avoids the pads, to obtain the semiconductor chip semi-finished product C; Obtain the lead frame, apply solder paste to the pads, attach the pins on the lead frame to the pads, and then perform reflow soldering to obtain a semiconductor chip semi-finished product D. A molding compound is injected into the semiconductor chip semi-finished product D. The molding compound covers the chip functional layer, the pads, and the connection between the pins and the pads. The free ends of the pins extend out of the molding compound. Then, a first heat treatment is performed until the molding compound reaches a semi-cured state to obtain the semiconductor chip semi-finished product E. The semiconductor chip semi-finished product E is subjected to a rib-cutting process, and then a second heat treatment is performed until the molding compound reaches a fully cured state.

[0006] Furthermore, the thickness of the green oil layer is 10μm-30μm.

[0007] Furthermore, the temperature of the first heat treatment is 120℃-130℃, and the time is 20min-40min.

[0008] Furthermore, the molding compound includes epoxy resin; when the first heat treatment is performed until the molding compound reaches a semi-cured state, the gel rate of the molding compound is 75%-85%.

[0009] Furthermore, the temperature of the second heat treatment is 140℃-160℃, and the time is 40min-80min.

[0010] Furthermore, the shearing force applied during the tendon cutting process does not exceed 50N.

[0011] Furthermore, the reflow soldering process is performed at a temperature of 255℃-265℃ for a duration of 8s-12s.

[0012] Furthermore, the pads are tin-plated before the green solder mask is formed.

[0013] The beneficial effects of this application are as follows: This application, through an integrated lead-cutting and molding process design, breaks through the limitations of traditional semiconductor lead packaging processes and structures, achieving a universal layout and flexible adaptation of the lead frame. This reduces mold development costs and shortens product development and mass production cycles from the source, effectively improving the compatibility of packaged products in different application scenarios. This solution simplifies the overall packaging process, eliminating the tedious operation of pre-identifying and manually removing dummy leads, reducing the risk of product damage during processing, and significantly improving production efficiency and product yield. Simultaneously, the lead-cutting process in the semi-cured state can rely on the buffering effect of the molding compound to isolate mechanical stress, avoiding defects such as cracking and poor soldering at the welding points, ensuring the stability of the packaging structure and the reliability of electrical connections. Overall, it improves the quality and durability of semiconductor device packaging, better adapting to the needs of large-scale, automated industrial production, and possesses outstanding practical value and industry promotion significance. Attached Figure Description

[0014] Figure 1This is a schematic diagram of the lead frame structure for traditional processes; Figure 2 This is a schematic diagram of the welding of the lead frame and the substrate using traditional methods. Figure 3 This is a schematic diagram of the lead frame structure in one embodiment of this application; Figure 4 This is a schematic diagram of the welding between the lead frame and the substrate in one embodiment of this application; Figure 5 for Figure 4 Enlarged view of point A in the middle; Figure 6 This is a schematic diagram of the structure of a semiconductor chip semi-finished product after rib cutting in one embodiment of this application.

[0015] In the attached diagram: 100 - lead frame; 110 - functional pin; 120 - non-functional pin; 200 - substrate; 210 - solder mask layer; 220 - solder pad; 230 - molding compound. Detailed Implementation

[0016] The present application will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Furthermore, it should be understood that after reading the contents of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope defined by the appended claims.

[0017] In traditional semiconductor manufacturing processes, during the manufacturing of the lead frame 100, the pins need to be pre-processed according to the specific application to distinguish between functional pins 110 and non-functional pins 120 (as shown in the schematic diagram of the traditional lead frame 100 structure). Figure 1 As shown, functional pin 110 is used for electrical connection and signal transmission of the chip, while non-functional pin 120 is only for frame layout and does not need to participate in electrical connection. Non-functional pins 120 need to be shortened to avoid touching the substrate 200; the soldering of the lead frame 100 to the substrate 200 is as follows... Figure 2 As shown, different application schemes require different pin definitions and frame structures. Not only is mold development costly and time-consuming, but unsoldered non-functional pins 120 also need to be manually or mechanically removed in subsequent processes. The process is cumbersome and can easily damage the product. At the same time, the process of separating lead cutting and molding can easily cause problems such as cracking of pads 220, poor soldering, or pin deformation.

[0018] refer to Figures 3-6 This application provides a method for manufacturing a semiconductor chip, comprising the following steps: Semiconductor chip semi-finished product A is obtained. Semiconductor chip semi-finished product A includes a substrate 200 and a chip functional layer disposed on one side of the substrate 200. Pads 220 are disposed at preset pin soldering positions on the edge of the substrate 200, so that the pads 220 and the chip functional layer are electrically connected to obtain semiconductor chip semi-finished product B. A green solder mask 210 is formed on the semiconductor chip semi-finished product B, such that the green solder mask 210 covers the chip functional layer and avoids the pads 220, to obtain the semiconductor chip semi-finished product C; Obtain lead frame 100 (e.g.) Figure 3 As shown), solder paste is applied to the pad 220, the leads on the lead frame 100 are attached to the pad 220, and then reflow soldering is performed to obtain a semiconductor chip semi-finished product D (as shown). Figure 4 (as shown) A molding compound 230 is injected into the semiconductor chip semi-finished product D. The molding compound 230 covers the chip functional layer, the pads 220, and the connection between the pins and the pads 220. The free ends of the pins extend outward from the molding compound 230. Then, a first heat treatment is performed until the molding compound 230 reaches a semi-cured state to obtain the semiconductor chip semi-finished product E. The semiconductor chip semi-finished product E is subjected to lead trimming (after lead trimming) Figure 6 (as shown), and then a second heat treatment is performed until the molding compound 230 reaches a fully cured state.

[0019] This application provides a semiconductor chip manufacturing method that achieves semiconductor chip packaging through an integrated lead-cutting and molding process. This method uses a semi-finished product comprising a substrate 200 and a chip functional layer (in some specific implementations, the chip functional layer can be a wiring layer; the chip functional layer can also include a wiring layer and components disposed on the wiring layer) as the processing basis. First, pads 220 are set at predetermined positions on the edge of the substrate 200, establishing a stable electrical connection between the pads 220 and the chip functional layer (this can be achieved by connecting the pads 220 and the chip functional layer through conductive lines laid on the substrate 200, or by achieving electrical bonding between the two through metal bonding wires), providing a reliable path for subsequent pin soldering and signal transmission. When forming a solder mask 210 on the surface of the chip functional layer (the solder mask 210 can be formed by screen printing, spraying, or photolithography to coat the solder mask material, followed by drying and curing), the solder mask 210 completely covers the chip functional layer and avoids the area of ​​the pads 220. Figure 3 As shown, the pins on the lead frame 100 used in this application do not need to be pre-processed to distinguish between functional pins 110 and non-functional pins 120 during the manufacturing stage; they are simply arranged according to uniform safety requirements (electrical safety specifications). Figures 4-5As shown, when the lead frame 100 is bonded to the substrate 200, the position of the functional pin 110 on the substrate 200 is the pad 220, and the position of the non-functional pin 120 is covered by the solder mask 210. This achieves solder isolation and electrical isolation at the corresponding positions of the non-functional pin 120, enabling pin arrangement to be completed according to unified safety regulations and greatly improving the universal adaptability of the lead frame. After the lead frame 100 and the substrate 200 are precisely aligned, the functional pin 110 on the lead frame 100 is firmly bonded to the pad 220 by solder paste bonding and reflow soldering. At this time, the non-functional pin 120 is blocked by the solder mask 210 and cannot form a solder connection with the substrate 200, only maintaining physical contact with the substrate 200. There is no need to remove the non-functional pin 120 in advance. The semiconductor chip semi-finished product after reflow soldering is then placed in a molding die, and molding compound 230 is poured in. This ensures the molding compound 230 completely covers the chip's functional layer, pads 220, and the connection points between the pins and pads 220, while allowing the free ends of the pins to extend beyond the molding compound 230 to meet subsequent external connection requirements. A first heat treatment adjusts the molding compound 230 to a semi-cured state, ensuring it retains basic structural strength while maintaining elastic cushioning properties, providing protection and support for subsequent lead cutting operations. While the molding compound 230 is in a semi-cured state, lead cutting equipment is used to cut the semi-finished product. The semi-cured molding compound 230 effectively absorbs the stress generated during lead cutting, preventing stress transmission to the soldering area and causing cracking or poor soldering of the pads 220. Non-functional pins 120 not soldered to the substrate 200 will automatically detach after losing their binding force (e.g., ...). Figure 6 As shown in the diagram, no manual or mechanical removal is required, simplifying the processing steps and reducing the risk of product damage. After lead cutting, a second heat treatment completely cures the molding compound 230, forming a stable and well-insulated molding compound. This completes the integrated lead cutting and molding process, improving the production efficiency and product reliability of semiconductor chip packaging.

[0020] In some specific implementations, the lead frame 100 uses copper alloy as the processing material. Copper alloy has excellent electrical conductivity, thermal conductivity, and mechanical strength, which can stably support the pin structure of the semiconductor chip while ensuring efficient transmission of electrical signals between the pins. During the processing of the lead frame 100, the pin array is uniformly arranged in strict accordance with the electrical clearances and creepage distances specified in electrical safety regulations. There is no need to pre-distinguish between functional pins 110 and non-functional pins 120 for different application scenarios. The overall frame is formed and processed with a uniform safety spacing standard. This allows the lead frame 100 of the same specification to adapt to the packaging requirements of semiconductor chips with different pin definitions, effectively improving the universal adaptability of the lead frame 100, reducing the number of frame molds developed for different chip models, and reducing the overall processing cost and production cycle.

[0021] In some specific implementations, the substrate 200 is a metal substrate. The metal substrate has excellent structural stability and heat dissipation performance, which can provide a solid support foundation for the chip functional layer, pads 220 and lead frame 100, avoid problems such as substrate deformation and warping during packaging and processing, and ensure the relative positional accuracy of each component. At the same time, it can quickly dissipate the heat generated during chip operation, adapt to the heat dissipation requirements of high heat load semiconductor products such as power devices and intelligent power modules, and extend the stable operation time of the product.

[0022] In some specific implementations, the solder paste is either solder paste or silver paste. After melting and cooling, the solder paste forms a solder joint with stable conductivity and a strong connection structure. This ensures a reliable and smooth electrical connection between the functional pin 110 and the substrate 200 pad 220, and also provides sufficient solder strength to withstand the mechanical stress generated by subsequent lead cutting processes. This effectively avoids defects such as cold solder joints, desoldering, and insufficient solder strength, thus ensuring the electrical connection stability and overall structural reliability of the semiconductor chip after packaging.

[0023] In some specific implementations, the thickness of the solder mask 210 is 10μm-30μm. This thickness range ensures the soldering and electrical isolation effect of the solder mask 210 on the non-functional pin 120 area, while avoiding excessive thickness from affecting the overall flatness of the substrate 200. This prevents lead frame 100 misalignment due to insufficient flatness of the substrate 200, ensuring the accuracy of subsequent pin soldering and packaging processes. In this specific embodiment of the application, the thickness of the solder mask 210 is 20μm (in some other specific implementations, the thickness of the solder mask 210 can be any value within the range of 10μm-30μm, such as 10μm, 15μm, or 30μm).

[0024] In some specific implementations, the temperature of the first heat treatment is 120℃-130℃, and the time is 20min-40min. This first heat treatment allows the molding compound 230 to gradually complete the initial cross-linking reaction. This temperature and time range prevents the molding compound 230 from under-curing due to excessively low temperature or short time, maintaining its soft and easily deformable state. It also prevents the molding compound 230 from prematurely hardening and losing its buffering capacity due to excessively high temperature or long time. This allows the molding compound 230 to simultaneously possess the basic strength of a supporting structure and the elastic buffering performance for stress absorption in a semi-cured state, providing stable protective support conditions for subsequent reinforcement cutting processes. In this specific embodiment of the application, the temperature of the first heating treatment is 125°C (in some other specific embodiments, the temperature of the first heating treatment can be any value in the range of 120°C-130°C, such as 120°C, 122°C, 124°C, 128°C, 130°C), and the time of the first heating treatment is 30 min (in some other specific embodiments, the time of the first heating treatment can be any value in the range of 20 min-40 min, such as 20 min, 25 min, 40 min).

[0025] In some specific implementations, the molding compound 230 includes epoxy resin; when the first heat treatment is performed until the molding compound 230 reaches a semi-cured state, the gel rate of the molding compound 230 is 75%-85%. Epoxy resin possesses excellent high-temperature resistance, electrical insulation, and structural adhesion, enabling it to tightly encapsulate the chip functional layer, pads 220, and lead soldering areas, effectively isolating external moisture, dust, and mechanical stress, meeting the protection requirements for long-term reliable use of semiconductor devices. When the molding compound 230 reaches a semi-cured state during the first heat treatment, the gel rate is controlled within the range of 75%-85%. At this point, the degree of cross-linking and elastic buffering performance of the molding compound 230 achieves the optimal balance, providing sufficient structural support for the leads and soldering areas while fully absorbing the mechanical stress generated during lead cutting, minimizing stress transmission to the pads 220 and preventing defects such as cracking and poor soldering. In this specific embodiment of the application, the gel rate of the molding compound 230 is 80% (in some other specific embodiments, the gel rate of the molding compound 230 can be any value in the range of 75%-85%, such as 75%, 77%, 82%, 85%). The gel rate test can be performed in accordance with ASTM D2765-16.

[0026] In some specific implementations, the temperature of the second heat treatment is 140℃-160℃, and the time is 40min-80min. The second heat treatment is used to completely cure the molding compound 230, enabling it to undergo a sufficient cross-linking and curing reaction. This process condition ensures that the internal structure of the molding compound 230 is dense and stable, comprehensively improving the mechanical strength, insulation performance, and moisture resistance and aging resistance of the molding compound, avoiding problems such as softening, cracking, and insulation failure caused by insufficient curing. Simultaneously, this temperature and time range is adapted to the heat resistance characteristics of semiconductor devices, preventing thermal damage to the chip's functional layers and pin soldering areas, thus ensuring the overall reliability of the packaged product. In this specific embodiment of the application, the temperature of the second heating treatment is 150°C (in some other specific embodiments, the temperature of the second heating treatment can be any value in the range of 140°C-160°C, such as 140°C, 142°C, 144°C, 158°C, 160°C), and the time of the second heating treatment is 60 min (in some other specific embodiments, the time of the second heating treatment can be any value in the range of 40 min-80 min, such as 40 min, 45 min, 50 min, 70 min, 80 min).

[0027] In some specific implementations, the shearing force applied during the lead-cutting process does not exceed 50N. The lead-cutting process can be performed at a uniform speed. Excessive shearing force can directly lead to pin deformation, cracking of the pad 220 under stress, and poor solder joint detachment. A uniform and moderate shearing force, combined with the buffering effect of the semi-cured molding compound 230, smoothly cuts off the connecting rods of the lead frame 100 while protecting the functional pins 110 and the soldered structure from damage. Unsoldered non-functional pins 120, freed from their binding after the connecting rods are cut, can automatically detach without additional manual or mechanical removal, simplifying the process and effectively improving product yield and production stability. In this specific embodiment of the application, the shearing force applied during the lead-cutting process is 40N (in some other specific implementations, the shearing force applied during the lead-cutting process is any value within the range of no more than 50N, such as 10N, 20N, 30N, or 50N).

[0028] In some specific implementations, the reflow soldering process is performed at a temperature of 255℃-265℃ for 8s-12s. Too low a temperature or too short a time during reflow soldering will result in insufficient solder paste melting, preventing a strong solder joint between the functional pin 110 and the pad 220, leading to cold solder joints or false solder joints. Too high a temperature or too long a time will cause oxidation of the pad 220, thermal damage to the solder mask layer 210, and may even affect the structural stability of the chip's functional layer and the substrate 200. The above parameter range ensures a strong solder joint between the functional pin 110 and the pad 220, reliable conductivity, and avoids the risk of product damage caused by prolonged high-temperature heating. In this specific embodiment of the application, the reflow soldering temperature is 260°C (in some other specific embodiments, the reflow soldering temperature can be any value in the range of 255°C-265°C, such as 255°C, 257°C, 262°C, 265°C), and the reflow soldering time is 10s (in some other specific embodiments, the reflow soldering time can be any value in the range of 8s-12s, such as 8s, 9s, 12s).

[0029] In some specific implementations, the pads 220 are tin-plated before the formation of the green solder mask layer 210. The tin plating layer improves the wettability and solderability of the pads 220, reducing the difficulty of lead soldering. During reflow soldering, the tin-plated pads 220 can quickly and fully fuse with the solder paste, forming a tightly bonded and electrically stable solder joint between the functional pins 110 of the lead frame 100 and the pads 220, reducing defects such as cold solder joints, missing solder joints, and insufficient solder strength. Simultaneously, the tin plating layer has good oxidation resistance, preventing oxidation of the pads 220 during storage and processing, continuously ensuring soldering quality, and improving the electrical connection stability and product lifespan of the semiconductor chip package.

[0030] In some specific implementations, the product that has undergone the second heat treatment until the molding compound 230 reaches a fully cured state is subjected to overflow removal, cleaning, and electroplating. Subsequently, appearance inspection and electrical testing are performed. After passing the inspection, the final semiconductor chip product is obtained.

[0031] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and additions without departing from the method of this application, and these improvements and additions should also be considered within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor chip, characterized in that, Includes the following steps: Semiconductor chip semi-finished product A is obtained. Semiconductor chip semi-finished product A includes a substrate and a chip functional layer disposed on one side of the substrate. Pads are disposed at preset pin soldering positions on the edge of the substrate so that the pads are electrically connected to the chip functional layer to obtain semiconductor chip semi-finished product B. A green solder mask layer is formed on the semiconductor chip semi-finished product B, such that the green solder mask layer covers the chip functional layer and avoids the pads, to obtain the semiconductor chip semi-finished product C; Obtain the lead frame, apply solder paste to the pads, attach the pins on the lead frame to the pads, and then perform reflow soldering to obtain a semiconductor chip semi-finished product D. A molding compound is injected into the semiconductor chip semi-finished product D. The molding compound covers the chip functional layer, the pads, and the connection between the pins and the pads. The free ends of the pins extend out of the molding compound. Then, a first heat treatment is performed until the molding compound reaches a semi-cured state to obtain the semiconductor chip semi-finished product E. The semiconductor chip semi-finished product E is subjected to a rib-cutting process, and then a second heat treatment is performed until the molding compound reaches a fully cured state.

2. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The thickness of the green oil layer is 10μm-30μm.

3. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The temperature of the first heat treatment is 120℃-130℃, and the time is 20min-40min.

4. The method for manufacturing a semiconductor chip according to claim 3, characterized in that, The molding compound includes epoxy resin; when the molding compound undergoes the first heat treatment until it reaches a semi-cured state, the gel rate of the molding compound is 75%-85%.

5. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The second heat treatment is performed at a temperature of 140℃-160℃ for a time of 40min-80min.

6. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The shear force applied during the rebar cutting process shall not exceed 50N.

7. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The reflow soldering process is performed at a temperature of 255℃-265℃ for 8s-12s.

8. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, Before the green solder mask is formed, the pads are tin-plated.

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