Embedded component package structure and method of manufacturing the same

Abstract

An embedded component package structure and a method for manufacturing the same. The embedded component package structure includes a dielectric structure, a semiconductor chip and a patterned conductive layer. The semiconductor chip is embedded in the dielectric structure, the dielectric structure covers the semiconductor chip and has a first thickness, the semiconductor chip has a second thickness, the first thickness is greater than the second thickness, and the ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extends into a first opening of the dielectric structure, the first opening exposes an electrical contact pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical contact pad of the semiconductor chip.

Description

[0001] Information related to divisional application This application is a divisional application of the invention patent application filed on November 12, 2019, with application number "201911100304.4" and invention title "Embedded Component Packaging Structure and Manufacturing Method Thereof". Technical Field

[0002] This invention relates to a component packaging structure and a method for manufacturing the same, and more particularly to an embedded component packaging structure and a method for manufacturing the same. Background Technology

[0003] In system-in-package (SiP) architectures, the technology of embedding semiconductor chips within the package substrate (SESUB) has become a key research focus for manufacturers in this field in recent years due to its advantages of reducing noise interference to the package substrate and reducing product size. To improve production yield, the embedded components must be fixed within the dielectric structure to facilitate electrical connection between the subsequently fabricated patterned conductive layer and the embedded components.

[0004] However, the dielectric structure currently covering embedded components is a resin sheet, which is only 80 micrometers thick at most, thus making it impossible to provide a thicker dielectric structure. To ensure that the chip is completely covered by resin, the current practice is to thin the chip, but when the chip is thinned, warpage occurs, causing difficulties in subsequent processes. Summary of the Invention

[0005] This invention relates to an embedded component packaging structure and its manufacturing method, which replaces the traditional resin sheet with an encapsulating material to increase the thickness of the dielectric structure and / or without reducing the thickness of the semiconductor chip, thereby preventing chip warpage. Furthermore, in the subsequent aperture-opening process, the encapsulating material is dry-blasted to expose the electrical pads of the semiconductor chip.

[0006] According to one aspect of the present invention, an embedded component packaging structure is provided, comprising a dielectric structure, a semiconductor chip, and a patterned conductive layer. The semiconductor chip is embedded in the dielectric structure, the dielectric structure covering the semiconductor chip and having a first thickness, the semiconductor chip having a second thickness, the first thickness being greater than the second thickness, and the ratio of the first thickness to the second thickness being between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extends into a first opening in the dielectric structure, the first opening exposing an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.

[0007] According to one aspect of the present invention, an embedded component packaging structure is provided, comprising a dielectric structure, a semiconductor chip, and a patterned conductive layer. The dielectric structure is a thermosetting encapsulating material. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure covers the semiconductor chip. The patterned conductive layer covers an upper surface of the dielectric structure and extends into a first opening in the dielectric structure, the first opening exposing an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip, wherein the first opening is formed by sandblasting.

[0008] According to one aspect of the present invention, a method for manufacturing an embedded component package structure is provided, comprising the following steps: providing a semiconductor chip on a carrier; providing a dielectric structure on the carrier to encapsulate the semiconductor chip, the dielectric structure being thermoformed using a mold; dry blasting the dielectric structure to form a first opening exposing an electrical pad of the semiconductor chip; forming a patterned conductive layer on an upper surface of the dielectric structure and extending into the first opening, the patterned conductive layer being electrically connected to the electrical pad of the semiconductor chip. Attached Figure Description

[0009] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0010] Figures 1A to 1D A schematic diagram illustrating a method for manufacturing an embedded component packaging structure according to an embodiment of the present invention.

[0011] Figures 2 to 6 Schematic diagrams illustrating embedded component packaging structures according to different embodiments of the present invention.

[0012] Figures 7A to 7I A schematic diagram illustrating a method for manufacturing an embedded component packaging structure according to an embodiment of the present invention.

[0013] Figures 8A to 8L A schematic diagram illustrating a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention is shown.

[0014] Figures 9A to 9L A schematic diagram illustrating a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention is shown.

[0015] Figures 10A to 10L A schematic diagram illustrating a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention is shown.

[0016] Explanation of component labels in the diagram:

[0017] 100: Embedded component packaging structure

[0018] 102: Carrier

[0019] 104: Release membrane

[0020] 106: Patterned sandblasting resistant photoresist

[0021] 110: Dielectric structure

[0022] 111: First opening

[0023] 112: Upper surface

[0024] 113: Second opening

[0025] 114: Lower surface

[0026] 115: Blind Hole

[0027] 116, 118: Welding cover layer

[0028] 120: Semiconductor chip

[0029] 121: Electrical pad

[0030] 122: Back

[0031] 124: Heatsink

[0032] 125: Chip bonding film

[0033] 126: Circuit Layer

[0034] 130: Patterned conductive layer

[0035] 131: Seed layer

[0036] 132: Electroplated copper layer

[0037] 133: Joint pad

[0038] 134: Conductive post

[0039] 140: First line structure

[0040] 141: Upper dielectric layer

[0041] 142: Upper conductive layer

[0042] 143: Opening

[0043] 144: Seed Layer

[0044] 145: Electroplated copper layer

[0045] 146: Joint pad

[0046] 150: Second line structure

[0047] 151: Lower Dielectric Layer

[0048] 152: Lower conductive layer

[0049] 153: Welding ball

[0050] 154: Joint Pad

[0051] 160: Passive components

[0052] 170: Application-Specific Integrated Circuit Chips

[0053] 172: Sealing

[0054] 173: Side View

[0055] H1: First thickness

[0056] H2, H2': Second thickness Detailed Implementation

[0057] The following embodiments are provided for detailed description. These embodiments are merely illustrative and are not intended to limit the scope of protection of this invention. The same / similar symbols are used to denote the same / similar elements in the description. Directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0058] According to one embodiment of the present invention, an embedded component packaging structure and its manufacturing method are provided. Please refer to... Figures 1A to 1D The diagram illustrates a method for manufacturing an embedded component package structure 100 according to an embodiment of the present invention. First, a dielectric structure 110 is formed to encapsulate a semiconductor chip 120. Next, the dielectric structure 110 is dry-blasted to form a first opening 111 exposing the electrical pads 121 of the semiconductor chip 120. Then, a patterned conductive layer 130 is formed on an upper surface 112 of the dielectric structure 110 and extends into the first opening 111, and the patterned conductive layer 130 is electrically connected to the electrical pads 121 of the semiconductor chip 120. Figure 1D Furthermore, this manufacturing method can grind the back surface 122 of the semiconductor chip 120 to reduce the thickness of the semiconductor chip 120.

[0059] Please refer to Figure 1A The dielectric structure 110 has a first thickness H1, and the semiconductor chip 120 has a second thickness H2. The first thickness H1 is greater than the second thickness H2, and the ratio of the first thickness H1 to the second thickness H2 is between 1.1 and 28.4. In one embodiment, the first thickness H1 is, for example, between 110 and 1420 micrometers, and the second thickness H2 is, for example, between 100 and 50 micrometers or higher. The difference between the first thickness H1 and the second thickness H2 is, for example, between 10 and 1370 micrometers.

[0060] In this embodiment, the dielectric structure 110 uses an epoxy molding compound (EMC) instead of a traditional resin sheet. Both traditional resin sheets and encapsulants are primarily composed of epoxy resin and fillers, but the composition and weight percentage of the fillers differ, resulting in different properties. Traditional resin sheets have a filler weight percentage of only 60-85 wt%, while the encapsulant has a filler weight percentage greater than 85 wt% (e.g., 87 wt%). Please refer to Tables 1 and 2 for details on the encapsulant's properties.

[0061] In one embodiment, since the thickness of the encapsulating material (between 110 and 1420 micrometers) is much greater than the thickness limit of the resin sheet (less than 80 micrometers), the thickness and electrical insulation of the dielectric structure 110 can be improved. Furthermore, the encapsulating material is, for example, a thermosetting epoxy resin, which is placed in a mold and thermoset to encapsulate the semiconductor chip 120. It is not limited to a sheet form, but can also be in a liquid or molten state. After the encapsulating material is demolded, a post-mold cure process can be performed on the encapsulating material in a high-temperature environment to ensure complete curing. The cured encapsulating material can prevent the semiconductor chip 120 from warping. Compared to the conventional method of fixing the semiconductor chip to a carrier plate with a resin sheet and then encapsulating the semiconductor chip with another resin sheet, this embodiment only requires an encapsulation process, and the thickness of the dielectric structure 110 can be significantly increased according to the overall thickness of the packaging structure 100, overcoming the thickness limitation problem of traditional resin sheets.

[0062] Please refer to Figure 1B The dielectric structure 110 is dry-blasted to form a plurality of first openings 111, each first opening 111 exposing a corresponding electrical pad 121. The greater the thickness of the dielectric structure 110, the more blasting passes are required to form the predetermined opening depth. Furthermore, the size of the electrical pad 121 is preferably less than 60 micrometers, so the aperture of the first openings 111 formed by the blasting process is preferably less than 40 micrometers. Additionally, after dry blasting, the hole walls of the dielectric structure 110 can be finely surface-treated to avoid the formation of a granular, rough surface. In one embodiment, a small-particle filler (e.g., SiO2) can be selected and added to the dielectric structure 110. The particle size of the filler is, for example, between 5 and 15 micrometers, preferably between 5 and 10 micrometers. This ensures that the filler exposed in the subsequent blasting process will not have excessively large particles, which would affect the adhesion between the seed layer and the encapsulating material in the subsequent electroless plating process.

[0063] Please refer to Figure 1CThe patterned conductive layer 130 includes, for example, an electroless seed layer 131 and an electroplated copper layer 132. The electroplated copper layer 132 may cover the electroless seed layer 131, and the patterned conductive layer 130 is formed by locally etching the electroplated copper layer 132 and the seed layer 131. Please refer to... Figure 1C The lower surface 114 of the dielectric structure 110 can be flush with the back surface 122 of the semiconductor chip 120, and the dielectric structure 110 can expose the back surface 122 of the semiconductor chip 120.

[0064] Please refer to Figure 1D The back surface 122 of the semiconductor chip 120 and part of the dielectric structure 110 are polished to reduce the thickness of the semiconductor chip 120 and the dielectric structure 110. For example, the second thickness H2' of the semiconductor chip 120 is reduced to 2 / 3 or less of the second thickness H2, so that the second thickness H2' of the polished semiconductor chip 120 is between 50 and 100 micrometers.

[0065] Please refer to Figures 2 to 6 The diagrams illustrate the embedded component packaging structures according to different embodiments of the present invention. Figures 2 to 6 Each of the embodiments is based on Figure 1C The embedded component packaging structure 100 is the main architecture, and other secondary structures will be added later according to different requirements. Please refer to... Figure 2 This packaging structure may further include a first circuit structure 140 disposed on the upper surface 112 of the dielectric structure 110, for example, made of a copper clad laminate. The first circuit structure 140 may include a dielectric layer 141, which may be made of, for example, an Ajinomoto build-up film (ABF), pre-impregnated composite fibers, polyimide, or polypropylene. (Related information...) Figure 2 For the fabrication method of the packaging structure, please refer to... Figures 8A to 8L More details to follow later.

[0066] Please refer to Figure 3A and Figure 3B This packaging structure may further include a first circuit structure 140 and a second circuit structure 150, which respectively cover the upper surface 112 and the opposite lower surface 114 of the dielectric structure 110, for example, made of a copper-clad laminate. The first circuit structure 140 and the second circuit structure 150 may each include a dielectric layer 141 and 151, respectively, which are made of, for example, laminated film (ABF), pre-impregnated composite fibers, polyimide, or polypropylene. (Related information...) Figure 3A and Figure 3B For the fabrication method of the packaging structure, please refer to... Figures 9A to 9L and Figures 10A to 10L More details to follow later.

[0067] Please refer to Figure 3A and Figure 3B This encapsulation structure may further include at least one conductive post 134 penetrating the dielectric structure 110. The conductive post 134 is electrically connected to the first circuit structure 140 and the second circuit structure 150. The method of forming the conductive post 134 includes sandblasting, and the conductive post 134 may be formed together with the fabrication process of the first circuit structure and the second circuit structure.

[0068] Please refer to Figures 4A to 4B This package structure may further include two solder mask layers 116 and 118, which respectively cover the upper surface 112 and lower surface 114 of the dielectric structure 110, and the back surface 122 of the semiconductor chip 120 is exposed to the solder mask layer 118. Figure 4B In the package structure, a circuit structure 150 may be further included below the dielectric structure 110, and a solder mask layer 116 below the dielectric structure 110 is used to form a solder mask opening to expose the bonding pad 154 for the solder ball 153 to electrically connect to the bonding pad 154.

[0069] Please refer to Figure 4C , and Figure 4B The packaging structure is similar, but differs in that it may further include a heat sink 124 disposed above the dielectric structure 110 and in thermal contact with the back surface 122 of the semiconductor chip 120. The heat sink 124 is used to absorb waste heat from the semiconductor chip 120 to reduce the temperature of the semiconductor chip 120.

[0070] Please refer to Figure 5A and Figure 5B , and Figure 3A and Figure 3B The packaging structure is similar, but differs in that: this packaging structure may further include two solder mask layers 116 and 118, which respectively cover the top and bottom of the first circuit structure 140 and the second circuit structure 150, and the solder mask layer 118 below the dielectric structure 110 of the packaging structure 100 is used to form a solder mask opening to expose the bonding pad 154 for the solder ball 153 to electrically connect to the bonding pad 154. Furthermore, in Figure 5B In this embodiment, the semiconductor chip 120 may further include a dieattach film 125 and a circuit layer 126 embedded within the dieattach film 125. The circuit layer 126 is pre-formed in the dieattach film 125 and exposed on the surface of the dielectric structure 110. Subsequently, a first circuit structure 140 is formed on the dielectric structure 110 to electrically connect the circuit layer 126 to the first circuit structure 140 above it.

[0071] Please refer to Figure 6 , and Figure 5BThe packaging structure is similar to that of the first circuit structure 140, but differs in that it may further include a passive component 160 and an application-specific integrated circuit (ASIC) chip 170, disposed above the first circuit structure 140 and electrically connected to the circuit layer 126 in the first circuit structure 140 or the chip adhesive film 125. In one embodiment, the passive component 160 may be, for example, a capacitor, inductor, or resistor, and the ASIC chip 170 may work in conjunction with the semiconductor chip 120 or operate independently to improve the overall performance of the chip. Furthermore, this packaging structure further includes an encapsulant 172 that covers the passive component 160 and the ASIC chip 170, and the side 173 of the encapsulant 172 may be flush with the side of the packaging structure 100. Referring to Table 1, the main components of the encapsulant 172 are epoxy resin and fillers, with the filler having a weight percentage of 87 wt% or 89 wt%, an average size of 14 or 17 micrometers, and a screen size of 55 or 75 micrometers. Please refer to Table 2. The main components of dielectric structure 110 are epoxy resin and filler. The difference is that the filler has a weight percentage of 89 wt%, an average size of 5 micrometers, and a screen size of 25 micrometers.

[0072] Please refer to Figures 7A to 7I The diagram illustrates a method for manufacturing an embedded component packaging structure according to an embodiment of the present invention. First, in Figure 7A and Figure 7B In this process, a release film 104 is formed on a carrier 102. A semiconductor chip 120 is disposed on the release film 104, so that the semiconductor chip 120 is temporarily disposed on the carrier 102. The carrier 102 is, for example, a rigid substrate, such as a metal plate or a plastic plate. The release film 104 is adhesive and adheres to the semiconductor chip 120 to position the semiconductor chip 120. Figure 7C In this process, a dielectric structure 110 is provided on a carrier 102 to encapsulate a semiconductor chip 120. The dielectric structure 110 is thermosetting using a mold. That is, the dielectric structure 110 is a thermosetting encapsulating material, different in material and thickness from traditional resin sheets. Furthermore, compared to traditional methods, it is not necessary to fix the semiconductor chip 120 to the carrier plate with a resin sheet; only a removable release film 104 is needed, simplifying the process and saving costs. Figure 7D In the middle, a patterned, sandblast-resistant photoresist 106 is formed on the dielectric structure 110. Figure 7E In the process, a portion of the upper surface 112 of the dielectric structure 110 is dry-blasted to form a first opening 111 recessed in the dielectric structure 110, and the first opening 111 exposes the electrical pads 121 of the semiconductor chip 120. Next, in... Figure 7F and Figure 7GIn this process, a patterned conductive layer 130 is formed on the upper surface 112 of the dielectric structure 110 and extends into the first opening 111. The patterned conductive layer 130 is electrically connected to the electrical pads 121 of the semiconductor chip 120. The patterned conductive layer 130 includes, for example, an electroless seed layer 131 and an electroplated copper layer 132. The electroplated copper layer 132 may cover the electroless seed layer 131, and the patterned conductive layer 130 is formed by locally etching the electroplated copper layer 132 and the seed layer 131. Figure 7H In the process, the carrier 102 and the release membrane 104 are removed. Figure 7I In the process, two bonding layers 116 and 118 are formed on the upper surface 112 and lower surface 114 of the dielectric structure 110, which can expose the back side 122 of the semiconductor chip 120 and the bonding pad 133 of the patterned conductive layer 130.

[0073] Please refer to Figures 8A to 8L The diagram illustrates a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention. Figures 8A to 8G The steps have been mentioned in the above embodiments and will not be repeated here. Figure 8H In this process, a dielectric layer 141 is formed on the dielectric structure 110, and an upper conductive layer 142 (e.g., copper foil) is laminated onto the dielectric layer 141, followed by heat curing of the dielectric layer 141. The dielectric layer 141 is made, for example, of a laminated film (ABF, Ajinomoto build-up film), prepreg composite fibers, polyimide, or polypropylene. Figure 8I In the middle, multiple openings 143 are formed in the dielectric layer 141, and then, Figure 8J In this process, an electroless seed layer 144 is formed on the upper surface of the upper conductive layer 142 and in the opening 143, and then an electroplated copper layer 145 is formed on the seed layer 144, so that the upper conductive layer 142 and the patterned conductive layer 130 are electrically connected. Figure 8K In the process, a patterned circuit is formed by etching a conductive layer 142, a seed layer 144, and electroplating a copper layer 145, thus completing the first circuit structure 140. Figure 8L In the process, two bonding layers 116 and 118 are formed above and below the dielectric structure 110 and the first circuit structure 140, respectively, and the back surface 122 of the semiconductor chip 120 and the bonding pad 146 of the first circuit structure 140 are exposed.

[0074] Please refer to Figures 9A to 9L The diagram illustrates a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention. Figures 9A to 9G The steps have been mentioned in the above embodiments and will not be repeated here. Figure 9HIn this process, an upper dielectric layer 141 and a lower dielectric layer 151 are formed above and below the dielectric structure 110, respectively, and an upper conductive layer 142 and a lower conductive layer 152 (e.g., copper foil) are laminated onto the upper dielectric layer 141 and the lower dielectric layer 151, followed by heating and curing of the upper dielectric layer 141 and the lower dielectric layer 151. Figure 9I In this process, at least one second opening 113 is formed, penetrating the dielectric structure 110, the upper dielectric layer 141, and the lower dielectric layer 151. The method for forming the second opening 113 includes sandblasting. Figure 9J In this process, an electroless seed layer 144 is formed on the upper conductive layer 142 and the lower conductive layer 152, and in the second opening 113. Then, an electroplated copper layer 145 is formed on the seed layer 144, so that the upper conductive layer 142 and the lower conductive layer 152 are electrically connected via conductive posts 134 in the second opening 113. Figure 9K In the process, a patterned circuit is formed by etching an upper conductive layer 142, a seed layer 144, an electroplated copper layer 145, and a lower conductive layer 152, thus completing the first circuit structure 140 and the second circuit structure 150. Figure 9L In the process, two bonding layers 116 and 118 are formed above and below the first circuit structure 140 and the second circuit structure 150, respectively, and the bonding pads 146 of the first circuit structure 140 and the bonding pads 154 of the second circuit structure 150 are exposed.

[0075] Please refer to Figures 10A to 10L The diagram illustrates a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention. Figures 10A to 10G Steps and Figures 9A to 9G The steps are similar, and the similarities will not be repeated here. The difference lies in... Figure 10E Furthermore, it includes at least one second opening 113 forming a through-dielectric structure 110. Therefore, in subsequent... Figure 10I In this process, only two blind vias 115 are formed that penetrate the first dielectric layer 141 and the second dielectric layer 151. The above-mentioned methods for forming the second opening 113 and the blind via 115 include sandblasting. Figures 10J to 10L Steps and Figures 9J to 9L The steps are similar, used to form the first circuit structure 140 and the second circuit structure 150 above and below the dielectric structure 110, and will not be described in detail here.

[0076] According to the above embodiments of the present invention, since the thickness of a conventional resin sheet is at most only 80 micrometers, it is impossible to provide a thicker dielectric structure 110 to cover the semiconductor chip 120. In this embodiment, an encapsulating material is used instead of a conventional resin sheet, so that the thickness of the dielectric structure 110 is between 110 and 1420 micrometers. As long as the thickness of the semiconductor chip 120 is less than the thickness of the dielectric structure 110, it is not necessary to thin the chip, thus solving the problem of warpage caused by chip thinning. At the same time, in fifth-generation mobile communication technology (5G), the thickness of the dielectric structure 110 is, for example, 750 micrometers or more, and the thickness ratio of the dielectric structure 110 to the semiconductor chip 120 is greater than 2 or 3, which can effectively reduce inductive coupling interference and improve the electrical insulation of the packaging structure 100 to meet market demands.

[0077] Please refer to Table 1 for this embodiment. Figure 6 For example, the encapsulant 172 used in quad flat package (QFN) structures has good thermal hardness, low water absorption, low viscosity, low thermal conductivity, and high flexural strength, making it suitable for use in component packaging structures. The material properties and parameters of encapsulant 172 are as follows:

[0078] Table 1

[0079]

[0080]

[0081] Please refer to Table 2. Taking the encapsulating material used in a flip chip ball grid array (BGA) structure as an example, the dielectric structure 110 in this embodiment has good thermal hardness, low water absorption, low viscosity, and low thermal conductivity. Furthermore, it has a higher filler content than traditional resin sheets, thus exhibiting higher flexural strength, making it suitable for use in embedded component packaging structures. The characteristics and parameters of the encapsulating material for the dielectric structure 110 are as follows:

[0082] Table 2

[0083]

[0084] In one embodiment, a filler with small particle size (e.g., Al2O3 / SiO2) can be selected and added to the dielectric structure 110. The particle size of the filler is, for example, between 5 and 15 micrometers, preferably between 5 and 10 micrometers. The weight percentage of the filler is, for example, 89%. The higher the content, the higher the coefficient of thermal expansion, so that the coefficient of thermal expansion of the dielectric structure 110 matches that of the semiconductor chip 120. In addition, the smaller the particle size of the filler, the less likely the surface roughness of the hole wall will be too large during the dry blasting of the encapsulating material in the subsequent hole-opening process, which would affect the adhesion between the seed layer and the encapsulating material in the subsequent electroless plating.

[0085] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A packaging structure, comprising: A first dielectric structure, wherein the first dielectric structure is a first encapsulating material, the first encapsulating material includes a first epoxy resin and a first filler, and the size of the first filler is between 5 and 15 micrometers; A semiconductor chip is embedded in the first dielectric structure, and the first dielectric structure covers the semiconductor chip. as well as A patterned conductive layer covers the upper surface of the first dielectric structure and extends into the first opening of the first dielectric structure, and the patterned conductive layer is electrically connected to the electrical pads of the semiconductor chip.

2. The packaging structure of claim 1, wherein the weight percentage of the first filler is greater than 87%, and the weight percentage of the first filler is used to match the coefficient of thermal expansion of the semiconductor chip.

3. The packaging structure of claim 2, wherein the first dielectric structure has a first thickness, the semiconductor chip has a second thickness, and the ratio of the first thickness to the second thickness is between 1.1 and 28.

4.

4. The packaging structure as described in claim 1, further comprising: A conductive post is disposed within a second opening defined by the first dielectric structure, wherein the depth of the first opening is less than the depth of the second opening.

5. The packaging structure of claim 1, wherein the first dielectric structure covers the upper surface of the semiconductor chip.

6. The packaging structure as described in claim 1, further comprising: The first circuit structure is disposed above the patterned conductive layer; and The chip is positioned above the first circuit structure. The chip is electrically connected to the patterned conductive layer through the first circuit structure.

7. The packaging structure as described in claim 6, further comprising: A second dielectric structure covers the chip. The second dielectric structure is a second encapsulating material, which includes a second epoxy resin and a second filler. The average size of the second filler is different from the average size of the first filler.

8. The packaging structure as described in claim 6, further comprising: The second circuit structure is located below the semiconductor chip; and Solder balls are placed below the second circuit structure.

9. The packaging structure as described in claim 8, further comprising: A conductive post penetrates the first dielectric structure and is electrically connected between the first circuit structure and the second circuit structure.

10. The packaging structure of claim 6, wherein the chip is electrically connected to the first circuit structure via solder balls.

11. A packaging structure, comprising: A first dielectric structure, wherein the first dielectric structure is a first encapsulating material, the first encapsulating material includes a first epoxy resin and a first filler, and the size of the first filler is between 5 and 15 micrometers; Semiconductor chip, wherein the first dielectric structure covers the semiconductor chip; as well as The circuit layer is placed above the semiconductor chip; as well as A first electronic component and a second electronic component are disposed above the circuit layer, wherein the first electronic component is electrically connected to the circuit layer and the second electronic component is electrically connected to the circuit layer.

12. The packaging structure of claim 11, wherein the circuit layer is laterally surrounded by the first dielectric structure.

13. The packaging structure of claim 11, wherein the weight percentage of the first filler is greater than 87%, and the weight percentage of the first filler is used to match the coefficient of thermal expansion of the semiconductor chip.

14. The packaging structure as described in claim 11, further comprising: A conductive post that penetrates the first dielectric structure.

15. The packaging structure of claim 14, further comprising: The first circuit structure is placed on the circuit layer. The first electronic component is electrically connected to the circuit layer through the first circuit structure.

16. The packaging structure of claim 15, further comprising: A patterned conductive layer, wherein the semiconductor chip has a first surface and a second surface opposite to the first surface, the circuit layer is disposed above the first surface, and the patterned conductive layer is disposed below the second surface.

17. The packaging structure of claim 16, further comprising: A second circuit structure is disposed below the patterned conductive layer and electrically connected to the patterned conductive layer.

18. The packaging structure of claim 17, further comprising: Solder balls, which are disposed beneath the patterned conductive layer and electrically connected to the patterned conductive layer.

19. The packaging structure of claim 16, wherein the first circuit structure is electrically connected to the patterned conductive layer via the conductive pillars.

20. The packaging structure of claim 11, further comprising: A second dielectric structure covers the first electronic component and the second electronic component. The second dielectric structure is a second encapsulating material, which includes a second epoxy resin and a second filler. The average size of the second filler is different from the average size of the first filler.

Images