Stackable flip chip package

Abstract

Examples described herein provide stackable flip chip packages. In one example, a memory package includes a first flip chip package including a first memory die and a metal pad. The first flip chip package can also include a molded support at least partially surrounding the first memory die. The first memory die and the metal pad can be located on opposite sides of a redistribution layer. The package also includes a second flip chip package vertically stacked on the first flip chip package, the second flip chip package including a second memory die and an interconnect configured to contact the metal pad. The interconnect can protrude from a redistribution layer of the second flip chip package. The first flip chip package can be coupled to a printed circuit board of a solid state drive.

Description

Background Technology

[0001] This disclosure relates to storage devices. More specifically, this disclosure relates to stackable flip-chip memory dies.

[0002] With technological advancements, the capacity and speed of memory arrays in data storage devices, such as solid-state drives (SSDs), are constantly increasing. The demand for higher processing speeds necessitates increased throughput from these memory arrays. Therefore, storage device manufacturers seek to increase both the storage capacity and data throughput of their devices. While increasing the storage capacity of the memory array is desirable, increasing the size of the packaged memory components may be undesirable. Furthermore, there is almost always a search for achieving such improvements at a lower cost. Summary of the Invention

[0003] Printed circuit boards (PCBs) used in SSDs have limited space for memory dies (such as NAND dies). As an example, the PCB footprint of an M.2 2280 SSD allows up to eight flip-chip NAND dies to be filled on the top side of the PCB for storage capacity up to 1 terabyte (TB).

[0004] For storage exceeding 1TB (e.g., 2TB), a second set of flip-chip NAND dies can be mounted on the bottom side (e.g., the opposite side) of the PCB. While using the bottom side of the PCB provides additional storage space, it also presents challenges in terms of driver handling during assembly and testing. Additionally, to accommodate use on both sides of the PCB, additional PCB layers may be required for routing on both sides.

[0005] The examples described in this article provide packages (e.g., memory packages, SSD packages) that use stacked flip-chip memory dies. For example, two flip-chip dies can be stacked. The stacked flip-chip memory dies are then placed adjacent to each other on one side of an SSD PCB. Stacking flip-chip memory dies provides increased storage capacity while utilizing the same PCB coverage area as current single-sided SSD PCB designs. Stacking flip-chip memory dies also eliminates the need for additional PCB layers.

[0006] This invention provides a package comprising a first flip-chip package and a second flip-chip package vertically stacked on the first flip-chip package. The first flip-chip package includes a first memory die, metal pads, and a redistribution layer. The first memory die is connected to a first side of the redistribution layer, and the metal pads are integrated into a second side of the redistribution layer. The second flip-chip package includes a second memory die and interconnects configured to contact the metal die. The center of the first memory die is aligned with the center of the second memory die.

[0007] This disclosure also provides a package including a first vertically stacked package and a second vertically stacked package. The first vertically stacked package includes a first memory die electrically coupled and physically coupled to a second memory die, and a first sidewall surrounding at least a portion of the first memory die. The second vertically stacked package includes a third memory die electrically coupled and physically coupled to a fourth memory die, and a second sidewall surrounding at least a portion of the third memory die. The first sidewall contacts the second sidewall.

[0008] This disclosure also provides a package including a first stacked package and a second stacked package coupled to the top portion of the first stacked package. The first stacked package includes a first memory die electrically coupled and physically coupled to a second memory die. The second stacked package includes a third memory die electrically coupled and physically coupled to a fourth memory die. The first memory die, second memory die, third memory die, and fourth memory die are vertically aligned on the same axis.

[0009] In this way, various aspects of this disclosure provide improvements, at least in the technical field and design and architecture of packages (such as memory packages). The foregoing summary is intended only to give a general idea of ​​various aspects of this disclosure and is not intended to limit the scope of this disclosure in any way. Other aspects of this disclosure will become apparent from the detailed description, claims, abstract, and drawings. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a data storage system according to the implementation scheme described herein.

[0011] Figure 2 This is a diagram illustrating the PCB coverage area of ​​a single-sided M.2 2280 SSD PCB according to the implementation described herein.

[0012] Figure 3A This is a diagram illustrating the first side of the PCB coverage area of ​​a dual-sided M.2 2280 SSD PCB according to the implementation described herein.

[0013] Figure 3B This is a diagram illustrating the second side of the PCB coverage area of ​​a dual-sided M.2 2280 SSD PCB according to the implementation described herein.

[0014] Figure 4 This is a diagram illustrating a first example of a first package according to the implementation described herein.

[0015] Figure 5 This is a second example of a first package according to the implementation described herein.

[0016] Figure 6 This is a diagram illustrating an example of a second package according to the implementation described herein.

[0017] Figure 7A This is an example of an implementation scheme described herein, including... Figure 4 The first package and Figure 6 A diagram showing an example of a stacked package for the second package.

[0018] Figure 7B It is based on the implementation scheme described in this article. Figure 7A A bottom view of the stacked package.

[0019] Figure 8A This is an example of an implementation scheme described herein, including... Figure 7A and Figure 7B A cross-sectional view of a portion of the stacked package SSDPCB architecture.

[0020] Figure 8B It is based on the implementation scheme described in this article. Figure 8A A top view of the SSD PCB architecture.

[0021] Figure 8C This is an example Figure 8A A diagram of the SSD architecture.

[0022] Figure 8D This is an example Figure 8A A top view diagram of the SSD architecture.

[0023] Figure 9 This is an example of an implementation scheme described herein, including... Figure 7A and Figure 7B A second example of an SSD architecture with stacked packages is shown in the figure.

[0024] Figure 10 This is a cross-sectional view illustrating an FC memory die tower according to the embodiment described herein. Detailed Implementation

[0025] Before explaining any embodiment of this disclosure in detail, it should be understood that this disclosure, in its application, is not limited to the construction details and component arrangements set forth in the following description or illustrated in the following drawings. This disclosure can have other embodiments and can be practiced or implemented in various ways. Those skilled in the art will also understand that the drawings are not drawn to scale, and some features have been exaggerated to highlight them.

[0026] Figure 1 This is a block diagram illustrating a data storage system 100 having a storage device 106 that can be combined with a host device 104, according to one or more technologies of this disclosure. For example, the host device 104 can use the non-volatile memory included in the storage device 106 to store and retrieve data.

[0027] Storage system 100 includes host device 104, which can store data to and / or retrieve data from storage device 106. For example... Figure 1 As illustrated, host device 104 can communicate with storage device 106 via interface 114. Host device 104 may include any of a wide range of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, mobile phones (such as so-called "smart" phones, so-called "smart" tablets), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc.

[0028] like Figure 1 As illustrated, storage device 106 includes a controller 108, non-volatile memory (NVM) 110, volatile memory 112, and interface 114. In some examples, storage device 106 may include additional components, which are shown in the image for clarity. Figure 1Not shown. For example, storage device 106 may include a printed circuit board (PCB) to which components of storage device 106 are mechanically attached, and the PCB includes conductive traces for electrically interconnecting components of storage device 106, etc. In some embodiments, storage device 106 may include fewer components, for example, where one or more of volatile memory 112 and interface 114 are part of controller 108. In some examples, the physical dimensions and connector configuration of storage device 106 may conform to one or more standard form factors. Some example standard form factors for storage devices may include 3.5” data storage devices, 2.5” data storage devices, and 1.8” data storage devices. Some example standard form factors for interface 114 may include Peripheral Component Interconnect (PCI), PCI Expansion (PCI-X), and PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini-card, MiniPC1, etc.). In some examples, storage device 106 may be directly attached (e.g., directly soldered) to the motherboard of host device 104.

[0029] The interface 114 of storage device 106 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), etc. Interface 114 is communicatively connected (e.g., a data bus, control bus, or other suitable connection) to controller 108, thereby allowing data exchange between host device 104 and controller 108. In some examples, interface 114 may also allow storage device 106 to receive power from host device 104.

[0030] NVM 110 may be part of a packaged integrated circuit (IC) or other packaged silicon device, such as a stacked memory package. NVM 110 may also include read / write circuitry for reading data from and writing data to another part of the memory device. For example, the read / write circuitry of NVM 110 may receive data and messages from controller 108 instructing the read / write circuitry to store data in NVM 110. Similarly, the read / write circuitry of NVM 110 may receive messages from controller 108 instructing the read / write circuitry to retrieve data from NVM 110. In some examples, each die (i.e., controller 108 and the memory dies constituting the NVM 110 of the memory device) may be individually referred to as a silicon die.

[0031] In some examples, the stacked memory package can include any type of non-volatile memory. For example, the NVM 110 can include flash memory or any other suitable non-volatile memory. The flash memory can include NAND-based or NOR-based flash memory and can store data based on the charge contained in the floating gate of the transistor in each flash memory cell. In NAND-based flash memory, the flash memory can be divided into multiple blocks, which can be further divided into multiple pages. Each block can include multiple NAND cells. Rows of NAND cells can be electrically connected using word lines to define pages within the multiple pages. The corresponding cells in each page can be electrically connected to the corresponding bit lines. Furthermore, the NAND-based flash memory can be 2D or 3D and can be configured as a single-level cell (SLC) memory, a multi-level cell (MLC) memory, a three-level cell (TLC) memory, or a four-level cell (QLC) memory.

[0032] Controller 108 may use volatile memory 112 to store information. Volatile memory 112 may consist of one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 before writing it to NVM 110. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0033] Controller 108 manages one or more operations of storage device 106. For example, controller 108 may manage reading data from and / or writing data to NVM 110. In some embodiments, when storage device 106 receives a write command from host device 104, controller 108 may initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. In other embodiments, controller 108 may determine at least one operational characteristic of storage system 100 and store at least one operational characteristic in NVM 110.

[0034] In some cases, comparing the PCB of an SSD package (such as an M.2 2280 SSD) allows for up to eight flip-chip NAND dies on the top side of the PCB, thus allowing for up to one terabyte (TB) of memory. As a comparison example, Figure 2 This diagram illustrates the PCB coverage area 200 of a single-sided M.2 2280 SSD PCB. Multiple flip-chip (FC) NAND memory dies 202 are located on the top portion of PCB 204. An electronic processor 206 (e.g., controller 108) is also located on PCB 204. Figure 2 In the example, the multiple FC NAND memory dies 202 include eight memory dies providing 1TB of memory. While the examples described herein primarily exemplify the M.2 2280 SSD, the implementations described herein can also be implemented in other types of SSDs.

[0035] To increase storage capacity, in some cases, FCNAND memory dies are provided on both the top and bottom portions of the PCB. As another comparative example, Figure 3A This is a diagram illustrating the first side of the PCB coverage area 300 of a dual-sided M.22280 SSD PCB. A first plurality of FC NAND memory dies 302 are located on the top portion of the PCB 204, next to the electronic processor 206. Figure 3B This diagram illustrates the second side of the PCB coverage area 300 of a dual-sided M.2 2280 SSD PCB. A second plurality of FCNAND memory dies 304 are located on the bottom portion of the PCB 204. Figures 3A to 3B In the example, eight memory dies are provided on the top section and eight memory dies are provided on the bottom section, thus providing a total of 2TB of memory.

[0036] While using the bottom portion of the SSD PCB provides additional memory, additional PCB layers are also necessary to accommodate the routing of memory dies on both sides of the SSD PCB. The examples described in this article provide packages with stacked FC memory dies, such as SSD memory packages, to achieve greater memory using only one side of the SSD PCB.

[0037] Figure 4 This is a diagram illustrating a first example of a first FC package 400 (e.g., an FC NAND package). In some examples, the first FC package 400 is a fan-out wafer-level package (FO-WLP). The example first FC package 400 includes a memory die 402, molded sidewalls 404 (e.g., molded supports), a redistribution layer (RDL) 406, a plurality of metal pads 408, and interconnects 410. Figure 4 In the example, memory die 402 is an exposed die, such that the top portion of memory die 402 is exposed to air and contacts the molded sidewall 404 adjacent to the side portion of memory die 402.

[0038] In some cases, the memory die 402 is completely covered by the molded shell. For example, Figure 5 This is an example and Figure 4 The first FC package 400 is substantially similar to a second example of the first FC package 500. In the example first FC package 500, the memory die 402 is made of a material similar to... Figure 4 The molded shell 502 of the molded sidewall 404 encapsulates (e.g., covers) the memory die 402. The molded shell 502 can be achieved by surrounding the memory die 402 with plastic material or by covering the memory die 402 with tape.

[0039] return Figure 4 The memory die 402 and molded sidewall 404 are located on the top portion of the RDL 406. Multiple metal pads 408 are located on the bottom portion of the RDL 406 (e.g., integrated or embedded into this bottom portion). The multiple metal pads 408 may be made of, for example, gold, silver, aluminum, copper, or some other conductive metal. The multiple metal pads 408 are configured to receive corresponding interconnects 606 of the second FC package 600, as per [reference to...]. Figure 6 As described. The interconnect 410 may be, for example, solder balls filling the peripheral side of the first FC package 400. The interconnect 410 can connect the first FC package 400 to the PCB.

[0040] Figure 6This is an example diagram illustrating a second FC package 600. In some examples, the second FC package 600 is a fan-in wafer-level package (FI-WLP). The example second FC package 600 includes a memory die 602, an RDL 604, and multiple interconnects 606. The memory die 602 is located on the opposite side of the RDL 604 compared to the multiple interconnects 606. The memory die 602 can be a memory package of a similar type to the memory die 402. For example, the memory die 602 and the memory die 402 can be silicon dies of approximately the same size. In other cases, the memory die 602 and the memory die 402 can be memory dies of different types. For example, the memory die 602 can be physically smaller than the memory die 402. The multiple interconnects 606 protrude (e.g., extend) from the RDL 604. The multiple interconnects 606 can be made of tin-plated copper, can be solder balls, can be gold bumps, can be copper pillars, etc.

[0041] The second FC package 600 is physically connected to and electrically connected to the first FC package 400 to form a stacked FC package. For example, Figure 7A and Figure 7B This is a diagram illustrating an example of a stacked FC package 700. The stacked FC package 700 includes a second FC package 600 connected to a first FC package 400. In some embodiments, the second FC package 600 is vertically connected below the first FC package 400. For example, the center of the first FC package 400 may be aligned with the center of the second FC package 600. A plurality of interconnects 606 of the second FC package 600 are connected to a plurality of metal pads 408 of the first FC package 400. For example, the plurality of interconnects 606 may be soldered to the plurality of metal pads 408. In other examples, the plurality of interconnects 606 are connected to the plurality of metal pads 408 via an adhesive (such as a conductive adhesive).

[0042] An electrical path 702 is provided between the first FC package 400 and the second FC package 600. Figure 7A and Figure 7B In the example, electrical path 702 travels from memory die 602 through multiple interconnects 606 and multiple metal pads 408 to memory die 402, and then through interconnect 410. Interconnect 410 can then be connected to a PCB, such as the SSD PCB on which the stacked FC package 700 is located. Therefore, signals can travel directly between memory die 402 and memory die 602 without crossing a PCB. Electrical path 702 can travel through the SSD PCB to connect to a controller, such as controller 108. Figure 7A and Figure 7B (Not shown in the image).

[0043] After forming the stacked FC package 700, multiple stacked memory packages 700 are placed on the SSD PCB. For example, Figure 8A This is a cross-sectional view illustrating a portion of the SSD PCB architecture 800. Figure 8B yes Figure 8A A top view of the SSD PCB architecture 800. (See attached image.) Figure 8A As shown, the first stacked FC package 700A and the second stacked FC package 700B are positioned adjacent to each other as a combined package having a shared RDL 406. The first stacked FC package 700A and the second stacked FC package 700B can be... Figure 8C Two of the stacked FC packages 700 shown are examples of stacked FC packages. For example, interconnect 410 is soldered to SSD PCB 802. In some examples, such as Figure 8A As illustrated, the first stacked FC package 700A and the second stacked FC package 700B are in contact with each other. In other examples, the first stacked FC package 700A and the second stacked FC package 700B are separated from each other (e.g., through an air gap).

[0044] Figure 8C This is a plan view illustrating an SSD PCB architecture 800. Multiple stacked FC packages 700 are disposed on a first side (e.g., top) of the SSD PCB 802 (next to the electronic processor 206). Figure 8D This is a diagram illustrating the second side (e.g., the bottom) of an SSD PCB architecture 800, opposite the first side. Figure 8C As seen, the second side of the SSD PCB 802 is empty.

[0045] In some cases, such as Figure 8C As shown, multiple stacked FC packages 700 are evenly spaced above the SSD PCB 802. In other cases, two or more of the stacked FC packages 700 may be connected together or arranged directly adjacent to each other.

[0046] Figure 9 This is a diagram illustrating a second example of an SSD PCB architecture 900, which includes multiple stacked FC packages 700 on an SSD PCB 902. Figure 9As shown, multiple stacked FC packages 700 can be configured in pairs 904, where each stacked FC package 700 within a pair 904 is connected to another stacked FC package 700. This paired configuration of the multiple stacked FC packages 700 increases the distance 906 between the multiple stacked FC packages 700 and the electronic processor 206, thereby utilizing a smaller area of ​​the SSD PCB 902. In some specific implementations, the multiple stacked FC packages 700 may be connected in triples (e.g., a 1×3 matrix), quads (e.g., a 1×4 matrix), or some other combination (e.g., up to a 1×N matrix) instead of in pairs 904 (e.g., a 1×2 matrix).

[0047] In some implementations, stacked FC packages can be further stacked on top of each other to create a memory die tower. Figure 10 This is a cross-sectional view illustrating an FC memory die tower 1000, which includes a first stacked FC package 1002A connected to the top portion of a second stacked FC package 1002B. The first stacked FC package 1002A includes a first memory die 1004 and a second memory die 1006. The second stacked FC package 1002B includes a third memory die 1008 and a fourth memory die 1010. Interconnects 410 of the first stacked FC package 1002A are connectable to molded sidewalls 1014 of the second stacked FC package 1002B. The first stacked FC package 1002A and the second stacked FC package 1002B are stackable such that the first memory die 1004, the second memory die 1006, the third memory die 1008, and the fourth memory die 1010 are positioned along a coaxial axis 1012.

[0048] To enable communication between the first stacked FC package 1002A and the second stacked FC package 1002B, the molded sidewall 1014 may include metal interconnects 1016, such as through-holes. The metal interconnects 1016 may be connected to electrical paths 702 and interconnects 410, thereby electrically connecting the first stacked FC package 1002A and the second stacked FC package 1002B.

[0049] In some specific implementations, the stacked FC package is (i) further stacked into the tower (e.g. Figure 10 (ii) connected to an adjacent stacked FC package (as previously shown) Figure 9 (As shown in the diagram). In this way, multiple stacked FC packages can be connected in an M×N matrix instead of a 1×N matrix.

[0050] While the examples described herein primarily refer to memory dies, the packages described herein can also be used for other types of dies. For example, controller dies can be implemented within the packages described herein.

[0051] While the foregoing description pertains to embodiments of this disclosure, other and additional embodiments of this disclosure may be devised without departing from its basic scope. The scope of this disclosure shall be determined by the appended claims.

Claims

1. A package, the package comprising: A first flip-chip package, the first flip-chip package comprising: First memory die, Metal pads, and A redistribution layer, wherein the first memory die is connected to a first side of the redistribution layer, and wherein the metal pads are integrated into a second side of the redistribution layer; and A second flip-chip package is vertically stacked on top of the first flip-chip package. The second flip-chip package includes: Second memory die, and Interconnectors, the interconnectors being configured to contact the metal pads, The center of the first memory die is aligned with the center of the second memory die.

2. The package according to claim 1, wherein the second memory die is smaller than the first memory die.

3. The package of claim 1, wherein the first flip chip package further comprises a molding support configured to contact a side portion of the first memory die.

4. The package according to claim 1, further comprising: The third flip-chip package includes: The third die, and Second metal pad; and A fourth flip-chip package, which is vertically stacked on top of the third flip-chip package, comprises: The fourth die, and The second interconnect is configured to contact the second metal pad.

5. The package according to claim 4, wherein the third die is a first controller die, and wherein the fourth die is a second controller die.

6. The package of claim 1, wherein the second flip-chip package further comprises a redistribution layer, wherein the second die is connected to a first side of the redistribution layer, and wherein the interconnect is connected to a second side of the redistribution layer.

7. The package of claim 1, wherein the first memory die is electrically connected to the second die via an electrical path, wherein the electrical path travels through the metal pads and the interconnect.

8. The package of claim 7, wherein the first flip-chip package is connected to a printed circuit board, and wherein the electrical path travels from the first memory die to the printed circuit board.

9. A package, the package comprising: A first vertically stacked package, comprising: A first memory die, which is electrically and physically coupled to a second memory die, and A first sidewall, the first sidewall surrounding at least a portion of the first memory die; and The second vertically stacked package includes: A third memory die, which is electrically and physically coupled to a fourth memory die, and A second sidewall, the second sidewall surrounding at least a portion of the third memory die, The first sidewall contacts the second sidewall.

10. The package of claim 9, wherein the first stacked package further includes a first redistribution layer supporting the first memory die, and wherein the second stacked package further includes a second redistribution layer supporting the third memory die.

11. The package of claim 10, wherein the first redistribution layer contacts the second redistribution layer.

12. The package according to claim 9, further comprising: A third stacked package, the third stacked package comprising: The fifth memory die, which is electrically and physically coupled to the sixth memory die, and A third sidewall, the third sidewall surrounding at least a portion of the fifth memory die, The second sidewall contacts the third sidewall.

13. The package of claim 9, wherein the first sidewall is a sidewall of a molded shell, and wherein the molded shell encapsulates the first memory die.

14. A package comprising: A first stacked package, the first stacked package comprising: A first memory die, which is electrically and physically coupled to a second memory die, and A second stacked package, coupled to the top portion of the first stacked package, the second stacked package comprising: A third memory die, which is electrically and physically coupled to a fourth memory die. The first memory die, the second memory die, the third memory die, and the fourth memory die are vertically aligned on the same axis.

15. The package of claim 14, wherein the first stacked package includes a first molded sidewall surrounding at least a portion of the first memory die, and wherein the second stacked package includes a second molded sidewall surrounding at least a portion of the second memory die.

16. The package of claim 15, wherein the first molded sidewall includes a first through-hole that electrically couples the first stacked package to the second stacked package.

17. The package of claim 15, wherein the first stacked package includes an interconnect located between the first molded sidewall and the second molded sidewall.

18. The package of claim 14, wherein the first memory die and the second memory die are electrically connected and physically connected via a plurality of interconnects.

19. The package of claim 18, wherein the second memory die is located on the redistribution layer, and wherein the plurality of interconnects protrude from the redistribution layer.

20. The package of claim 14, wherein the second stacked package is connected to the printed circuit board of the M.2 2280SSD.

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