High-low temperature cycle performance test method and device, electronic equipment and storage medium

Abstract

The application discloses a high-low temperature cycle performance test method and device, electronic equipment and a storage medium, and aims at solving the problems of high artificial dependence, low test consistency and low test efficiency in the prior art. The application is applied to a performance test system for high-low temperature cycle test. The system comprises multiple devices under test placed in a high-low temperature box, each device under test corresponds to an independent power supply channel and a performance test channel. When it is detected that the high-low temperature box starts to operate, all performance test channels are automatically triggered, each performance test channel performs high-low temperature power-on and power-off cycle test based on preset cycle test parameters, the first performance test channel with an abnormality is subjected to abnormality level determination to determine whether to continue to perform cycle test, when all the first performance test channels that continue to perform cycle test and the second performance test channels without abnormality complete power-on and power-off cycle test, the cycle test process is terminated, and a comprehensive test analysis report is generated based on the test condition.

Description

Technical Field

[0001] This invention relates to the field of automated testing technology, and in particular to a method, apparatus, electronic device, and storage medium for high and low temperature cycling performance testing. Background Technology

[0002] In the development of electronic devices, environmental adaptability testing is a crucial step in ensuring the stability and reliability of equipment or products under different temperature conditions. High and low temperature cycling testing, as a common environmental testing method, aims to evaluate the performance of the device under test (DUT) under extreme temperature changes.

[0003] Traditional high and low temperature testing methods typically require manual operation of the equipment's power-on and power-off processes. Furthermore, functional tests must be performed manually after each power-on. This manual operation is not only inefficient but also prone to human error, resulting in inconsistent testing. When facing large-scale testing needs (such as completing at least 10 tests per device, 100 cycles per device), it also leads to significantly extended testing cycles, increasing development costs and time pressure. Summary of the Invention

[0004] This invention provides a method, apparatus, electronic device, and storage medium for testing high and low temperature cycling performance, which solves or partially solves the technical problems of high dependence on manual labor, low test consistency, and low test efficiency in current high and low temperature cycling performance testing technologies.

[0005] This invention provides a high and low temperature cycling performance testing method and a performance testing system applied to high and low temperature cycling testing; the performance testing system includes multiple devices under test placed inside a high and low temperature chamber, each device under test corresponding to an independent power supply channel and a performance testing channel; the method includes:

[0006] Upon detecting that the high and low temperature chamber has started operation, all the performance test channels are automatically triggered, and each of the performance test channels performs high and low temperature power-on and power-off cycle tests based on its own preset cycle test parameters;

[0007] An anomaly level is determined for the first performance test channel where an anomaly is detected, and the decision to continue or stop the cyclic test for the first performance test channel is made based on the anomaly level determination result.

[0008] The entire cyclic test process is terminated when all the first performance test channels that continue to execute the cyclic test and the second performance test channels that have not encountered any abnormalities have completed their respective power-on and power-off cyclic tests.

[0009] Based on the test results of this cyclical test process, a comprehensive test analysis report is generated.

[0010] Optionally, the performance testing system further includes a visualization terminal and a monitoring module; the monitoring module includes a video acquisition device and a time-point monitoring module installed outside the high and low temperature chamber; each device under test also corresponds to an independent serial port log acquisition channel and an anomaly locking module; the method further includes:

[0011] When all the performance test channels are automatically triggered, the display interface of the visualization terminal, the video acquisition device, the time point monitoring module, the serial port log acquisition channel and the anomaly locking module corresponding to each of the devices under test are simultaneously triggered and started.

[0012] During the loop test:

[0013] The video acquisition device records the test process video stream of all the tested equipment inside the high and low temperature chamber in real time.

[0014] The time point monitoring module records the time point information corresponding to the video stream of the test process in real time.

[0015] For each device under test, the SOC serial port log information of the device under test is collected and output in real time through the serial port log acquisition channel, and the abnormal situation of the device under test is monitored in real time through the abnormal locking module.

[0016] The display interface of the visualization terminal displays the test status of each performance test channel and the SOC serial port log information of each device under test in real time.

[0017] Optionally, the step of determining the anomaly level of the first performance test channel where an anomaly is detected, and determining whether the first performance test channel should continue or stop executing the cyclic test based on the anomaly level determination result, includes:

[0018] The device under test that is detected to be abnormal in real time by the abnormal locking module is identified as the abnormal device under test, and the performance test channel of the abnormal device under test is identified as the first performance test channel.

[0019] The first performance test channel is assessed for anomaly level based on a preset anomaly level to determine the anomaly level of the first performance test channel.

[0020] When the anomaly level is the first level of anomaly, the first performance test channel continues to execute subsequent loop tests.

[0021] When the anomaly level is the second level of anomaly, the first performance test channel maintains the current test state and stops executing subsequent loop tests.

[0022] Optionally, the abnormal situations corresponding to the first level of abnormality include the tested device currently operating normally, the core functions, communication, and control logic of the tested device not failing, and the tested device exhibiting non-critical phenomena; the non-critical phenomena include no change in status indicator lights and incomplete logs; the abnormal situations corresponding to the second level of abnormality include the failure of the core functions of the tested device, the inability of the tested device's critical business, control, communication, and sampling functions to work normally, and the tested device exhibiting obvious fault phenomena; the obvious fault phenomena include inability to start, automatic restart, system crash, and component overheating.

[0023] Optionally, the comprehensive test analysis report generated based on the test results of this cyclic test process includes:

[0024] The test process video streams and time points of all devices under test in this cyclic test process are summarized, along with the complete SOC serial port log information, test pass rate and anomaly statistics of each device under test, to generate a comprehensive test analysis report for the entire process.

[0025] Optionally, the performance testing system further includes a temperature acquisition module placed inside a high and low temperature chamber; the method further includes:

[0026] During the cyclic test, the actual internal temperature of the high and low temperature chamber is collected in real time by the temperature acquisition module, and the actual internal temperature is compared with the preset internal temperature.

[0027] When the temperature deviation between the actual internal temperature and the preset chamber temperature exceeds the preset temperature difference threshold, the cyclic testing of all performance test channels is immediately stopped, and an alarm prompt window for abnormal temperature field pops up on the display interface of the visualization terminal, and the temperature deviation value between the actual internal temperature and the preset chamber temperature is displayed simultaneously in the alarm prompt window.

[0028] Optionally, the method further includes:

[0029] The visualization terminal receives the cyclic test parameters input by the user for each of the devices under test through its display interface, and completes the parameter settings for the devices under test based on the cyclic test parameters.

[0030] Save all parameter settings of the device under test, trigger the preliminary test mode to perform preliminary verification of the performance test system, and enter the test preparation state after the preliminary verification is completed.

[0031] This invention also provides a high and low temperature cycling performance testing device, a performance testing system applied to high and low temperature cycling testing; the performance testing system includes multiple devices under test placed inside a high and low temperature chamber, each device under test corresponding to an independent power supply channel and performance testing channel; the device includes:

[0032] The cyclic test execution unit is used to detect the start-up of the high and low temperature chamber and automatically trigger all the performance test channels. Each of the performance test channels performs high and low temperature power-on and power-off cyclic tests based on its own preset cyclic test parameters.

[0033] The test anomaly handling unit is used to determine the anomaly level of the first performance test channel that has detected an anomaly, and to determine whether the first performance test channel should continue or stop executing the loop test based on the anomaly level determination result.

[0034] The loop test termination unit is used to terminate the entire loop test process when all the first performance test channels that continue to execute the loop test and the second performance test channels that have not encountered any abnormalities have completed their respective power-on and power-off loop tests.

[0035] The analysis report generation unit is used to generate a comprehensive test analysis report based on the test results of this test cycle.

[0036] The present invention also provides an electronic device, the device comprising a processor and a memory:

[0037] The memory is used to store program code and transmit the program code to the processor;

[0038] The processor is used to execute the high and low temperature cycling performance test method as described above, according to the instructions in the program code.

[0039] The present invention also provides a computer-readable storage medium for storing program code for executing the high and low temperature cycling performance testing method as described in any of the preceding claims.

[0040] As can be seen from the above technical solutions, the present invention has the following advantages:

[0041] A high and low temperature cycling performance testing method is provided. A performance testing system for high and low temperature cycling testing is also provided. The system includes multiple devices under test (DUTs) placed inside a high and low temperature chamber, each DUT corresponding to an independent power supply channel and performance testing channel. Upon detection of the chamber's startup, all performance testing channels are automatically triggered. Each performance testing channel performs high and low temperature power-on / off cycling tests based on its preset cycling test parameters. This allows for the construction of a performance testing system with independent test channels for multiple devices, enabling synchronous parallel testing of multiple devices. Each device can independently complete multiple cycles of power-on / off performance tests. Since each DUT's test channel is independent, even if a single-channel anomaly occurs, it does not affect other normal devices from continuing to perform cycling tests, significantly improving overall testing efficiency. For test anomaly scenarios, the first performance testing channel where an anomaly is detected is assessed for an anomaly level, and the decision to continue or stop the cycling test for that channel is based on the anomaly level assessment result. Therefore, by addressing test anomalies through anomaly level assessment and corresponding handling methods, the targeted nature of anomaly handling is improved, avoiding over-intervention for minor anomalies and failure to handle serious anomalies in a timely manner. Once all the first performance test channels and the second performance test channels that did not exhibit any abnormalities have completed their respective power-on / off cycle tests, the entire cycle test process terminates. Based on the test results of this cycle test process, a comprehensive test analysis report is generated. Thus, through automated processes such as automatic data acquisition, automatic judgment, automatic storage, and automatic test report generation, the entire high and low temperature cycle performance testing process is automated, overcoming the high reliance on manual labor in traditional methods, avoiding human intervention, and significantly improving test consistency. This process requires no manual intervention, significantly reducing on-site manpower and achieving efficient optimization of testing personnel. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a performance testing system for high and low temperature cycling tests;

[0044] Figure 2 A flowchart illustrating the steps of a high and low temperature cycling performance testing method;

[0045] Figure 3 This is a schematic diagram of the overall process of a high and low temperature cycling performance testing method.

[0046] Figure 4This is a structural block diagram of a high and low temperature cycling performance testing device. Detailed Implementation

[0047] This invention provides a method, apparatus, electronic device, and storage medium for high and low temperature cycling performance testing, which solves or partially solves the technical problems of high dependence on manual labor, low test consistency, and low test efficiency in current high and low temperature cycling performance testing technologies.

[0048] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0049] As an example, in the development of electronic devices, environmental adaptability testing is a crucial step in ensuring the stability and reliability of equipment or products under different temperature conditions. High and low temperature cycling testing, a common environmental testing method, aims to evaluate the performance of the device under test under extreme temperature variations.

[0050] Traditional high and low temperature testing methods typically require manual operation of the equipment's power-on and power-off processes. Furthermore, functional tests must be performed manually after each power-on. This manual operation is not only inefficient but also prone to human error, resulting in inconsistent testing. When facing large-scale testing needs (such as completing at least 10 tests per device, 100 cycles per device), it also leads to significantly extended testing cycles, increasing development costs and time pressure.

[0051] Further analysis of this invention reveals that the currently used high and low temperature testing methods have the following main drawbacks:

[0052] 1. High reliance on manual intervention, resulting in poor test consistency and efficiency.

[0053] Specifically, the entire testing process requires personnel to be present to perform power-on / off, function verification, and result recording, resulting in high labor costs and high labor intensity. At the same time, this method is easily affected by personnel's operating habits, fatigue, and reaction speed, and human deviations can occur in the timing of power-on / off, test sequence, and function judgment, resulting in poor consistency, low reliability, and low overall efficiency of test data.

[0054] 2. A single machine failure can block the entire process, resulting in poor test parallelism.

[0055] In traditional testing methods, multiple devices share the same testing process and environment. If any device malfunctions, all tests must be paused for processing. This makes it impossible to "preserve the site of malfunctioning devices and continue testing of normal devices," which significantly lengthens the overall testing cycle and results in low utilization of testing resources.

[0056] 3. Lack of accurate time and status traceability capabilities.

[0057] The current solution lacks a unified timestamp and status monitoring mechanism, making it impossible to accurately pinpoint the time of anomaly occurrence, ambient temperature, and equipment operating status. Furthermore, traditional methods lack a visual real-time monitoring interface, preventing developers from intuitively reproducing and judging abnormal phenomena, thus making anomaly localization and analysis extremely difficult.

[0058] 4. Without full log collection, it is difficult to analyze the root causes of problems.

[0059] Traditional solutions cannot capture and synchronize the serial port logs, startup logs, and runtime logs of the storage device SOC (System on Chip) in real time during testing. This not only easily leads to incomplete and untraceable test data, but also results in a lack of crucial evidence chains when problems such as crashes, restarts, or communication anomalies occur, making it difficult to conduct root cause analysis.

[0060] 5. Functional verification relies on unpacking, which disrupts the incubator environment.

[0061] Most functional verifications require brief manual operation or transfer testing by opening the high and low temperature chamber door, leading to sudden temperature changes and disruption of the temperature field, resulting in distorted test conditions. Furthermore, it can only perform simple functional assessments and cannot automatically cover complex scenarios, compromising both data accuracy and testing efficiency.

[0062] Therefore, one of the core inventive points of this invention is to address the shortcomings of current technologies by proposing a high and low temperature cycling performance testing system and a high and low temperature cycling performance testing method applicable to this system. On one hand, by building a performance testing system with independent test channels for multiple devices, it supports simultaneous parallel testing of at least 10 devices, each capable of independently completing 100 cycles (or other customizable cycles) of power-on / off and functional testing. The test channels of each device under test are completely independent; even if a single-channel anomaly occurs, it does not affect other normal devices from continuing the cyclic testing, significantly improving overall testing efficiency. On the other hand, by completely retaining anomaly information, data loss is effectively avoided, improving the efficiency of problem reproduction and localization. A data retention mechanism based on timestamps, logs, and video recording enables rapid tracing of anomaly causes, significantly shortening the problem analysis cycle. Through anomaly classification identification and corresponding anomaly classification prompts, the targeting of anomaly handling is improved, avoiding over-intervention of minor anomalies and failure to handle serious anomalies in a timely manner. Simultaneously, during the cyclic testing process, the actual temperature inside the temperature chamber is collected in real time and the temperature difference is compared to ensure accurate and stable ambient temperature, improving the effectiveness and reliability of the test.

[0063] Reference Figure 1 The diagram shows a structural schematic of a high and low temperature cycling performance testing system provided in an embodiment of the present invention.

[0064] First, the performance testing system consists of multiple devices under test housed inside a high and low temperature chamber. For ease of demonstration and explanation, Figure 1 Only two devices under test are shown inside the high and low temperature chamber as examples, namely DUT1 and DUT2.

[0065] Each device under test (DUT) corresponds to an independent main control board. For example, DUT1 corresponds to main control board 1, and DUT2 corresponds to main control board 2. The internal structures of main control board 1 and main control board 2 are similar; therefore, Figure 1 The main structure of the main control board 1 is shown only as an example.

[0066] Taking the main control board 1 as an example, the main control board 1 includes at least a network interface for external network transmission, a power interface for obtaining power support from an external power supply 1, a power-on / off module for controlling the power on / off of the DUT1 (power supply 1, the power interface, and the power-on / off module together constitute the independent power supply channel of the DUT1), a component hotspot monitoring module (which can also be regarded as an anomaly locking module) for monitoring hotspots of the DUT1 components, and a log module for real-time acquisition of the DUT1's SOC serial port logs (the communication connection between the log module and the DUT1 constitutes the serial port log acquisition channel of the DUT1). The network interface of the main control board 1 is connected to the test server outside the high and low temperature chamber through a network switch. At the same time, the monitoring module located outside the high and low temperature chamber communicates with the network switch to record the cyclic test status of each device under test inside the high and low temperature chamber in real time, and transmits the real-time recorded data back to the test server through the network switch. Among them, the communication connection between the network interface of the main control board 1, the network switch, and the test server can be regarded as constituting the performance test channel of the device under test (DUT1). The external monitoring module of the high and low temperature chamber can further include video acquisition equipment (such as a high-definition camera) and a time-point monitoring module (such as a time synchronization system or time synchro). In addition, the monitoring module can also employ an integrated monitoring and time-point recording device. That is, it uses a monitoring camera or data acquisition device with timestamp functionality to embed precise time directly into video frames or sensor data.

[0067] The performance testing system also includes a visual terminal with a display interface (such as a smartphone, computer, tablet, or other terminal that supports a visual interface) that communicates with the test server.

[0068] In addition, the performance testing system includes a temperature acquisition module placed inside the high and low temperature chamber. This module collects the actual temperature inside the chamber in real time during the cyclic testing process and compares the collected temperature with the pre-set temperature inside the chamber. When the temperature deviation exceeds a pre-set temperature threshold (e.g., 5°C), the system determines it as a temperature field anomaly and immediately triggers a global protection mechanism. At this point, all cyclic testing channels are stopped. Simultaneously, a temperature field anomaly alarm window pops up on the visual terminal interface, clearly indicating the temperature deviation value to urge testing personnel to take timely action.

[0069] Based on the aforementioned performance testing system, each Device Under Test (DUT) is equipped with an independent power supply channel, an independent performance testing channel, and an independent SOC serial port log acquisition channel, with each performance testing channel also featuring an independent anomaly locking module. This invention enables completely independent testing of multiple DUTs without interference, ensuring that the testing process, data acquisition, and anomaly handling of a single DUT do not affect other DUTs.

[0070] On the other hand, the main control unit of the test server can automatically trigger the power-on / off cycle of the independent performance test channels corresponding to each device under test according to preset performance test parameters (including cycle count, power-on / off sequence, functional judgment criteria, etc.), synchronously collect and parse the serial port logs of each device under test in real time, and complete the functional compliance judgment. No manual intervention is required throughout the process, avoiding human error.

[0071] Meanwhile, when a performance test channel corresponding to a device under test malfunctions (such as functional failure, power-on failure, serial port interruption, abnormal current or voltage, etc.), the channel immediately triggers the fault lockout mechanism, maintaining the current test state (including power supply state and log collection state) and stopping subsequent loop tests. Other normal performance test channels remain unaffected and continue to complete the power-on / off loop and testing according to the preset procedure, thus ensuring overall test efficiency.

[0072] In addition, at the moment an anomaly occurs, the system can automatically trigger a high-precision timestamp mark and simultaneously link the camera to start recording. This will completely preserve the footage before the anomaly occurs, at the moment of the anomaly, and after the anomaly occurs for a preset duration. It will also simultaneously save the complete serial port log, test data, and ambient temperature data of the performance test channel, providing a complete and intuitive chain of evidence for subsequent anomaly analysis and reducing the difficulty of analysis.

[0073] The performance testing system provided by this invention operates independently, without direct communication with the high and low temperature chamber, and requires no modification to the chamber's program. Its external wiring design is simple. In practical applications, only one network cable and power supply lines for each channel are needed externally to the high and low temperature chamber, maximizing wiring simplification and better adapting to the limited wiring holes and space within the chamber.

[0074] Based on the aforementioned performance testing system embodiment, referring to Figure 2 This document illustrates a flowchart of a high and low temperature cycling performance testing method provided by an embodiment of the present invention. The method is applied to the performance testing system for high and low temperature cycling testing as described above; the performance testing system includes multiple devices under test placed inside a high and low temperature chamber, each device under test corresponding to an independent power supply channel and performance testing channel. Specifically, the method may include the following steps:

[0075] Step 201: Upon detecting that the high and low temperature chamber has started operation, all performance test channels are automatically triggered. Each performance test channel performs high and low temperature power-on and power-off cycle tests based on its own preset cycle test parameters.

[0076] In practical applications, preliminary preparations are necessary before conducting actual high and low temperature cycling tests. Specifically, the temperature acquisition probe should be placed in a suitable position inside the high and low temperature chamber to ensure accurate temperature data acquisition. Then, at least 10 devices under test (DUTs) should be stably placed inside the chamber. Each device should be connected to its dedicated performance test interface, independent power supply interface, and SOC serial log output interface, ensuring reliable connections and good contact. Simultaneously, a camera should be mounted outside the chamber, aimed at the transparent observation window. The camera should be adjusted to clearly capture the operating status of all DUTs inside the chamber, completing the camera setup.

[0077] Next, log in to the test control system via a smart terminal (such as a computer or tablet) to configure test parameters independently for each device under test. Test parameters include the preset number of cycles (default 100) and the duration of a single power outage. Simultaneously, set the target high and low temperature test temperatures, temperature cycling rate, and configure output parameters such as the SOC serial port log output baud rate and log storage path. Define the grading criteria for abnormal situations (e.g., classifying abnormalities as minor or severe) and the corresponding handling rules. Complete the camera linkage configuration (including abnormal trigger recording duration and recording storage path). After all parameters are configured, save and confirm their effectiveness. In this embodiment of the invention, the handling rule refers to continuing subsequent cyclic tests in the event of a minor abnormality, and stopping subsequent cyclic tests in the event of a severe abnormality.

[0078] Among them, minor anomalies are defined as those with a relatively mild degree of abnormality. These anomalies include situations where the equipment continues to operate normally, core functions, communication, and control logic have not failed, and non-critical phenomena occur, such as status indicator lights not changing or logs being incomplete.

[0079] When an anomaly is severe, it is defined as a serious anomaly. Such anomalies include the failure of core equipment functions, the inability of critical business, control, communication, and sampling functions to work properly, and obvious faults such as failure to start, automatic restart, system crash, and component overheating.

[0080] Next, preliminary verification is performed. Specifically, the system's preliminary test mode is initiated, and the entire test program is run to verify the power supply stability of each channel, the validity of serial port log collection, the reliability of camera linkage, and the smoothness of test program execution. Once it is confirmed that there are no program errors, poor interface contact, or other issues, the preliminary verification ends, and the system enters the formal test preparation state.

[0081] Based on the preceding discussion, in the specific implementation, before the formal start of the high and low temperature cycle test, the user can receive the cycle test parameters for each device under test through the display interface of the visualization terminal, and complete the parameter settings for the devices under test based on the cycle test parameters; then save the parameter settings of all devices under test, trigger the preliminary test mode to perform preliminary verification of the performance test system, and after completing the preliminary verification, enter the test preparation state.

[0082] The temperature and humidity cycling program is set through the high and low temperature chamber control system (e.g., -40℃ → +85℃ constant temperature cycle; the temperature change rate and constant temperature duration can be adjusted according to actual test requirements). After the high and low temperature chamber starts up and begins running according to the preset program, the performance testing system is started with one click, simultaneously activating all performance testing channels. Each of the 10 devices under test independently starts the power-on and power-off cycle test. That is, when the high and low temperature chamber is detected to be running, all performance testing channels are automatically triggered, and each performance testing channel performs high and low temperature power-on and power-off cycle tests based on its own preset cycle test parameters. At the same time, the SOC serial port log output module (serial port log acquisition channel), the time point monitoring module, and the camera anomaly viewing module are started simultaneously. The serial port log acquisition channel collects and outputs the SOC serial port log of each device under test in real time; the time point monitoring module and the camera start recording in real time simultaneously, and the computer terminal display interface displays the test status, chamber temperature, and log data of each performance testing channel in real time.

[0083] In this embodiment of the invention, the entire cyclic testing process is executed fully automatically without manual intervention. The temperature acquisition module collects real-time temperature data from the high and low temperature chambers and simultaneously uploads it to the test server for transmission back to the computer terminal. Each performance test channel independently triggers the corresponding device under test according to a preset timing sequence to complete the complete process of "power-on → performance testing / functional detection → real-time acquisition and output of SOC serial port logs → test result recording → power-off → waiting for the next cycle." During this process, the 10 devices under test proceed simultaneously without interference between channels.

[0084] As discussed above, the performance testing system provided in this embodiment of the invention also includes a visualization terminal and a monitoring module. The monitoring module includes a video acquisition device and a time-point monitoring module located outside the high and low temperature chamber. Each device under test also has a corresponding independent serial port log acquisition channel and an anomaly locking module. In some embodiments, when all performance test channels are automatically triggered, the display interface of the visualization terminal, the video acquisition device, the time-point monitoring module, and the serial port log acquisition channel and anomaly locking module corresponding to each device under test are simultaneously triggered and activated.

[0085] During the loop test, each module performs the following actions:

[0086] The video stream of the testing process of all the tested equipment inside the high and low temperature chamber is recorded in real time using video acquisition equipment.

[0087] The time point monitoring module records the time point information corresponding to the video stream of the test process in real time.

[0088] For each device under test, the SOC serial port log information of the device under test is collected and output in real time through the serial port log acquisition channel, and the abnormal situation of the device under test is monitored in real time through the anomaly locking module.

[0089] The display interface of the visual terminal shows the test status of each performance test channel and the SOC serial port log information of each device under test in real time.

[0090] Therefore, by combining the performance testing system described in the foregoing embodiments and implementing the corresponding high and low temperature cycling performance testing methods, this invention supports simultaneous parallel testing of at least 10 devices. Each device can independently complete 100 cycles (or other customizable number of cycles) of power-on / off and functional testing. The entire process is automated, requiring no manual intervention, significantly reducing on-site manpower and achieving highly efficient optimization of testing personnel. Furthermore, the test channels of each device under test are completely independent; even if a single-channel anomaly occurs, it will not affect other normal devices from continuing to perform cyclic testing, greatly improving overall testing efficiency.

[0091] Step 202: Determine the anomaly level of the first performance test channel that has detected an anomaly, and determine whether the first performance test channel should continue or stop executing the loop test based on the anomaly level determination result;

[0092] During the cyclic testing process, if a device experiences an anomaly such as startup failure or functional malfunction, the anomaly locking module immediately determines the anomaly level according to preset standards, accurately records the timestamp of the anomaly, triggers the channel keep-alive mechanism (i.e., maintains the power supply and log collection status at the time of the anomaly), and issues a corresponding level of warning. The computer terminal receives the anomaly push notification in real time, synchronously displays the anomaly time, anomaly level, and the corresponding real-time video stream from the camera, and automatically locks the SOC serial port log segment, anomaly timestamp, and camera video segment at the time of the anomaly. Meanwhile, other normal performance test channels remain unaffected, and the system continues to complete the cyclic testing, log output, timestamp recording, and camera capture process. This effectively avoids data loss by completely retaining information about the anomaly scene, significantly improving the efficiency of problem reproduction and localization. Based on the three-in-one data retention mechanism of timestamp + log + video, the cause of the anomaly can be quickly traced, greatly shortening the problem analysis cycle.

[0093] When an anomaly occurs in a performance test channel, if it is determined to be a minor anomaly, the system issues a warning and the channel continues to execute loop tests while continuously recording anomaly-related data. If it is determined to be a higher-level or severe anomaly, subsequent loop tests for that channel are terminated, and an anomaly alarm window immediately pops up on the computer terminal, along with an audible and visual alert, reminding testers to investigate and handle the issue promptly. This anomaly classification and corresponding warning system improves the targeted nature of anomaly handling, avoiding over-intervention for minor anomalies and failure to address severe anomalies in a timely manner.

[0094] When the temperature acquisition module detects a deviation of more than 5°C between the actual temperature inside the high and low temperature chamber and the preset temperature, the system determines that a temperature field anomaly has occurred and immediately triggers the global protection mechanism. At this point, all performance test channels cease cyclic testing, and a temperature field anomaly alarm window pops up on the computer terminal, clearly indicating the temperature deviation value to urge test personnel to take timely action. By acquiring the actual temperature inside the chamber in real time and comparing the temperature difference, the system ensures accurate and stable ambient temperature, improving the effectiveness and reliability of the test.

[0095] Based on the preceding discussion, in the specific implementation, the process of determining the anomaly level of the first performance test channel when an anomaly is detected, and deciding whether to continue or stop the execution of the cyclic test based on the anomaly level determination result, may include: identifying the device under test (DUT) that is detected as having an anomaly by the anomaly locking module in real time as an abnormal DUT, and designating the performance test channel of the abnormal DUT as the first performance test channel; determining the anomaly level of the first performance test channel based on a preset anomaly level; in one scenario, when the anomaly level is the first level of anomaly, the first performance test channel continues to execute subsequent cyclic tests; in another scenario, when the anomaly level is the second level of anomaly, the first performance test channel maintains its current test state and stops executing subsequent cyclic tests.

[0096] Furthermore, the first level of anomaly corresponds to the following abnormal situations: the device under test (DUT) is currently operating normally, its core functions, communication, and control logic are not malfunctioning, and the DUT exhibits non-critical phenomena. Non-critical phenomena include no change in status indicator lights and incomplete logs. The second level of anomaly corresponds to the following abnormal situations: the core functions of the DUT fail, its critical business, control, communication, and sampling functions cannot function properly, and the DUT exhibits obvious fault phenomena. Obvious fault phenomena include inability to start, automatic restart, system crashes, and component overheating.

[0097] In some embodiments, the performance testing system may further include a temperature acquisition module placed inside the high and low temperature chamber. During cyclic testing, the temperature acquisition module can also collect the actual internal temperature of the high and low temperature chamber in real time and compare it with a preset chamber temperature. When the temperature deviation between the actual internal temperature and the preset chamber temperature exceeds a preset temperature difference threshold (e.g., the deviation exceeds 5°C), the cyclic testing of all performance testing channels is immediately stopped, and an alarm window indicating an abnormal temperature field pops up on the display interface of the visualization terminal. The alarm window also simultaneously displays the temperature deviation value between the actual internal temperature and the preset chamber temperature.

[0098] Step 203: When all the first performance test channels that continue to perform the loop test and the second performance test channels that have not encountered any abnormalities have completed their respective power-on and power-off loop tests, the entire loop test process is terminated.

[0099] The entire cyclic testing process terminates when all the first performance test channels and the second performance test channels that did not exhibit any abnormalities have completed their respective power-on and power-off cycle tests. Specifically, after all the devices under test corresponding to the normal test channels have completed the preset 100 cycle tests, the performance testing system automatically shuts down, and the high and low temperature chambers simultaneously stop their temperature cycling programs.

[0100] Step 204: Based on the test results of this cycle test process, generate a comprehensive test analysis report.

[0101] After the cyclic testing process is terminated, the computer terminal receives a test completion notification in real time and automatically generates a multi-dimensional test analysis report, which summarizes the complete SOC serial port logs of all devices under test, full process time point records, abnormal video data (when there are abnormalities), test pass rate, abnormal statistics and other analysis results, which are convenient for testers and developers to view and analyze.

[0102] Based on the foregoing discussion, in some embodiments, the process of generating a comprehensive test analysis report based on the test results of this cyclic test process may include: summarizing the test process video streams and time point information of all devices under test in this cyclic test process, as well as the complete SOC serial port log information, test pass rate and abnormal situation statistics of each device under test, and generating a comprehensive test analysis report for the entire process.

[0103] In this embodiment of the invention, a high and low temperature cycling performance testing method is provided, in conjunction with the performance testing system described in the foregoing embodiments. On one hand, this invention supports simultaneous parallel testing of at least 10 devices, each capable of independently completing 100 cycles (or other customizable cycles) of power-on / off and functional testing. Furthermore, the test channels of each device under test are completely independent; even if a single-channel anomaly occurs, it does not affect other normal devices from continuing the cyclic testing, significantly improving overall testing efficiency. On the other hand, by completely retaining anomaly information, data loss is effectively avoided, significantly improving the efficiency of problem reproduction and localization. A data retention mechanism based on timestamps, logs, and video recording enables rapid tracing of anomaly causes, greatly shortening the problem analysis cycle. Moreover, through anomaly classification identification and corresponding anomaly classification prompts, the targeting of anomaly handling is improved, avoiding over-intervention of minor anomalies and failure to handle serious anomalies in a timely manner. Simultaneously, during the cyclic testing process, the actual temperature inside the temperature chamber is collected in real time and the temperature difference is compared to ensure accurate and stable ambient temperature, improving the effectiveness and reliability of the test.

[0104] In summary, this invention achieves full automation of high and low temperature cycling performance testing through automated processes including automatic data acquisition, automatic judgment, automatic storage, and automatic test report generation. This overcomes the high reliance on manual labor inherent in traditional methods, avoids human intervention, and significantly improves test consistency. The process requires no manual intervention, significantly reducing on-site manpower and achieving efficient optimization of testing personnel.

[0105] For better illustration, based on the content described in the foregoing embodiments, refer to... Figure 3 This diagram illustrates the overall flow of a high and low temperature cycling performance testing method provided by an embodiment of the present invention. It should be noted that this embodiment only provides a brief description of the general flow of the high and low temperature cycling performance testing. The specific implementation process of each step can be understood by referring to the relevant content in the foregoing embodiments, and will not be elaborated upon here. It is understood that the present invention does not impose any limitations on this.

[0106] Step 301: Receive the loop test parameters input by the user for each device under test through the display interface of the visual terminal, and complete the parameter settings for the device under test based on the loop test parameters; trigger the preliminary test mode, perform preliminary verification of the performance test system, and enter the test preparation state;

[0107] Step 302: Upon detecting that the high and low temperature chamber has started running, all performance test channels are automatically triggered, and the display interface of the visualization terminal, video acquisition equipment, time point monitoring module, serial port log acquisition channel and anomaly locking module corresponding to each device under test are triggered simultaneously.

[0108] Step 303: Each performance test channel performs high and low temperature power-on and power-off cycle tests based on its own preset cycle test parameters; during the cycle test, the video acquisition device records the test process video stream of all the tested devices inside the high and low temperature chamber in real time, and the time point information corresponding to the test process video stream is recorded in real time through the time point monitoring module;

[0109] Step 304: For each device under test, the SOC serial port log information of the device under test is collected and output in real time through the serial port log acquisition channel, and the abnormal situation of the device under test is monitored in real time through the anomaly locking module; the test status of each performance test channel and the SOC serial port log information of each device under test are displayed in real time through the display interface of the visualization terminal.

[0110] Step 305: Identify the device under test that is detected to have an abnormal situation in real time by the anomaly locking module as an abnormal device under test, and determine the anomaly level of the first performance test channel corresponding to the abnormal device under test based on the preset anomaly level.

[0111] Step 306: When the anomaly level is the first level, the first performance test channel continues to execute subsequent loop tests; when the anomaly level is the second level, the first performance test channel maintains the current test state and stops executing subsequent loop tests.

[0112] Step 307: When all the first performance test channels that continue to perform the loop test and the second performance test channels that have not encountered any abnormalities have completed their respective power-on and power-off loop tests, terminate the entire loop test process; summarize the test process video streams and time point information of all devices under test, as well as the complete SOC serial port log information, test pass rate and abnormal situation statistics of each device under test, and generate a comprehensive test analysis report of the entire process.

[0113] Reference Figure 4 This diagram illustrates a structural block diagram of a high and low temperature cycling performance testing device according to an embodiment of the present invention. The device is applied to the performance testing system for high and low temperature cycling testing as described above; the performance testing system includes multiple devices under test placed inside a high and low temperature chamber, each device under test corresponding to an independent power supply channel and performance testing channel. Specifically, the device may include:

[0114] The cyclic test execution unit 401 is used to detect the start-up of the high and low temperature chamber and automatically trigger all the performance test channels. Each of the performance test channels performs high and low temperature power-on and power-off cyclic tests based on its own preset cyclic test parameters.

[0115] The test anomaly handling unit 402 is used to determine the anomaly level of the first performance test channel that has detected an anomaly, and to determine whether the first performance test channel should continue or stop executing the loop test based on the anomaly level determination result.

[0116] The loop test termination unit 403 is used to terminate the entire loop test process when all the first performance test channels that continue to execute the loop test and the second performance test channels that have not encountered any abnormalities have completed their respective power-on and power-off loop tests.

[0117] Analysis report generation unit 404 is used to generate a comprehensive test analysis report based on the test results of this test cycle.

[0118] In one optional embodiment, the performance testing system further includes a visualization terminal and a monitoring module; the monitoring module includes a video acquisition device and a time-point monitoring module disposed outside the high and low temperature chamber; each device under test also corresponds to an independent serial port log acquisition channel and an anomaly locking module; the device further includes:

[0119] The synchronous triggering startup unit is used to synchronously trigger the display interface of the visualization terminal, the video acquisition device, the time point monitoring module, the serial port log acquisition channel and the anomaly locking module corresponding to each of the devices under test when all the performance test channels are automatically triggered.

[0120] The real-time video stream recording unit for the test process is used to record the test process video stream of all the tested equipment inside the high and low temperature chamber in real time through the video acquisition device.

[0121] The real-time recording unit for time points is used to record the time point information corresponding to the video stream of the test process in real time through the time point monitoring module.

[0122] The device under test test information acquisition unit is used to collect and output the SOC serial port log information of each device under test in real time through the serial port log acquisition channel, and to monitor the abnormal situation of the device under test in real time through the abnormal locking module.

[0123] The test information display unit is used to display the test status of each performance test channel and the SOC serial port log information of each device under test in real time through the display interface of the visualization terminal.

[0124] In one optional embodiment, the test anomaly handling unit 402 includes:

[0125] The first performance test channel determination unit is used to determine the device under test that has an abnormal situation detected in real time by the abnormal locking module as an abnormal device under test, and to determine the performance test channel of the abnormal device under test as the first performance test channel.

[0126] An anomaly level determination unit is used to determine the anomaly level of the first performance test channel based on a preset anomaly level, and to determine the anomaly level of the first performance test channel.

[0127] The loop test execution unit is used to ensure that when the exception level is the first level of exception, the first performance test channel continues to execute subsequent loop tests.

[0128] The loop test stop execution unit is used to ensure that when the exception level is the second level of exception, the first performance test channel maintains the current test state and stops executing subsequent loop tests.

[0129] In one optional embodiment, the abnormal situation corresponding to the first level of abnormality includes the device under test currently operating normally, the core functions, communication, and control logic of the device under test not failing, and the device under test exhibiting non-critical phenomena; the non-critical phenomena include no change in status indicator lights and incomplete logs; the abnormal situation corresponding to the second level of abnormality includes the failure of the core functions of the device under test, the inability of the critical business, control, communication, and sampling functions of the device under test to work normally, and the device under test exhibiting obvious fault phenomena; the obvious fault phenomena include inability to start, automatic restart, system crash, and component overheating.

[0130] In one optional embodiment, the analysis report generation unit 404 is specifically used for:

[0131] The test process video streams and time points of all devices under test in this cyclic test process are summarized, along with the complete SOC serial port log information, test pass rate and anomaly statistics of each device under test, to generate a comprehensive test analysis report for the entire process.

[0132] In one optional embodiment, the performance testing system further includes a temperature acquisition module placed inside a high and low temperature chamber; the device further includes:

[0133] The temperature difference comparison unit is used to collect the actual internal temperature of the high and low temperature chamber in real time through the temperature acquisition module during the cyclic test, and compare the actual internal temperature with the preset chamber temperature.

[0134] The temperature field anomaly handling unit is used to immediately stop the cyclic testing of all performance test channels when the temperature deviation between the actual internal temperature and the preset chamber temperature exceeds a preset temperature difference threshold. The unit will pop up an alarm window for the temperature field anomaly through the display interface of the visualization terminal and simultaneously display the temperature deviation value between the actual internal temperature and the preset chamber temperature in the alarm window.

[0135] In one alternative embodiment, the device further includes:

[0136] The parameter setting unit is used to receive the cyclic test parameters input by the user for each of the devices under test through the display interface of the visualization terminal, and to complete the parameter setting of the devices under test based on the cyclic test parameters.

[0137] The preliminary verification unit is used to save the parameter settings of all the devices under test, trigger the preliminary test mode to perform preliminary verification of the performance test system, and enter the test preparation state after the preliminary verification is completed.

[0138] As the device embodiment is basically similar to the method embodiment, it is described in a relatively simple way. For relevant details, please refer to the description of the method embodiment above.

[0139] It should be noted that, in order to enable those skilled in the art to better distinguish data of the same type but with different actual meanings, the embodiments of the present invention use "first" and "second" to distinguish and describe some technical features. "First" and "second" are only used to distinguish data and have no other special meaning. It is understood that the present invention does not impose any limitations on them.

[0140] This invention also provides an electronic device, which includes a processor and a memory:

[0141] The memory is used to store program code and transfer the program code to the processor;

[0142] The processor is used to execute the high and low temperature cycling performance testing method of any embodiment of the present invention according to the instructions in the program code.

[0143] This invention also provides a computer-readable storage medium for storing program code for executing the high and low temperature cycling performance testing method of any embodiment of this invention.

[0144] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0145] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this invention are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0146] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some interfaces, and may be electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0149] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0150] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing high and low temperature cycling performance, characterized in that, A performance testing system for high and low temperature cycling tests; the performance testing system includes multiple devices under test placed inside a high and low temperature chamber, each device under test corresponding to an independent power supply channel and performance testing channel; the method includes: Upon detecting that the high and low temperature chamber has started operation, all the performance test channels are automatically triggered, and each of the performance test channels performs high and low temperature power-on and power-off cycle tests based on its own preset cycle test parameters; An anomaly level is determined for the first performance test channel where an anomaly is detected, and the decision to continue or stop the cyclic test for the first performance test channel is made based on the anomaly level determination result. The entire cyclic test process is terminated when all the first performance test channels that continue to execute the cyclic test and the second performance test channels that have not encountered any abnormalities have completed their respective power-on and power-off cyclic tests. Based on the test results of this cyclical test process, a comprehensive test analysis report is generated.

2. The high and low temperature cycling performance testing method according to claim 1, characterized in that, The performance testing system also includes a visualization terminal and a monitoring module; the monitoring module includes a video acquisition device and a time point monitoring module installed outside the high and low temperature chamber. Each of the devices under test also corresponds to an independent serial port log acquisition channel and an anomaly locking module; the method further includes: When all the performance test channels are automatically triggered, the display interface of the visualization terminal, the video acquisition device, the time point monitoring module, the serial port log acquisition channel and the anomaly locking module corresponding to each of the devices under test are simultaneously triggered and started. During the loop test: The video acquisition device records the test process video stream of all the tested equipment inside the high and low temperature chamber in real time. The time point monitoring module records the time point information corresponding to the video stream of the test process in real time. For each device under test, the SOC serial port log information of the device under test is collected and output in real time through the serial port log acquisition channel, and the abnormal situation of the device under test is monitored in real time through the anomaly locking module. The display interface of the visualization terminal displays the test status of each performance test channel and the SOC serial port log information of each device under test in real time.

3. The high and low temperature cycling performance testing method according to claim 2, characterized in that, The step of determining the anomaly level of the first performance test channel where an anomaly is detected, and determining whether the first performance test channel should continue or stop executing the cyclic test based on the anomaly level determination result, includes: The device under test that is detected to be abnormal in real time by the abnormal locking module is identified as the abnormal device under test, and the performance test channel of the abnormal device under test is identified as the first performance test channel. The first performance test channel is assessed for anomaly level based on a preset anomaly level to determine the anomaly level of the first performance test channel. When the anomaly level is the first level of anomaly, the first performance test channel continues to execute subsequent loop tests. When the anomaly level is the second level of anomaly, the first performance test channel maintains the current test state and stops executing subsequent loop tests.

4. The high and low temperature cycling performance testing method according to claim 3, characterized in that, The first level of anomaly corresponds to the following abnormal situations: the device under test is currently operating normally, its core functions, communication, and control logic are not malfunctioning, and the device under test exhibits non-critical phenomena; these non-critical phenomena include no change in status indicator lights and incomplete logs. The second level of anomaly corresponds to the following abnormal situations: the core functions of the device under test fail, its critical business, control, communication, and sampling functions cannot function normally, and the device under test exhibits obvious fault phenomena; these obvious fault phenomena include inability to start, automatic restart, system crash, and component overheating.

5. The high and low temperature cycling performance testing method according to claim 2, characterized in that, Based on the test results of this cyclical test process, a comprehensive test analysis report is generated, including: The test process video streams and time points of all devices under test in this cyclic test process are summarized, along with the complete SOC serial port log information, test pass rate and anomaly statistics of each device under test, to generate a comprehensive test analysis report for the entire process.

6. The high and low temperature cycling performance testing method according to any one of claims 2 to 5, characterized in that, The performance testing system also includes a temperature acquisition module placed inside a high and low temperature chamber; the method further includes: During the cyclic test, the actual internal temperature of the high and low temperature chamber is collected in real time by the temperature acquisition module, and the actual internal temperature is compared with the preset internal temperature. When the temperature deviation between the actual internal temperature and the preset chamber temperature exceeds the preset temperature difference threshold, the cyclic testing of all performance test channels is immediately stopped, and an alarm prompt window for abnormal temperature field pops up on the display interface of the visualization terminal, and the temperature deviation value between the actual internal temperature and the preset chamber temperature is displayed simultaneously in the alarm prompt window.

7. The high and low temperature cycling performance testing method according to any one of claims 2 to 5, characterized in that, Also includes: The visualization terminal receives the cyclic test parameters input by the user for each of the devices under test through its display interface, and completes the parameter settings for the devices under test based on the cyclic test parameters. Save all parameter settings of the device under test, trigger the preliminary test mode to perform preliminary verification of the performance test system, and enter the test preparation state after the preliminary verification is completed.

8. A high and low temperature cycling performance testing device, characterized in that, A performance testing system for high and low temperature cycling tests; the performance testing system includes multiple devices under test placed inside a high and low temperature chamber, each device under test corresponding to an independent power supply channel and performance testing channel; the device includes: The cyclic test execution unit is used to detect the start-up of the high and low temperature chamber and automatically trigger all the performance test channels. Each of the performance test channels performs high and low temperature power-on and power-off cyclic tests based on its own preset cyclic test parameters. The test anomaly handling unit is used to determine the anomaly level of the first performance test channel that has detected an anomaly, and to determine whether the first performance test channel should continue or stop executing the loop test based on the anomaly level determination result. The loop test termination unit is used to terminate the entire loop test process when all the first performance test channels that continued to execute the loop test and the second performance test channels that did not encounter any abnormalities have completed their respective power-on and power-off loop tests. The analysis report generation unit is used to generate a comprehensive test analysis report based on the test results of this test cycle.

9. An electronic device, characterized in that, The device includes a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the high and low temperature cycling performance testing method according to any one of claims 1-7 according to the instructions in the program code.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store program code for executing the high and low temperature cycling performance testing method according to any one of claims 1-7.

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