A method for rapidly evaluating dynamic resistance characteristics of GaN HEMT

Abstract

The application discloses a kind of fast evaluation test methods of GaN HEMT dynamic resistance characteristics, and the initial basic electrical parameter before stress is applied to the device to be tested is obtained by extracting experiment;Through the stress experiment, the gate-drain access area trap and buffer layer trap that lead GaN HEMT dynamic resistance characteristics degradation are applied controllable stress;By comparing the change amount of basic electrical parameter, drain current and on-resistance before and after stress is applied to the device to be tested, and combining the failure judgment standard set, the fast evaluation of GaN HEMT dynamic resistance characteristics is realized.The application significantly improves the test efficiency of GaN HEMT dynamic reliability evaluation, and can efficiently complete the fast evaluation of device dynamic on-resistance degradation in a short time, and does not need complex test platform construction and experimental condition design, simplifies the complicated procedure required for evaluating HEMT dynamic resistance characteristics, and is suitable for fast screening and dynamic reliability evaluation of device in engineering.

Description

Technical Field

[0001] This invention relates to the field of electrical characteristic testing technology for power semiconductor devices, and in particular to a rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMTs. Background Technology

[0002] With the ever-increasing demands for high frequency, high efficiency, and high power density in power electronic systems, gallium nitride high electron mobility transistors (GaN HEMTs) have become a research hotspot for next-generation power devices due to their wide bandgap, high critical breakdown electric field, and excellent electron mobility. However, in practical high-speed switching applications, the dynamic on-resistance degradation problem, dominated by buffer layer and gate-drain access region traps, has consistently hindered the further promotion and application of GaN HEMTs in high-reliability fields.

[0003] Currently, the testing methods for the dynamic reliability of GaN HEMTs are mainly divided into two categories: one is dynamic high-temperature operating life testing. Although this method has been certified by JEDEC, its testing cycle is long, the equipment is complex, and the testing conditions adopted by different manufacturers are different, making it difficult to unify; the other is hard switching testing based on double pulse testing. This method can simulate the actual switching transients of the device, but its test results are greatly affected by circuit parasitic parameters, and it is difficult to distinguish the contribution of traps in different regions.

[0004] Because the mechanisms by which traps in the under-gate, gate-drain access region, and buffer layer of GaN HEMTs affect the dynamic characteristics of the device differ, a single testing method cannot fully characterize the response of traps in each region. Therefore, designing a testing method that can efficiently excite and distinguish the trap effects in different regions and quickly evaluate the dynamic on-resistance degradation behavior has become an urgent technical problem to be solved in the field of GaN HEMT dynamic reliability. Summary of the Invention

[0005] This invention provides a rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMTs, overcoming the technical problem of imperfect dynamic on-resistance evaluation in current GaNHEMT industrial testing and practical applications.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: A rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMTs, comprising the following steps: The initial basic electrical parameters of the device under test before stress is applied are obtained by extraction experiments, which include gate current voltage testing and on-resistance testing. The basic electrical parameters include threshold voltage, linear region on-resistance, and saturation region on-resistance; The stress experiment applies controllable stress to the gate-drain access region traps and buffer layer traps that dominate the dynamic resistance characteristics degradation of GaN HEMTs. The response of the gate-drain access region traps to stress is quantified by measuring the change in drain current before and after stress is applied to the device under test. The response of the buffer layer traps to stress is quantified by extracting the change in on-resistance before and after stress is applied to the device under test. The stress test includes drain current and voltage testing and off-state drain voltage prestress testing; The basic electrical parameters of the device under test after stress were applied were obtained through extraction experiments. By comparing the changes in basic electrical parameters, drain current, and on-resistance of the device under test before and after stress is applied, and in conjunction with the established failure judgment criteria, the dynamic resistance characteristics of GaN HEMTs can be rapidly evaluated.

[0007] Furthermore, the gate current and voltage test involves linearly scanning the gate voltage at a preset drain voltage to obtain the threshold voltage of the device under test. The on-resistance test includes linear region on-resistance test and saturation region on-resistance test, which are measured under preset low leakage voltage and high leakage voltage conditions, respectively.

[0008] Furthermore, the drain current and voltage test is performed under the condition of fixed gate voltage and linear scan of drain voltage, so as to apply controllable stress to the gate-drain access region trap; The off-state leakage voltage pre-stress test includes applying a preset high voltage for a predetermined time under off-state conditions to apply controllable stress to the buffer layer trap; and the off-state leakage voltage pre-stress test also includes extracting the change in on-resistance of the device under test before and after applying stress through pulse current and voltage testing. The pulse current-voltage test uses a low duty cycle pulse signal to eliminate the influence of static stress on the on-resistance measurement and is used to extract the change in on-resistance before and after stress is applied.

[0009] Furthermore, the specific steps for rapid evaluation of the dynamic resistance characteristics of GaN HEMT based on the extraction and stress experiments include: Phase 1: The first round of gate current and voltage tests and the first round of on-resistance tests were performed sequentially to obtain the initial basic electrical parameters; The first round of drain current and voltage test and the first round of off-state drain voltage pre-stress test were performed sequentially to obtain the changes in drain current and on-resistance before and after stress was applied to the device under test. Phase Two: The second round of gate current and voltage testing and the second round of on-resistance testing were performed sequentially to obtain the basic electrical parameters of the device under test after stress was applied. The second round of drain current and voltage test and the second round of off-state drain voltage pre-stress test were performed sequentially to obtain the changes in drain current and on-resistance before and after stress was applied to the device under test. Phase Three: The third round of gate current and voltage testing and the third round of on-resistance testing were performed sequentially to obtain the basic electrical parameters after the second stress application.

[0010] Furthermore, the failure judgment criteria include preset threshold voltage change threshold, saturation region on-resistance change threshold, linear region on-resistance change threshold, and drain current change threshold. When the change of any parameter exceeds the corresponding threshold, the dynamic resistance characteristic of the device is determined to be unqualified.

[0011] Beneficial Effects: This invention, through a combination of extraction and stress experiments, applies controllable stress to the two major trap distribution regions affecting the dynamic on-resistance of GaN HEMTs: the gate-drain access region and the buffer layer. The changes in electrical parameters before and after stress application rapidly characterize the trap characteristics of the device, and this feedback serves as the basis for judging the dynamic resistance characteristics of the GaN HEMT. Compared with traditional dynamic high-temperature operating life testing or hard-switching testing, this invention significantly improves the testing efficiency of GaN HEMT dynamic reliability assessment. It can efficiently complete the rapid assessment of device dynamic on-resistance degradation in a short time, without requiring complex test platform construction and experimental condition design, simplifying the cumbersome procedures originally required for evaluating HEMT dynamic resistance characteristics. It is suitable for rapid device screening and dynamic reliability assessment in engineering applications. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMT in this invention. Figure 2 This is a schematic diagram of the test circuit for a rapid evaluation test method of the dynamic resistance characteristics of GaN HEMT in an embodiment of the present invention. Figure 3 This is a threshold voltage characteristic curve of the device under test extracted from the Id-Vg test in the embodiment of the present invention; Figure 4This is a graph showing the on-resistance characteristic of the device under test extracted from the Ron test, a sub-item of the present invention. Figure 5 This is a characteristic curve of the gate-drain access region trap of the device under test extracted from the Id-Vd test of the test sub-item in this embodiment of the invention; Figure 6 This is a pulse IV test curve of the VOFF-D test sub-item in an embodiment of the present invention. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This embodiment provides a rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMTs, such as... Figure 1 As shown, it specifically includes: The initial basic electrical parameters of the device under test before stress is applied are obtained by extraction experiments, which include gate current voltage testing and on-resistance testing. The basic electrical parameters include threshold voltage, linear region on-resistance, and saturation region on-resistance; The stress experiment applies controllable stress to the gate-drain access region traps and buffer layer traps that dominate the dynamic resistance characteristics degradation of GaN HEMTs. The response of the gate-drain access region traps to stress is quantified by measuring the change in drain current before and after stress is applied to the device under test. The response of the buffer layer traps to stress is quantified by extracting the change in on-resistance before and after stress is applied to the device under test. The stress test includes drain current and voltage testing and off-state drain voltage prestress testing; The basic electrical parameters of the device under test after stress were applied were obtained through extraction experiments. By comparing the changes in basic electrical parameters, drain current, and on-resistance of the device under test before and after stress is applied, and in conjunction with the established failure judgment criteria, the dynamic resistance characteristics of GaN HEMTs can be rapidly evaluated.

[0016] Specifically, the changes in the threshold voltage, linear region on-resistance, and saturation region on-resistance of GaN HEMT obtained from the experiment before and after stress application can reflect the response characteristics of the traps in the region below the gate and the gate-drain access region, respectively. The stress experiment utilizes the hot electron effect under the semi-conducting condition and the virtual back gate effect under the off-state high-voltage pre-stress condition to controllably fill the traps in the gate-drain access region and the buffer layer traps, effectively stimulating the response of traps in different regions.

[0017] In a specific embodiment, the gate current voltage test is performed by linearly scanning the gate voltage under a preset drain voltage to obtain the threshold voltage of the device under test; The on-resistance test includes linear region on-resistance test and saturation region on-resistance test, which are measured under preset low leakage voltage and high leakage voltage conditions, respectively.

[0018] In a specific embodiment, the drain current-voltage test is performed under the condition of fixed gate voltage and linear scanning of drain voltage, so as to apply controllable stress to the gate-drain access region trap; The off-state leakage voltage pre-stress test includes applying a preset high voltage for a predetermined time under off-state conditions to apply controllable stress to the buffer layer trap; and the off-state leakage voltage pre-stress test also includes extracting the change in on-resistance of the device under test before and after applying stress through pulse current and voltage testing. The pulse current-voltage test uses a low duty cycle pulse signal to eliminate the influence of static stress on the on-resistance measurement and is used to extract the change in on-resistance before and after stress is applied.

[0019] In a specific embodiment, The specific steps for rapid evaluation of the dynamic resistance characteristics of GaN HEMTs based on the extraction and stress experiments include: Phase 1: The first round of gate current and voltage tests and the first round of on-resistance tests were performed sequentially to obtain the initial basic electrical parameters; The first round of drain current and voltage test and the first round of off-state drain voltage pre-stress test were performed sequentially to obtain the changes in drain current and on-resistance before and after stress was applied to the device under test. Phase Two: The second round of gate current and voltage testing and the second round of on-resistance testing were performed sequentially to obtain the basic electrical parameters of the device under test after stress was applied. The second round of drain current and voltage test and the second round of off-state drain voltage pre-stress test were performed sequentially to obtain the changes in drain current and on-resistance before and after stress was applied to the device under test. Phase Three: The third round of gate current and voltage testing and the third round of on-resistance testing were performed sequentially to obtain the basic electrical parameters after the second stress application.

[0020] Specifically, the combined design of extraction and stress experiments proposed in this embodiment is based on an in-depth study of the distribution law of trap effect regions in GaN HEMT: the influence mechanism of traps under the gate, in the gate-drain access region, and in the buffer layer on the dynamic characteristics of the device is different. A single test cannot fully characterize the trap response of each region. By combining extraction and stress experiments in sequence, the contribution of traps in different regions can be distinguished by the change in electrical parameters before and after applying stress to the device under test. This enables a rapid assessment of dynamic on-resistance degradation.

[0021] Specifically, the implementation scheme and theoretical basis of the rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMT proposed in this embodiment are as follows: The testing scheme includes two parts: extraction experiments and stress experiments. The extraction experiments include Id-Vg tests and Ron tests to obtain the basic electrical parameters of the device before and after stress; the stress experiments include Id-Vd tests and VOFF-D tests to controllably fill traps in different regions. By comparing the changes in electrical parameters before and after stress, the rapid characterization of the device's dynamic on-resistance degradation behavior is achieved.

[0022] Specifically, the experimental principle of this embodiment is as follows: The Id-Vg test is used to extract the threshold voltage of the device under test. By measuring the change in the threshold voltage before and after stress is applied, it reflects the charge trapping state of the trap under the gate. The charge trapping of the trap under the gate will directly change the gate's control over the channel, which is manifested as threshold voltage drift. Since threshold voltage drift will cause the dynamic on-resistance of HEMT to degrade, this parameter can be used to help verify the conclusions of HEMT on-resistance characteristics obtained by Ron test. Ron testing is used to extract the on-resistance of a device. By measuring the changes in on-resistance in the linear and saturation regions before and after stress application, it distinguishes the influence of traps in different regions on the device's conduction characteristics. The change in on-resistance in the linear region is mainly affected by the threshold voltage drift, while the change in on-resistance in the saturation region reflects the depletion effect of traps in the gate-drain access region and buffer layer traps on channel carriers. In other words, it reflects the dynamic on-resistance characteristic degradation caused by the two stress tests, Id-Vd and VOFF-D, on the HEMT. The Id-Vd test is used to evaluate the response characteristics of the gate-drain access region trap. By using a bias condition combining semi-conduction and a moderate drain voltage, the hot electron effect that dominates the degradation of the gate-drain access region trap is controlled, reducing the possibility of threshold voltage drift caused by this effect. At the same time, some hot electrons escape from the two-dimensional electron gas channel and are captured by the gate-drain access region trap. The response degree of the gate-drain access region trap is quantified by measuring the change in drain current before and after stress is applied to the device under test. VOFF-D testing is used to evaluate the response characteristics of buffer layer traps. By using a prestress condition with off-state high voltage bias, the acceptor traps in the buffer layer are charged and ionized, forming a virtual back grid that depletes the two-dimensional electron gas channel. The change in on-resistance after stress is applied is extracted by pulse IV testing to quantify the response of the buffer layer traps. The test circuit required for the rapid evaluation and testing method of GaN HEMT dynamic resistance characteristics proposed in this embodiment is as follows: Figure 2 As shown in the figure, VG is the gate voltage source, Rg is the gate drive circuit, DZ is the Zener diode, DUT is the device under test, R is the sampling resistor, and VD is the drain voltage source. Among them, the gate voltage source and drain voltage source are used to provide the stress conditions required for testing, Rg is used to suppress gate oscillation caused by power supply noise and limit the gate current during unexpected transient spikes, and DZ is used to limit the gate voltage to prevent it from exceeding the safe voltage range due to noise or transient overshoot voltage.

[0023] Table 1 shows the GaN HEMT chip selected in this embodiment and its typical parameters. Table 2 shows the sub-experiments and test conditions included in the rapid evaluation test method for the dynamic resistance characteristics of GaN HEMT proposed in this embodiment. The specific operation process of each sub-experiment is as follows: In the Id-Vg test, the gate and drain of the device under test are shorted to form a diode connection. The gate-source voltage scan range is set to 0 to 2V in 0.1V increments. The drain current is monitored. When the drain current reaches 10mA, the current gate-source voltage is recorded as the threshold voltage, and the gate voltage is stopped from being increased further to avoid applying unnecessary electrical stress to the traps distributed in the area below the gate. After the test, the device is annealed at room temperature for 10s to release any trap charges that may be introduced. The threshold voltage characteristic curve of GaN HEMT based on the data obtained from the Id-Vg test is shown in the figure below. Figure 3 As shown; in the Ron test, the gate voltage was scanned from 2V to 5V in 0.5V increments, and the drain current was set to a constant 3A. By measuring the drain-source voltage and calculating the on-resistance, the on-resistance in the linear region at a gate voltage of 2.5V and the on-resistance in the saturation region at a gate voltage of 5V were extracted as key parameters. The on-resistance characteristic curve of GaN HEMT, plotted based on the data obtained from the Ron test, is shown in the figure. Figure 4As shown; in the Id-Vd test, the source voltage was set to 0V and the gate voltage was fixed at 0.6V. The drain voltage was scanned stepwise from 0V to 60V in 10V increments, and the drain current at each voltage point was recorded. The drain current at Vd=60V was used as the characteristic parameter of the Id-Vd test. The GaN HEMT drain current characteristic curve plotted based on the Id-Vd test data is shown in the figure. Figure 5 As shown; In the VOFF-D test, the device is biased to the off state, and both the gate and source voltages are set to 0V. A 70V high-voltage stress is applied to the drain and maintained for 60s. Immediately after the stress ends, a pulse IV test is performed. A single pulse is applied with the gate voltage set to 2.5V and the drain voltage set to 0.5V. The drain current under this pulse is recorded, and the on-resistance ROD is calculated as a characteristic parameter of the VOFF-D test. The waveform captured by the oscilloscope during the pulse IV test phase of the VOFF-D test is shown in the figure. Figure 6 As shown.

[0024] Table 1. GaN HEMT chips selected in this invention and their typical parameters

[0025] Specifically, this embodiment preferably uses a 100V withstand voltage GaN HEMT chip for testing. In practice, the testing method proposed in this embodiment can also be extended to GaN HEMT chips with other withstand voltage ranges, including but not limited to 40V, 60V, 150V, 650V, and 700V GaN HEMT chips.

[0026] Table 2. Sub-items and test conditions included in the rapid evaluation test method for GaN HEMT dynamic resistance characteristics.

[0027] As shown in Table 3, the rapid evaluation test method for the dynamic resistance characteristics of GaN HEMT proposed in this embodiment is divided into three stages executed sequentially: The first stage begins with an Id-Vg-1 test to record the initial threshold voltage of the device. This is followed by a Ron-1 test to record the initial linear region on-resistance and saturation region on-resistance. Then, an Id-Vd-1 test is performed to record the drain current Id. Finally, a VOFF-D-1 test is performed to record the on-resistance ROD. After each Id-Vg test, a 10-second room temperature annealing step is set to release any trap charges that may have been introduced by the Id-Vg test. The second stage repeats the above test procedure, performing Id-Vg-2, Ron-2, Id-Vd-2 and VOFF-D-2 tests in sequence, recording the changes in each parameter after the first stress is applied. After this stage is completed, room temperature annealing is set for 60 seconds to allow the device to fully recover before entering the third stage. The third stage only involves Id-Vg-3 and Ron-3 tests, recording the threshold voltage and on-resistance after the second stress. By comparing the changes in each parameter in the three stages, a rapid assessment of the device's dynamic on-resistance degradation can be achieved.

[0028] Table 3. Test Procedure Steps for Rapid Evaluation of Dynamic Resistance Characteristics of GaN HEMTs

[0029] As shown in Table 4, this embodiment has established corresponding failure judgment criteria for the device under test, GAN3R2-100CBE. These criteria are based on the rated parameters provided in the official datasheet of the device and the reliability test data of the same type of device. The criteria are determined by extrapolation through conversion ratio. For other types or different specifications of GaN HEMT devices, the corresponding reference indicators can be adjusted proportionally by referring to their datasheet parameters and the experimental statistical results of similar devices, so that a suitable failure judgment criteria can be established.

[0030] Specifically, the failure judgment criteria include preset threshold voltage change threshold, saturation region on-resistance change threshold, linear region on-resistance change threshold, and drain current change threshold. When the change of any parameter exceeds the corresponding threshold, the dynamic resistance characteristics of the device are deemed unqualified.

[0031] Table 4. Data and failure criteria obtained from the rapid evaluation test method for dynamic resistance characteristics based on GAN3R2-100CBE.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fast evaluation of dynamic resistance characteristics of GaN HEMT, characterized in that, The specific steps include: The initial basic electrical parameters of the device under test before stress is applied are obtained by extraction experiments, which include gate current voltage testing and on-resistance testing. The basic electrical parameters include threshold voltage, linear region on-resistance, and saturation region on-resistance; The stress experiment applies controllable stress to the gate-drain access region traps and buffer layer traps that dominate the dynamic resistance characteristics degradation of GaN HEMTs. The response of the gate-drain access region traps to stress is quantified by measuring the change in drain current before and after stress is applied to the device under test. The response of the buffer layer traps to stress is quantified by extracting the change in on-resistance before and after stress is applied to the device under test. The stress test includes drain current and voltage testing and off-state drain voltage prestress testing; The basic electrical parameters of the device under test after stress were applied were obtained through extraction experiments. By comparing the changes in basic electrical parameters, drain current, and on-resistance of the device under test before and after stress is applied, and in conjunction with the established failure judgment criteria, the dynamic resistance characteristics of GaN HEMTs can be rapidly evaluated.

2. The rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMT according to claim 1, characterized in that, The gate current and voltage test involves linearly scanning the gate voltage under a preset drain voltage to obtain the threshold voltage of the device under test. The on-resistance test includes linear region on-resistance test and saturation region on-resistance test, which are measured under preset low leakage voltage and high leakage voltage conditions, respectively.

3. The rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMT according to claim 2, characterized in that, The drain current and voltage test is performed under the condition of fixed gate voltage and linear scan of drain voltage, so as to apply controllable stress to the gate-drain access region trap; The off-state leakage pressure prestress test includes applying a preset high pressure and continuing for a predetermined time under off-state conditions to apply controllable stress to the buffer layer trap; Furthermore, the off-state leakage voltage prestress test also includes extracting the change in on-resistance of the device under test before and after applying stress through pulse current and voltage testing; The pulse current-voltage test uses a low duty cycle pulse signal to eliminate the influence of static stress on the on-resistance measurement and is used to extract the change in on-resistance before and after stress is applied.

4. The rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMT according to claim 3, characterized in that, The specific steps for rapid evaluation of the dynamic resistance characteristics of GaN HEMTs based on the extraction and stress experiments include: Phase 1: The first round of gate current and voltage tests and the first round of on-resistance tests were performed sequentially to obtain the initial basic electrical parameters; The first round of drain current and voltage test and the first round of off-state drain voltage pre-stress test were performed sequentially to obtain the changes in drain current and on-resistance before and after stress was applied to the device under test. Phase Two: The second round of gate current and voltage testing and the second round of on-resistance testing were performed sequentially to obtain the basic electrical parameters of the device under test after stress was applied. The second round of drain current and voltage test and the second round of off-state drain voltage pre-stress test were performed sequentially to obtain the changes in drain current and on-resistance before and after stress was applied to the device under test. Phase Three: The third round of gate current and voltage testing and the third round of on-resistance testing were performed sequentially to obtain the basic electrical parameters after the second stress application.

5. The rapid evaluation and testing method for the dynamic resistance characteristics of GaN HEMT according to claim 4, characterized in that, The failure judgment criteria include preset threshold voltage change threshold, saturation region on-resistance change threshold, linear region on-resistance change threshold, and drain current change threshold. When the change of any parameter exceeds the corresponding threshold, the dynamic resistance characteristic of the device is determined to be unqualified.

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