GTM module-based timing signal generation method, device and system

Abstract

The application relates to the technical field of integrated circuit design, and discloses a timing signal generation method, device and system based on a GTM module, wherein the timing signal generation method comprises the following steps: initializing the GTM module; compiling target program code for generating a timing signal according to an external communication protocol; loading the target program code into a program space of a multi-channel sequencer of the GTM module; and controlling the GTM module to run the target program code in the program space, so that the GTM module outputs a timing signal of the external communication protocol. The target program code for generating the timing signal is loaded into the program space of the multi-channel sequencer of the GTM module, the calculation of generating the timing signal and the processing task of the external communication protocol are realized in the GTM module, thereby a large amount of tasks originally borne by a CPU in the related art are transferred to the GTM module, and the calculation pressure of the CPU in the timing signal generation process is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and for example to a method, apparatus and system for generating timing signals based on a GTM module. Background Technology

[0002] With the rapid development and continuous iteration of automotive electronics technology, the electronic devices and functions involved in automotive control systems are becoming increasingly complex. Modern automobiles not only involve interaction with external devices such as onboard controllers, sensors, and actuators, but also require more efficient computing and control capabilities. These complex systems demand that control chips be able to communicate with a large number of external devices at high speed and reliably, while also requiring the CPU (Central Processing Unit) to undertake increasingly more computational tasks. Furthermore, timing signal generation is a crucial step in integrated circuit design to verify the correctness and performance of digital circuit designs.

[0003] In related technologies, a timing signal generation method is disclosed, comprising: the CPU initiating a transmission, wherein the transmission includes multiple commands; the connection between multiple commands in the command sequence is achieved through a transmission completion interrupt; when a command is transmitted, a transmission completion interrupt is triggered; in the transmission completion interrupt, the next command to be sent is prepared and sent; that is, each action of controlling peripheral devices will enter the transmission completion interrupt multiple times. If the peripheral device needs to detect the status information of the I / O (Input / Output) port before it can send and receive data, the I / O port interrupt needs to be added.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] In related technologies, timing signal generation methods require the CPU to perform multiple command transmissions, which can lead to excessive CPU utilization.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a method, apparatus, and system for generating timing signals based on a GTM (General Timer Module) module, in order to reduce the computational burden on the CPU during the timing signal generation process.

[0009] In some embodiments, a timing signal generation system based on a GTM module includes: a master device configured to initialize a GTM module; write target program code for timing signal generation according to an external communication protocol; load the target program code into the program space of the multi-channel sequencer of the GTM module; control the GTM module to run the target program code in the program space; and a GTM module, located on the master device, configured to run the target program code in the program space in response to control commands from the master device, and output timing signals of the external communication protocol.

[0010] Optionally, the GTM module includes: a clock management unit configured to generate all clocks and counters for the GTM module; a time base unit connected to the clock management unit configured to generate a common time base for the GTM module; a multi-channel sequencer connected to the time base unit configured to control the output and input data of the GTM module; an advanced routing unit connected to the multi-channel sequencer configured to generate complex output waveforms according to the instructions of the multi-channel sequencer; a timer output module connected to the advanced routing unit configured to output timing signals according to the complex output waveforms; a timer input module connected to the advanced routing unit configured to capture input signals; and a random access memory connected to the multi-channel sequencer configured to store target program code and interact with the multi-channel sequencer.

[0011] In some embodiments, the timing signal generation method based on the GTM module includes: initializing the GTM module; writing target program code for timing signal generation according to an external communication protocol; loading the target program code into the program space of the multi-channel sequencer of the GTM module; and controlling the GTM module to run the target program code in the program space so that the GTM module outputs timing signals of the external communication protocol.

[0012] Optionally, the GTM module is initialized, including: initializing the clock and counter output by the clock divider in the clock management unit; initializing the resolution and accuracy of the time base in the time base unit; resetting the multi-channel sequencer; initializing the routing table of the advanced routing unit; configuring the timer output module to signal immediate output mode; configuring the timer input module to timer input event mode; and initializing the stored data in the random access memory.

[0013] Optionally, loading the target program code includes: compiling and linking the target program code to generate an array in C language format; and moving the array in C language format into the program space of the multichannel sequencer to load the target program code.

[0014] Optionally, moving the C-formatted array into the program space of the multichannel sequencer includes: calculating the total length of the array; calculating the target address corresponding to each unit length of the array in the program space and converting the target address into a pointer; and writing the value of each unit length in the array to the corresponding target address based on the pointer to the target address.

[0015] Optionally, the external communication protocol includes the SPI (Serial Peripheral Interface) communication protocol; the timing signals of the SPI communication protocol include slave device select signal, clock signal, and master device transmit signal.

[0016] Optionally, the timing signal generation method further includes: after the GTM module outputs the timing signal of the external communication protocol, performing data interaction with the slave device based on the timing signal.

[0017] Optionally, data interaction with the slave device is achieved based on timing signals, including: selecting the slave device for communication based on the slave device selection signal in the timing signals; sending data bit by bit to the slave device and receiving the data sent by the slave device bit by bit based on the clock signal in the timing signals; and ending communication with the slave device after all data transmission and reception are completed, thus completing the data interaction with the slave device.

[0018] Optionally, the timing signal generation method further includes: performing result calculation based on the multi-channel sequencer in the GTM module during the timing signal generation process and the data interaction process with the slave device; the result calculation includes CRC check value calculation, data encryption, and data decryption.

[0019] In some embodiments, the timing signal generation apparatus based on the GTM module includes a processor and a memory storing program instructions, the processor being configured to execute the timing signal generation method based on the GTM module as described above when the program instructions are executed.

[0020] The timing signal generation method, apparatus, and system based on the GTM module provided in this disclosure can achieve the following technical effects:

[0021] In this embodiment, the target program code for generating timing signals is loaded into the program space of the multi-channel sequencer of the GTM module. This enables the calculation of timing signal generation and the processing of external communication protocols to be performed within the GTM module. This transfers a large number of tasks originally handled by the CPU to the GTM module, reducing the CPU's burden and computational pressure during timing signal generation. Furthermore, the GTM module provides high-precision timing functionality, accurately controlling the generation of timing signals and improving the accuracy and efficiency of timing signal generation.

[0022] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0024] Figure 1 This is a schematic diagram of a timing signal generation system based on a GTM module provided in an embodiment of this disclosure;

[0025] Figure 2 This is a schematic diagram of a GTM module provided in an embodiment of this disclosure;

[0026] Figure 3 This is a schematic diagram of a timing signal generation method based on a GTM module provided in an embodiment of this disclosure;

[0027] Figure 4 This is a schematic diagram of another timing signal generation method based on a GTM module provided in this embodiment of the present disclosure;

[0028] Figure 5 This is a waveform diagram of SPI communication protocol data interaction between a master device and a slave device based on timing signals generated by a GTM module, provided in an embodiment of this disclosure.

[0029] Figure 6 This is a schematic diagram of a timing signal generation device based on a GTM module provided in an embodiment of this disclosure. Detailed Implementation

[0030] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0031] The terms "first," "second," etc., used in the technical solutions described in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0032] Unless otherwise stated, the term "multiple" means two or more.

[0033] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0034] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0035] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0036] Combination Figure 1 As shown, this disclosure provides a timing signal generation system based on a GTM module, including a master device 10 and a GTM module 20. The master device 10 is configured to initialize the GTM module 20; write target program code for timing signal generation according to an external communication protocol; load the target program code into the program space of the multi-channel sequencer of the GTM module 20; and control the GTM module 20 to run the target program code in the program space. The GTM module 20 is located on the master device and is configured to respond to the control commands of the master device, run the target program code in the program space, and output timing signals of the external communication protocol.

[0037] In this embodiment, the main device 10 writes target program code for generating timing signals and loads the target program code into the program space of the multi-channel sequencer in the GTM module 20. This enables the calculation of timing signal generation and the processing of external communication protocols to be performed within the GTM module 20. This transfers a large number of tasks originally handled by the CPU to the GTM module 20, reducing the burden on the CPU in the main device and lowering the computational pressure on the CPU during timing signal generation. Furthermore, the GTM module 20 provides high-precision timing functionality, accurately controlling the generation of timing signals and improving the accuracy and efficiency of timing signal generation.

[0038] Optionally, combined Figure 2 As shown, the GTM module includes: a clock management unit 21, a time base unit 22, a multi-channel sequencer 23, an advanced routing unit 24, a timer output module 25, a timer input module 26, and a random access memory 27. The clock management unit 21 is configured to generate all clocks and counters for the GTM module. The time base unit 22 is connected to the clock management unit 21 and is configured to generate a common time base for the GTM module. The multi-channel sequencer 23 is connected to the time base unit 22 and is configured to control the output and input data of the GTM module. The advanced routing unit 24 is connected to the multi-channel sequencer 23 and is configured to generate complex output waveforms according to the instructions of the multi-channel sequencer 23. The timer output module 25 is connected to the advanced routing unit 24 and is configured to output timing signals according to the complex output waveforms. The timer input module 26 is connected to the advanced routing unit 24 and is configured to capture input signals. The random access memory 27 is connected to the multi-channel sequencer 23 and is configured to store the target program code and interact with the multi-channel sequencer 23.

[0039] Optionally, the GTM module also includes an energy-saving module 28. The energy-saving module 28 is connected to the advanced routing unit 24. The energy-saving module 28 optimizes the power consumption of the GTM module, minimizing energy consumption without sacrificing performance. The energy-saving module 28 reduces unnecessary energy consumption by placing the GTM module in a low-power state. When the timing signal generation function is not used, the GTM module automatically enters a power-saving mode to save power. Reducing the power consumption of the GTM module hardware helps extend the lifespan of the device, especially in battery-powered applications.

[0040] Optionally, the Clock Management Unit (CMU) obtains clock signals from the chip-level clock control system and adjusts the clock speed as needed to generate all clocks and counters for the GTM module. The CMU can select one of multiple clock sources as the clock input for the GTM module, divide the selected clock source to generate clock signals suitable for the operation of the GTM module and other sub-modules, control the start and stop of the clock, ensure that clock signals are provided when needed, and save power when not needed.

[0041] Optionally, the TimeBase Unit (TBU) is responsible for providing the global timebase signal for the GTM module.

[0042] Alternatively, a multi-channel sequencer (MCS) allows programs to compute complex output sequences that depend on a time base value.

[0043] Optionally, the Advanced Routing Unit (ARU) provides a mechanism for routing data streams between data sources and transmitting them to their destination. The ARU is the core of the GTM module and can generate complex output waveforms according to the instructions of the MCS.

[0044] Optionally, the ARU-connected Timer Output Module (ATOM) can generate complex output signals through interconnection with the ARU and other modules.

[0045] Optionally, a Timer Input Module (TIM) is used to capture signal input.

[0046] Optionally, the Random Access Memory (RAM) includes RAM0 with a storage space of 16K and RAM1 with a storage space of 8K. RAM0 stores the MCS's operating program and data, which are actively copied from FLASH to RAM0 by the host device. RAM1 stores communication data between the host device and the MCS; RAM1 serves as shared memory between the host device and the MCS.

[0047] Optionally, a memory region can be mapped to the communication interface between the master device and the GTM module through shared memory, enabling data sharing and access between the master device and the GTM module; or, data interaction between the master device and the GTM module can be achieved through a hardware FIFO (First In First Out) queue.

[0048] This embodiment provides two methods for data interaction between the master device and the GTM module to ensure data reliability and real-time performance. For the shared memory method, both the master device and the GTM module are configured to access the same memory region, i.e., shared memory. This shared memory can store data or control information. The master device writes data, such as timing configurations and peripheral instructions, to the shared memory, while the GTM module reads this data from the shared memory for timing simulation or processing. Similarly, the GTM module can write simulation results, status, or response information back to the shared memory for the master device to read. Because the memory is shared, both parties can exchange data quickly and efficiently, reducing additional communication overhead. For the hardware FIFO queue, data is transmitted in a first-in, first-out order through the FIFO queue. The master device writes data to the FIFO queue, and the GTM module reads data from the FIFO queue for timing signal generation or peripheral drive operations. The FIFO queue is implemented in hardware and is typically a deep buffer that can hold multiple data items. The design of the FIFO queue ensures that data exchange is not affected by the different processing speeds of the master device and the GTM module. Even if the main device has a fast processing speed, and the GTM module may need more time for timing simulation, the FIFO queue can still effectively buffer data and avoid data loss.

[0049] Combination Figure 3 As shown, this disclosure provides a timing signal generation method based on a GTM module. The execution subject of this timing signal generation method can be a master device, and the timing signal generation method includes:

[0050] S301, the master device initializes the GTM module.

[0051] S302, the master device writes target program code for generating timing signals according to the external communication protocol.

[0052] S303, the master device loads the target program code into the program space of the multichannel sequencer of the GTM module.

[0053] S304, the master device controls the GTM module to run the target program code in the program space so that the GTM module outputs the timing signal of the external communication protocol.

[0054] In this embodiment, the target program code for generating timing signals is loaded into the program space of the multi-channel sequencer of the GTM module. This enables the calculation of timing signal generation and the processing of external communication protocols to be performed within the GTM module. This transfers a large number of tasks originally handled by the CPU to the GTM module, reducing the CPU's burden and computational pressure during timing signal generation. Furthermore, the GTM module provides high-precision timing functionality, accurately controlling the generation of timing signals and improving the accuracy and efficiency of timing signal generation.

[0055] Optionally, the GTM module is initialized, including: initializing the clock and counter output by the clock divider in the clock management unit; initializing the resolution and accuracy of the time base in the time base unit; resetting the multi-channel sequencer; initializing the routing table of the advanced routing unit; configuring the timer output module to signal immediate output mode; configuring the timer input module to timer input event mode; and initializing the stored data in the random access memory.

[0056] In this embodiment, initializing each submodule of the GTM module ensures that the GTM module is in a known and stable state upon startup. This helps reduce system complexity, minimizes errors and malfunctions caused by improper initialization, and thus improves the overall reliability of the system.

[0057] Optionally, initializing the clock and counter output by the clock divider in the clock management unit includes: clearing the current value register of the clock divider to enable the clock divider to start working from the initial state; setting the division value of the clock divider according to system requirements; and clearing the counter in the clock management unit to enable the counter to start counting from 0.

[0058] Optionally, initializing the resolution and precision of the time base in the time base unit includes: clearing the resolution register and precision register of the time base unit to zero; and setting the resolution and precision of the time base according to system requirements.

[0059] Optionally, resetting the multichannel sequencer includes: writing a reset command to the reset register of the multichannel sequencer to restore the multichannel sequencer to its initial state; and clearing the status register of the multichannel sequencer to zero, so that the state of the sequencer starts from the initial state.

[0060] Optionally, initializing the routing table of the advanced routing unit includes: clearing the routing table of the advanced routing unit to zero, so that the routing table starts from the initial state; and writing the routing relationship of the signal into the routing table according to system requirements.

[0061] Optionally, configuring the timer output module to an immediate signal output mode includes configuring the mode register of the timer output module to an immediate signal output mode.

[0062] Optionally, configuring the timer input module to timer input event mode includes configuring the mode register of the timer input module to timer input event mode.

[0063] Optionally, initializing the stored data in the random access memory includes: clearing the stored data in the random access memory to zero, so that the memory starts from the initial state; and writing the initial data into the corresponding location of the random access memory according to the initial data preset by the system.

[0064] Optionally, the timer output module can be configured to Signal Immediate Output (SOMI) mode, which allows the ATOM channel to immediately generate an output signal when the zeroth bit of the output signal field is updated when the ARU is enabled. This reduces signal latency and improves the response speed of the GTM module.

[0065] Optionally, the MCS channel controls the ATOM channel by sending a high or low level signal to the ATOM channel. When the ATOM channel is configured with a level signal of zero, a low level is output on the I / O port; when the ATOM channel is configured with a level signal of 1, a high level is output on the I / O port.

[0066] Optionally, after configuring the timer input module to timer input event mode, the IO status can be obtained through registers.

[0067] Optionally, the master device enables or disables the MCS program by writing register values. Specifically, when the register value is 0, the MCS program is disabled; when the register value is 1, the MCS program is enabled.

[0068] Optionally, the master device resets the MCS via registers, including all general-purpose registers and the PC value. A register value of 0 indicates the register is invalid. A register value of 1 indicates the MCS is reset.

[0069] Optionally, loading the target program code into the program space of the multichannel sequencer of the GTM module includes: compiling and linking the target program code to generate an array in C language format; and moving the array in C language format into the program space of the multichannel sequencer to load the target program code.

[0070] In this embodiment, a compiler such as Hightec can be used as the development platform for the target program code. The Hightec compiler compiles and links the target program code to generate a "C-Array," which is an array in C language format. This "C-Array" is added to a software development environment such as GHS and compiled and linked together with the CPU source code to generate an executable file. The host device can also move the C language array into the program space of the multichannel sequencer.

[0071] Optionally, moving the C-formatted array into the program space of the multichannel sequencer includes: calculating the total length of the array; calculating the target address corresponding to each unit length of the array in the program space and converting the target address into a pointer; and writing the value of each unit length in the array to the corresponding target address based on the pointer to the target address.

[0072] In this embodiment, for arrays in C language format, the total number of elements in the array, i.e., the total length of the array, is calculated by dividing the size of the entire array by the size of each element in the array. For each unit length of the array, i.e., each element of the array, the target address in the program space MCS RAM is calculated, and the calculated target address is converted into a pointer of type unsigned int. Finally, based on the pointer of the target address, the value of each unit length of the array is written to the corresponding target address, completing the array transfer.

[0073] Optionally, the external communication protocol includes the SPI communication protocol; the timing signals of the SPI communication protocol include a slave device select signal, a clock signal, and a master device transmit signal.

[0074] Optionally, the timing signal generation method further includes: after the GTM module outputs the timing signal of the external communication protocol, performing data interaction with the slave device based on the timing signal.

[0075] Combination Figure 4 As shown, this disclosure provides another method for generating timing signals based on a GTM module, including:

[0076] S401, the master device initializes the GTM module.

[0077] S402, the master device writes target program code for generating timing signals according to the external communication protocol.

[0078] S403, the master device loads the target program code into the program space of the multichannel sequencer of the GTM module.

[0079] S404, the master device controls the GTM module to run the target program code in the program space so that the GTM module outputs timing signals of the external communication protocol.

[0080] S405, the master device interacts with the slave device based on timing signals.

[0081] In this embodiment, the master device can interact with the slave device based on the timing signal generated by the GTM module.

[0082] Optionally, data interaction with the slave device is achieved based on timing signals, including: selecting the slave device for communication based on the slave device selection signal in the timing signals; sending data bit by bit to the slave device and receiving the data sent by the slave device bit by bit based on the clock signal in the timing signals; and ending communication with the slave device after all data transmission and reception are completed, thus completing the data interaction with the slave device.

[0083] In this embodiment, the master device selects the slave device for communication based on the slave device selection signal in the timing signal and then begins sending data to the slave device. First, the clock signal in the timing signal is initialized to a low level to prepare for sending and receiving one bit of data. When the master device sends data to the slave device, it sets its transmit signal MOSI to high or low based on the most significant bit of the data to be sent, txData. When the most significant bit is 1, MOSI is pulled high; when the most significant bit is 0, MOSI is pulled low. Then, txData is shifted left by one bit to prepare for sending the next bit of data. Next, the clock signal in the timing signal is pulled high to trigger data transmission, and the master device receives the data bit sent by the slave device through its transmit signal MISO, storing the received data bit in the received data rxData. Finally, the clock signal in the timing signal is pulled low to complete the data transmission of the current bit. Since each byte consists of 8 bits, 8 bit-by-bit data transmissions are required during each data transmission process. After all data transmissions are completed, communication with the slave device ends, rxData is returned, and the data interaction with the slave device is complete. In addition, the delay time during data transmission can be adjusted according to the clock requirements of the peripheral device.

[0084] Combination Figure 5The diagram shows a waveform of SPI communication protocol data interaction between a master device and a slave device based on timing signals generated by a GTM module, according to an embodiment of this disclosure. During the generation of timing signals for the SPI communication protocol, the timing signals need to consider the slave device select signal SPI-SCS, the clock signal SPI-SCLK, and the master device transmit signal SPI-MOSI. Therefore, the target program code used to generate the timing signals for the SPI communication protocol needs to be written around these three signals so that the target program code can correctly generate the timing signals for the SPI communication protocol. Furthermore, during the data interaction between the master device and the slave device using the SPI communication protocol, the master device will also receive the slave device transmit signal SPI-MISO returned by the slave device. For other communication protocols, the timing requirements of different communication protocols need to be considered, and the target program code needs to be written according to the key timing parameters of the communication protocol. For example, for the I2C communication protocol, the clock line SCL, data line SDA, start condition, and stop condition need to be considered; for the UART communication protocol, the baud rate, data bits, stop bits, and parity bits need to be considered. Based on the target program code corresponding to different communication protocols, the MCS of the GTM module can run the target program code, thereby generating timing signals for different communication protocols.

[0085] Optionally, during the generation of timing signals and the data interaction with slave devices, the result is calculated based on the multi-channel sequencer in the GTM module; the result calculation includes CRC check value calculation, data encryption, and data decryption.

[0086] In this embodiment, taking an 8-channel MCS in the GTM module as an example, for the SPI communication protocol, only 4 channels are used during the timing signal generation process and data interaction with the slave device: the slave device select signal SPI-SCS, the clock signal SPI-SCLK, the master device transmit signal SPI-MOSI, and the slave device transmit signal SPI-MISO. Therefore, unused channels in the MCS can be used for result calculation, enabling data verification and encryption / decryption during timing signal generation and data interaction, thus improving data security.

[0087] Combination Figure 6As shown, this disclosure provides a timing signal generation device 600 based on a GTM module, including a processor 601 and a memory 602. Optionally, the device may further include a communication interface 603 and a bus 604. The processor 601, communication interface 603, and memory 602 can communicate with each other via the bus 604. The communication interface 603 can be used for information transmission. The processor 601 can call logical instructions in the memory 602 to execute the timing signal generation method based on the GTM module described in the above embodiment.

[0088] Furthermore, the logic instructions in the aforementioned memory 602 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0089] The memory 602, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 601 executes functional applications and data processing by running the program instructions / modules stored in the memory 602, that is, it implements the timing signal generation method based on the GTM module in the above embodiments.

[0090] The memory 602 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 602 may include high-speed random access memory and may also include non-volatile memory.

[0091] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the aforementioned timing signal generation method based on a GTM module.

[0092] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.

[0093] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the technical solutions described herein. As used in the technical solutions described herein, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0095] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A method for generating time-series signals based on a GTM module, characterized in that, include: Initialize the GTM module; Write target program code for generating timing signals based on the external communication protocol; Load the target program code into the program space of the multichannel sequencer in the GTM module; Control the target program code within the program space of the GTM module to enable the GTM module to output timing signals of the external communication protocol.

2. The time-series signal generation method according to claim 1, characterized in that, The GTM module includes a clock management unit, a time base unit, a multi-channel sequencer, an advanced routing unit, a timer output module, a timer input module, and a random access memory. The time base unit is connected to the clock management unit, the multi-channel sequencer is connected to the time base unit, the advanced routing unit is connected to the multi-channel sequencer, the timer output module and the timer input module are both connected to the advanced routing unit, and the random access memory is connected to the multi-channel sequencer. Initialize the GTM module, including: Initialize the clock and counter outputs of the clock divider in the clock management unit; and, Initialize the resolution and accuracy of the time base in the initial time base cell; and, Reset the multichannel sequencer; and, Initialize the routing table of the high-level routing unit; and, Configure the timer output module to output signal immediately; and, Configure the timer input module to timer input event mode; and, Initialize the data stored in the random access memory.

3. The time-series signal generation method according to claim 1, characterized in that, Load the target program code into the program space of the multichannel sequencer of the GTM module, including: The target program code is compiled and linked to generate arrays in C language format; The C language format array is moved into the program space of the multichannel sequencer to load the target program code.

4. The timing signal generation method according to claim 3, characterized in that, Moving C-formatted arrays into the program space of the multichannel sequencer includes: Calculate the total length of the array; Calculate the target address in the program space corresponding to each unit length of the array, and convert the target address into a pointer; Based on the pointer to the target address, write the value of each unit length in the array to the corresponding target address.

5. The time-series signal generation method according to claim 1, characterized in that, External communication protocols include the SPI communication protocol; the timing signals of the SPI communication protocol include slave device select signal, clock signal, and master device transmit signal.

6. The timing signal generation method according to any one of claims 1 to 5, characterized in that, Also includes: After the GTM module outputs the timing signal of the external communication protocol, it performs data interaction with the slave device according to the timing signal.

7. The timing signal generation method according to claim 6, characterized in that, Data interaction with slave devices is achieved based on timing signals, including: Select the slave device for communication based on the slave device selection signal in the timing signals; Based on the clock signal in the timing signal, data is sent bit by bit to the slave device and received bit by bit from the slave device. After completing the sending and receiving of all data, the communication with the slave device ends, and the data interaction with the slave device is completed.

8. The timing signal generation method according to claim 6, characterized in that, Also includes: During the generation of timing signals and the data interaction with slave devices, the results are calculated based on the multi-channel sequencer in the GTM module. The result calculation includes CRC check value calculation, data encryption, and data decryption.

9. A timing signal generation device based on a GTM module, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute, when running the program instructions, the timing signal generation method based on the GTM module as described in any one of claims 1 to 8.

10. A timing signal generation system based on a GTM module, characterized in that, include: The master device is configured to initialize the GTM module; and to write target program code for generating timing signals according to the external communication protocol. Load the target program code into the program space of the multichannel sequencer of the GTM module; control the GTM module to run the target program code in the program space; The GTM module, located on the host device, is configured to respond to the host device's control commands, run the target program code in the program space, and output timing signals for the external communication protocol. The GTM module includes: a clock management unit configured to generate all clocks and counters for the GTM module; a time base unit connected to the clock management unit configured to generate a common time base for the GTM module; a multi-channel sequencer connected to the time base unit configured to control the output and input data of the GTM module; an advanced routing unit connected to the multi-channel sequencer configured to generate complex output waveforms according to the instructions of the multi-channel sequencer; a timer output module connected to the advanced routing unit configured to output timing signals according to the complex output waveforms; a timer input module connected to the advanced routing unit configured to capture input signals; and a random access memory connected to the multi-channel sequencer configured to store the target program code and interact with the multi-channel sequencer.

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