Transmission control method and system of cross-chip coherence transaction and chip

Abstract

The embodiment of the application relates to the field of semiconductor chips, and provides a transmission control method and system of cross-chip consistency transactions and a chip, which comprises the following steps: a consistency master node queries directory information after receiving a consistency request, determines a request node and whether a cross-chip snoop transaction needs to be transmitted; a target C2C cross-chip node is determined before transmission, an in-transit count value corresponding to the target C2C cross-chip node is obtained and compared with a preset threshold value, if the preset threshold value is not reached, the target C2C cross-chip node is allowed to be transmitted and the in-transit count value is updated, and if the preset threshold value is reached, transmission in the corresponding direction is stopped; after receiving a snoop response, an in-transit count value corresponding to a source C2C cross-chip node is updated. According to the embodiment of the application, independent counting and independent control are performed on different C2C cross-chip nodes, so that the risk of blocking and deadlock can be reduced, and the reliability of multi-chip consistency transaction processing can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chips, and more specifically to a method, system, and chip for transmission control of cross-chip consistent transactions. Background Technology

[0002] With the advancement of semiconductor technology, the number of processing cores integrated on a network-on-a-chip (NoC) is constantly increasing. In multi-core processor and multi-chip interconnect systems, a cache coherence interconnect mechanism is usually required to ensure data consistency when different processor cores or functional nodes access shared cache lines.

[0003] In a single-chip (CHIP) system, snoop transactions are typically routed only within the same chip to the target requesting node. In a multi-chip system, if the target cache line copy is located on another chip, a cross-chip snoop transaction needs to be generated, reaching the target requesting node via the intra-chip routing node and the C2C cross-chip node. When cross-chip snoop traffic is excessive, the snoop buffer of the C2C cross-chip node and the snoop channel of the intra-chip routing node may be filled with incomplete cross-chip snoop transactions, causing both or more parties to be unable to continue receiving or forwarding snoop transactions from the other end, thus creating a deadlock.

[0004] To address the aforementioned issues, related technologies can isolate transactions from different sources or directions into different logical channels by adding virtual channels, thereby alleviating mutual congestion between channels. Adding virtual channels typically requires additional caching, arbitration, and flow control logic in routing nodes, leading to significant area, power consumption, and verification complexity. Another related technical solution involves adding or reserving Snoop buffer resources in C2C cross-chip nodes to enhance transaction caching capabilities in congested scenarios. However, relying solely on reserved buffer resources in C2C cross-chip nodes may still be insufficient to effectively alleviate congestion in complex interconnection structures such as three-chip or higher chain topologies due to resource contention on multi-hop cross-chip transmission paths.

[0005] Therefore, how to reduce the risk of channel blocking caused by cross-chip Snoop transactions in multi-chip systems with lower hardware implementation costs has become an urgent technical problem to be solved. Summary of the Invention

[0006] This application provides a method, system, and chip for transmission control of cross-chip consistent transactions. It can solve the blocking or deadlock problem caused by cross-chip Snoop transactions in multi-chip systems easily consuming inter-chip buffer resources and intra-chip Snoop channels while reducing hardware overhead and ensuring applicability to complex topologies.

[0007] In a first aspect, embodiments of this application provide a transmission control method for cross-chip consistency transactions. This method is applied to a multi-chip system, where each chip in the multi-chip system includes a consistency master node, a request node, an on-chip routing node, and a C2C cross-chip node for connecting different chips. The method includes: The consistency master node receives the consistency request and queries the directory information based on the consistency request to determine the requesting node that holds a copy of the target cache line. Based on the chip location of the requesting node holding the target cache line copy, determine whether the snooping transaction to be launched is a cross-chip snooping transaction; Before launching the cross-slice eavesdropping transaction, the target C2C cross-slice node corresponding to the cross-slice eavesdropping transaction is determined, and the in-transit count value corresponding to the target C2C cross-slice node is obtained. The in-transit count value is used to count the number of cross-slice eavesdropping transactions launched through the corresponding C2C cross-slice node that have not yet received the corresponding eavesdropping response. Compare the in-transit count value corresponding to the target C2C cross-slice node with a preset threshold; If the in-transit count value does not reach the preset threshold, the cross-shard eavesdropping transaction is allowed to be launched, and the in-transit count value corresponding to the target C2C cross-shard node is updated. If the in-transit count reaches the preset threshold, then the transmission of the corresponding cross-slice eavesdropping transaction to the target C2C cross-slice node is stopped; after receiving the eavesdropping response corresponding to the transmitted cross-slice eavesdropping transaction, the in-transit count corresponding to the source C2C cross-slice node is updated according to the source C2C cross-slice node of the eavesdropping response. Among them, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, and are used to independently control the transmission of cross-chip eavesdropping transactions in different cross-chip transmission directions.

[0008] Secondly, embodiments of this application provide a transmission control system for cross-chip consistency transactions, which has the function of implementing the transmission control method for cross-chip consistency transactions corresponding to the first aspect described above. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function, and the modules can be software and / or hardware.

[0009] In one implementation, the system is deployed in at least one chip of a multi-chip system. The system includes a consistency master node, request nodes, on-chip routing nodes, and C2C cross-chip nodes for connecting different chips. The consistency master node is configured to execute the transmission control method for cross-chip consistency transactions as provided in the first aspect; The requesting node is configured to hold a copy of the target cache line and respond to a snoop transaction launched by the consistency master node to return a corresponding snoop response to the consistency master node; The on-chip routing node is configured to forward transactions transmitted between the consistency master node, the request node, and the C2C cross-chip node within the chip. The C2C cross-chip node is configured to forward cross-chip snooping transactions and / or snooping responses corresponding to cross-chip snooping transactions between this chip and other chips; Among them, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, and are used to independently control the transmission of cross-chip eavesdropping transactions in different cross-chip transmission directions.

[0010] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the transmission control method for cross-chip consistency transactions as described in the first aspect.

[0011] Fourthly, embodiments of this application provide a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the cross-chip consistency transaction transmission control method described in the first aspect.

[0012] Fifthly, embodiments of this application provide a chip including a processor coupled to a transceiver for executing the technical solution provided in the first aspect of this application. In one possible design, the chip can also be a dedicated hardware structure for implementing the technical solution provided in the first aspect.

[0013] In a sixth aspect, embodiments of this application provide a chip system including a processor for implementing the functions involved in the first aspect above, such as generating or processing information involved in the transmission control method for cross-chip consistency transactions provided in the first aspect above.

[0014] In one possible design, the aforementioned chip system further includes a memory connected to the processor via a circuit structure. This memory stores program instructions and data necessary for the terminal. The chip system can be composed of a single chip or may include chips and other discrete devices. Further optionally, the chip also includes a communication interface to which the processor connects. The communication interface receives data and / or information that needs to be processed. The processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. This communication interface can be an input / output interface.

[0015] In a seventh aspect, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on a computer, cause the computer to execute the cross-chip consistency transaction transmission control method provided in the first aspect.

[0016] Compared to existing technologies, in this embodiment, after receiving a consistency request, the consistency master node first determines the requesting node holding a copy of the target cache line through directory information, and distinguishes between local snooping transactions and cross-chip snooping transactions based on the chip location of the requesting node. For cross-chip snooping transactions, the consistency master node determines the corresponding target C2C cross-chip node before transmission and obtains the in-transit count value corresponding to the target C2C cross-chip node. This in-transit count value is then compared with a preset threshold to pre-determine whether the corresponding cross-chip transmission direction still has acceptable transaction carrying space before the cross-chip snooping transaction enters the on-chip routing node and the C2C cross-chip node. When the in-transit count value does not reach the preset threshold, the transmission of the cross-chip snooping transaction is allowed and the corresponding in-transit count value is updated. When the in-transit count value reaches the preset threshold, the transmission of cross-chip snooping transactions to the corresponding target C2C cross-chip node is stopped. Furthermore, after receiving a snooping response corresponding to a transmitted cross-chip snooping transaction, the corresponding in-transit count value is updated based on the source C2C cross-chip node of the snooping response. Therefore, this application embodiment can use the number of cross-chip snoop transactions that have been sent but have not yet received a corresponding snoop response as the basis for transmission control, and independently limit the cross-chip transmission direction corresponding to different C2C cross-chip nodes. This avoids cross-chip Snoop transactions in a certain direction from continuously occupying inter-chip buffer resources and intra-chip Snoop channels, reducing the risk of channel blocking and deadlock from the source. At the same time, since this control process is mainly completed on the consistency master node side based on the in-transit count value and preset threshold, there is no need to add virtual channels in the intra-chip routing node or C2C cross-chip node, nor does it rely on the real-time feedback of the buffer availability status of the C2C cross-chip node. Therefore, it can reduce the overhead of additional caching, arbitration, flow control and cross-module wiring. Furthermore, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, so that the blocking and recovery of different cross-chip transmission directions are decoupled, thereby adapting to dual-chip, three-chip chain topologies and complex interconnection topologies composed of more chips. Attached Figure Description

[0017] The objectives, features, and advantages of the embodiments of this application will become readily understood by referring to the accompanying drawings and reading the detailed description of the embodiments.

[0018] Figure 1 This is a schematic diagram of a dual-CHIP interconnection system; Figure 2 This is a schematic diagram of a Snoop channel blocking scenario in a dual-CHIP interconnect system; Figure 3A schematic diagram of a three-chip interconnection system; Figure 4 This is a flowchart illustrating the transmission control method for cross-chip consistency transactions according to an embodiment of this application. Figure 5 This is a schematic diagram of the transmission control system for cross-chip consistency transactions according to an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that, in the cases involving user information in the embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse. In addition, the various models involved in this application (including but not limited to language models or large models) comply with relevant laws and standards. Furthermore, the sequence of steps in the following method embodiments is merely an example and not a strict limitation.

[0021] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0022] With the advancement of semiconductor technology, the number of processing cores integrated on a single chip is constantly increasing. In multi-core processor and multi-chip interconnect systems, a cache consistency interconnect mechanism is typically required to ensure data consistency when different processor cores or functional nodes access shared cache lines. For example, in a system conforming to the ARM AMBA CHI protocol, a requesting node (RN-F) can initiate a consistency request to the consistency master node (HN-F). The consistency master node determines whether the target cache line is held by other requesting nodes based on its maintained directory information (Snoop Filter), and sends a snooping transaction (or simply snoop transaction) to the corresponding requesting node when necessary to obtain the cache line status, reclaim cache line copies, or complete the consistency state transition.

[0023] In this application embodiment, NoC is an abbreviation for Network-on-Chip, which refers to a communication network set up inside a chip to connect processor cores, caches, master nodes, request nodes, storage controllers, and other functional IPs. NoC typically uses on-chip routing nodes to forward different types of transactions, such as request transactions, response transactions, data transactions, and snooping transactions, within the chip.

[0024] A die, or bare silicon interposer, is a single, unpackaged silicon wafer unit formed during the integrated circuit manufacturing process. A single die can contain a processor core, cache, on-chip network, memory controller, inter-chip interconnect interfaces, or other functional circuitry. In some multi-chip packaging scenarios, multiple dies can be integrated into the same package to collectively achieve greater-scale computing or interconnect capabilities.

[0025] A chip, or chip, refers to an electronic device formed by packaging a single die (DIE), or a multi-die electronic device formed by interconnecting multiple dies through packaging. In the embodiments of this application, a chip may include hardware structures such as a master node, request nodes, on-chip routing nodes, and C2C cross-die nodes, and can perform consistent transaction transmission with other chips through C2C cross-die nodes.

[0026] The ARM AMBA CHI protocol is an on-chip interconnect protocol that supports cache coherency transaction transmission. In this protocol, requesting nodes can initiate coherency access requests, and the coherent master node can determine the holding status of cache line replicas based on directory information. It then obtains or updates the cache line status in relevant requesting nodes by sending Snop transactions, thereby maintaining cache coherency in multi-core or multi-chip systems. CHI stands for Coherent Hub Interface, a high-performance cache coherency interconnect protocol defined by ARM, applicable to multi-core processors, on-chip networks, and multi-chip interconnect systems. The CHI protocol transmits consistency-related information between requesting nodes, master nodes, slave nodes, and the interconnect network through request, response, data, and snoop transactions, thus supporting cache coherency maintenance in multi-core or multi-chip systems. The CHI protocol can carry Snop type and related control information through SnpInfo (Snoop Information) fields.

[0027] Snoop transactions are a key operational mechanism in cache coherence protocols used to maintain data consistency in multiprocessor or multi-core systems. In parallel computing systems with shared memory, when multiple processor cores or chips maintain their own local caches, if copies of the same memory address exist in different caches, the system must ensure that the states of these copies are synchronized to avoid computational errors caused by data inconsistency. Snoop transactions are the core means to achieve this goal.

[0028] The basic working principle of Snoop transactions is as follows: When a processor (called a requesting node) needs to read or modify data at a specific memory address, it actively snoops on the caches of other processors to check if a valid copy of that address exists. Specifically, the data request initiated by the requesting node triggers the consistency master node to query the consistency directory (Snoop Filter). If it finds that a copy of the target cache line is distributed in the caches of other processors, the consistency master node sends a Snoop transaction instruction to these processors. Processors receiving the Snoop transaction must respond according to their own cache state, such as providing the latest data (if it is a modification operation) or marking their local copy as invalid (if the data is about to be updated).

[0029] Within the ARM AMBA CHI (Coherent Hub Interface) protocol framework, the Snoop transaction is a standardized communication unit for achieving cache consistency. When a data request involves cross-chip access (i.e., the target cache line is located on another physical chip), the consistency master node (HN-F) forwards the Snoop transaction to the target chip via the inter-chip interconnect unit (C2C). The target chip's request node agent (RN-F) then performs local cache probing and returns the results. This process is transparent to the software but must strictly adhere to the timing and state transition rules defined by the protocol to ensure that the system maintains data consistency even under high concurrency scenarios.

[0030] It is worth noting that the transmission of Snoop transactions relies on hardware-level buffers and routing resources. When cross-chip Snoop transaction traffic surges, if the inter-chip interface buffers are exhausted, it may lead to transaction backlog or even channel deadlock, which is a risk that needs to be carefully avoided in multi-chip system design.

[0031] Understandably, in a single-chip system, requesting nodes, consistency master nodes, and routing nodes typically reside within the same on-chip network. Snoop transactions generated by the consistency master node can be transmitted within the chip via on-chip routing nodes and ultimately reach the target requesting node. Since this type of transmission mainly occurs within the single chip, the routing and caching resources occupied by Snoop transactions are relatively concentrated. Snoop transactions can usually be managed through on-chip network channel partitioning, caching configuration, and flow control mechanisms.

[0032] As system scale increases, multi-chip consistency interconnect systems are increasingly used to expand computing power and cache consistency domains. In such systems, different chips are typically connected via inter-chip interconnect nodes. When the target cache line replica is located on a requesting node in another chip, the consistency master node needs to generate a cross-chip Snoop transaction. This transaction typically needs to pass through the intra-chip routing node of the same chip, the inter-chip interconnect node of the same chip, the inter-chip interconnect node of the peer chip, and the intra-chip routing node of the peer chip before reaching the target requesting node. Therefore, cross-chip Snoop transactions not only consume intra-chip network resources of the same chip but also consume inter-chip interconnect node and intra-chip network resources of the peer chip.

[0033] In related technologies, the buffer, queue, and link bandwidth resources in intra-chip routing nodes and inter-chip interconnect nodes are typically limited. When multiple chips simultaneously generate a large number of cross-chip snoop transactions, incomplete cross-chip snoop transactions may accumulate at intra-chip routing paths or inter-chip interconnect nodes. For example, once the buffer resources used to cache snoop transactions in an inter-chip interconnect node are full, its ability to continue receiving or forwarding snoop transactions from other chips will be limited. Simultaneously, the snoop channels of intra-chip routing nodes may also be occupied by transactions waiting for cross-chip transmission or waiting for downstream resource release. In dual-chip or multi-chip scenarios, if snoop transactions in multiple directions are waiting for each other to release channels or buffer resources, snoop transactions may be unable to continue being transmitted to the target requesting node, thus affecting the normal completion of the consistency process. When cross-shard Snoop traffic is too high, the C2C buffer and the RS Snoop channel may be filled with incomplete cross-shard Snoop transactions, causing both or more parties to be unable to continue receiving or forwarding the other party's Snoop transactions, thus creating a deadlock.

[0034] For example, in a multi-chip consensus interconnect system supporting the ARM AMBA CHI protocol, the master node (HN-F) can be used to maintain cache consistency among requesting nodes (RN-F) within its management scope. When an HN-F receives a consistency request from an RN-F, it can query its internally maintained Snoop Filter. If the Snoop Filter records that other RN-Fs hold a copy of the target cache line corresponding to the consistency request, the HN-F can send a Snoop transaction to the corresponding RN-F to obtain the cache line status, reclaim the cache line copy, or complete the consistency state transition.

[0035] like Figure 1 As shown, in a dual-chip interconnect system, if the target RN-F is located on another chip, the Snoop transaction generated by HN-F needs to be transmitted across chips. Taking the Snoop transaction sent from HN-F in chip 0 to RN-F in chip 1 as an example, after HN-F in chip 0 generates the Snoop transaction, the Snoop transaction is transmitted to the C2C cross-chip node of chip 0 via one or more intra-chip routing nodes RS within chip 0; subsequently, the C2C cross-chip node of chip 0 sends the Snoop transaction to the C2C cross-chip node of chip 1 through the inter-chip link; the C2C cross-chip node of chip 1 then forwards the Snoop transaction to the intra-chip routing node RS within chip 1, and finally routes it to the target RN-F by RS.

[0036] Figure 1 The diagram illustrates the flow direction of cross-CHIP Snoop transactions in a dual-CHIP interconnect system. CHIP 0 and CHIP 1 include HN-F, RN-F, RS, and C2C cross-chip nodes, respectively. Arrows ① to ⑦ in the diagram represent the transmission path of a cross-CHIP Snoop transaction originating from HN-F of CHIP 0 and reaching the target RN-F via the source chip's on-chip network, the inter-chip interconnect node, and the target chip's on-chip network.

[0037] In the aforementioned dual-chip interconnect system, C2C cross-chip nodes can typically be configured with buffers to temporarily store Snoop transactions. When inter-chip links are busy, downstream routing resources are limited, or the peer chip is temporarily unable to process transactions in a timely manner, Snoop transactions may be temporarily stored in this buffer. If cross-chip Snoop transactions are concentrated in the system, the Snoop channels of intra-chip routing nodes and the buffers of C2C cross-chip nodes may experience increased occupancy, thereby affecting the transmission of subsequent Snoop transactions.

[0038] like Figure 2As shown, in a dual-chip interconnect system, when there is a high intensity of cross-chip Snoop transaction transmission between Chip 0 and Chip 1 simultaneously, the RS Snoop channels within the two chips and the Snoop buffers of the C2C cross-chip nodes may be either busy or fully loaded. In this situation, Snoop transactions from the peer chip may have difficulty entering the intra-chip network in a timely manner and continuing to be routed to the target RN-F, thus affecting the processing progress of related consistency transactions.

[0039] Figure 2 This paper illustrates a Snoop channel congestion scenario in a dual-chip interconnect system. Both Chip 0 and Chip 1 have cross-chip Snoop transaction transmissions, and relevant channel resources in intra-chip routing nodes and inter-chip interconnect nodes are occupied. When both parties have difficulty receiving or forwarding Snoop transactions sent by the other end in a timely manner, Snoop transactions may accumulate at intra-chip routing paths or inter-chip interconnect nodes, potentially preventing related Snoop transactions from proceeding in the system.

[0040] Therefore, the specific problems with the relevant technology are as follows: In a multi-chip consensus interconnect system, cross-chip Snoop transactions need to pass through multiple stages, including on-chip routing nodes, inter-chip interconnect nodes, and the on-chip network of the peer chip. The transmission process is affected by the combined influence of on-chip channels, inter-chip links, and node buffer resources. When cross-chip Snoop traffic is large, related channels and buffer resources are prone to congestion or blockage, which in turn affects the Snoop transaction's arrival at the target RN-F and the normal completion of the consensus process, potentially leading to system malfunctions in severe cases.

[0041] To address the aforementioned issues, related technologies can isolate transactions from different sources or directions into different logical channels by adding virtual channels, thereby alleviating mutual congestion between channels. Adding virtual channels typically requires additional caching, arbitration, and flow control logic in routing nodes or inter-chip interconnect nodes, which leads to significant area, power consumption, and verification complexity.

[0042] Another related technical solution is to add or reserve Snoop buffer resources in the inter-chip interconnection nodes to enhance their transaction pausing capabilities under congestion scenarios. However, relying solely on reserved buffer resources in the inter-chip interconnection nodes may still be insufficient to effectively resolve congestion in complex interconnection structures such as three-chip or higher chain topologies due to resource contention on multi-hop cross-chip transmission paths.

[0043] by Figure 3Taking the three-chip chain or unidirectional forwarding topology as an example, cross-chip Snoop transactions may need to be forwarded through intermediate chips before reaching the target RN-F. When the Snoop channels of each chip are in a high-occupancy state, even if the inter-chip interconnection nodes have reserved Snoop buffer resources, these reserved resources may only be able to temporarily receive partially blocked Snoop transactions within the current chip, making it difficult to simultaneously meet the needs of receiving new transactions from upstream chips and forwarding them to downstream chips. Due to the limited nature of the reserved buffer resources, Snoop transactions across multi-hop transmission paths may still remain in the intra-chip routing path of intermediate chips and cannot continue to advance to the target chip. It is evident that in complex interconnection structures with three or more chips, simply increasing or reserving Snoop buffer resources in inter-chip interconnection nodes is insufficient to eliminate resource contention in multi-hop transmission paths as a whole. When multiple chips are in similar occupancy states, cross-chip Snoop transactions may still fail to reach the target RN-F, resulting in persistent channel congestion or deadlock.

[0044] In summary, how to reduce the risk of channel blocking caused by cross-chip Snoop transactions in multi-chip systems with lower hardware implementation costs has become an urgent technical problem to be solved.

[0045] This application provides a method, system, and chip for transmission control of cross-chip consistent transactions, which will be described in detail below with reference to specific embodiments.

[0046] The cross-chip consistency transaction transmission control method provided in this application can be applied to multi-chip consistency interconnect systems. This multi-chip consistency interconnect system may include two or more chips, which can be connected through inter-chip interconnect units to form dual-chip interconnects, chain interconnects, ring interconnects, mesh interconnects, or other multi-chip topologies. This application does not limit the specific connection method between chips, nor does it limit the underlying physical link or protocol type used by the inter-chip interconnect units.

[0047] In some embodiments, each chip in a multi-chip system may include a consistency master node, a request node, an on-chip routing node, and a C2C cross-chip node. The consistency master node can be used to receive consistency requests, query directory information, generate snoop transactions, and maintain the processing order of consistency transactions. The request node can be used to initiate consistency access requests and respond to snoop transactions sent by the consistency master node. The on-chip routing node can be used to forward request transactions, response transactions, data transactions, and snoop transactions within its own chip. The C2C cross-chip node can be used to connect different chips and forward cross-chip consistency transactions between different chips, such as cross-chip snoop transactions and their corresponding snoop responses.

[0048] Reference Figure 4 , Figure 4 This is a flowchart illustrating a cross-chip consistency transaction transmission control method provided in an embodiment of this application. The method can be executed by the main chip and includes the following steps: Step 101: The consistency master node receives the consistency request and queries the directory information based on the consistency request to determine the requesting node that holds a copy of the target cache line.

[0049] In this embodiment, the consistency master node can be a hardware node used to maintain cache consistency and coordinate consistency transaction processing. It can correspond to the consistency master node or consistency management node in the consistency protocol. For example, the consistency master node can correspond to HN-F in the CHI protocol, used as the coordinating node for consistency transactions to maintain cache consistency among multiple requesting nodes within its management scope. The requesting node can correspond to RN-F in the CHI protocol, used to initiate consistency requests and return corresponding probe responses when a probe transaction is received.

[0050] The requesting node can be a hardware node capable of initiating consistency requests and / or responding to sniffer transactions, such as a processor core, cache proxy, or other functional unit with cache access capabilities.

[0051] Consistency requests can include read requests, write requests, state transition requests, or other access requests that require consistency maintenance, targeting a cache line. A target cache line can be understood as a cache-level data unit accessed by the consistency request. Upon receiving a consistency request, the consistency master node can store information such as the request address, request type, source node information, and transaction status in the processing context corresponding to the request. It can then query directory information based on the request address or cache line identifier to determine whether a listening transaction needs to be triggered subsequently.

[0052] In some embodiments, PoC is an abbreviation for Point of Coherence, which can be referred to as a consistency point. It is a logical location or functional unit in the CHI protocol used to coordinate consistent transaction processing. Within the consistent master node, each consistency request can correspond to a PoC Entry for processing. An Entry, also called an entry or transaction entry, can be a resource unit within the consistent master node used to store and process a consistency request. Different Entries can correspond to different consistency requests and can support out-of-order creation, parallel processing, or out-of-order completion.

[0053] In practical applications, when the consistency master node receives a consistency request from a requesting node, it can allocate or create a corresponding Entry for the consistency request and cache the relevant information of the consistency request in the Entry. This relevant information may include the request address, request type, source requesting node identifier, transaction identifier, cache line status information, and / or subsequent processing status information. By caching the context of the consistency request through the Entry, the consistency master node can continue to perform operations such as directory lookup, snooping transaction generation, response collection, and consistency status updates based on the Entry in subsequent processing stages. Further optionally, a local Snoop queue is located on the local Snoop transmission path and is used to receive consistency request information from HN-Fentries. It performs round-robin polling based on the local RN-F list in all snoop targets (snoop vectors) to generate corresponding local Snoop Flit transmission outputs one by one. It is worth noting that the local snoop queue (Snoopqueue) does not involve mask control for invalidating cross-shard snoop targets. A Flit is the basic unit of data transmission at the CHI protocol link layer and includes fields such as TgtID, SrcID, and transaction type. TgtID, short for Target Node ID, is the identifier of the target C2C node and is a field used to identify the target node in a CHI transaction. SrcID, short for Source Node ID, is the identifier of the source node (i.e., the master node) and is a field used to identify the source node in a CHI transaction.

[0054] In some embodiments, SF is an abbreviation for Snoop Filter, which can be called a sniffing filter directory or a listening filter directory. It is directory information maintained internally by the consistency master node. The Snoop Filter can be used to record the status of each requesting node holding a copy of the cache line. For example, it can record whether a certain cache line is held by one or more requesting nodes, or record the status of each requesting node holding a copy of the cache line. The consistency master node can query the Snoop Filter based on the target address or cache line identifier carried in the consistency request to determine whether there are other requesting nodes holding a copy of the target cache line.

[0055] If the Snoop Filter records that one or more requesting nodes hold a copy of the target cache line, the consistency master node can identify these requesting nodes as the target requesting nodes for subsequent snoop transactions and generate a corresponding Snoop target list. If the Snoop Filter does not record that other requesting nodes hold a copy of the target cache line, the consistency master node may choose not to generate snoop transactions for other requesting nodes, or continue to execute subsequent processing procedures according to the consistency protocol.

[0056] In the above manner, step 101 can convert the consistency request into the target request node information required for the generation of subsequent snoop transactions. That is, firstly, the request processing context is saved using Entry, and then the holder of the target cache line copy is determined using Snoop Filter. This makes it easier to determine whether the snoop transaction needs to be transmitted across chips and helps to control the transmission of cross-chip snoop transactions.

[0057] Step 102: Determine whether the listening transaction to be transmitted is a cross-chip listening transaction based on the chip location of the requesting node.

[0058] In this embodiment of the application, the listening transaction can be a transaction sent by the consistency master node to the requesting node to maintain the consistency of the target cache line. It is used to obtain the status of the target cache line in the requesting node, reclaim cache line copies, request the return of cache line data, or trigger a cache line status update.

[0059] A probe transaction to be launched can be a transaction that the consistency master node determines needs to send based on directory information but has not yet been output through the probe launch path. Chip location is used to characterize the chip affiliation or cross-chip routing relationship between the requesting node and the consistency master node. By distinguishing probe transactions to be launched based on chip location, it can be identified whether the probe transaction needs to be transmitted through C2C cross-chip nodes, thus providing a basis for subsequent judgment to perform in-transit quantity control only for probe transactions that require cross-chip transmission resources.

[0060] A C2C cross-chip node can include a transmit channel (TX) and a receive channel (RX). TX, short for Transmit, is used to send probe transactions generated by the local chip or forwarded by the local chip to the peer chip. RX, short for Receive, is used to receive probe transactions sent by the peer chip. Through TX and RX, a C2C cross-chip node can transmit cross-chip probe transactions and related consistency transactions between different chips.

[0061] In some embodiments, RS is an abbreviation for Router, and can be referred to as an on-chip routing node. The on-chip routing node is located in the on-chip network within the chip and is used to forward different types of transactions, such as request transactions, response transactions, eavesdropping transactions, and data transactions, to the corresponding target nodes based on routing algorithms, target node identifiers, or other routing information. The on-chip routing node can connect to consistency master nodes, request nodes, C2C cross-chip nodes, or other functional nodes, thereby enabling transaction transmission between nodes within the chip.

[0062] As an optional embodiment, in step 102, determining whether the snoop transaction to be sent is a cross-chip snoop transaction based on the chip location of the requesting node includes: determining the requesting node holding the target cache line copy according to the snoop filter directory; determining whether the chip where the requesting node is located is the same as the chip where the consistency master node is located; if the chip where the requesting node is located is the same as the chip where the consistency master node is located, then the snoop transaction sent to the requesting node is determined to be a local snoop transaction; if the chip where the requesting node is located is different from the chip where the consistency master node is located, then the snoop transaction sent to the requesting node is determined to be a cross-chip snoop transaction.

[0063] In this embodiment of the application, the target cache line copy corresponding to the consistency request can be held by one requesting node or by multiple requesting nodes simultaneously.

[0064] For example, when a shared cache line is in a shared state, multiple processor cores or cache proxies may hold copies of the target cache line. Upon receiving a consistency request, the consistency master node can query its maintained directory information to obtain the set of requesting nodes holding copies of the target cache line. This set of requesting nodes may include one or more requesting nodes; these requesting nodes may all be located on the local chip where the consistency master node resides, all on other chips, or partially on the local chip and partially on other chips.

[0065] In some embodiments, the directory information may include a Snoop Filter. The Snoop Filter can be used to record whether each requesting node holds a copy of the target cache line, or to record the status information of each requesting node holding a copy of the target cache line. The consistency master node can determine one or more requesting nodes that need to be sniffered by a transaction by querying the Snoop Filter. These requesting nodes that need to be sniffered by a transaction can be understood as nodes that, during the processing of the current consistency request, require access by a transaction sent by the consistency master node to complete cache line status acquisition, cache line copy recycling, cache line state transition, or data consistency maintenance.

[0066] After identifying one or more requesting nodes, the consistency master node can determine the chip location of each requesting node. If a requesting node and the consistency master node are located on the same chip, a probe transaction sent to that requesting node can be transmitted only through the on-chip routing node within that chip, and this probe transaction can be identified as a local probe transaction. If a requesting node and the consistency master node are located on different chips, a probe transaction sent to that requesting node needs to be transmitted through the on-chip routing node within that chip, the C2C cross-chip node, and the relevant routing resources within the target chip, and this probe transaction can be identified as a cross-chip probe transaction.

[0067] In some embodiments, a single consistency request can correspond to multiple snoop transactions. These multiple snoop transactions can all be local snoop transactions, all be cross-chip snoop transactions, or include both local and cross-chip snoop transactions simultaneously. For example, after querying the Snoop Filter, the consistency master node determines that the requesting nodes holding a replica of the target cache line include a first requesting node, a second requesting node, and a third requesting node. The first requesting node is located within the same chip as the consistency master node, while the second and third requesting nodes are located in other chips. In this case, the consistency master node can generate a local snoop transaction for the first requesting node and cross-chip snoop transactions for the second and third requesting nodes, respectively.

[0068] In this way, the consistency master node does not determine whether cross-chip transmission is needed solely based on the overall granularity of the consistency request. Instead, it can determine the transmission attributes of each probe transaction separately, using either the requesting node or the probe transaction as the granularity. Thus, when the same consistency request corresponds to both a local requesting node and cross-chip requesting nodes, probe transactions destined for the local requesting node can be processed differently from those destined for other chip requesting nodes. This provides a foundation for subsequent direction-level transmit control of cross-chip probe transactions.

[0069] Alternatively, in addition to the above-mentioned methods, the determination of whether a transaction is a cross-chip snooping transaction can also be based on the node affiliation table, topology configuration information, or the range to which the node identifier belongs. For example, the consistency master node can pre-maintain the correspondence between each requesting node and its associated chip. After determining the target requesting node, it can directly query the correspondence table to determine whether the target requesting node is located on the same chip. Alternatively, the consistency master node can also combine the system topology configuration information with the intra-chip routing path connected to the target requesting node, inter-chip connection node information, or the range to which the node identifier belongs to determine whether the snooping transaction needs to be transmitted via a C2C cross-chip node. Through the above methods, even without directly relying on the node location description in the directory information, it is possible to distinguish between local snooping transactions and cross-chip snooping transactions.

[0070] In this embodiment, before generating or transmitting a probe transaction, the consistency master node first classifies the probe transaction to be transmitted into local or cross-chip attributes based on the chip location of the requesting node. Since cross-chip probe transactions require the use of intra-chip routing nodes, C2C cross-chip nodes, and peer chip routing resources, while local probe transactions only use routing resources within their own chip, their impact on system channel resources differs. By distinguishing between the probe transaction generation stage and the transmission preparation stage, subsequent in-transit counting, threshold comparison, and transmission pause can be applied only to probe transactions requiring cross-chip transmission, without restricting local probe transactions.

[0071] Furthermore, when a consistency request corresponds to multiple requesting nodes, even if some cross-chip snooping transactions are temporarily unable to be transmitted due to the in-transit count of the corresponding C2C cross-chip node reaching a preset threshold, the consistency master node can still continue to process or transmit local snooping transactions destined for the local requesting node within the same consistency request, or process cross-chip snooping transactions in other unrestricted directions. This avoids the blocking of all snooping transactions associated with the entire consistency request due to restrictions in a single cross-chip direction, reducing the probability of the consistency master node's snooping transmission path being completely shut down, and improving the transmission efficiency of local consistency transactions and cross-chip transactions in other directions.

[0072] Furthermore, the chip location in this embodiment can be the identifier of the chip where the requesting node resides, the topological relationship between the requesting node and the consistency master node, the routing domain information corresponding to the requesting node, or other location information that can distinguish whether the requesting node is located within the chip where the consistency master node resides. The consistency master node can determine the chip location of the requesting node through directory information, node identifier mapping information, system address mapping information, or pre-configured topology information; this embodiment does not limit this.

[0073] Step 103: Before launching the cross-slice eavesdropping transaction, determine the target C2C cross-slice node corresponding to the cross-slice eavesdropping transaction, and obtain the in-transit count value corresponding to the target C2C cross-slice node.

[0074] The in-transit count is used to track the number of cross-shard snooping transactions sent through the corresponding C2C cross-shard node that have not yet received a corresponding snooping response. A counter can be used to manage the in-transit count; the counter can be deployed on each node and maintained by the node itself, or it can be managed by an on-chip or off-chip management unit.

[0075] After determining that the probe transaction to be transmitted is a cross-chip probe transaction, the consistency master node needs to further determine which C2C cross-chip node should send the cross-chip probe transaction through. It is understandable that in a multi-chip system, one or more C2C cross-chip nodes can be set on a single chip, and different C2C cross-chip nodes can connect to different peer chips, different inter-chip links, or different cross-chip transmission directions. Therefore, for the cross-chip probe transaction to be transmitted, simply determining that it is a cross-chip transaction is insufficient to complete subsequent transmission control; it is also necessary to determine its corresponding cross-chip exit direction.

[0076] In this embodiment, the target C2C cross-chip node can be understood as the C2C cross-chip node that the cross-chip probe transaction must pass through when it is sent from the chip where the consistency master node is located. This target C2C cross-chip node can be a C2C cross-chip node connecting the chip where the target requesting node is located, or it can be a C2C cross-chip node in a chain, ring, or mesh topology used to forward the cross-chip probe transaction to the next-hop chip. That is, the target C2C cross-chip node does not necessarily represent a node on the final target chip, but can represent the cross-chip transmission exit in the current chip used to carry the cross-chip probe transaction.

[0077] In some embodiments, the consistency master node can maintain in-transit counts for different C2C cross-slice nodes. Each in-transit count can correspond to a C2C cross-slice node or a cross-chip transmission direction, reflecting the number of cross-slice probe transactions that have been sent via that C2C cross-slice node but have not yet received a corresponding probe response. "Not yet received a corresponding probe response" can be understood as: the cross-slice probe transaction has entered the cross-slice transmission path, but the probe response returned by the target requesting node has not yet reached the consistency master node; therefore, the cross-slice probe transaction still occupies or may occupy relevant cross-slice transmission resources and consistency transaction processing resources.

[0078] In practical applications, the in-transit count can be set to an initial value during system initialization, such as 0. When the consistency master node is preparing to launch a cross-chip eavesdropping transaction, it can read the in-transit count corresponding to the target C2C cross-chip eavesdropping node. This in-transit count can be used to compare with a preset threshold to determine whether it is currently suitable to launch a new cross-chip eavesdropping transaction in this cross-chip transmission direction.

[0079] The improvement in this embodiment lies in the fact that, in addition to using the existence of cross-chip snooping transactions as a unified control criterion, the consistency master node can further associate cross-chip snooping transactions with specific target C2C cross-chip nodes and perform control based on the in-transit count value corresponding to the target C2C cross-chip node. Therefore, the cross-chip transmission directions corresponding to different C2C cross-chip nodes can be statistically analyzed and judged separately, avoiding the mixing of multiple cross-chip directions into a single global state, which would lead to overly coarse control granularity. Especially in scenarios where a chip connects to multiple peer chips or multiple cross-chip links, this method can more accurately reflect the transaction occupancy status of each cross-chip direction.

[0080] Furthermore, since the in-transit count represents the number of cross-shard probe transactions that have been sent but have not yet received a corresponding probe response, it can reflect the occupancy status of cross-shard probe transactions in the corresponding C2C cross-shard node direction throughout their complete lifecycle. Compared to focusing only on the availability of a channel at a certain instant, the embodiments of this application can perform more stable transmission control based on the completion status of cross-shard probe transactions, thereby providing a foundation for reducing the channel congestion risk caused by cross-shard probe transactions in the future.

[0081] As an optional embodiment, step 103, determining the target C2C cross-chip node corresponding to the cross-chip eavesdropping transaction, includes: querying the address mapping information maintained by the consistency master node based on the target address and / or target request node information corresponding to the cross-chip eavesdropping transaction; determining the target C2C cross-chip node that the cross-chip eavesdropping transaction needs to pass through when it is sent from the chip where the consistency master node is located, based on the address mapping information, and obtaining the target node identifier corresponding to the target C2C cross-chip node; and carrying the target node identifier in the eavesdropping transaction to be sent, so that the eavesdropping transaction is transmitted to the chip where the target request node is located via the target C2C cross-chip node.

[0082] In this embodiment, the address mapping information may include a System Address Mapping Table (SAM). The SAM can be used to record the mapping relationships between different physical address ranges, target requesting nodes, target chips, or routing domains and their corresponding target requesting nodes. When generating a cross-chip snooping transaction, the consistency master node can query this address mapping information based on the target address, target cache line address, target requesting node identifier, or target chip identifier corresponding to the consistency request, thereby determining which C2C cross-chip node the cross-chip snooping transaction should be routed to within the current chip. For example, for a cross-chip RN-F selected by the cross-chip snooping queue (Snoopqueue), the snooping system address mapping table (Snoop SAM) queries the target C2C node ID (i.e., TgtID) based on the physical address corresponding to the RN-F, and appends the TgtID information to the Snoop Flit for subsequent in-transit counter management and C2C routing.

[0083] In some embodiments, the target node identifier can be the node ID of the target C2C cross-chip node, such as the TgtID in a CHI transaction. This target node identifier can be used to identify the current routing target of the cross-chip probe transaction, enabling the intra-chip routing node to forward the probe transaction to the corresponding C2C cross-chip node based on the target node identifier. In other words, after the cross-chip probe transaction is sent from the consistency master node, the intra-chip routing node can perform routing selection based on the target node identifier, allowing the probe transaction to reach the target C2C cross-chip node along the on-chip network within the chip, and further transmit it to other chips via inter-chip links.

[0084] In this embodiment, the target node identifier can be used not only for intra-chip routing and C2C cross-chip forwarding, but also for the consistency master node to select the corresponding in-transit count value before transmission. Specifically, after obtaining the target node identifier, the consistency master node can index or match the in-transit count value corresponding to the target C2C cross-chip node based on the target node identifier, and process the subsequent transmission judgment, post-transmission update, and response return update processes at the granularity of the target C2C cross-chip node. In this way, a correspondence can be formed between the address mapping result, the transaction routing field, and the in-transit count resource, which facilitates consistent transmission control for different cross-chip directions.

[0085] In practical applications, for dual-chip interconnect systems, address mapping information can map the target requesting node or target address range located on the peer chip to a unique C2C cross-chip node within the current chip. For chain, ring, or other topologies with three or more chips, address mapping information can determine the next-hop C2C cross-chip node that a cross-chip snooping transaction needs to enter based on the positional relationship between the target requesting node's chip and the current chip. For example, if the final target requesting node of a cross-chip snooping transaction is located on a non-directly connected chip, the consistency master node can determine the first C2C cross-chip node that the transaction needs to pass through in the current chip based on the address mapping information, and that C2C cross-chip node will forward the transaction to the next chip.

[0086] In this embodiment, the routing determination process for cross-shard eavesdropping transactions is integrated with the subsequent in-transit count management process. The consistency master node first determines the target C2C cross-shard node and its identifier based on address mapping information, and then obtains the corresponding in-transit count value based on the target C2C cross-shard node. Therefore, the cross-shard direction of a cross-shard eavesdropping transaction can be determined before it is launched, ensuring that subsequent threshold comparisons and launch control accurately apply to the C2C cross-shard nodes that the transaction will actually occupy, rather than indiscriminately processing all cross-shard eavesdropping transactions.

[0087] Besides the aforementioned methods for obtaining target node identifiers, they can also be obtained through routing tables, direct encoding, or configuration registers. For example, the consistency master node can pre-store the corresponding routing relationships between each target address range and the target C2C cross-slice node. When generating a cross-slice snooping transaction, it can directly obtain the corresponding target node identifier by querying the routing table. Alternatively, the target node identifier can be pre-encoded into the snooping transaction generation logic for a specific topology, allowing the consistency master node to directly output the corresponding target node identifier after determining the target request node. Furthermore, target node identifiers corresponding to different address ranges, different target request nodes, or different transmission directions can be pre-configured through configuration registers, so that the consistency master node can read and determine the corresponding target node identifier before launching the cross-slice snooping transaction. Through these methods, the determination of the target C2C cross-slice node can be flexibly completed according to different system topologies and implementation requirements.

[0088] Furthermore, in some embodiments, the consistency master node can write the target node identifier into the target node field of the probe transaction to be transmitted. If the probe transaction is transmitted in the Flit form of the CHI protocol, the target node identifier can be carried in the TgtID field of the Snoop Flit. Intra-chip routing nodes can determine the next-hop routing direction based on the TgtID field, and C2C cross-chip nodes can also use this field to identify whether the probe transaction needs to be forwarded to the inter-chip link by themselves.

[0089] In other embodiments, the target node identifier may also be carried in the routing field, destination node field, inter-segment forwarding field, or control field defined by protocol extension of the listening transaction. As long as the field enables the intra-segment routing node or C2C cross-segment node to identify the target C2C cross-segment node corresponding to the cross-segment listening transaction, it can be used as the target node identifier carrying method in the embodiments of this application, and the embodiments of this application do not limit it in this way.

[0090] Furthermore, on the consistency master node side, the target node identifier can also serve as index information for managing in-transit counts. That is, when the consistency master node sends a cross-segment snooping transaction, it can determine the in-transit count value that needs to be increased based on the target node identifier. Upon receiving a snooping response, it can determine the in-transit count value that needs to be decreased based on the source node identifier or source C2C cross-segment node information carried in the response. Therefore, in this embodiment, the target node identifier serves both as a routing indicator for cross-segment snooping transactions and as an association for cross-segment direction statistics and control, thereby improving the accuracy and feasibility of cross-segment snooping transaction transmission control.

[0091] Step 104: Compare the in-transit count value corresponding to the target C2C cross-shard node with a preset threshold.

[0092] After identifying the target C2C cross-shard node and obtaining its corresponding in-transit count, the consistency master node can further determine whether new cross-shard eavesdropping transactions are still allowed to be launched in the direction corresponding to that target C2C cross-shard node. The preset threshold here can be understood as the upper limit of the number of cross-shard eavesdropping transactions allowed to be in transit under the current configuration conditions for the corresponding C2C cross-shard node. This preset threshold, used in conjunction with the in-transit count, is used to determine the launch of transactions in that direction before the cross-shard eavesdropping transaction enters the intra-shard routing path and the C2C cross-shard node.

[0093] In this embodiment, the preset threshold is set through the CSR (Configuration and Status Register). In some embodiments, different C2C cross-chip nodes can each have their own preset threshold. This is because the peer chips, inter-chip link bandwidth, cache resources, forwarding paths, and topology locations connected to different C2C cross-chip nodes may differ, and the cross-chip eavesdropping transaction pressure that each C2C cross-chip node can bear may also differ. Setting thresholds separately for each C2C cross-chip node allows the consistency master node to adopt differentiated transmission judgment criteria for different cross-chip transmission directions, rather than using a uniform threshold for all cross-chip eavesdropping transactions.

[0094] Based on the above settings, before comparing the in-transit count value corresponding to the target C2C cross-shard node with the preset threshold, the method further includes: reading the corresponding field in the CSR configuration register of the consistency master node to obtain the preset threshold corresponding to the target C2C cross-shard node. The preset thresholds corresponding to different C2C cross-shard nodes are configured independently.

[0095] In some embodiments, the target C2C cross-slice node for eavesdropping can be determined by a target node identifier. For example, the consistency master node can determine the target node identifier of the target C2C cross-slice node based on the target address, target request node information, or address mapping information corresponding to the cross-slice eavesdropping transaction; this target node identifier is carried in the eavesdropping transaction to be transmitted for routing forwarding between the intra-slice routing node and the C2C cross-slice node. Simultaneously, the consistency master node can also index the in-transit count value and CSR configuration register corresponding to the target node identifier to ensure consistency in routing direction determination, count value selection, and threshold reading.

[0096] In this embodiment, the preset threshold can be configured independently for different C2C cross-slice nodes, without needing to be fixed for a unified cross-slice snooping transaction. Thus, when a chip has multiple C2C cross-slice nodes, or when a multi-chip system has different link bandwidths, cache depths, and topology distances, the consistency master node can perform independent comparisons based on the preset threshold corresponding to each C2C cross-slice node. Therefore, if the threshold in a certain cross-slice direction is low or reaches the threshold, it will not change the threshold judgment results for the corresponding directions of other C2C cross-slice nodes, which helps maintain the control independence between different cross-slice directions.

[0097] Further optionally, the preset threshold is the sum of the snooping transaction cache depth and the on-chip routing node cache depth of the corresponding C2C cross-chip node; the method further includes: determining the target threshold corresponding to the C2C cross-chip node based on the chip interconnect topology of the multi-chip system, the cache depth of the C2C cross-chip node, the cache depth of the on-chip routing node, and / or the cross-chip snooping transaction traffic; if the target threshold is less than 1, limiting the threshold written to the corresponding CSR configuration register to 1; if the target threshold is not less than 1, writing the target threshold to the CSR configuration register of the corresponding C2C cross-chip node to update the preset threshold of the corresponding C2C cross-chip node; wherein, the CSR configuration registers corresponding to different C2C cross-chip nodes are written independently, so that the preset thresholds corresponding to different C2C cross-chip nodes are independently and dynamically adjusted as the network topology and network traffic of the multi-chip system change.

[0098] The snooping transaction cache depth represents the size of the buffer resources used to cache snooping transactions in the C2C cross-chip node; the intra-chip routing node cache depth represents the size of the cache resources used to temporarily store related snooping transactions in the intra-chip routing node. Setting the preset threshold to be related to the sum of the snooping transaction cache depth of the corresponding C2C cross-chip node and the intra-chip routing node cache depth allows the threshold configuration to match the actual hardware resource scale, thereby controlling the number of cross-chip snooping transactions transmitted while minimizing the impact on normal cross-chip transmission bandwidth.

[0099] In some embodiments, the minimum configurable value of the preset threshold can be limited to 1. This way, even if the software or configuration logic attempts to write a target threshold less than 1, the actual threshold written to the CSR configuration register can be limited to 1, preventing a C2C cross-slice node from being unable to transmit cross-slice eavesdropping transactions in a given direction due to the threshold being configured to 0. It is understood that when the preset threshold is 1, the number of cross-slice eavesdropping transactions allowed to remain in transit in the corresponding C2C cross-slice node direction at the same time is relatively small, which is equivalent to applying stricter transmission control to that direction. When the preset threshold is larger, more cross-slice eavesdropping transactions can be allowed to be in transit in the corresponding direction, thereby achieving higher cross-slice transmission throughput.

[0100] In some embodiments, the target threshold can be configured during system initialization or adjusted during system operation. For example, during multi-chip system initialization, an initial threshold can be written for different C2C cross-chip nodes based on the snooping transaction cache depth of each C2C cross-chip node, the cache depth of adjacent intra-chip routing nodes, and the default topology. During multi-chip system operation, the target threshold corresponding to some or all C2C cross-chip nodes can also be updated based on changes in chip interconnect topology, link bandwidth configuration, service load, or cross-chip snooping transaction traffic.

[0101] Through the above method, this embodiment enables the preset threshold to combine hardware resource matching and configuration flexibility. The default threshold can be determined based on the cache depth of C2C cross-chip nodes and intra-chip routing nodes, making it related to the actual resources that can be supported. The CSR configuration register allows the threshold of different C2C cross-chip nodes to be adjusted independently, which helps to adapt to complex topologies such as dual-chip interconnects, three-chip chain interconnects, and more chips.

[0102] Furthermore, when the in-transit counts for multiple C2C cross-shard nodes all reach their respective preset thresholds, the consistency master node can pause sending new cross-shard probe transactions to the corresponding directions of these C2C cross-shard nodes and wait for the already sent cross-shard probe transactions to return their corresponding probe responses. As probe responses return, the in-transit counts for the corresponding C2C cross-shard nodes can gradually decrease. When the in-transit count in a certain direction falls below the corresponding preset threshold, the sending of cross-shard probe transactions in that direction can resume. Since the in-transit counts and preset thresholds for different C2C cross-shard nodes are maintained separately, even if multiple directions reach the threshold simultaneously, their recovery process can be carried out independently according to their respective response returns.

[0103] Another improvement in this application's embodiments is that the consistency master node reads a preset threshold based on the CSR configuration register and compares it with the in-transit count value corresponding to the target C2C cross-chip node. This allows the transmit control logic to operate without relying on the real-time feedback of the cache availability status from the C2C cross-chip node. In other words, the consistency master node can perform conservative judgments based on its own maintained in-transit count and pre-configured thresholds, reducing the need for additional real-time feedback signals between the consistency master node and the C2C cross-chip node. This helps reduce hardware implementation complexity and cross-module wiring overhead.

[0104] Furthermore, in some embodiments, a range check can be performed on the target threshold written to the CSR configuration register. For example, the target threshold can be limited to a range that is not less than 1 and not greater than a preset upper limit. This preset upper limit can be related to the snooping transaction cache depth of the corresponding C2C cross-slice node, the cache depth of the intra-slice routing node, or the maximum number of packets allowed in transit by the system. This range check can reduce the risk of cross-slice transmission performance degrading due to an excessively low threshold configuration, or the risk of rate limiting effectiveness weakening due to an excessively high threshold configuration.

[0105] Therefore, the comparison process in step 104 can be combined with target C2C cross-slice node identification, CSR threshold configuration, hardware cache resource scale, and system topology characteristics, enabling the transmission judgment of cross-slice eavesdropping transactions to be executed separately according to different C2C directions. This allows for targeted prevention and control of directions prone to cross-slice channel congestion, while ensuring the continued progress of local eavesdropping transactions and eavesdropping transactions in unrestricted directions.

[0106] Step 105: If the in-transit count value does not reach the preset threshold, then the cross-shard eavesdropping transaction is allowed to be sent, and the in-transit count value corresponding to the target C2C cross-shard node is updated.

[0107] Specifically, if the in-transit count value does not reach the preset threshold, the cross-chip eavesdropping transaction is allowed to be transmitted. This can be implemented as follows: After confirming that the in-transit count value corresponding to the target C2C cross-chip node is less than the preset threshold, the consistency master node determines the cross-chip eavesdropping transaction as a currently transmittable transaction and outputs it to the eavesdropping transaction transmission path, so as to send it to the target C2C cross-chip node via the intra-chip routing node. After receiving the cross-chip eavesdropping transaction, the target C2C cross-chip node can continue to send it to the chip where the target requesting node is located through the inter-chip link, or send it to the next-hop chip leading to the chip where the target requesting node is located.

[0108] Here, allowing transmission can be understood as the consistency master node removing the transmission restriction on the cross-slice probe transaction, enabling it to participate in arbitration and output during the current or subsequent transmission cycles. If multiple probe transactions are available to transmit at the same time, the consistency master node can select one of them for transmission according to a preset arbitration method. If the cross-slice probe transaction is selected by arbitration, the consistency master node can encapsulate it into a corresponding transaction transmission unit and output it to the intra-slice routing node through the probe transmission interface.

[0109] In practical applications, cross-slice snooping transactions can be transmitted in the form of Flits. A Flit can be understood as a basic transmission unit used to carry transaction information in a consensus interconnection protocol. A Flit can carry the target node identifier, source node identifier, snooping transaction type, address information, and other control information. The target node identifier indicates the target C2C cross-slice node through which the cross-slice snooping transaction should pass, enabling the intra-slice routing node to route the cross-slice snooping transaction to the corresponding C2C cross-slice node.

[0110] Compared to processing cross-slice snooping transactions only after they have entered the C2C cross-slice node or inter-slice link, in this embodiment, the consistency master node determines whether to allow transmission based on the in-transit count value and a preset threshold corresponding to the target C2C cross-slice node before the cross-slice snooping transaction is transmitted. This allows for directional transmission judgment before the cross-slice snooping transaction enters the intra-slice routing node and the C2C cross-slice node, thereby reducing the continued accumulation of incomplete cross-slice snooping transactions in the direction of the target C2C cross-slice node.

[0111] Furthermore, since the in-transit count value corresponds to the count value of the target C2C cross-chip node, the decision to allow transmission only applies to the cross-chip transmission direction corresponding to that target C2C cross-chip node. In other words, when the transmission conditions are met for a certain direction corresponding to a C2C cross-chip node, cross-chip eavesdropping transactions in that direction can continue to be transmitted. Whether transmission is allowed for other directions corresponding to other C2C cross-chip nodes can be determined separately based on their respective in-transit count values ​​and preset thresholds. This avoids interference between multiple cross-chip directions and makes the transmission control of cross-chip eavesdropping transactions more precise.

[0112] As an optional embodiment, in step 105, updating the in-transit count value corresponding to the target C2C cross-chip node includes: increasing the in-transit count value corresponding to the target C2C cross-chip node when the cross-chip eavesdropping transaction is allowed to be transmitted and the transmission is completed.

[0113] "Completion of transmission" can be understood as the consistency master node having output the cross-slice probe transaction from the probe transmission interface, or the cross-slice probe transaction having been received by the intra-slice routing node and beginning transmission to the target C2C cross-slice node. It can also be understood as the cross-slice probe transaction having left the consistency master node's transmission control range and entering a transmission phase that may consume intra-slice routing resources, C2C cross-slice node resources, or inter-slice link resources. This application's embodiments do not strictly limit this, as long as it reflects that the cross-slice probe transaction has entered the subsequent transmission path.

[0114] In practical applications, the consistency master node can increment the in-transit count corresponding to the target C2C cross-slice node at the same clock cycle as the successful transmission of the cross-slice probe transaction or at a subsequent preset timing point. For example, after the Snoop Flit corresponding to the cross-slice probe transaction is output to the on-chip routing node, the consistency master node can determine the target C2C cross-slice node corresponding to the cross-slice probe transaction based on the target node identifier carried in the Snoop Flit, and increment the in-transit count corresponding to the target C2C cross-slice node by one.

[0115] Optionally, increasing the in-transit count can mean incrementing the corresponding counter by one, or it can mean increasing the value by a preset counting granularity. For example, when each cross-slice eavesdropping transaction corresponds to one requesting node, the in-transit count can be incremented by one for each successfully transmitted cross-slice eavesdropping transaction. When a transaction transmission unit carries multiple eavesdropping targets or multiple sub-transactions, the in-transit count can also be increased accordingly based on the actual number of cross-slice eavesdropping transactions carried.

[0116] This application's embodiments bind the timing of the transit count to the actual transmission behavior of cross-chip snooping transactions, rather than counting only when a transaction is generated. This avoids cross-chip snooping transactions that have been generated but not yet transmitted, or those that remain within the consistency master node due to arbitration not being selected, from prematurely occupying the transit quota of the corresponding C2C cross-chip node, making the transit count more accurately reflect the number of transactions that have entered the cross-chip transmission path.

[0117] Furthermore, the consistency master node can update the transit counts for different directions based on the target C2C cross-shard node identifier. For example, if the first cross-shard probe transaction is sent via the first C2C cross-shard node, the transit count for the first C2C cross-shard node is increased. If the second cross-shard probe transaction is sent via the second C2C cross-shard node, the transit count for the second C2C cross-shard node is increased. In this way, the transit counts for different C2C cross-shard nodes can change independently according to the transaction issuance in their respective directions.

[0118] In summary, step 105 allows the consistency master node to record the occupancy status of the corresponding cross-chip transmission direction while allowing cross-chip eavesdrop transactions to be launched. Subsequently, when the consistency master node prepares to launch a new cross-chip eavesdrop transaction to the same target C2C cross-chip node, it can perform a threshold comparison based on the updated in-transit count, which helps to keep the number of incomplete cross-chip eavesdrop transactions in each C2C cross-chip node direction within a controllable range.

[0119] Step 106: If the in-transit count value reaches the preset threshold, then stop sending the corresponding cross-shard eavesdropping transaction to the target C2C cross-shard node.

[0120] Here, the in-transit count reaching the preset threshold indicates that the number of cross-shard probe transactions sent via the target C2C cross-shard node that have not yet received a corresponding probe response has reached the upper limit allowed in the corresponding direction of the target C2C cross-shard node. In this case, if new cross-shard probe transactions continue to be sent to the target C2C cross-shard node, it may further increase the transaction backlog in that cross-shard direction. Therefore, the consistency master node can suspend sending the corresponding cross-shard probe transactions to the target C2C cross-shard node.

[0121] Stopping the transmission of the corresponding cross-shard probe transaction to the target C2C cross-shard node can be implemented as follows: the consistency master node temporarily refrains from outputting the cross-shard probe transaction to the probe transmission interface, or temporarily prevents the cross-shard probe transaction from participating in the arbitration of the current transmission cycle, or skips the cross-shard probe transaction in the direction of the target C2C cross-shard node during the transmission selection process. In this embodiment, stopping can be implemented by keeping the cross-shard probe transaction in a pending transmission state within the consistency master node, waiting for the in-transit count value corresponding to the target C2C cross-shard node to decrease before resuming the transmission decision.

[0122] For example, the consistency master node can perform blocking control based on the direction of the target C2C cross-shard node. That is, if the in-transit count value corresponding to the first C2C cross-shard node reaches its preset threshold, the consistency master node can suspend cross-shard eavesdropping transactions destined for the first C2C cross-shard node. However, for the second C2C cross-shard node, if the in-transit count value corresponding to that node has not reached the corresponding preset threshold, cross-shard eavesdropping transactions destined for the second C2C cross-shard node can still continue to be processed according to the corresponding issuance rules. Therefore, blocking control can be limited to the direction of a specific C2C cross-shard node, rather than uniformly blocking all cross-shard eavesdropping transactions.

[0123] Therefore, the consistency master node performs a transmit pause based on the in-transit count and preset threshold of the target C2C cross-slice node before the cross-slice probe transaction enters the target C2C cross-slice node. This avoids the accumulation of too many incomplete cross-slice probe transactions in the corresponding cross-slice direction, thereby reducing the risk of continuous occupation of the probe transaction cache resources of the C2C cross-slice node and related intra-slice routing channels. Since the pause decision occurs on the consistency master node side, there is no need to wait for the C2C cross-slice node to return the cache availability status to the consistency master node in real time, nor is it necessary to rely on the intra-slice routing node to provide additional virtual channel resources.

[0124] Furthermore, since the in-transit counts for different C2C cross-shard nodes are independent, when a target C2C cross-shard node direction reaches a threshold, it only affects the transmission of cross-shard probe transactions in that direction. Other cross-shard directions that have not reached the threshold can still continue to transmit, and already transmitted cross-shard probe transactions can continue to wait for the target requesting node to return a probe response. As the probe response returns, the in-transit count for the corresponding direction will decrease. When the in-transit count falls below the preset threshold again, the consistency master node can resume the judgment of transmission of cross-shard probe transactions in that direction. Thus, stopping and resuming can be performed separately for each C2C cross-shard node direction, avoiding mutual interference between different cross-shard directions.

[0125] Further optionally, in step 106, after stopping the transmission of the corresponding cross-segment eavesdropping transaction to the target C2C cross-segment node, the local eavesdropping transaction to be transmitted and the cross-segment eavesdropping transaction to be transmitted can be scheduled separately; continue to determine whether there is a local eavesdropping transaction to be transmitted; if there is a local eavesdropping transaction to be transmitted, then the transmission of the local eavesdropping transaction is allowed.

[0126] The local snooping transaction is a snooping transaction sent to a requesting node located in the same chip as the consistency master node.

[0127] Local snooping transactions and cross-chip snooping transactions can correspond to different launch paths or different scheduling queues. For example, the consistency master node can set up local snooping transaction queues and cross-chip snooping transaction queues. The local snooping transaction queue can be used to cache snooping transactions sent to requesting nodes within the same chip; the cross-chip snooping transaction queue can be used to cache snooping transactions sent to requesting nodes within other chips. For transactions in the cross-chip snooping transaction queue, the consistency master node can make a launch decision based on the in-transit count value of each C2C cross-chip node and a preset threshold. For transactions in the local snooping transaction queue, they can continue to be processed according to the launch rules of the local on-chip routing resources.

[0128] In practical applications, the outputs of both the local and cross-slice probe queues are connected to an output multiplexer (MUX). The MUX merges probe transactions from the two transmit paths and outputs them uniformly to the interface of the consistency master node for subsequent routing. Within the same clock cycle, if both the local and cross-slice probe queues have available probe transmission units to transmit, the MUX selects one unit from both using a round-robin arbitration method, thus preventing one transmission path from occupying output resources for an extended period. This approach achieves unified output for both local and cross-slice probe transactions while ensuring fairness in transmission between different types of probe transactions, improving resource utilization and transaction scheduling efficiency on the consistency master node's probe transmission path.

[0129] When a cross-chip snooping transaction is paused because the in-transit count of the target C2C cross-chip node reaches a preset threshold, the consistency master node can continue to check for the existence of a local snooping transaction. If a local snooping transaction exists, the consistency master node can treat it as a transmittable transaction and send it to the corresponding requesting node via the on-chip routing node within the chip. Since the local snooping transaction does not need to pass through the C2C cross-chip node and does not occupy the inter-chip link resources in the corresponding cross-chip transmission direction, it is unaffected by the target C2C cross-chip node's in-transit count reaching the threshold.

[0130] Using the above method, even if a new cross-chip probe transaction cannot be launched temporarily in a certain cross-chip direction, the probe launch capability of the consistency master node will not be completely shut down. For the same consistency request, if the request corresponds to both a local request node and a cross-chip request node, the local probe transaction sent to the local request node can still proceed during the cross-chip probe transaction pause. For other consistency requests, if their corresponding probe transaction is a local probe transaction or a cross-chip probe transaction in an unrestricted direction, they can also continue to participate in subsequent scheduling.

[0131] Clearly, this embodiment decouples the stop control across chip directions from the normal transmission of local snooping transactions. Since cross-chip snooping transactions and local snooping transactions occupy system resources differently, the pause conditions for cross-chip snooping transactions do not directly affect local snooping transactions, thus reducing the impact of cross-chip congestion on the local consistency processing flow. This allows for both transmission restrictions on cross-chip directions reaching thresholds and the maintenance of the processing continuity of consistency transactions within the chip itself, which is beneficial for improving the overall transaction processing efficiency of multi-chip systems in high cross-chip traffic scenarios.

[0132] Step 107: After receiving the probe response corresponding to the transmitted cross-chip probe transaction, update the in-transit count value corresponding to the source C2C cross-chip node according to the source C2C cross-chip node of the probe response.

[0133] After a cross-shard snooping transaction is launched, the target requesting node, upon receiving the transaction and completing the corresponding cache state processing, can return a snooping response to the consistency master node. The snooping response can be used to characterize the target requesting node's processing result of the snooping transaction, such as the status of the target cache line, whether it carries returned data, and whether it has completed the cache line replica status update.

[0134] For a consistency master node, receiving a probe response corresponding to a previously launched cross-chip probe transaction indicates that the cross-chip probe transaction has completed at least one full probe processing cycle and can release its in-transit occupancy in the corresponding cross-chip direction.

[0135] In this context, the source C2C cross-chip node can be understood as the C2C cross-chip node that the probe response passes through when it returns to the chip where the consistency master node resides, or a C2C cross-chip node that can characterize the cross-chip transmission direction to which the probe response belongs. Since cross-chip probe transactions are counted according to the target C2C cross-chip node when they are transmitted, it is also necessary to determine the source C2C cross-chip node corresponding to the probe response when it returns, so as to reduce and update the on-transit count value of the same cross-chip direction or the corresponding C2C cross-chip node.

[0136] As an optional embodiment, step 107, updating the in-transit count value corresponding to the source C2C cross-chip node based on the source C2C cross-chip node of the probe response, includes: determining the source C2C cross-chip node based on the source node information carried in the probe response, and querying the in-transit count value corresponding to the source C2C cross-chip node; if the cross-chip probe transaction corresponding to the probe response has been completed, then reducing the in-transit count value corresponding to the source C2C cross-chip node. The source node information may include a source node identifier, a source chip identifier, a source C2C cross-chip node identifier, a source node field of the response transaction, or other information that can characterize the return path of the probe response. For example, in an implementation conforming to the CHI protocol, the probe response may carry a source identifier field such as SrcID, and the consistency master node can determine which C2C cross-chip node or which cross-chip transmission direction the probe response originates from based on this source identifier field.

[0137] Here, even if the probe responses corresponding to multiple cross-shard probe transactions are returned out of order, the consistent master node can still assign them to the corresponding C2C cross-shard node based on the source node information carried by each probe response and update the correct in-transit count value.

[0138] Further optionally, in step 107, if the cross-shard listening transaction corresponding to the listening response has been completed, the in-transit count value corresponding to the source C2C cross-shard node is reduced, including: when a transaction response of transaction type SnpResp or SnpRespData is received, determining that the corresponding cross-shard listening transaction has been completed, and performing a decrement operation on the in-transit count value corresponding to the source C2C cross-shard node.

[0139] SnpResp (Snoop Response) can represent a snoop response transaction without data, which can be used to return cache line status, snoop processing results, or other consistency status information. SnpRespData (Snoop Response with Data) can represent a snoop response transaction with data, which can carry the target cache line data along with the snoop response. For the consistency master node, regardless of whether the snoop response carries data, as long as the response indicates that the corresponding cross-shard snoop transaction has been processed and returned by the target requesting node, the in-transit occupancy of the cross-shard snoop transaction in the direction of the corresponding C2C cross-shard node can be considered to have ended. Therefore, the consistency master node can decrement the in-transit count value corresponding to the source C2C cross-shard node by one when it receives SnpResp or SnpRespData.

[0140] It should be noted that the timing of reducing the in-transit count can be related to the moment when the probe response is received, recognized, or processed by the consistency master node. In one implementation, the consistency master node can reduce the corresponding in-transit count after the response transaction enters the consistency master node's response processing logic and is recognized as a valid probe response; in another implementation, it can also reduce the corresponding in-transit count after the probe response is matched with the corresponding transaction context. This application does not limit this, as long as the reduction operation reflects that the corresponding cross-shard probe transaction no longer occupies the in-transit quota in the corresponding direction.

[0141] In this way, step 107 corresponds to step 105: when a cross-slice listening transaction is allowed and transmission is completed, the in-transit count value corresponding to the target C2C cross-slice node is increased; when the corresponding listening response is returned and indicates that the transaction is completed, the in-transit count value corresponding to the source C2C cross-slice node is decreased. Therefore, the number of incomplete transactions in each C2C cross-slice node direction can be dynamically maintained based on the lifecycle of the cross-slice listening transaction from transmission to response return.

[0142] The advantage of this embodiment is that the in-transit count value can represent the number of transactions that have entered the cross-chip transmission path but have not yet received the corresponding probe response. This counting method can cover the transmission process of cross-chip probe transactions in intra-chip routing nodes, C2C cross-chip nodes, inter-chip links, and the internal path of the peer chip, thereby more accurately reflecting the resource occupancy status of the transaction in the cross-chip transmission direction. By releasing the count quota after the response is returned, it is possible to avoid the corresponding direction being unnecessarily blocked due to the count value remaining high for a long time.

[0143] Among them, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, and are used to independently control the transmission of cross-chip eavesdropping transactions in different cross-chip transmission directions.

[0144] Further optionally, the in-transit count values ​​corresponding to the different C2C cross-chip nodes are independent of each other. Specifically, the in-transit count value corresponding to each C2C cross-chip node is maintained separately; the in-transit count value corresponding to each C2C cross-chip node is compared with its corresponding preset threshold; and the cross-chip listening transactions in the corresponding direction of each C2C cross-chip node are controlled according to the comparison results to determine whether to allow transmission, so that the stopping or resumption of the corresponding direction of any C2C cross-chip node does not change the transmission control results of the corresponding directions of other C2C cross-chip nodes.

[0145] In this embodiment, independent maintenance can be understood as each C2C cross-shard node having its own corresponding counting resources, such as independent counters, independent counting fields, or independent entries in a centralized counting table. When the consistency master node launches a cross-shard probe transaction, it updates the corresponding counting resources based on the target C2C cross-shard node. Upon receiving a probe response, it updates the corresponding counting resources based on the source C2C cross-shard node. The count values ​​between different C2C cross-shard nodes are not accumulated, nor are they erroneously released due to responses from other directions.

[0146] This independent maintenance approach is particularly suitable for scenarios with multiple cross-chip directions in multi-chip systems. For example, a chip can connect to different peer chips through different C2C cross-chip nodes, or in a chain topology, it can connect upstream and downstream chips through C2C cross-chip nodes in different directions. If a cross-chip listening transaction in one direction becomes too numerous and reaches a threshold, that direction can be temporarily restricted. However, if there is still available quota in transit in another direction, cross-chip listening transactions can continue to be sent. This avoids the congestion in one direction from spreading to a unified suspension of all cross-chip directions.

[0147] Furthermore, when a C2C cross-shard node direction is stopped, its recovery is determined by the response status of that direction's own snooping. As SnpResp or SnpRespData from that direction is returned, the consistency master node decrements the in-transit count for that direction. When this in-transit count falls below a preset threshold, that direction can re-participate in the cross-shard snooping transaction's transmission decision. Other C2C cross-shard node directions do not need to wait for this direction to recover, nor will their transmission control results change due to the recovery of this direction.

[0148] This application embodiment can form an independent closed-loop control based on the C2C cross-chip node direction: before transmission, a threshold judgment is performed based on the target C2C cross-chip node; after transmission, the in-transit count value corresponding to the target C2C cross-chip node is increased; after the response is returned, the corresponding in-transit count value is decreased based on the source C2C cross-chip node. Compared with related technologies that rely on the real-time feedback of the buffer availability status of C2C cross-chip nodes, this application embodiment reflects the completion status of cross-chip eavesdropping transactions through the in-transit count value maintained by the consistency master node, thereby reducing the risk of channel congestion caused by the continuous backlog of cross-chip eavesdropping transactions with lower hardware implementation complexity.

[0149] As an optional embodiment, when there are multiple probe transactions to be launched, the comparison result between the in-transit count value of the C2C cross-shard node corresponding to each probe transaction to be launched and a preset threshold can be obtained; the cross-shard probe transactions corresponding to C2C cross-shard nodes that have reached the preset threshold are marked as non-launchable in this round. Following a polling arbitration method, one probe transaction is selected from the multiple probe transactions marked as launchable in this round for launch. After the in-transit count value corresponding to the cross-shard probe transactions marked as non-launchable in this round drops below the preset threshold, the cross-shard probe transactions marked as non-launchable in this round are restored to the launchable state.

[0150] In the above optional embodiments, when multiple probe transactions awaiting launch exist simultaneously within the consistency master node, these multiple probe transactions can correspond to different requesting nodes or different C2C cross-shard node directions. For example, the same consistency request may generate multiple probe transactions sent to different requesting nodes, and multiple consistency requests may also generate their own probe transactions separately. To select among multiple probe transactions awaiting launch, the consistency master node can set up a probe transaction queue and screen and arbitrate the candidate probe transactions in the queue before launch.

[0151] The polling arbitration method can be understood as a scheduling method that selects the transaction to be launched from among multiple candidate listener transactions according to a preset polling order. This method can avoid the long-term fixed selection of a certain candidate transaction or a transaction in a certain direction, thereby reducing the probability that other candidate transactions will not get a launch opportunity for a long time. For multiple listener transactions that have not been stopped, the consistency master node can select one listener transaction to output through the listener launch interface according to the polling pointer, polling priority, or other polling status.

[0152] For example, the RR (Round Robin) arbitration method can be used to select one of the multiple transmittable probe transactions to transmit in the order of the round-robin, so as to avoid a certain requesting node or a certain transmission direction occupying the transmission opportunity for a long time.

[0153] For example, a polling arbitration method, a weighted polling arbitration method, a fixed priority arbitration method, or a combination thereof can be used to select one of the multiple transmittable snooping transactions for transmission.

[0154] In this embodiment, before executing polling arbitration, the consistency master node can first obtain the comparison result between the corresponding in-transit count value and a preset threshold based on the C2C cross-shard nodes corresponding to each cross-shard probe transaction to be launched. If the in-transit count value of the C2C cross-shard node corresponding to a certain cross-shard probe transaction has reached the preset threshold, then the cross-shard probe transaction can be marked as unlaunchable in this round. Here, unlaunchable in this round can be understood as the transaction not participating in arbitration during the current launch selection period, rather than indicating that the transaction is canceled or discarded.

[0155] In some embodiments, the aforementioned marking can be implemented using masking information. For example, the consistency master node can generate corresponding valid or invalid bits for each candidate requesting node or each candidate listening transaction in the cross-shard listening transaction queue. When the in-transit count value in the direction corresponding to a candidate listening transaction reaches a preset threshold, the valid bit corresponding to the candidate listening transaction is set to invalid, or the candidate listening transaction is masked by a masking signal so that it does not participate in the current round of polling arbitration. When the in-transit count value of the corresponding C2C cross-shard node drops below the preset threshold, the mask can be removed, restoring the candidate listening transaction to a transmittable state.

[0156] This embodiment combines the transit count comparison results with the polling arbitration process, enabling the consistent master node to automatically skip cross-shard directions that are currently unsuitable for continued transmission when selecting a transmission target from multiple candidate snooping transactions, rather than stopping the entire snooping transmission path simply because a certain direction has reached a threshold. In this way, even with multiple cross-shard directions or multiple requesting nodes, directions that have not reached the threshold can still participate in the transmission selection, thereby improving the utilization rate of the snooping transmission path.

[0157] Furthermore, this method can also prevent a single cross-slice direction from occupying a transmission opportunity for an extended period. If there are many cross-slice eavesdropping transactions in a certain C2C cross-slice node direction, its in-transit count may reach a preset threshold earlier. At this time, by using a mask or a "cannot transmit in this round" flag, candidate transactions in that direction can be temporarily excluded, allowing other directions that have not reached the threshold or local eavesdropping transactions to obtain transmission opportunities. After the eavesdropping response from that direction returns and the in-transit count decreases, that direction can resume participating in arbitration. Thus, a better balance can be achieved between rate limiting control and transmission fairness.

[0158] Optionally, local snooping transactions and cross-chip snooping transactions to be launched can be scheduled separately. When both local snooping transactions and cross-chip snooping transactions are available to be launched within the same launch cycle, one of the snooping transactions is selected to be launched through the same snooping launch interface according to a preset arbitration method.

[0159] For example, the consistency master node can set up a local snooping transaction queue and a cross-chip snooping transaction queue. The local snooping transaction queue is used to cache snooping transactions sent to requesting nodes within the same chip, while the cross-chip snooping transaction queue is used to cache snooping transactions sent to requesting nodes in other chips. When selecting candidate transactions, the cross-chip snooping transaction queue can read the in-transit count value and preset threshold corresponding to each C2C cross-chip node, and block directions that reach the threshold; the local snooping transaction queue can select according to the local intra-chip routing transmission rules. The above independent queue method can further save queue area and ensure scheduling flexibility.

[0160] Furthermore, local snooping transactions and cross-shard snooping transactions can share the same snooping launch interface. That is, a consistent master node can launch at most one snooping transaction through this launch interface within a launch cycle. When both the local snooping transaction queue and the cross-shard snooping transaction queue have launchable transactions, the consistent master node can select one of the two types of transactions to launch by outputting arbitration logic. This preset arbitration method can be round-robin arbitration, fixed-priority arbitration, weighted round-robin arbitration, or other arbitration methods that enable launch selection.

[0161] By scheduling local and cross-chip snooping transactions separately, cross-chip transmit restrictions can prevent local snooping transactions from being unable to transmit. In other words, when a cross-chip snooping transaction is marked as untransmittable because its corresponding C2C cross-chip node has reached a threshold, a local snooping transaction can still participate in transmit arbitration as a candidate transaction. This reduces the impact of cross-chip congestion on local consistency transaction processing and prevents the snooping transmit interface of the consistency master node from becoming idle or shut down due to cross-chip restrictions.

[0162] Further optionally, if the in-transit count values ​​corresponding to multiple C2C cross-shard nodes all reach their respective preset thresholds, then the transmission of corresponding cross-shard eavesdropping transactions to the multiple C2C cross-shard nodes is stopped, while the transmission of local eavesdropping transactions continues to be allowed; when the in-transit count value corresponding to any of the multiple C2C cross-shard nodes drops below the corresponding preset threshold, the transmission of corresponding cross-shard eavesdropping transactions to any of the C2C cross-shard nodes is resumed.

[0163] For example, when all cross-chip directions reach their respective preset thresholds, the consistency master node can pause the issuance of all cross-chip snoop transactions, but this pause does not affect the issuance of local snoop transactions. At this time, if there are still local snoop transactions waiting to be issued in the local snoop transaction queue, the consistency master node can continue to issue local snoop transactions through the snoop issuance interface to maintain the progress of the internal consistency process of this chip.

[0164] In some embodiments, recovery across chip directions can be triggered by changes in the on-transit count value of each direction. For example, when a C2C cross-chip node direction returns a probe response, the on-transit count value corresponding to that direction can be reduced. If the reduced on-transit count value is lower than a preset threshold for that direction, the consistency master node can remove the non-emitting flag for that direction, allowing the corresponding cross-chip probe transaction to re-participate in candidate selection and polling arbitration. Other C2C cross-chip node directions that are still above the preset threshold can remain in a suspended state.

[0165] This embodiment further demonstrates the independent control relationship between different C2C cross-chip node directions. Even if multiple directions reach the threshold simultaneously, each direction can resume independently based on its own probe response return, without waiting for all directions to meet the resumption conditions simultaneously. This avoids the control dependency of one side stopping affecting the other side, enabling multi-chip systems in chain topologies, ring topologies, or other complex topologies to gradually resume cross-chip probe transaction transmission based on the actual transaction completion status of each cross-chip direction.

[0166] Through the aforementioned scheduling, masking, and round-robin arbitration mechanisms, the consistency master node can achieve finer-grained launch selection among multiple candidate snooping transactions: cross-chip directions that have reached the threshold will temporarily not participate in launch, while cross-chip directions and local snooping transactions that have not reached the threshold can still participate in launch. This limits the continuous accumulation of cross-chip snooping transactions in specific C2C directions while maintaining the processing capacity of other directions and local consistency transactions, thereby improving the stability and throughput efficiency of multi-chip systems in high-concurrency consistency access scenarios.

[0167] by Figure 3Taking the three-chip chain topology shown as an example, the working principle of the embodiments of this application is explained in general. When the cross-chip snooping traffic in the system increases, the in-transit counter of the C2C cross-chip node in CHIP 1 targeting CHIP 2 reaches the threshold set by the CSR configuration register first. HN-F then blocks the cross-chip snooping transmission targeting CHIP 2, but cross-chip snooping and local snooping targeting CHIP 0 can still be transmitted normally. During this period, snooping transactions sent to CHIP 2 in CHIP 1 continue to receive snooping responses, and the in-transit counter in the CHIP 2 direction gradually decreases; when the counter drops below the threshold, the cross-chip snooping transmission in that direction automatically resumes. Since the in-transit counter values ​​corresponding to different C2C cross-chip nodes are independent of each other, that is, each C2C cross-chip node counts and limits independently, the blocking and recovery processes of different cross-chip transmission directions are not coupled. Therefore, in the chain topology scenario, there will be no situation where blocking in one direction further affects the control dependency of the other direction, fundamentally avoiding the deadlock risk caused by the continuous accumulation of channel blocking.

[0168] In this embodiment, by counting the in-transit transactions corresponding to different C2C cross-chip nodes and implementing transmission control before transmission based on the comparison between the in-transit count value in the corresponding direction and a preset threshold, independent flow limiting can be applied to different cross-chip transmission directions, avoiding excessive backlog of cross-chip probe transactions in a single direction that could lead to channel congestion. Since this scheme uses the number of cross-chip probe transactions that have been sent but not yet received a probe response as the control basis, it does not require the addition of virtual channels or rely on real-time feedback from C2C ​​cross-chip nodes. This reduces the risk of congestion and deadlock in cross-chip probe transactions, improves the reliability and stability of multi-chip consistent transaction transmission, and is suitable for dual-chip, chained multi-chip, and other complex interconnection topology scenarios.

[0169] The above describes a method for transmission control of cross-chip consistency transactions in the embodiments of this application. The following describes the transmission control system for cross-chip consistency transactions that executes the above method.

[0170] See Figure 5 ,like Figure 5 The diagram shows a structural schematic of a cross-chip consistency transaction transmission control system. The cross-chip consistency transaction transmission control device in this embodiment can achieve the above-described... Figure 4The steps of the cross-chip consistency transaction transmission control method executed in the corresponding embodiments are described below. The functions implemented by the cross-chip consistency transaction transmission control system can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions, and these modules can be software and / or hardware. The cross-chip consistency transaction transmission control system may include a consistency master node, a request node, an on-chip routing node, and a C2C cross-chip node for connecting different chips. The implementation of these functions can be found in [reference needed]. Figure 4 The operations performed in the corresponding embodiments will not be described in detail here. Further optionally, the transmission control device for cross-chip consistency transactions includes the following parts: The consistency master node is configured to receive consistency requests and query directory information based on the consistency requests to determine the requesting node holding a copy of the target cache line; determine whether the probe transaction to be launched is a cross-chip probe transaction based on the chip location of the requesting node; before launching the cross-chip probe transaction, determine the target C2C cross-chip node corresponding to the cross-chip probe transaction and obtain the in-transit count value corresponding to the target C2C cross-chip node. The in-transit count value is used to count the number of cross-chip probe transactions launched through the corresponding C2C cross-chip node that have not yet received a corresponding probe response; compare the in-transit count value corresponding to the target C2C cross-chip node with a preset threshold; if the in-transit count value does not reach the preset threshold, the launch of the cross-chip probe transaction is allowed, and the in-transit count value corresponding to the target C2C cross-chip node is updated; if the in-transit count value reaches the preset threshold, the launch of the cross-chip probe transaction is stopped. The target C2C cross-chip node transmits a corresponding cross-chip snooping transaction; upon receiving a snooping response corresponding to the transmitted cross-chip snooping transaction, it updates the in-transit count value corresponding to the source C2C cross-chip node based on the source C2C cross-chip node of the snooping response; the requesting node is configured to hold a copy of the target cache line and respond to the snooping transaction transmitted by the consistency master node to return a corresponding snooping response to the consistency master node; the intra-chip routing node is configured to forward transactions transmitted between the consistency master node, the requesting node, and the C2C cross-chip node within the same chip; the C2C cross-chip node is configured to forward cross-chip snooping transactions and / or snooping responses corresponding to cross-chip snooping transactions between the same chip and other chips; wherein, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, and are used to perform independent transmission control of cross-chip snooping transactions in different cross-chip transmission directions.

[0171] In some implementations, when the consistency master node determines whether the snooping transaction to be transmitted is a cross-chip snooping transaction based on the chip location of the requesting node, it is configured as follows: The requesting node holding the target cache line copy is determined according to the Snoop Filter; it is then determined whether the chip where the requesting node is located is the same as the chip where the consistency master node is located; if the chip where the requesting node is located is the same as the chip where the consistency master node is located, the snoop transaction sent to the requesting node is determined as a local snoop transaction; if the chip where the requesting node is located is different from the chip where the consistency master node is located, the snoop transaction sent to the requesting node is determined as a cross-chip snoop transaction.

[0172] In some implementations, the consistency master node, when determining the target C2C cross-shard node corresponding to the cross-shard snooping transaction, is configured as follows: Based on the target address and / or target request node information corresponding to the cross-chip snooping transaction, query the address mapping information maintained by the consistency master node; based on the address mapping information, determine the target C2C cross-chip node that the cross-chip snooping transaction needs to pass through when it is sent from the chip where the consistency master node is located, and obtain the target node identifier corresponding to the target C2C cross-chip node; carry the target node identifier in the snooping transaction to be sent, so that the snooping transaction is transmitted to the chip where the target request node is located via the target C2C cross-chip node.

[0173] In some implementations, when the consistency master node updates the in-transit count value corresponding to the target C2C cross-shard node, it is configured to increment the in-transit count value corresponding to the target C2C cross-shard node when the cross-shard snooping transaction is allowed to be sent and the sending is completed.

[0174] When the consistency master node updates the in-transit count value corresponding to the source C2C cross-shard node based on the source C2C cross-shard node of the probe response, it is configured to: determine the source C2C cross-shard node based on the source node information carried in the probe response, and query the in-transit count value corresponding to the source C2C cross-shard node; if the cross-shard probe transaction corresponding to the probe response has been completed, then decrease the in-transit count value corresponding to the source C2C cross-shard node.

[0175] In some implementations, the consistency master node, if the cross-shard snooping transaction corresponding to the snooping response has been completed, is configured to, when reducing the in-transit count value corresponding to the source C2C cross-shard node, determine that the corresponding cross-shard snooping transaction has been completed upon receiving a transaction response of transaction type SnpResp or SnpRespData, and decrement the in-transit count value corresponding to the source C2C cross-shard node by one.

[0176] In some implementations, the preset threshold is obtained by setting a configuration status register.

[0177] The consistency master node is further configured to: before comparing the in-transit count value corresponding to the target C2C cross-shard node with a preset threshold, read the CSR configuration register corresponding to the target C2C cross-shard node to obtain the preset threshold corresponding to the target C2C cross-shard node; wherein, the preset threshold corresponding to different C2C cross-shard nodes is configured independently.

[0178] In some implementations, the preset threshold is the sum of the snooping transaction cache depth of the corresponding C2C cross-slice node and the cache depth of the intra-slice routing node.

[0179] The consistency master node is further configured to: determine the target threshold corresponding to the C2C cross-chip node based on the chip interconnect topology of the multi-chip system, the cache depth of the C2C cross-chip node, the cache depth of the on-chip routing node, and / or the cross-chip snooping transaction traffic; if the target threshold is less than 1, limit the threshold written to the corresponding CSR configuration register to 1; if the target threshold is not less than 1, write the target threshold to the CSR configuration register of the corresponding C2C cross-chip node to update the preset threshold of the corresponding C2C cross-chip node; wherein, the CSR configuration registers corresponding to different C2C cross-chip nodes are written independently, so that the preset thresholds corresponding to different C2C cross-chip nodes are independently and dynamically adjusted as the network topology and network traffic of the multi-chip system change.

[0180] In some implementations, when there are multiple probe transactions to be launched, the consistency master node is further configured to: obtain the comparison result of the in-transit count value of the C2C cross-shard node corresponding to each probe transaction to be launched with a preset threshold; mark the cross-shard probe transactions corresponding to the C2C cross-shard nodes whose comparison results indicate that they have reached the preset threshold as unlaunchable in this round; select one probe transaction from the multiple probe transactions marked as launchable in this round according to the round-robin arbitration method; and restore the cross-shard probe transactions marked as unlaunchable in this round to the launchable state after the in-transit count value corresponding to the cross-shard probe transactions marked as unlaunchable in this round drops below the preset threshold.

[0181] In this embodiment of the application, the above system reduces the risk of blocking and deadlock and improves the reliability of multi-chip consistency transaction processing by independently limiting the rate of probe transactions in different cross-chip directions and updating the status in transit in combination with the probe response. This is done without adding new virtual channels or relying on real-time feedback.

[0182] This application also proposes a microarchitecture for the internal snooping transmission path of the consensus master node. This transmission path mainly includes a polling arbitration unit, a consensus master node request entry (HN-F entry), a snoop filter catalog, a multiplexer (MUX), a register slice module (regslice), a snoop queue, a snoop system address mapping table (Snoop SAM), an in-transit cross-slice snooping counter, in-transit snooping count comparison logic, transmission status control logic, a configuration status register (CSR), and a consensus master node CHI interface (HN-F CHI Interface). The system includes a polling arbitration unit for selecting from multiple pending consistency requests, a consistency master node request entry for storing consistency request processing information, a snooping filter directory for recording request nodes holding target cache line copies, a snooping queue for caching and scheduling snooping transactions, a snooping system address mapping table for determining target inter-chip connection nodes based on addresses, an in-transit cross-chip snooping counter for counting the number of cross-chip snooping transactions that have been sent but have not yet received a response, a launch status control logic for shielding targets that cannot be launched temporarily based on the status of the corresponding direction, a configuration status register for configuring the in-transit quantity threshold corresponding to each inter-chip connection direction, and a consistency master node CHI interface for sending selected snooping transactions to subsequent interconnection paths.

[0183] The specific functions of the above-mentioned units or modules can be found in the above embodiments, and will not be repeated here.

[0184] This application also relates to a chip that includes at least one processor and an interface circuit. The processor includes multiple vector storage units and is used to execute instruction and / or data interaction through the interface circuit, causing the chip to perform the cross-chip consistency transaction transmission control method of any of the above embodiments.

[0185] In one possible implementation, the chip may also directly include a memory that stores computer programs or computer instructions.

[0186] For example, the memory can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM).

[0187] This application also relates to a processor, which includes multiple storage units for calling computer programs or computer instructions stored in the memory to cause the processor to execute the cross-chip consistency transaction transmission control method described in any of the above embodiments. For example, in this application embodiment, the processor is an integrated circuit chip with signal processing capabilities. For instance, the processor may be an FPGA, a general-purpose processor, a DSP, an ASIC, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, a SoC, a CPU, a network processor (NP), a microcontroller unit (MCU), a PLD, or other integrated chips, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0188] In one possible implementation, this application also provides a computer-readable storage medium storing program code that, when executed on a computer, causes the computer to perform the above-described method embodiments.

[0189] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0190] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0191] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or modules, and may be electrical, mechanical, or other forms.

[0192] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0193] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0194] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0195] The computer program product includes one or more computer instructions. When the computer program is loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0196] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this application to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. A method for transmission control of cross-chip consistent transactions, characterized in that, The method is applied to a multi-chip system, wherein each chip in the multi-chip system includes a consistency master node, a request node, an on-chip routing node, and a C2C cross-chip node for connecting different chips. The method includes: The consistency master node receives the consistency request and queries the directory information based on the consistency request to determine the requesting node that holds a copy of the target cache line. Based on the chip location of the requesting node, determine whether the eavesdropping transaction to be transmitted is a cross-chip eavesdropping transaction; Before launching the cross-slice eavesdropping transaction, the target C2C cross-slice node corresponding to the cross-slice eavesdropping transaction is determined, and the in-transit count value corresponding to the target C2C cross-slice node is obtained. The in-transit count value is used to count the number of cross-slice eavesdropping transactions launched through the corresponding C2C cross-slice node that have not yet received the corresponding eavesdropping response. Compare the in-transit count value corresponding to the target C2C cross-slice node with a preset threshold; If the in-transit count value does not reach the preset threshold, the cross-shard eavesdropping transaction is allowed to be launched, and the in-transit count value corresponding to the target C2C cross-shard node is updated. If the in-transit count reaches the preset threshold, then the transmission of the corresponding cross-slice eavesdropping transaction to the target C2C cross-slice node is stopped; after receiving the eavesdropping response corresponding to the transmitted cross-slice eavesdropping transaction, the in-transit count corresponding to the source C2C cross-slice node is updated according to the source C2C cross-slice node of the eavesdropping response. Among them, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, and are used to independently control the transmission of cross-chip eavesdropping transactions in different cross-chip transmission directions.

2. The method for transmission control of cross-chip consistent transactions according to claim 1, characterized in that, The step of determining whether the snooping transaction to be transmitted is a cross-chip snooping transaction based on the chip location of the requesting node includes: The requesting node holding a copy of the target cache line is determined based on the listening filter directory; Determine whether the chip where the requesting node is located is the same as the chip where the consistency master node is located; If the chip where the requesting node is located is the same as the chip where the consistency master node is located, then the snooping transaction sent to the requesting node is determined to be a local snooping transaction. If the chip where the requesting node is located is different from the chip where the consistency master node is located, then the snooping transaction sent to the requesting node is determined to be a cross-chip snooping transaction.

3. The method for transmission control of cross-chip consistent transactions according to claim 1, characterized in that, The process of determining the target C2C cross-shard node corresponding to the cross-shard eavesdropping transaction includes: Based on the target address and / or target request node information corresponding to the cross-shard snooping transaction, query the address mapping information maintained by the consistency master node; Based on the address mapping information, determine the target C2C cross-chip node that the cross-chip snooping transaction needs to pass through when it is sent from the chip where the consistency master node is located, and obtain the target node identifier corresponding to the target C2C cross-chip node; The target node identifier is carried in the probe transaction to be transmitted, so that the probe transaction is transmitted to the chip where the target request node is located via the target C2C cross-chip node.

4. The method for transmission control of cross-chip consistent transactions according to claim 1, characterized in that, Updating the in-transit count value corresponding to the target C2C cross-shard node includes: When the cross-chip eavesdropping transaction is allowed to be transmitted and the transmission is completed, the in-transit count value corresponding to the target C2C cross-chip node is incremented; The step of updating the in-transit count value corresponding to the source C2C cross-shard node based on the source C2C cross-shard node of the eavesdropping response includes: The source C2C cross-shard node is determined based on the source node information carried in the probe response, and the in-transit count value corresponding to the source C2C cross-shard node is queried. If the cross-shard snooping transaction corresponding to the snooping response has been completed, then the in-transit count value corresponding to the source C2C cross-shard node is reduced.

5. The method for transmission control of cross-chip consistent transactions according to claim 4, characterized in that, If the cross-shard eavesdropping transaction corresponding to the eavesdropping response has been completed, then the in-transit count value corresponding to the source C2C cross-shard node is reduced, including: When a transaction response of type SnpResp or SnpRespData is received, it is determined that the corresponding cross-shard snooping transaction is completed, and the in-transit count value corresponding to the source C2C cross-shard node is decremented by one.

6. The method for transmission control of cross-chip consistent transactions according to claim 1, characterized in that, The preset threshold is obtained by configuring the status register; Before comparing the in-transit count value corresponding to the target C2C cross-shard node with a preset threshold, the method further includes: Read the CSR configuration register corresponding to the target C2C cross-slice node to obtain the preset threshold corresponding to the target C2C cross-slice node; wherein, the preset threshold corresponding to different C2C cross-slice nodes is configured independently.

7. The method for transmission control of cross-chip consistent transactions according to claim 6, characterized in that, The preset threshold is the sum of the snooping transaction cache depth of the corresponding C2C cross-slice node and the cache depth of the intra-slice routing node; the method further includes: Based on the chip interconnect topology of the multi-chip system, the cache depth of the C2C cross-chip node, the cache depth of the on-chip routing node, and / or the cross-chip eavesdropping transaction traffic, determine the target threshold corresponding to the C2C cross-chip node; If the target threshold is less than 1, the threshold for writing to the corresponding CSR configuration register will be limited to 1. When the target threshold is not less than 1, the target threshold is written to the CSR configuration register of the corresponding C2C cross-chip node to update the preset threshold of the corresponding C2C cross-chip node; wherein, the CSR configuration registers corresponding to different C2C cross-chip nodes are written independently, so that the preset thresholds corresponding to different C2C cross-chip nodes are independently and dynamically adjusted as the network topology and network traffic of the multi-chip system change.

8. The method for transmission control of cross-chip consistent transactions according to claim 1, characterized in that, When there are multiple eavesdropping transactions to be transmitted, the method further includes: Obtain the comparison result between the in-transit count value of each eavesdropping transaction to be launched and the preset threshold; The comparison results indicate that the cross-shard eavesdropping transactions corresponding to C2C cross-shard nodes that have reached the preset threshold are marked as non-transmittable in this round. According to the polling arbitration method, one spying transaction is selected from the multiple spying transactions marked as eligible to be launched in this round for launch; Once the in-transit count value corresponding to a cross-chip eavesdropping transaction marked as non-emittable in this round drops below the preset threshold, the cross-chip eavesdropping transaction marked as non-emittable in this round will be restored to an emittable state.

9. A transmission control system for cross-chip consistent transactions, characterized in that, The system is deployed on at least one chip in a multi-chip system. The system includes a consistency master node, request nodes, on-chip routing nodes, and C2C cross-chip nodes for connecting different chips. The consistency master node is configured to execute the transmission control method for cross-chip consistency transactions as described in any one of claims 1 to 8; The requesting node is configured to hold a copy of the target cache line and respond to a snoop transaction launched by the consistency master node to return a corresponding snoop response to the consistency master node; The on-chip routing node is configured to forward transactions transmitted between the consistency master node, the request node, and the C2C cross-chip node within the chip. The C2C cross-chip node is configured to forward cross-chip snooping transactions and / or snooping responses corresponding to cross-chip snooping transactions between this chip and other chips; Among them, the in-transit count values ​​corresponding to different C2C cross-chip nodes are independent of each other, and are used to independently control the transmission of cross-chip eavesdropping transactions in different cross-chip transmission directions.

10. A chip comprising computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the transmission control method for cross-chip consistent transactions as described in any one of claims 1-8.

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