A Behavioral Modeling Method for Multi-Chip Parallel SiC-MOSFETs

Abstract

This invention discloses a behavioral modeling method for multi-chip parallel SiC-MOSFETs, belonging to the field of power electronics technology. The method first measures the transfer and output characteristic curves of each parallel SiC-MOSFET chip and extracts key parameters. Then, it establishes an equivalent circuit for the multi-chip parallel connection, including parasitic parameters and drive loops. Finally, combining the extracted parameters, based on Kirchhoff's voltage and current laws, it establishes the power loop equation, gate drive loop equation, and node current balance equation of the equivalent circuit, and unifies them into a state-space behavioral model. This invention can accurately characterize the dynamic characteristics and input-output relationships of multi-chip parallel SiC-MOSFET modules. The model structure is automatically determined according to the number of parallel chips, possessing good scalability, versatility, and parameter portability.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology and relates to a behavioral modeling method for multi-chip parallel SiC-MOSFETs. Background Technology

[0002] Double-pulse testing is a widely used testing method for evaluating the characteristics of switching devices, such as... Figure 11 As shown, the double-pulse test involves giving the switching device under test two pulses as drive control signals. The falling edge of the first pulse is used as the observation time of the turn-off process, while the rising edge of the second pulse is used as the observation time of the turn-on process.

[0003] With the rapid development of power electronics technology, silicon carbide (SiC) power devices have gradually become important components in new energy vehicles, power converters, and high-voltage direct current transmission due to their excellent performance, such as high voltage withstand capability, high-frequency switching capability, and low conduction loss. To meet the demands of high-current applications, a single device often cannot withstand the system-level current; therefore, multi-chip parallel SiC-MOSFET modules have become a common structure for improving module current carrying capacity and power density. However, multi-chip parallel systems exhibit highly complex dynamic behavior in practical operation. Their overall performance depends not only on the static characteristics of individual devices but also on the combined effects of inter-chip parasitic parameters, circuit topology, differences in drive signals, and environmental conditions.

[0004] Existing device modeling methods mainly focus on single-transistor characteristics or empirical equivalent circuits, typically employing fixed parameters or idealized assumptions for simulation. While these methods can meet basic requirements in single-chip modeling, they fail to accurately depict the overall dynamic response and input-output relationships of the system in multi-chip parallel scenarios, and are also difficult to efficiently utilize in circuit-level simulations. Specifically, on the one hand, existing models cannot reflect the interactions and parasitic effects between multiple chips; on the other hand, as the number of parallel chips increases, the complexity of the model significantly increases, making it difficult for traditional methods to provide a scalable, unified, and accurate modeling framework.

[0005] Therefore, there is an urgent need to propose a novel behavioral modeling method for multi-chip parallel SiC-MOSFETs to achieve accurate prediction of the dynamic characteristics, frequency domain response, and system-level behavior of multi-chip parallel SiC-MOSFET modules. Summary of the Invention

[0006] The technical solution of the present invention is used to solve the problem that existing device modeling methods mainly target single-transistor characteristics or use empirical equivalent circuits, based on fixed parameters or idealized assumptions, and cannot accurately reflect the complex dynamic response, inter-chip interaction and the comprehensive influence of parasitic parameters in multi-chip parallel systems.

[0007] The present invention solves the above-mentioned technical problems through the following technical solutions:

[0008] This invention provides a behavioral modeling method for multi-chip parallel SiC-MOSFETs, comprising the following steps: Step 1: Use a static tester to measure the transfer characteristic curve and output characteristic curve of each SiC-MOSFET chip connected in parallel; Step 2: Based on the transfer characteristic curve and output characteristic curve, extract the key parameters of each SiC-MOSFET chip using curve fitting method; Step 3: Establish the equivalent circuit of the multi-chip parallel SiC-MOSFET, including parasitic inductance parameters, junction capacitance parameters, and drive circuit parameters; Step 4: Combining the extracted key parameters, establish the power loop equation, gate drive loop equation, and node current balance equation of the equivalent circuit based on Kirchhoff's voltage law and current law, and transform them into a state-space behavior model. Step 5: In the simulation environment, by setting the time step, the state-space behavior model is iteratively numerically solved to obtain the switching waveform of the multi-chip parallel SiC-MOSFET.

[0009] Furthermore, the power loop equation includes the drain parasitic inductance, source parasitic inductance, drain-source voltage, load inductance, load resistance, and DC bus voltage for the corresponding parallel branch; the gate drive loop equation includes the gate parasitic inductance, gate drive resistance, drive signal voltage, gate-source voltage, and source parasitic inductance for the corresponding chip; the node current balance equation includes the drain-source capacitance current, gate-source capacitance current, gate current, drain current, and the current of the equivalent on-resistance or body diode resistance controlled by the switching state function for the corresponding chip.

[0010] Furthermore, the general form of the state-space behavior model is: , Where x is the state variable vector, Let be the derivative of the state variable vector, u be the input signal vector, y be the output signal vector, and A, B, C, and D be the system matrices.

[0011] Furthermore, the dimensions of the state variable vector and the output signal vector are 4N+1, where N is the total number of switching transistors. The state variables include at least the drain current, gate current, gate-source voltage, and drain-source voltage of each chip. The input signal vector includes at least the gate drive signals of the upper bridge arm switching device module and the lower bridge arm switching device module.

[0012] Furthermore, the aforementioned behavioral modeling method for multi-chip parallel SiC-MOSFETs is applicable to the behavioral modeling of a dual-pulse test half-bridge circuit for switching devices, where both the upper and lower bridge arm switching device modules of the dual-pulse test half-bridge circuit are composed of multiple parallel SiC-MOSFET chips.

[0013] The present invention also provides an electronic device, including a memory and a processor, wherein the memory is used to store a program that supports the processor in executing the above-described behavioral modeling method for multi-chip parallel SiC-MOSFETs, and the processor is configured to execute the program stored in the memory.

[0014] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the above-described behavioral modeling method for multi-chip parallel SiC-MOSFETs.

[0015] This invention also provides a state-space behavioral model of a multi-chip parallel SiC-MOSFET based on the above-described behavioral modeling method for multi-chip parallel SiC-MOSFETs. This model can automatically expand or reduce its order according to the number of parallel chips.

[0016] Furthermore, the state-space behavior model can accurately simulate the impact of parasitic effects between chips, differences in driving signals, and mutual coupling on the overall dynamic response of a multi-chip parallel system.

[0017] The present invention also provides a power electronics simulation system, which includes the above-mentioned multi-chip parallel SiC-MOSFET state-space behavior model, for performing switching process simulation and performance prediction on circuits containing multi-chip parallel SiC-MOSFET modules.

[0018] The beneficial effects of this invention are as follows: The behavioral modeling method for multi-chip parallel SiC-MOSFETs provided by this invention extracts parameters based on the actual characteristics of the devices, enabling the established behavioral model to accurately reflect the dynamic characteristics and input-output relationships of the multi-chip parallel system. The specific form of the model is based on Kirchhoff's voltage and current laws, including power loop equations for each parallel branch, gate drive loop equations for each chip, and node current balance equations for each chip. These equations together constitute a set of state equations describing the dynamic behavior of the system. By constructing a state-space model and automatically determining the model order based on the number of parallel chips, the scalability and versatility of the model structure are achieved. The modeling process is simple and efficient, and can be quickly invoked in circuit-level simulation platforms, facilitating module design, performance prediction, and system optimization. Furthermore, the method of this invention has good parameter portability and can be applied to SiC-MOSFET modules of different models and structures, providing a unified modeling tool for multi-chip module development. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of the dual-pulse test half-bridge circuit for the switching device of the present invention; Figure 2 This is a flowchart of the behavioral modeling method for multi-chip parallel SiC-MOSFETs of the present invention; Figure 3 This is the equivalent circuit diagram of the double-pulse test half-bridge circuit of the upper and lower bridge arm switching device modules of Embodiment 1 of the present invention, which uses two SiC-MOSFET chips connected in parallel. Figure 4 This is a schematic diagram of the power loop and gate drive loop of the equivalent circuit of the dual-pulse test half-bridge circuit of the upper and lower bridge arm switching device modules of the present invention, which both use two SiC-MOSFET chips connected in parallel. Figure 5 This is a schematic diagram of the node current of the equivalent circuit of the half-bridge circuit in Embodiment 1 of the present invention, in which both the upper and lower bridge arm switching device modules adopt two SiC-MOSFET chips connected in parallel as switching devices for dual-pulse testing of the half-bridge circuit. Figure 6 This is a simulation result of the behavior model of the half-bridge circuit of the dual-pulse test of the upper and lower bridge arm switching device modules of the present invention, which both use two SiC-MOSFET chips connected in parallel. Figure 7 This is the equivalent circuit diagram of the double-pulse test half-bridge circuit of the upper and lower bridge arm switching device modules of the second embodiment of the present invention, which uses three SiC-MOSFET chips connected in parallel. Figure 8This is a schematic diagram of the power loop and gate drive loop of the equivalent circuit of the dual-pulse test half-bridge circuit of the upper and lower bridge arm switching device modules of the present invention, which both use three SiC-MOSFET chips connected in parallel. Figure 9 This is a schematic diagram of the node current of the equivalent circuit of the half-bridge circuit in Embodiment 2 of the present invention, in which both the upper and lower bridge arm switching device modules adopt three SiC-MOSFET chips connected in parallel as switching devices for dual-pulse testing of the half-bridge circuit. Figure 10 This is a simulation result diagram of the behavior model of the half-bridge circuit of the upper bridge arm switching device module and the lower bridge arm switching device module of the present invention, which both use three SiC-MOSFET chips connected in parallel. Figure 11 This is a waveform diagram of a double-pulse test. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: like Figure 1 The diagram shows a half-bridge circuit for a dual-pulse test of switching devices. Both the upper and lower bridge arm switching device modules are integrated using multiple parallel SiC-MOSFET chips. DC power supply To support the capacitor, This is the gate drive signal for the upper bridge arm switching device module. This is the gate drive signal for the lower bridge arm switching device module. It is the load inductance.

[0022] like Figure 2 As shown, this invention proposes a behavioral modeling method for multi-chip parallel SiC-MOSFETs, used for... Figure 1 Behavioral modeling of the switching device dual-pulse test half-bridge circuit includes the following steps: Step 1: Use a static tester to measure the transfer characteristic curve and output characteristic curve of each SiC-MOSFET chip connected in parallel; Step 2: Based on the transfer characteristic curve and the output characteristic curve, the key parameters of each SiC-MOSFET chip are extracted using the curve fitting method; the key parameters include: threshold voltage, on-resistance, transconductance, gate-source capacitance, gate-drain capacitance, and drain-source capacitance; Step 3: Establish the equivalent circuit of the multi-chip parallel SiC-MOSFET, including parasitic inductance parameters, junction capacitance parameters, and drive circuit parameters; Step 4: Combining the extracted key parameters, establish the power loop equation, gate drive loop equation, and node current balance equation of the equivalent circuit based on Kirchhoff's voltage law and current law, and transform them into a state-space behavior model. The state-space behavior model is a multi-input multi-output structure, where the input is the drive signal and the output is the circuit response. Step 5: In the MATLAB simulation environment, by setting the time step, the output of the previous step is used as the input of the next step to iteratively solve the state-space behavior model numerically, thereby obtaining the switching waveform of the multi-chip parallel SiC-MOSFET.

[0023] Example 1 In this embodiment, both the upper and lower bridge arm switching modules use two SiC-MOSFET chips connected in parallel, resulting in a total of 4 switches (N=4). The upper bridge arm switching module uses switches T1 and T3 connected in parallel, while the lower bridge arm switching module uses switches T2 and T4 connected in parallel. Figure 3 The diagram shows the equivalent circuit. Parasitic inductance for power circuit, For the parasitic resistance of the power circuit, Let T1 be the equivalent drain inductance of the switching device. Let T1 be the equivalent drain-source capacitance of the switching device. Let T1 be the equivalent source inductance of the switching device. Let T1 be the equivalent gate-drain capacitance of the switching device. Let T1 be the equivalent gate-source capacitance of the switching device. Let T1 be the equivalent gate inductance of the switching device. This is the equivalent gate resistance of the switching device T1; Let T3 be the equivalent drain inductance of the switching device. This is the equivalent drain-source capacitance of the switching device T3. Let T3 be the equivalent source inductance of the switching device. This is the equivalent gate-drain capacitance of the switching device T3. This is the equivalent gate-source capacitance of the switching device T3. Let T3 be the equivalent gate inductance of the switching device. This is the equivalent gate resistance of the switching device T3. This is the common gate external resistor for the upper bridge arm switching device module; The equivalent drain inductance of switching device T2 is... Let T2 be the equivalent drain-source capacitance of the switching device. Let T2 be the equivalent source inductance of the switching device. Let T2 be the equivalent gate-drain capacitance of the switching device. Let T2 be the equivalent gate-source capacitance of the switching device. The equivalent gate inductance of switching device T2 is... This is the equivalent gate resistance of the switching device T2; This is the equivalent drain inductance of the switching device T4. This is the equivalent drain-source capacitance of the switching device T4. This is the equivalent source inductance of the switching device T4. This is the equivalent gate-drain capacitance of the switching device T4. This is the equivalent gate-source capacitance of the switching device T4. This is the equivalent gate inductance of the switching device T4. This is the equivalent gate resistance of the switching device T4; This is the common gate external resistor of the lower bridge arm switching device module.

[0024] like Figure 4 As shown, based on Kirchhoff's voltage law, the power loop equation for each parallel branch is given. The power loop equation includes the drain parasitic inductance, source parasitic inductance, drain-source voltage, load inductance, load resistance, and DC bus voltage for that branch. The formula for the power loop equation is as follows: (1) (2) (3) (4) like Figure 4 As shown, based on Kirchhoff's voltage law, the gate drive loop equation for each switching device is given. This equation includes the chip's gate parasitic inductance, gate drive resistance, drive signal voltage, gate-source voltage, and source parasitic inductance. The formula for the gate drive loop equation is as follows: (5) (6) (7) (8) like Figure 5As shown, based on Kirchhoff's current law, the node current balance equation for each switching device is given. This equation includes the drain-source capacitance current, gate-source capacitance current, gate current, drain current, and the current of the equivalent on-resistance or body diode resistance controlled by the switching state function. The formula for the node current balance equation is as follows: (9) (10) (11) (12) (13) (14) (15) (16) (17) By combining formulas (1) to (17) of this embodiment, a state-space behavior model of multi-chip parallel SiC-MOSFETs is formed. The general form of the state-space behavior model is as follows:

[0025]

[0026] in, For the state variable vector, The derivative of the state variable vector. The input signal vector, Let A, B, C, and D be the output signal vectors, and let A, B, C, and D be the system matrices.

[0027] The state variable vector and output signal vector are represented as follows:

[0028] Where N is the total number of switching transistors, and in this embodiment N=4, the order of the behavioral model state space is 4N+1=17.

[0029] The input signal vector is represented as follows:

[0030] in, This is the gate drive signal for the upper bridge arm switching device module. This is the gate drive signal for the lower bridge arm switching device module.

[0031] like Figure 6As shown in the figure, the simulation results are as follows: both the upper and lower bridge arm switching device modules in this embodiment use two SiC-MOSFET chips connected in parallel, that is, the total number of switching transistors N=4. It can be seen from the figure that the behavioral model established in this embodiment can realize the waveform simulation of the circuit switching process well and obtain relatively clear results of voltage and current dynamic changes.

[0032] Example 2 In this embodiment, both the upper and lower bridge arm switching device modules use three SiC-MOSFET chips connected in parallel, resulting in a total of 6 switches (N=6). The upper bridge arm switching device module uses switches T1, T3, and T5 connected in parallel, while the lower bridge arm switching device module uses switches T2, T4, and T6 connected in parallel. Figure 7 The diagram shows the equivalent circuit. Parasitic inductance for power circuit, For the parasitic resistance of the power circuit, Let T1 be the equivalent drain inductance of the switching device. Let T1 be the equivalent drain-source capacitance of the switching device. Let T1 be the equivalent source inductance of the switching device. Let T1 be the equivalent gate-drain capacitance of the switching device. Let T1 be the equivalent gate-source capacitance of the switching device. Let T1 be the equivalent gate inductance of the switching device. This is the equivalent gate resistance of the switching device T1; Let T3 be the equivalent drain inductance of the switching device. This is the equivalent drain-source capacitance of the switching device T3. Let T3 be the equivalent source inductance of the switching device. This is the equivalent gate-drain capacitance of the switching device T3. This is the equivalent gate-source capacitance of the switching device T3. Let T3 be the equivalent gate inductance of the switching device. This is the equivalent gate resistance of the switching device T3. This is the common gate external resistor for the upper bridge arm switching device module; The equivalent drain inductance of switching device T2 is... Let T2 be the equivalent drain-source capacitance of the switching device. Let T2 be the equivalent source inductance of the switching device. Let T2 be the equivalent gate-drain capacitance of the switching device. Let T2 be the equivalent gate-source capacitance of the switching device. The equivalent gate inductance of switching device T2 is... This is the equivalent gate resistance of the switching device T2; This is the equivalent drain inductance of the switching device T4. This is the equivalent drain-source capacitance of the switching device T4. This is the equivalent source inductance of the switching device T4. This is the equivalent gate-drain capacitance of the switching device T4. This is the equivalent gate-source capacitance of the switching device T4. This is the equivalent gate inductance of the switching device T4. This is the equivalent gate resistance of the switching device T4; Let T5 be the equivalent drain inductance of the switching device. This is the equivalent drain-source capacitance of the switching device T5. Let T5 be the equivalent source inductance of the switching device. This is the equivalent gate-drain capacitance of the switching device T5. This is the equivalent gate-source capacitance of the switching device T5. Let T5 be the equivalent gate inductance of the switching device. This is the equivalent gate resistance of the switching device T5; The equivalent drain inductance of switching device T6 is... This is the equivalent drain-source capacitance of the switching device T6. This is the equivalent source inductance of switching device T6. This is the equivalent gate-drain capacitance of switching device T6. This is the equivalent gate-source capacitance of switching device T6. This is the equivalent gate inductance of switching device T6. This is the equivalent gate resistance of the switching device T6; This is the common gate external resistor of the lower bridge arm switching device module.

[0033] like Figure 8 As shown, based on Kirchhoff's voltage law, the power loop equation for each parallel branch is given. The power loop equation includes the drain parasitic inductance, source parasitic inductance, drain-source voltage, load inductance, load resistance, and DC bus voltage for that branch. The formula for the power loop equation is as follows: (1) (2) (3) (4) (5) (6) like Figure 8As shown, based on Kirchhoff's voltage law, the gate drive loop equation for each switching device is given. This equation includes the chip's gate parasitic inductance, gate drive resistance, drive signal voltage, gate-source voltage, and source parasitic inductance. The formula for the gate drive loop equation is as follows: (7) (8) (9) (10) (11) (12) like Figure 9 As shown, based on Kirchhoff's current law, the node current balance equation for each switching device is given. This equation includes the drain-source capacitance current, gate-source capacitance current, gate current, drain current, and the current of the equivalent on-resistance or body diode resistance controlled by the switching state function. The formula for the node current balance equation is as follows: (13) (14) (15) (16) (17) (18) (19) (20) (twenty one) (twenty two) (twenty three) (twenty four) (25) By combining formulas (1) to (25) of this embodiment, a state-space behavior model of the multi-chip parallel SiC-MOSFET of this embodiment is formed. The general form of the state-space behavior model is as follows:

[0034]

[0035] in, For the state variable vector, The derivative of the state variable vector. The input signal vector, Let A, B, C, and D be the output signal vectors, and let A, B, C, and D be the system matrices.

[0036] The state variable vector and output signal vector are represented as follows:

[0037] Where N is the total number of switching transistors, and in this embodiment N=6, the order of the behavioral model state space is 4N+1=25.

[0038] The input signal vector is represented as follows:

[0039] in, This is the gate drive signal for the upper bridge arm switching device module. This is the gate drive signal for the lower bridge arm switching device module.

[0040] like Figure 10 As shown in the figure, the simulation results are as follows: both the upper and lower bridge arm switching device modules in this embodiment use three SiC-MOSFET chips connected in parallel, i.e., the total number of switching transistors N=6. As can be seen from the figure, the behavioral model established in this embodiment can realize the waveform simulation of the circuit switching process well and obtain relatively clear results of voltage and current dynamic changes.

[0041] The formula parameters in Examples 1 and 2 are explained as follows: Let T1 be the equivalent drain inductance of the switching device. The equivalent drain inductance of switching device T2 is... Let T3 be the equivalent drain inductance of the switching device. This is the equivalent drain inductance of the switching device T4. Let T5 be the equivalent drain inductance of the switching device. This is the equivalent drain inductance of the switching device T6.

[0042] This is the drain current of switching device T1. This is the drain current of switching device T2. This is the drain current of switching device T3. This is the drain current of switching device T4. This is the drain current of switching device T5. This is the drain current of switching device T6.

[0043] This is the gate current of switching device T1. This is the gate current of switching device T2. This represents the gate current of switching device T3. This represents the gate current of switching device T4. This represents the gate current of switching device T5. This is the gate current of switching device T6.

[0044] This is the source current of the switching device T1. This refers to the source current of the switching device T2. This is the source current of switching device T3. This is the source current of switching device T4. This is the source current of switching device T5. This is the source current of the switching device T6.

[0045] This is the drain-source voltage of the switching device T1. This is the drain-source voltage of switching device T2. This is the drain-source voltage of switching device T3. This is the drain-source voltage of the switching device T4. This is the drain-source voltage of the switching device T5. This is the drain-source voltage of the switching device T6.

[0046] This is the gate-source voltage of the switching device T1. This is the gate-source voltage of switching device T2. This represents the gate-source voltage of the switching device T3. This is the gate-source voltage of switching device T4. This is the gate-source voltage of switching device T5. This is the gate-source voltage of the switching device T6.

[0047] Let T1 be the equivalent source inductance of the switching device. Let T2 be the equivalent source inductance of the switching device. Let T3 be the equivalent source inductance of the switching device. This is the equivalent source inductance of the switching device T4. Let T5 be the equivalent source inductance of the switching device. This is the equivalent source inductance of the switching device T6.

[0048] Let T1 be the equivalent gate inductance of the switching device. The equivalent gate inductance of switching device T2 is... Let T3 be the equivalent gate inductance of the switching device. This is the equivalent gate inductance of the switching device T4. Let T5 be the equivalent gate inductance of the switching device. This is the equivalent gate inductance of the switching device T6.

[0049] , , , , , These represent the on / off states of switching devices T1, T2, T3, T4, T5, and T6, respectively. A value of 1 indicates on, and a value of 0 indicates off.

[0050] For load inductance, This is the equivalent load resistance. For the load inductor current, DC power supply This is the gate drive signal for the upper bridge arm switching device module. This is the gate drive signal for the lower bridge arm switching device module. Parasitic inductance for power circuit, For the parasitic resistance of the power circuit, To support the capacitor.

[0051] For the common gate external resistor of the upper bridge arm switching device module, This is the common gate external resistance of the lower bridge arm switching device module; The on-resistance of switching device T1 is... The on-resistance of switching device T2 is... This is the on-resistance of the switching device T3. This is the on-resistance of the switching device T4. This is the on-resistance of the switching device T5. This is the on-resistance of the switching device T6.

[0052] Let T1 be the equivalent gate resistance of the switching device. Let T2 be the equivalent gate resistance of the switching device. This is the equivalent gate resistance of the switching device T3. This is the equivalent gate resistance of the switching device T4. This is the equivalent gate resistance of the switching device T5. This is the equivalent gate resistance of the switching device T6.

[0053] Let T1 be the equivalent source inductance of the switching device. Let T2 be the equivalent source inductance of the switching device. Let T3 be the equivalent source inductance of the switching device. This is the equivalent source inductance of the switching device T4. Let T5 be the equivalent source inductance of the switching device. This is the equivalent source inductance of the switching device T6.

[0054] Let T1 be the equivalent drain-source capacitance of the switching device. Let T2 be the equivalent drain-source capacitance of the switching device. This is the equivalent drain-source capacitance of the switching device T3. This is the equivalent drain-source capacitance of the switching device T4. This is the equivalent drain-source capacitance of the switching device T5. This is the equivalent drain-source capacitance of the switching device T6.

[0055] Let T1 be the equivalent gate-source capacitance of the switching device. Let T2 be the equivalent gate-source capacitance of the switching device. This is the equivalent gate-source capacitance of the switching device T3. This is the equivalent gate-source capacitance of the switching device T4. This is the equivalent gate-source capacitance of the switching device T5. This is the equivalent gate-source capacitance of the switching device T6.

[0056] This refers to the gate-drain capacitance of switching device T1. This refers to the gate-drain capacitance of switching device T2. This refers to the gate-drain capacitance of switching device T3. This refers to the gate-drain capacitance of switching device T4. This refers to the gate-drain capacitance of switching device T5. This is the gate-drain capacitance of switching device T6.

[0057] Existing device modeling methods primarily target single-transistor characteristics or employ empirical equivalent circuits, relying on fixed parameters or idealized assumptions. These methods fail to accurately reflect the complex dynamic responses, inter-chip interactions, and the combined effects of parasitic parameters in multi-chip parallel systems. As the number of parallel chips increases, the complexity of traditional modeling methods rises dramatically, making it difficult to provide a scalable, unified, and efficient modeling framework. This leads to difficulties in invoking these methods in circuit-level simulations and fails to meet the demands of modular design and rapid optimization. Existing methods are also difficult to apply to parallel SiC-MOSFET modules of different models and structures, lacking a universal modeling solution with good parameter portability. This invention extracts parameters based on the actual characteristics of the devices and considers actual physical parameters such as parasitic inductance and junction capacitance. This enables the established behavioral model to accurately reflect the dynamic characteristics and true input-output relationships of multi-chip parallel SiC-MOSFET modules. The model is systematically established based on Kirchhoff's voltage and current laws (power loop equations, gate drive loop equations, and node current balance equations). By constructing a state-space model, the complex physical system is transformed into a standard mathematical form, ensuring the model's rigor and computability. The model, using state-space equations, automatically determines its order (e.g., 4N+1) based on the number of parallel chips, enabling flexible expansion and versatility of the model structure, suitable for scenarios with any number of parallel chips. The modeling process is concise; the established model can be directly solved iteratively in mainstream simulation environments such as MATLAB, achieving rapid integration and efficient operation on circuit-level simulation platforms, greatly facilitating module design, performance prediction, and system-level optimization. This method exhibits excellent parameter portability; by updating key parameters extracted from different devices or modules, the model can be applied to SiC-MOSFET parallel modules of different models and structures, providing a unified and powerful modeling and analysis tool for the development of multi-chip power modules.

[0058] Example 3 An electronic device includes a memory and a processor, the memory being used to store a program that supports the processor in executing the behavioral modeling method for multi-chip parallel SiC-MOSFETs as described in Embodiment 1, the processor being configured to execute the program stored in the memory.

[0059] Example 4 A storage medium storing a computer program, which, when run by a processor, executes the steps of the behavioral modeling method for multi-chip parallel SiC-MOSFETs in Embodiment 1.

[0060] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for modeling the behavior of multi-chip parallel SiC-MOSFETs, characterized in that, Includes the following steps: Step 1: Use a static tester to measure the transfer characteristic curve and output characteristic curve of each SiC-MOSFET chip connected in parallel; Step 2: Based on the transfer characteristic curve and output characteristic curve, extract the key parameters of each SiC-MOSFET chip using curve fitting method; Step 3: Establish the equivalent circuit of the multi-chip parallel SiC-MOSFET, including parasitic inductance parameters, junction capacitance parameters, and drive circuit parameters; Step 4: Combining the extracted key parameters, establish the power loop equation, gate drive loop equation, and node current balance equation of the equivalent circuit based on Kirchhoff's voltage law and current law, and transform them into a state-space behavior model. Step 5: In the simulation environment, by setting the time step, the state-space behavior model is iteratively numerically solved to obtain the switching waveform of the multi-chip parallel SiC-MOSFET.

2. The behavioral modeling method for multi-chip parallel SiC-MOSFETs according to claim 1, characterized in that, The power loop equation includes the drain parasitic inductance, source parasitic inductance, drain-source voltage, load inductance, load resistance, and DC bus voltage of the corresponding parallel branch; the gate drive loop equation includes the gate parasitic inductance, gate drive resistance, drive signal voltage, gate-source voltage, and source parasitic inductance of the corresponding chip; the node current balance equation includes the drain-source capacitance current, gate-source capacitance current, gate current, drain current, and the current of the equivalent on-resistance or body diode resistance controlled by the switching state function of the corresponding chip.

3. The behavioral modeling method for multi-chip parallel SiC-MOSFETs according to claim 1 or 2, characterized in that, The general form of the state-space behavior model is as follows: , Where x is the state variable vector, Let y be the derivative of the state variable vector, u be the input signal vector, y be the output signal vector, and A, B, C, and D be the system matrices.

4. The behavioral modeling method for multi-chip parallel SiC-MOSFETs according to claim 3, characterized in that, The dimensions of the state variable vector and the output signal vector are 4N+1, where N is the total number of switching transistors. The state variables include at least the drain current, gate current, gate-source voltage, and drain-source voltage of each chip. The input signal vector includes at least the gate drive signals of the upper bridge arm switching device module and the lower bridge arm switching device module.

5. The behavioral modeling method for multi-chip parallel SiC-MOSFETs according to claim 1, characterized in that, Behavioral modeling of a half-bridge circuit for dual-pulse testing of switching devices is applicable, wherein the upper and lower bridge arm switching device modules of the dual-pulse testing half-bridge circuit are both composed of multiple parallel SiC-MOSFET chips.

6. An electronic device, characterized in that, The device includes a memory and a processor, the memory being used to store a program that supports the processor in executing the behavioral modeling method for multi-chip parallel SiC-MOSFETs according to any one of claims 1 to 5, and the processor being configured to execute the program stored in the memory.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps of the behavioral modeling method for multi-chip parallel SiC-MOSFETs according to any one of claims 1 to 5.

8. A state-space behavioral model of a multi-chip parallel SiC-MOSFET based on the behavioral modeling method of any one of claims 1 to 5, characterized in that, The model can automatically expand or reduce its model order based on the number of parallel chips.

9. The state-space behavior model according to claim 8, characterized in that, The model can accurately simulate the effects of parasitic effects between chips, differences in driving signals, and mutual coupling on the overall dynamic response of a multi-chip parallel system.

10. A power electronics simulation system, characterized in that, The system includes the state-space behavior model of the multi-chip parallel SiC-MOSFET as described in claim 8 or 9, which is used to simulate the switching process and predict the performance of circuits containing multi-chip parallel SiC-MOSFET modules.

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