Three-dimensional integrated active heat dissipation structure

Abstract

The application relates to the field of packaging heat dissipation technology, and provides a three-dimensional integrated active heat dissipation structure, which comprises an upper cover plate layer, an air inlet hole is arranged on the upper cover plate layer; a fan and pump layer is arranged below the upper cover plate layer; at least one liquid cooling flow channel layer is arranged below the fan and pump layer; a high-power device layer is arranged below the at least one liquid cooling flow channel layer; at least one vapor chamber layer is arranged on at least one surface of the high-power device layer; at least one heat conduction material layer is arranged between the high-power device layer and the vapor chamber layer; and a lower cover plate layer is arranged at the bottom of the whole structure. The structure can be combined by selecting and matching the air cooling layer, the single and double liquid cooling layers and the vapor chamber layer according to different high, medium and low power devices, and three-dimensional integration and synergic coupling of the air cooling, liquid cooling and solid heat conduction structure are achieved, so that three-dimensional heat management is realized.

Description

Technical Field

[0001] This application relates to the field of packaging and heat dissipation technology, and more specifically, to a three-dimensional integrated active heat dissipation structure. Background Technology

[0002] Currently, as microelectronics technology enters the "post-Moore's Law era," chip architecture has shifted from two-dimensional planar to three-dimensional stacking. System integration and computing power are soaring, and the resulting "power wall" and "thermal wall" problems have replaced transistor density as the ultimate bottlenecks restricting performance, reliability, and energy efficiency. Currently, the local heat flux density of high-power chips often exceeds 500 W / cm². 2 As technology advances towards kilowatt levels, traditional "external" passive cooling technologies are approaching their physical limits. Existing cooling solutions mainly include air cooling, liquid cooling, and vapor chamber heat dissipation. However, these solutions are often used independently and have significant drawbacks. Air cooling is limited by the low thermal conductivity of air, resulting in poor heat dissipation capacity and an inability to meet high heat flux density requirements. Liquid cooling, while more efficient, typically only cools one side of the chip using traditional modules, failing to effectively address the three-dimensional heat dissipation challenges of multi-layered chips or double-sided heating structures in 3D stacked packages, and the system is complex. While vapor chambers have good in-plane temperature uniformity, their own heat capacity is limited, making it difficult to cope with continuous high heat flux impacts on its own. More importantly, within the space-constrained 3D integrated package, the above cooling methods cannot achieve efficient synergy and coupling of multiple heat dissipation mechanisms (air, liquid, and solid) within a limited volume. It is difficult to form a multi-dimensional, three-dimensional thermal management channel that runs through the top, bottom, and surrounding areas of the chip, causing the interior of the stacked chip to become a "thermal island," severely restricting the further release of the performance of advanced electronic systems. Therefore, there is an urgent need for an integrated solution that can integrate multiple heat dissipation mechanisms in a compact space to achieve three-dimensional, double-sided, and collaborative efficient heat dissipation of high-power chips, in order to break through the heat dissipation bottleneck and ensure the performance and long-term reliability of chips under high load. Summary of the Invention

[0003] This application aims to at least address the technical problem in the related technologies that traditional heat dissipation methods are often used independently and cannot achieve efficient, collaborative, and layered heat dissipation in space-constrained 3D integrated packaging, thus failing to effectively solve the heat diffusion problem of stacked packaging or double-sided heat-generating structures.

[0004] To solve the above-mentioned technical problems, this application is implemented as follows:

[0005] This application provides a three-dimensional integrated active cooling structure, comprising: an upper cover layer with air inlets; a fan and pump layer disposed below the upper cover layer, the fan and pump layer including an inlet pump array region, an outlet pump array region, and a fan array region located between the inlet pump array region and the outlet pump array region; at least one liquid cooling channel layer disposed below the fan and pump layer, and having a microchannel array formed therein; a high-power device layer disposed below the at least one liquid cooling channel layer; at least one heat spreader layer disposed on at least one surface of the high-power device layer; at least one thermally conductive material layer disposed between the high-power device layer and the heat spreader layer; and a lower cover layer disposed at the bottom of the entire structure; wherein the fan array region is used to drive the airflow through the air inlets of the upper cover layer, and the inlet pump array region and the outlet pump array region are used to drive the coolant to circulate within the at least one liquid cooling channel layer.

[0006] This application provides a three-dimensional integrated active heat dissipation structure. Through the three-dimensional integration and synergistic coupling of air cooling, liquid cooling, and solid thermal conductive structures, it achieves efficient, uniform, and scalable three-dimensional thermal management. In the scenario of multi-state synergistic heat dissipation of gas, liquid, and solid, this structure integrates the top cover plate layer, fan and pump layer, liquid cooling channel layer, heat spreader layer, thermal conductive material layer, and high-power device layer in a three-dimensional stack from top to bottom. The forced convection generated by the fan array, the liquid circulation in the microchannel driven by the pump array, and the in-plane diffusion and interface conduction of the heat spreader and thermal conductive material work simultaneously to form a highly efficient heat dissipation system with gas, liquid, and solid three-state coupling, which significantly improves the overall heat transfer efficiency and thermal uniformity. In the scenario of bi-directional symmetrical liquid cooling, through the liquid cooling channel layers symmetrically arranged on the upper and lower sides of the device layer, and the pump array in the middle layer simultaneously driving the coolant to circulate independently in the upper and lower channels, it achieves bi-directional sandwich cooling of high-power devices, greatly shortening the heat conduction path, reducing the overall thermal resistance, and effectively solving the bottleneck of traditional liquid cooling that can only dissipate heat on one side. In modular and scalable scenarios, the heat dissipation structure proposes a variety of flexibly configurable modular combination schemes. For devices with different power densities (high, medium, and low), it can be combined by selecting air-cooled layers, single / dual liquid-cooled layers, and heat spreader layers. Each module maintains consistency in interlayer interfaces, electrical interconnections, and fluid channels, achieving standardized and scalable design while balancing performance, cost, and applicability. In drive and interconnect integration scenarios, fans and pumps are highly integrated into the same functional layer and can preferably be fabricated using a unified piezoelectric drive process. High-density, low-resistance interlayer electrical connections are achieved through advanced interconnection processes such as micro-bumps, ensuring fast response of the drive unit, low-power operation, and the compactness of the entire system structure.

[0007] Additional aspects and advantages of this application will become apparent in the following description or may be learned by practice of this application. Attached Figure Description

[0008] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0009] Figure 1 This is a schematic diagram of the upper cover layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0010] Figure 2 This is one of the structural schematic diagrams of the fan and pump layers in a three-dimensional integrated active cooling structure according to an embodiment of this application;

[0011] Figure 3 This is a second schematic diagram of the fan and pump layers in a three-dimensional integrated active cooling structure according to an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the fan exhaust layer in a three-dimensional integrated active cooling structure according to an embodiment of this application;

[0013] Figure 5 This is one of the structural schematic diagrams of the upper liquid cooling channel layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0014] Figure 6 This is a second schematic diagram of the upper liquid cooling channel layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0015] Figure 7 This is a schematic diagram of the upper heat dissipation plate layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application.

[0016] Figure 8 This is a schematic diagram of the thermally conductive material layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0017] Figure 9 This is a schematic diagram of the high-power device layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0018] Figure 10 This is a schematic diagram of the lower heat dissipation plate layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application.

[0019] Figure 11 This is a schematic diagram of the lower liquid cooling channel layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0020] Figure 12 This is a schematic diagram of the lower cover layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0021] Figure 13 This is one of the fabrication flowcharts of the piezoelectric drive structure in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application;

[0022] Figure 14 This is the second flowchart illustrating the fabrication process of the piezoelectric drive structure in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application.

[0023] Figure 15 This is a schematic diagram of a modular structure among various scalable modular structures, representing one embodiment of the three-dimensional integrated active heat dissipation structure of this application.

[0024] Figure 16 This is a schematic diagram of the auxiliary microchannel structure of the upper cover layer in a three-dimensional integrated active heat dissipation structure according to an embodiment of this application.

[0025] Figure 17 for Figure 15 One of the partial cross-sectional structural schematic diagrams of the three-dimensional integrated active heat dissipation structure of the embodiment shown;

[0026] Figure 18 for Figure 15 The second partial cross-sectional view of the three-dimensional integrated active heat dissipation structure of the embodiment shown.

[0027] in, Figures 1 to 18 The correspondence between the reference numerals and component names in the attached drawings is as follows:

[0028] 100 Three-dimensional integrated active cooling structure, 1 Top cover layer, 11 Air inlet, 12 Auxiliary microchannels, 2 Fan and pump layer, 21 Pump inlet array area, 22 Pump outlet array area, 23 Fan array area, 24 Electrical interconnection area, 25 External circulation interface, 26 Cooling fluid, 211 Pump inlet unit, 221 Pump outlet unit, 231 Fan unit, 3 Fan exhaust layer, 31 Pump inlet connection pipe, 32 Pump outlet connection pipe, 33 Boundary structure, 331 First boundary section, 33 2 Second boundary section, 333 Third boundary section, 334 Fourth boundary section, 34 Air flow layer, 35 Electrical interconnection region, 4 Upper liquid cooling channel layer, 41 Liquid inlet channel, 42 Liquid outlet channel, 43 Pump inlet main channel, 44 Pump outlet main channel, 45 Microchannel array, 46 Electrical interconnection region, 5 Upper heat spreader layer, 51 Pump inlet pipe, 52 Pump outlet pipe, 53 Heat spreader body, 54 Electrical interconnection region, 6 High-power device layer, 61 Pump inlet piping, 62 Pump outlet piping, 63 High-power device Component array area, 64 Electrical interconnection area, 7 Thermally conductive material layer, 71 Pump inlet channel, 72 Pump outlet channel, 73 Material area, 74 Electrical interconnection area, 8 Lower heat spreader layer, 81 Pump inlet channel, 82 Pump outlet channel, 83 Heat spreader body, 84 Electrical interconnection area, 9 Lower liquid cooling channel layer, 91 Liquid inlet channel, 92 Liquid outlet channel, 93 Main pump inlet channel, 94 Main pump outlet channel, 95 Microchannel array, 96 Electrical interconnection area, 10 Lower cover plate layer, 101 Cover plate body, 102 Mounting 103 Electrical interconnect region, 110 Bottom silicon dioxide layer, 111 Silicon support layer, 112 Buried silicon dioxide layer, 113 Silicon device layer, 114 Insulating layer, 115 Transition layer, 116 Lower electrode layer, 117 Piezoelectric thin film layer, 118 Upper electrode layer, 120 Custom substrate, 121 Silicon layer, 122 Lower silicon dioxide layer, 123 Upper silicon layer, 124 Insulating layer, 125 Transition layer, 126 Lower electrode layer, 127 Piezoelectric thin film layer, 128 Upper electrode layer. Detailed Implementation

[0029] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0030] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.

[0031] The following reference Figures 1 to 18 This application describes a three-dimensional integrated active heat dissipation structure 100 provided according to some embodiments, belonging to the fields of semiconductor devices and electronic packaging thermal management technology. Figure 15As shown, the three-dimensional integrated active cooling structure 100 includes, from top to bottom, an upper cover layer 1, a fan and pump layer 2, a fan exhaust layer 3, an upper liquid cooling channel layer 4, an upper heat spreader layer 5, a thermally conductive material layer 7 (upper thermally conductive material layer), a high-power device layer 6, a thermally conductive material layer 7 (lower thermally conductive material layer), a lower heat spreader layer 8, a lower liquid cooling channel layer 9, and a lower cover layer 10. The thermally conductive material layer 7 is a TIM (Thermal Interface Material) thermal interface layer. The fan and pump layer 2 constitutes the active drive unit of the system, capable of simultaneously providing liquid circulation power to a single layer or the upper and lower liquid cooling channel layers, achieving single-sided or double-sided liquid cooling; the fan array is used to create airflow to assist heat exchange. Both the upper and lower liquid cooling channel layers are equipped with microchannel networks and turbulence-enhancing structures to improve the turbulence and convective heat transfer capacity of the coolant. The vapor chamber layer is arranged close to both sides of the high-power device for in-plane heat diffusion and thermal homogenization. The TIM thermal interface layer is located between the device layer and the vapor chamber layer to reduce the interface thermal resistance. This application integrates and synergistically couples multiple heat dissipation methods, such as two or more of air cooling (fan convection), liquid cooling (liquid-cooled microchannel circulation), and solid heat conduction (vapor chamber diffusion), in a three-dimensional manner. Compared with traditional structures, this application has the advantages of high heat dissipation efficiency, low thermal resistance, compact structure, and arrayable and modular integration, and is applicable to various types of three-dimensional packaged heat dissipation systems.

[0032] like Figures 1 to 12 As shown, an embodiment of this application provides a three-dimensional integrated active cooling structure 100, comprising: an upper cover layer 1 with an air inlet 11; a fan and pump layer 2 disposed below the upper cover layer 1, the fan and pump layer 2 including an inlet pump array region 21, an outlet pump array region 22, and a fan array region 23 located between the inlet pump array region 21 and the outlet pump array region 22; at least one liquid cooling channel layer including an upper liquid cooling channel layer 4 and / or a lower liquid cooling channel layer 9, the at least one liquid cooling channel layer being disposed below the fan and pump layer 2 and having a microchannel array formed inside; a high-power device layer 6 disposed below the upper liquid cooling channel layer 4 or above the lower liquid cooling channel layer 9; at least one heat spreader layer disposed on at least one surface of the high-power device layer 6; and at least one thermally conductive material layer disposed between the high-power device layer 6 and the heat spreader layer. The lower cover plate layer 10 is located at the bottom of the entire structure; wherein, the fan array area 23 is used to drive the airflow through the air inlet 11 of the upper cover plate layer 1, and the pump inlet array area 21 and the pump outlet array area 22 are used to drive the coolant to circulate in the upper liquid cooling channel layer 4 and / or the lower liquid cooling channel layer 9.

[0033] Thus, the upper cover layer 1 serves as the gas flow inlet and structural protection component, while the fan and pump layer 2 below it constitutes the active drive core of the system. The fan array region 23 drives the gas, while the inlet pump array region 21 and outlet pump array region 22 drive the liquid. The coolant circulates within a microchannel array (microchannel array 45 of the upper liquid-cooled channel layer 4 or microchannel array 95 of the lower liquid-cooled channel layer 9) of at least one liquid-cooled channel layer (such as the upper liquid-cooled channel layer 4 or the lower liquid-cooled channel layer 9), directly carrying away the main heat. The high-power device layer 6 acts as a heat source, and the heat it generates is efficiently transferred to at least one heat spreader layer (such as the upper heat spreader layer 5 or the lower heat spreader layer 8) through at least one thermally conductive material layer (such as the thermally conductive material layer 7). The heat spreader layer utilizes its high in-plane thermal conductivity to rapidly diffuse the heat, preventing localized overheating. Finally, the lower cover layer 10 completes the sealing and support of the entire structure. Through this three-dimensional stacked design, forced gas convection, liquid circulation heat exchange, and efficient solid heat conduction work together in the vertical space to form a multi-dimensional thermal management channel, which significantly improves heat dissipation efficiency and temperature uniformity.

[0034] Compared with existing technologies, the three-dimensional integrated active heat dissipation structure 100 provided in this application has the following advantages: First, multi-state synergistic heat transfer mode: by integrating air cooling, liquid cooling and solid heat conduction mechanisms into the same structure, a highly efficient heat dissipation system with gas, liquid and solid three-state coupling is formed, which significantly improves the overall heat transfer efficiency; Second, double-sided liquid cooling circulation design: driven by the pump array of the second layer, the upper and lower liquid cooling channel layers form an independent and controllable circulation loop, realizing double-sided cooling of power devices, reducing thermal resistance and uniform temperature distribution; Third, high integration and modular structure: adopting a hierarchical stacking design, taking into account The compact structure and diverse heat dissipation functions make it suitable for high-density packaging and 3D integrated chip systems. Fourth, excellent thermal uniformity: the heat spreader is arranged above and below the chip (high-power device layer 6), effectively dissipating heat and reducing local hot spots, while the TIM thermal interface layer further reduces interface thermal resistance. Fifth, enhanced heat transfer through gas-liquid mixing: the airflow generated by the upper fan and the circulating flow of the liquid cooling layer work together to improve the heat dissipation capacity and stability of the entire system. Sixth, array scalability and controllable drive: both the pump array and the fan array can be paralleled and expanded according to heat dissipation requirements, realizing modular power regulation and thermal management control. Therefore, this application can achieve rapid heat dissipation and thermal balance control of high heat flux density power devices within a limited space. This application can also be applied to various types of heat dissipation needs, including high-power-density electronic devices with high heat flux density, optoelectronic devices, high-temperature sensitive sensors and micro / nano devices, computing chips in extreme environments or with limited space, energy and power conversion devices, etc., to ensure that the device temperature remains within the applicable range of electrical performance under the temperature range after heat dissipation, significantly reduce the junction temperature peak, and effectively avoid high-temperature electrical performance degradation, such as ohmic contact, defect effects, threshold voltage variation, gain reduction, and accelerated lifetime decay.

[0035] Specifically, such as Figure 1 As shown, the three-dimensional integrated active cooling structure 100 includes an upper cover layer 1, located at the top of the entire cooling structure, serving to introduce air, protect the structure, and homogenize the airflow. Several air inlets 11 are provided on the upper cover layer 1. The air inlets 11 penetrate the thickness direction of the upper cover layer 1, introducing external cold air and forming a stable flow channel, allowing air to be evenly distributed into the internal cooling module. The air inlets 11 are preferably elongated openings extending along the long side of the cover layer. Multiple air inlets 11 are arranged in parallel with equal spacing to ensure uniform airflow distribution and reduce flow resistance. The length of each air inlet can be designed according to the cover layer size and required airflow, generally 30% to 80% of the cover layer length. The upper cover layer 1 can be made of aluminum alloy, composite engineering plastics, or thermally conductive composite materials, ensuring structural strength while meeting the thermal conductivity requirements of the overall cooling system. The surface of the upper cover layer 1 can be further coated with a dustproof coating or a microporous filter structure to prevent dust particles from entering the cooling channel below. By rationally designing the shape, number, and arrangement of the air inlet 11, airflow resistance can be effectively reduced, heat exchange efficiency can be improved, and local temperature rise can be reduced.

[0036] Furthermore, a buffer gap layer or airflow guide groove can be provided between the upper cover plate layer 1 and the lower fan and pump layer 2 to improve fluid distribution and noise characteristics. The position of the air inlet 11 can correspond to the air inlet center of the fan to ensure smooth airflow and balanced flow. Through the above design, the upper cover plate layer 1 of this embodiment not only achieves efficient introduction and distribution of external cold air, but also serves as structural protection, airflow guidance, and flow field homogenization.

[0037] Specifically, such as Figure 2 As shown, the three-dimensional integrated active cooling structure 100 includes a fan and pump layer 2, which is located below the upper cover layer 1. This layer is a key functional layer in the entire system, enabling coordinated air-liquid cooling and liquid circulation. The fan and pump layer 2 includes an inlet pump array region 21, an outlet pump array region 22, a fan array region 23, and an electrical interconnection region 24. The inlet pump array region 21 is located on the left side of the layer and consists of one or more inlet pump units 211. Each inlet pump unit 211 can independently drive the liquid working fluid into the system. Its inlet end is connected to the external coolant storage chamber, and its outlet end is connected to the lower liquid-cooled microchannel layer through a fluid interface.

[0038] Specifically, the pump unit 211 can adopt structures such as micro centrifugal pumps, piezoelectric micropumps, electromagnetic micropumps, electrostatic micropumps, or electrohydraulic driven micropumps, possessing characteristics of small size, low power consumption, and fast response, and can be arrayed to meet system heat dissipation requirements. When the chip power density is high or the microchannel layer area is large, the flow rate can be rationally distributed by increasing the number of pump arrays or using a zone control method. The liquid working fluid used for cooling includes water-based working fluids (deionized water, ethylene glycol solution) applicable to the cooling of general electronic devices and equipment, liquid metals applicable to the cooling of extremely high heat flux densities, dielectric liquids such as fluorinated liquids (mineral oil can be used) selected for immersion cooling depending on whether direct contact is possible, phase change two-phase working fluids for achieving energy efficiency and quiet operation, or enhanced heat transfer working fluids that disperse and suspend nanoscale solid particles in the above basic working fluids. The fan array area 23 located in the middle consists of multiple fan units 231, which are arranged in a matrix and correspond to the air inlet holes 11 on the upper cover plate layer 1. The fan can be a piezoelectric fan, a DC brushless fan, a centrifugal micro fan, or a thin axial fan structure. The fan array and pump group can be constructed using the same manufacturing method to create different types of gas and liquid drive modules located in different areas of the same layer, which facilitates the optimization of the overall thickness of the heat dissipation structure.

[0039] To further optimize airflow distribution, a guide grille or duct partition can be installed within the fan array area 23 to evenly distribute airflow and reduce local flow resistance. The fan drive signal can be dynamically adjusted by the control module to achieve variable speed control based on temperature feedback, thereby maintaining the system's thermal balance under different power conditions. The pump outlet array area 22 is located to the right of the fan array area 23 and contains pump outlet units 221. Each pump outlet unit 221 is connected to the liquid outlet of the lower liquid-cooled microchannel layer to extract the heat-absorbing liquid working fluid. The pump outlet unit 221 can adopt the same structure as the inlet pump unit 211 to maintain flow matching and system stability. The pump outlet array can be connected in series or parallel to adapt to different system impedance and pressure requirements. The pump outlet can be further connected to an external radiator or condenser module to achieve closed-loop circulation of the liquid working fluid.

[0040] The pump unit includes an inlet pump unit 211 and an outlet pump unit 221. The pump unit and the fan unit 231 are controlled by an integrated drive circuit, and the power supply and signal paths are realized through the interlayer electrical interconnection area 24. The electrical interconnection adopts micro-bump interconnection technology or low-temperature co-fired ceramic (LTCC) technology. The micro-bump array is preferably 10μm~30μm in diameter and 30μm~50μm in spacing, which can meet the requirements of high-power drive signal transmission and multi-channel parallel power supply. After welding, a dense metal interconnection interface is formed, and epoxy underfill material can be filled around the interconnection area to improve thermal cycling reliability.

[0041] like Figure 3 As shown, this application also provides a three-pump array structure, whose operating principle is the same as that of a single pump.

[0042] like Figure 4 As shown, the fan exhaust layer 3 is located below the fan and pump layer 2, serving to receive the airflow generated by the fan and form an orderly exhaust path. It also provides inlet and outlet pump connection space for the liquid cooling system, achieving coordinated guidance of airflow and liquid flow. The fan exhaust layer 3 includes a left-side inlet pump connection pipe 31, a right-side outlet pump connection pipe 32, a lower boundary structure 33 providing support and limiting, a central airflow layer 34, and an electrical interconnection area 35. The boundary structure 33 includes multiple boundary segments along its bottom edge: a first boundary segment 331, a second boundary segment 332, a third boundary segment 333, and a fourth boundary segment 334, which define the boundary shape of the airflow layer 34 and provide overall structural support. The inlet pump connection pipe 31 is located on the left side of the fan exhaust layer 3 and connects to the inlet pump array area 21 in the upper fan and pump layer 2, drawing the liquid working fluid from the upper layer to the lower liquid cooling microchannel layer. This pipe serves as a connector for the liquid circulation path and can be designed as a single-channel or multi-channel structure according to the system flow requirements. Specifically, the pipeline is equipped with flow stabilization or anti-backflow structures to ensure stable and balanced liquid flow when multiple pumps are operating in parallel. The airflow layer 34, located in the central region of the fan outlet layer 3, is the main gas flow space for this layer. This layer is connected to the outlet of the upper fan array and is used to receive and uniformly diffuse and guide the high-speed airflow from the fans. During operation, a longitudinal airflow field is formed inside the fan outlet layer 3. To optimize airflow distribution, the airflow layer 34 can be optionally equipped with guide vanes, bleed ribs, or airflow equalization plates to reduce local velocity differences and minimize vortex areas. The inner wall of the airflow layer 34 can be made of high thermal conductivity metal or ceramic composite materials to achieve partial heat diffusion and buffering, thereby further improving gas cooling efficiency. A boundary structure 33 is arranged around the bottom edge of the airflow layer 34 to define the airflow channel range and provide mechanical support and sealing space for this layer. The boundary structure 33 consists of multiple boundary segments, each with a frame or strip shape and a certain height, forming a closed flow field space within the airflow layer 34. The height between each boundary section can be designed according to the system airflow resistance and interlayer spacing to control the duct thickness and maintain stable internal airflow. The pump outlet connection pipe 32 is located on the right side of the fan outlet layer 3 and is connected to the pump outlet array area 22 in the upper fan and pump layer 2. It is used to discharge the liquid working fluid after heat absorption in the lower liquid-cooled microchannel and return it to the upper layer or external cooling unit.

[0043] like Figure 5 and Figure 6As shown, the upper liquid cooling channel layer 4 is one of the core heat dissipation units of the entire 3D integrated heat dissipation system. Its main function is to rapidly conduct and convect the heat generated by high-power devices during operation through the liquid cooling medium, thereby reducing the junction temperature of the devices and improving the reliability of the system.

[0044] The upper liquid-cooled flow channel layer 4 has a multi-level fluid channel structure, including an inlet channel 41, an outlet channel 42, a pump inlet main flow channel 43, a pump outlet main flow channel 44, an electrical interconnection region 46, and a microchannel array 45 distributed in the central region. The inlet channel 41 is connected to the outlet end of an external cooling pump, used to introduce coolant from the circulation system into the upper liquid-cooled flow channel layer 4. The coolant can be deionized water, ethylene glycol solution, fluorinated liquid, or liquid gallium. The pump inlet main flow channel 43 is located on one side of the liquid-cooled flow channel layer 4 and is connected to the inlet channel 41. Its internal width is greater than that of a single microchannel, serving to equalize pressure and distribute the liquid before it enters the microchannel array 45. The pump inlet main flow channel 43 is connected to the microchannel array 45 through several microchannel inlets, allowing the liquid to be evenly distributed throughout the heat exchange area, avoiding uneven flow velocity and local overheating caused by localized flow concentration. The microchannel array 45 is the main heat exchange zone, forming a dense serpentine channel structure within which the liquid flows in an S-shaped path. The width of the microchannel array 45 is typically between 0.1mm and 1.0mm, the depth between 0.1mm and 0.8mm, and the channel spacing between 0.05mm and 0.5mm, ensuring a sufficiently large heat exchange area within a small volume, which can be adjusted according to heat dissipation requirements. The coolant enters a turbulent state as it flows through the microchannel array 45, significantly increasing the thermal convection coefficient between the channel walls and the fluid, thereby improving heat dissipation efficiency. A main outlet channel 44 is located at the end of the microchannel array 45 to collect the heat-exchanged liquid. The main outlet channel 44 connects to the liquid outlet channel 42, which in turn connects to the suction port of an external cooling pump, creating a closed-loop circulation path for the liquid in the system and achieving a continuous cooling process. To further improve heat exchange efficiency, the upper liquid-cooled flow channel layer 4 in this embodiment is preferably made of silicon carbide, but high thermal conductivity metal materials (such as pure copper, copper, aluminum, or copper-tungsten alloys) or metal-based composite materials (such as copper-graphene composite materials) can also be used. During use, the coolant enters through the inlet channel 41, is distributed to multiple microchannel arrays 45 through the pump inlet main flow channel 43, absorbs heat while flowing in the heat exchange area, and then flows out through the outlet channel 42 after merging through the outlet main flow channel 44, thus achieving circulating cooling.

[0045] In this embodiment, the upper liquid-cooled flow channel layer 4 can also be customized according to the heat dissipation area distribution and heat flux density. For example, a denser microchannel structure can be arranged in areas with higher heat flux density, or the local flow rate can be optimized by adjusting the channel width and depth, thereby achieving precise temperature control. Figure 6As shown, this application also provides a structure with three pumps driving three sets of flow channels, with the microchannel structure in the middle being more densely packed.

[0046] like Figure 7 As shown, the upper heat spreader layer 5 is located below the upper liquid cooling channel layer 4 and is directly attached to the surface of the high-power device layer 6. It is the first-level heat conduction and temperature equalization unit of the system, thereby reducing local temperature rise and improving overall thermal stability. This layer mainly includes the inlet pump pipe 51, the outlet pump pipe 52, the heat spreader body 53, and the electrical interconnection area 54. The heat spreader body 53 adopts a vacuum-sealed cavity structure, which forms a closed vapor-liquid two-phase heat transfer space. A certain amount of working fluid is encapsulated in the cavity, and the filling volume of the working fluid is 30% to 70% of the total cavity volume. The working fluid is preferably a metallic working fluid such as sodium, potassium, or lithium, but deionized water, ethanol, methanol, acetone, ammonia, or fluorinated liquids can also be used. The heat spreader body 53 has a capillary wick structure inside. The capillary wick can be made of sintered metal powder, microporous copper foam, porous graphite structure, or microgroove processing structure to realize liquid reflux and vapor-liquid separation. This capillary structure not only stabilizes liquid circulation but also forms liquid supply channels in different areas of the heat spreader, thereby improving heat conduction uniformity and resistance to drying out.

[0047] The heat spreader body 53 can also be made of SiC material, which can utilize its high thermal conductivity (>200 W / m·K), excellent electrical insulation and low thermal expansion characteristics to form a high-strength thermally compatible interface with the upper liquid cooling channel layer 4 and the lower structure, effectively preventing thermal stress damage. It can also be made of high thermal conductivity metal or ceramic matrix composite materials, such as copper, copper-molybdenum alloy, aluminum nitride, silicon nitride or graphene.

[0048] like Figure 8As shown, the thermally conductive material layer 7 is disposed below the high-power device layer 6. The thermally conductive material layer 7 is a TIM (Thermal Interface Material) thermal interface layer, serving as the bottom thermally conductive connection layer of the entire 3D integrated heat dissipation structure. It is used to achieve efficient heat transfer and mechanical connection between the high-power device layer 6 and the underlying heat dissipation layer. The thermally conductive material layer 7 includes an inlet pump channel 71, an outlet pump channel 72, a material region 73, and an electrical interconnection region 74. The inlet pump channel 71 is located on one side of the thermally conductive material layer 7, communicating with the inlet pump channel in the upper structure. It provides coolant to the lower liquid cooling layer, ensuring a complete circulation path for the entire system. The outlet pump channel 72 is located on the opposite side of the inlet pump channel 71, communicating with the upper outlet pump system. It carries the heat absorbed by the lower liquid cooling layer back to the circulation system via fluid, achieving a closed heat exchange path. The material region 73, located in the middle area, is the core functional area of ​​this layer, providing a low thermal resistance thermal interface between the high-power device layer 6 and the heat dissipation layer to achieve efficient heat conduction and diffusion. Material region 73 can use various forms of thermally conductive interface materials, including but not limited to: metal sintered TIM, polymer composite TIM, carbon-based reinforced TIM and composite multilayer structure TIM.

[0049] like Figure 9 As shown, the high-power device layer 6 is located in the middle of the 3D integrated heat dissipation structure and serves as the heat source layer for the entire system, directly and tightly bonded to the bottom surface of the upper heat sink layer 5. This layer is used to integrate high-power-density semiconductor devices and achieve efficient heat dissipation. The high-power device layer 6 includes an inlet pump pipe 61, an outlet pump pipe 62, a high-power device array region 63, and an electrical interconnection region 64. The central region is the high-power device array region 63, which in this embodiment is a 3×3 GaN power device array structure. Each power device unit is independently packaged and can be electrically interconnected through metallized leads or redistribution layers (RDLs). The high-power device array region 63 is the main heat source region of the system. A high thermal conductivity metal substrate or packaging substrate (such as Cu, Cu-Mo, AlN, or SiC substrate), preferably a SiC substrate, is disposed below the array to rapidly conduct the heat generated by each device.

[0050] like Figure 10As shown, the lower heat spreader layer 8 is located below the thermally conductive material layer 7 and serves as the bottom heat diffusion and temperature equalization unit of the entire 3D integrated heat dissipation system. It is connected to the lower liquid cooling channel layer 9 below. This layer is used to quickly absorb heat transferred from the high-power device layer 6 above via the thermally conductive material layer 7, and achieves in-plane heat diffusion and efficient heat conduction through phase change conduction and internal fluid circulation. The lower heat spreader layer 8 includes an inlet pump channel 81, an outlet pump channel 82, a heat spreader body 83, and an electrical interconnection area 84. The heat spreader body 83 is the main heat spreader area, which contains an evaporation chamber, a condensation chamber, and a capillary reflux structure, forming a typical phase change heat transfer channel. This area is the core of the entire layer structure for heat conduction, used to achieve rapid diffusion and temperature equalization control of localized high heat flux.

[0051] like Figure 11 As shown, the lower liquid-cooled flow channel layer 9 has a structure basically the same as the upper liquid-cooled flow channel layer 4, both driven by a pump array to achieve closed-loop circulation and efficient heat exchange of the liquid working fluid. The lower liquid-cooled flow channel layer 9 includes an inlet channel 91, an outlet channel 92, a main pump inlet channel 93, a main pump outlet channel 94, a microchannel array 95, and an electrical interconnection region 96. The inlet channel 91 is connected to the pump inlet unit 211 and is used to introduce the liquid working fluid from outside the system into the lower liquid-cooled flow channel layer 9; the outlet channel 92 is connected to the pump outlet unit 221 and is used to discharge the heat-exchanged liquid working fluid, achieving a closed loop. The main pump inlet channel 93 and the main pump outlet channel 94 are located on opposite sides of the lower liquid-cooled flow channel layer 9, respectively, and are used to distribute and collect the liquid within the layer. A microchannel array 95 is provided between the two, and this region is in direct contact with the lower heat spreader layer 8, used to remove the heat conducted down from the heat spreader layer through forced convection of the liquid.

[0052] like Figure 12 As shown, the lower cover layer 10 is located at the bottom of the entire 3D integrated heat dissipation system. It is used to seal, support, and reinforce the overall structure of the lower liquid cooling channel layer 9, while also serving as an auxiliary heat dissipation and system mounting component. The lower cover layer 10 includes a cover body 101, mounting holes 102, and an electrical interconnection area 103. The material selection for the lower cover layer 10 must consider thermal conductivity, structural strength, and sealing reliability; preferred materials are copper, aluminum, copper alloys, or aluminum alloys.

[0053] Specifically, the three-dimensional integrated active heat dissipation structure provided in this application proposes various scalable modular structural forms to adapt to the heat dissipation requirements of devices with different power densities, as exemplified below:

[0054] A: This indicates the fan cooling enhancement layer, which includes an upper cover layer 1, a drive layer (including a fan and pump layer 2), and a drive interface layer. The upper cover layer 1 has an air inlet 11 for introducing external air and protecting the overall encapsulated structure. The drive layer (including the fan and pump layer 2) consists of an inlet pump array area, a fan array area, and an outlet pump array area. The inlet and outlet pump arrays achieve liquid working fluid circulation drive through micro-pump units; the fan array provides airflow to form the upper air cooling path. The drive interface layer includes channels connected to the inlet and outlet drives and an airflow layer. Air convection is formed through internal airflow channels to remove heat from the upper area; the boundary structure has a certain height to define the airflow path.

[0055] B: Indicates the liquid cooling channel layer: It includes pipes, main channels, and microchannel structures that communicate with the inlet and outlet pumps, and is used for the distribution, collection, and flow of cooling liquid. The cross-section of the microchannel can be rectangular, trapezoidal, or needle-ribbed to enhance turbulence and improve heat transfer efficiency.

[0056] C: Indicates heat spreader layer: The heat spreader layer is in close contact with the upper surface of the high-power device and is used to rapidly diffuse heat in the in-plane direction to achieve temperature uniformity; the heat spreader layer can be equipped with a vapor chamber and capillary structure to achieve phase change heat transfer.

[0057] D: Indicates the thermally conductive material layer: used to fill the gap between the device and the heat sink below, reducing the interfacial thermal resistance and improving thermal coupling performance.

[0058] E: Indicates the chip layer to be cooled: Taking the high-power device layer as an example, it integrates a high-power chip array, which is arranged as a single chip or a matrix.

[0059] F: Indicates the bottom cover layer: This is the bottom enclosed structure of the system, used for fixation and protection, and may also include the overall chip structure and external electrical connection structures. The layers are tightly bonded together using highly thermally conductive interface materials, and high-density, reliable electrical interconnections are achieved, ensuring the coordinated integration of heat conduction and electrical connections.

[0060] Thus, the three-dimensional integrated active heat dissipation structure provided in this application has multiple expandable modular structural forms, specifically A+B+C+D+E+D+C+B+F, B+C+D+E+D+C+B+F, A+B+C+D+E+F, A+C+D+E+F, E+D+C+B+F, or B+C+D+E+F, etc.

[0061] Taking the high-power module as an example: it adopts a three-dimensional integrated structure of "air cooling + double-layer liquid cooling + heat spreader (A+B+C+D+E+D+C+B+F)" to form a symmetrical liquid cooling channel. The cooling working fluid is circulated by an array pump to achieve efficient heat exchange.

[0062] Taking the medium power module as an example: it adopts the structure of "air cooling + single-layer liquid cooling + heat spreader (A+B+C+D+E+F)", retaining the main liquid cooling channels, and balancing performance and manufacturing complexity;

[0063] Taking low-power modules as an example: they adopt a "air-cooled + heat spreader (A+C+D+E+F)" structure, or a "single-layer liquid-cooled + heat spreader (E+D+C+B+F or B+C+D+E+F)" structure, or a "double-layer liquid-cooled + heat spreader (B+C+D+E+D+C+B+F)" structure, to achieve compact heat dissipation through air and liquid cooling and solid heat conduction.

[0064] The multiple modules maintain consistency in structural interfaces, electrical interconnections, and fluid channel layout, allowing for flexible combination or replacement based on device power density, thus achieving modular hierarchical design. This application overcomes the performance bottleneck of traditional two-dimensional heat dissipation structures by achieving multi-level thermal management capabilities within a single package architecture.

[0065] In some embodiments, optionally, such as Figure 16 , Figure 17 and Figure 18 As shown, an auxiliary microchannel 12 is also provided inside or on the lower surface of the upper cover layer 1; the two ends of the auxiliary microchannel 12 are fluidly connected to the pump inlet array region 21 and the pump outlet array region 22 of the fan and pump layer 2, respectively, and are connected in parallel with the microchannel array in at least one liquid cooling channel layer to form an internal circulation liquid cooling loop that can be selectively opened and closed; the pump inlet array region 21 and the pump outlet array region 22 of the fan and pump layer 2 are also provided with an external circulation interface 25 for connecting to an external cooling loop; the three-dimensional integrated active heat dissipation structure 100 is configured to have two working modes: in the internal circulation mode, the external circulation interface 25 is closed, and the cooling medium circulates in a closed loop formed by the auxiliary microchannel 12 and the microchannel array of at least one liquid cooling channel layer; in the external circulation mode, the external circulation interface 25 is opened and connected to the external liquid storage chamber, and the cooling medium circulates in a loop formed by the external liquid storage chamber and the microchannel array of at least one liquid cooling channel layer.

[0066] in, Figure 17 This is a partial cross-sectional view of the three-dimensional integrated active cooling structure in one embodiment, in the internal circulation mode, where the external circulation interface 25 is closed. The cooling medium flows in a completely closed internal circulation loop formed by the auxiliary microchannels 12 of the upper cover layer 1 and the microchannel array (such as 45 or 95) in the lower liquid cooling channel layer. This loop does not rely on an external liquid storage and cooling system, and is driven by a micro-pump unit (211, 221) and a fan unit 231 integrated on the fan and pump layer 2. This mode has the advantages of compact structure, rapid response, and no external dependence, and is particularly suitable for applications in the initial stage of equipment startup, short-term peak heat dissipation, or where space and interfaces are extremely limited.

[0067] in, Figure 18 This is a partial cross-sectional view of the three-dimensional integrated active cooling structure in another embodiment under external circulation mode. In this mode, the external circulation interface 25 is open and connected to external devices such as a larger capacity liquid storage chamber, heat sink, or chiller via pipes. At this time, the cooling medium mainly flows in the external circulation loop formed by the microchannel array of the external liquid storage chamber and the liquid-cooled flow channel layer. The auxiliary microchannel 12 in the upper cover layer 1 can be considered as a parallel bypass or is idle in this mode. The external circulation mode can utilize the larger heat capacity and stronger heat dissipation capability of the external system, making it suitable for scenarios where the chip operates under continuous high load and needs to dissipate a large amount of heat, thereby expanding the heat dissipation capability and ensuring long-term stable operation of the system.

[0068] It is understandable that when the fan and pump layer 2 do not have an external circulation interface 25, i.e., when the external circulation interface 25 is not provided, the three-dimensional integrated active cooling structure only performs internal circulation. When the fan and pump layer 2 have an external circulation interface 25, external circulation can be performed when the external circulation interface 25 is on, and internal circulation can be performed when the external circulation interface 25 is off. This design makes dynamic management more convenient.

[0069] The external circulation interface 25 is specifically a liquid cooling medium interface structure, which can be connected to an external liquid storage chamber to replace or drive the flow of coolant (cooling medium). If internal circulation mode is required, this interface remains closed and is not connected to the external liquid storage chamber. The cooling medium 26 is specifically a heat dissipation medium, including water and water-based media such as deionized water / ultrapure water, diol aqueous solutions, and water-based media with added special additives; single-phase liquids such as hydrocarbons and mineral oils, silicone oils, fluorinated liquids, esters, and synthetic oils; phase change media such as electronic fluorinated liquids, refrigerants, and liquid metals; and cutting-edge and special media such as nanofluids, ionic liquids, supercritical fluids, and magnetofluids. The pump inlet unit 211 and pump outlet unit 221 are specifically liquid-driven components, including mechanical micropumps such as piezoelectric pumps, electromagnetic pumps, pneumatic diaphragm pumps, and gear pumps; mechanical micropumps such as electrohydraulic pumps / ion-dragging pumps, electroosmotic pumps, magnetohydrodynamic pumps, ultrasonic pumps, and electrowetting digital micropumps; and active liquid-driven components such as syringe pumps and stirrers. They also include passive driven components such as thermally driven, capillary-driven, and magnetically driven components; and emerging and composite driven solutions such as field-coordinated driving and flexible / biomimetic driving that combine the above principles. The fan unit 231 is specifically a gas-driven component, including active mechanical microfans such as axial fans, centrifugal fans, blowers, crossflow fans, and mixed-flow fans; and passive or semi-passive gas-driven components such as ion wind and thermoelectric synthesis. The air inlet 11 in the upper cover layer 1 is specifically a key microstructure for gaseous heat dissipation. Its configuration includes key air duct structures integrated into the system, such as inlets, outlets, and channel structures; key structures for jet impact cooling, such as gaseous through-holes, nozzles, and spray holes; and may also include continuous fins, discrete protrusion structures, recessed / vortex generator structures, porous structures, biomimetic and fractal structures, and microstructures that enhance heat transfer surfaces. At least one liquid cooling channel layer is specifically a liquid heat dissipation layer, and at least one heat spreader layer is specifically a solid heat dissipation layer, including ultra-high thermal conductivity materials such as diamond, graphene, and carbon nanotubes; traditional high thermal conductivity metal materials such as copper, silver, aluminum, and aluminum alloys; and high thermal conductivity ceramics and composite materials such as aluminum nitride and silicon carbide. The electrical interconnect region 24 specifically comprises electrical connection structures, including connections directly implemented on the silicon wafer through semiconductor manufacturing processes. These connections enable primary interconnections from chip to package carrier, such as wire bonding, tape bonding, and flip-chip bonding. They may also utilize high-density interconnects and integration structures found in advanced packaging technologies, such as through-silicon vias, microbumps, and redistribution layers. Additionally, it includes secondary interconnect structures that connect packaged devices to the main system board.

[0070] In some embodiments, optionally, such as Figure 5 , Figure 6 and Figure 11 As shown, at least one liquid cooling channel layer includes an upper liquid cooling channel layer 4 and a lower liquid cooling channel layer 9; the upper liquid cooling channel layer 4 is disposed between the fan and pump layer 2 and the high-power device layer 6; the lower liquid cooling channel layer 9 is disposed between the high-power device layer 6 and the lower cover plate layer 10.

[0071] Specifically, this embodiment provides a preferred implementation of at least one liquid cooling channel layer, namely a symmetrical double-sided liquid cooling design. The upper liquid cooling channel layer 4 is in close contact with the upper surface of the high-power device layer 6, used to absorb and remove heat generated on the upper surface of the device. The lower liquid cooling channel layer 9 is in close contact with the lower surface of the high-power device layer 6, used to absorb and remove heat from the lower surface of the device and from the packaging substrate. This double-sided liquid cooling architecture, with its upper and lower clamping action, greatly increases the heat dissipation contact area and shortens the path from the heat source to the coolant, thereby enabling it to handle higher heat flux densities. It is particularly suitable for three-dimensional stacked chips or power devices with heat generation on both sides.

[0072] In some embodiments, optionally, such as Figure 7 , Figure 8 , Figure 9 and Figure 10 As shown, at least one heat spreader layer includes an upper heat spreader layer 5 and a lower heat spreader layer 8; the upper heat spreader layer 5 is disposed between the upper liquid cooling channel layer 4 and the high-power device layer 6; the lower heat spreader layer 8 is disposed between the high-power device layer 6 and the lower liquid cooling channel layer 9; at least one thermally conductive material layer 7 includes an upper thermally conductive material layer and a lower thermally conductive material layer; the upper thermally conductive material layer is disposed between the high-power device layer 6 and the upper heat spreader layer 5; the lower thermally conductive material layer is disposed between the high-power device layer 6 and the lower heat spreader layer 8.

[0073] Specifically, this embodiment further optimizes the heat conduction and temperature equalization paths based on double-sided liquid cooling. The upper heat spreader layer 5 is disposed between the upper liquid cooling channel layer 4 and the high-power device layer 6, and its function is to quickly diffuse the heat from the "hot spots" on the upper surface of the chip laterally to the entire contact surface of the upper liquid cooling channel layer 4. Similarly, the lower heat spreader layer 8 is disposed between the high-power device layer 6 and the lower liquid cooling channel layer 9 to diffuse heat from the bottom of the chip. The upper and lower thermally conductive material layers fill the microscopic gaps between the high-power device layer 6 and the upper and lower heat spreader layers, respectively, significantly reducing the interfacial contact thermal resistance and ensuring that heat can be efficiently transferred from the chip to the heat spreader. This combination constitutes an efficient heat diffusion and interfacial conduction system on both the upper and lower sides of the chip.

[0074] In some embodiments, optionally, such as Figure 5 , Figure 6 and Figure 11 As shown, the liquid cooling channel layer has a multi-level fluid channel structure, including: a liquid inlet channel, which is connected to the pump array region 21; a main pump inlet channel, which is connected to the liquid inlet channel and is used to equalize and distribute the coolant; a microchannel array, which is connected to the main pump inlet channel through several microchannel inlets; a main pump outlet channel, which is used to collect the liquid after heat exchange by the microchannel array; and a liquid outlet channel, which is connected to the main pump outlet channel and the pump outlet array region 22.

[0075] Specifically, this embodiment reveals a highly efficient fluid organization method within the liquid-cooled channel layer. Taking the upper liquid-cooled channel layer 4 as an example, after the coolant is pumped out from the inlet array region 21, it first enters through the inlet channel 41, and then flows into the larger cross-section inlet main channel 43, where pressure equalization and distribution are performed to ensure uniform flow. Subsequently, the coolant enters the microchannel array 45 through multiple microchannel inlets, forming high-speed turbulence within the narrow channels and undergoing intense heat exchange with the channel walls. The heat-absorbing coolant collects in the outlet main channel 44, and finally is drawn back by the upper outlet array region 22 through the outlet channel 42, completing one cycle. The structure and flow of the lower liquid-cooled channel layer 9 are exactly the same, achieving independent circulation through the inlet channel 91, inlet main channel 93, microchannel array 95, outlet main channel 94, and outlet channel 92. This multi-stage channel structure is key to achieving efficient and uniform heat exchange.

[0076] In some embodiments, optionally, such as Figure 7 As shown, the heat spreader layer is a vacuum-sealed cavity structure, including: a heat spreader body, the inside of which forms a closed vapor-liquid two-phase heat transfer space; a working fluid, which is encapsulated within the vapor-liquid two-phase heat transfer space; and a capillary wick structure, which is disposed inside the heat spreader body to realize capillary reflux of the liquid.

[0077] Specifically, the vapor chamber layer 5, as described above, is a highly efficient heat-conducting element utilizing phase change heat transfer. The interior of its vapor chamber body 53 is evacuated and encapsulated with a suitable amount of working fluid (such as deionized water, ethanol, or liquid metal). When the portion of the vapor chamber body 53 in contact with the heat source (evaporation end) is heated, the working fluid rapidly vaporizes and absorbs heat. Under the influence of the pressure difference, the vapor flows to the low-temperature portion of the vapor chamber body 53 (condensation end), where it condenses into a liquid and releases heat. A capillary structure (such as sintered metal powder, microgrooves, etc.) pumps the condensed liquid back from the condensation end to the evaporation end using capillary force, thus forming a continuous phase change heat transfer cycle that requires no external power. This method gives the vapor chamber layer an extremely high equivalent thermal conductivity, enabling rapid elimination of localized hot spots.

[0078] In some embodiments, optionally, such as Figure 9 As shown, the high-power device layer 6 includes: a high-power device array region 63, which integrates a power device array; and a packaging substrate, which is disposed below the high-power device array region and is used to support the devices and conduct heat.

[0079] Specifically, the high-power device layer 6 is the system's heat source. Its core is the high-power device array region 63, which can integrate power devices such as GaN HEMTs (High Electron Mobility Transistors). These devices are regularly distributed in an array, achieving a power density of up to 100 W / cm².2 Up to 300W / cm 2 Below the device array is the packaging substrate, which is made of silicon carbide with high thermal conductivity, but copper, Cu-Mo alloy, or aluminum nitride can also be used. This substrate not only provides mechanical support and electrical interconnection for the devices (such as through the RDL redistribution layer), but more importantly, it serves as the main heat conduction path, rapidly diffusing the heat generated by the devices to the heat dissipation structure below, such as the lower heat sink layer 8 and the lower liquid cooling channel layer 9.

[0080] In some embodiments, optionally, such as Figure 4 As shown, it also includes: a fan exhaust layer 3, which is disposed between the fan and pump layer 2 and at least one liquid cooling channel layer. The fan exhaust layer 3 includes an inlet pump connection pipe 31, an outlet pump connection pipe 32, and an air flow layer 34 in the middle.

[0081] Specifically, the fan exhaust layer 3 is a key transition layer for achieving gas-liquid synergy. It is located between the fan and pump layer 2 and the liquid cooling channel layer. Its left-side pump inlet connection pipe 31 connects to the upper pump inlet array region 21, and its right-side pump outlet connection pipe 32 connects to the upper pump outlet array region 22, together forming a liquid circulation channel that runs through both layers. The central airflow layer 34 is a cavity structure that directly connects to the air outlet of the upper fan array region 23. The cooling airflow generated by the fan enters this layer, is guided and evenly distributed, effectively blowing onto the upper surface of the liquid cooling channel layer below, carrying away its residual heat, thus achieving enhanced heat exchange through air cooling.

[0082] In some embodiments, optionally, such as Figure 2 and Figure 3 As shown, the fan and pump layer 2 also includes an electrical interconnection region 24, which is electrically connected to the upper and lower adjacent layers through a micro-bump interconnection process.

[0083] Specifically, the electrical interconnection area 24 of the fan and pump layer 2 is responsible for providing power and signals to the entire active cooling system. This area employs a micro-bump interconnection process, which involves placing metal pads at corresponding positions between layers and forming an array of micro-bumps with a diameter of 10μm to 30μm and a spacing of 30μm to 50μm using copper pillars or copper-nickel-gold composite structures. After alignment, reflow soldering is performed to form a dense, low-resistance vertical electrical connection interface. After soldering, epoxy resin underfill material can be filled around the interconnection area to improve mechanical strength and thermal cycling reliability. This process ensures that the power input and control signals of the fan unit 231 and the pump unit can be transmitted stably and reliably.

[0084] In some embodiments, optionally, such as Figure 13 , Figure 14 and Figure 15 As shown, the fan unit 231 in the fan array region 23 and / or the pump unit in the pump inlet array region 21 and the pump outlet array region 22 adopt a piezoelectric drive structure; the piezoelectric drive structure includes: a substrate; an insulating layer formed on the substrate; a transition layer formed on the insulating layer; a lower electrode layer formed on the transition layer; a piezoelectric thin film layer formed on the lower electrode layer; and an upper electrode layer formed on the piezoelectric thin film layer.

[0085] Specifically, this embodiment provides a scheme for driving a fan and a pump. The piezoelectric drive structure is fabricated using a multilayer thin-film process. An SOI (Silicon-On-Insulator) wafer is selected as the substrate. Detailed fabrication procedures can be found in [reference needed]. Figure 13 and Figure 14 And its related descriptions.

[0086] If both the fan array and the pump unit employ piezoelectric drive structures, their related drive functional layers can utilize high-performance piezoelectric thin film materials, such as PZT (lead zirconate titanate), aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), hafnium oxide (HfO2), and lithium niobate (LN). These materials possess excellent piezoelectric response characteristics and high electromechanical coupling coefficients, enabling high-frequency, low-power drive output for both fans and pumps. This embodiment uses a highly compatible SOI integration process as an example to detail the fabrication process of the piezoelectric drive layer. It mainly consists of two major steps. The first major step is the fabrication of a high-performance piezoelectric thin film, such as... Figure 13 As shown, it mainly includes the following seven sub-steps:

[0087] First, SOI substrate cleaning and preparation (as shown in 1a):

[0088] In some embodiments, an SOI (Silicon-On-Insulator) wafer is selected as the substrate. The SOI wafer, from top to bottom, comprises a silicon device layer 113, a silicon oxide buried oxide layer 112, a silicon handle layer 111, and a bottom silicon oxide layer 110. The SOI wafer is sequentially ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water to remove surface organic matter, oxides, and particulate impurities. After cleaning, it is dried in a nitrogen atmosphere, for example, heated at 80°C, 100°C, or 150°C for 10 to 30 minutes, but not limited to these temperatures and times, to ensure surface cleanliness and adhesion performance for subsequent thin film deposition.

[0089] Second, preparation of the insulating layer (as shown in 1b):

[0090] An insulating layer 114 is formed on the surface of the SOI wafer. The material of the insulating layer 114 can be one or more of silicon dioxide, aluminum oxide, silicon nitride, and hafnium oxide.

[0091] The insulating layer 114 can be formed by processes such as dry oxidation, wet oxidation, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, sol-gel method or magnetron sputtering.

[0092] The thickness of the insulating layer 114 is 10nm to 2000nm, for example, 50nm, 100nm, 200nm, 500nm or 1000nm, but is not limited to the values ​​mentioned above.

[0093] Third, preparation of the transition layer thin film (as shown in 1c):

[0094] A transition layer 115 is deposited on the insulating layer 114.

[0095] The transition layer 115 includes at least one adhesion promoting and blocking material, such as titanium, chromium, nickel-chromium alloy, etc., to improve the adhesion between the electrode and the substrate and prevent element diffusion during high-temperature processing.

[0096] The transition layer may also include a lattice matching and orientation control layer, such as lead titanate, strontium ruthenium oxide, or iridium oxide, to provide good lattice matching conditions for subsequent epitaxial or preferred orientation growth of piezoelectric thin films. The thickness of the transition layer is 5 nm to 500 nm, for example, 10 nm, 50 nm, 100 nm, or 200 nm, but is not limited to these values.

[0097] Fourth, lower electrode thin film deposition (as shown in 1d):

[0098] A lower electrode layer 116 is deposited on the transition layer 115.

[0099] The material of the lower electrode is platinum, gold, iridium, ruthenium, ruthenium oxide or alloy thereof.

[0100] The thickness of the lower electrode layer 116 is 20nm to 500nm, for example, 50nm, 100nm or 200nm, but is not limited to the values ​​mentioned above.

[0101] Fifth, preparation of piezoelectric thin film layer (as shown in 1e):

[0102] A piezoelectric thin film layer 117, also known as an electromechanical drive layer, is deposited on the lower electrode layer 116.

[0103] The electromechanical drive layer is made of one or more of lead zirconate titanate, aluminum nitride, scandium-doped aluminum nitride, lead magnesium niobate, barium titanate, shape memory alloys, polycrystalline silicon, or silicon nitride. The piezoelectric thin film can be prepared by sputtering, pulsed laser deposition (PLD), sol-gel method, screen printing, metal-organic chemical vapor deposition (MOCVD), aerosol deposition, solid-state reaction method, hot-pressing sintering, mixed oxide method, or chemical co-precipitation method. Preferably, PVD technology is used, with a Pb-excess Pb1.2Zr0.52Ti0.48O3 target, and the piezoelectric thin film is deposited by radio frequency magnetron sputtering.

[0104] The thickness of the electromechanical drive layer is 20nm to 10000nm, for example, 20nm, 100nm, 500nm, 1000nm, 5000nm or 10000nm, but is not limited to the values ​​mentioned above.

[0105] Sixth, fabrication of the upper electrode layer (as shown in 1f):

[0106] An upper electrode layer 118 is deposited on the piezoelectric thin film layer 117.

[0107] The material of the upper electrode can be gold, platinum, iridium, aluminum, silver, or ruthenium.

[0108] The upper electrode can be formed by methods such as physical vapor deposition (PVD), radio frequency magnetron sputtering, DC magnetron sputtering, reactive sputtering, pulsed laser deposition (PLD), or electron beam evaporation. Preferably, PVD sputtering is used. The thickness of the upper electrode layer 118 is 20 nm to 1000 nm, for example, 50 nm, 100 nm, 200 nm, or 500 nm, but is not limited to these values.

[0109] Seventh, heat treatment (as shown in 1g):

[0110] After the top electrode deposition is completed, the structure is heat-treated to promote the crystallization of the piezoelectric thin film and the formation of a perovskite crystalline phase. The heat treatment method includes one or more of conventional furnace tube annealing, rapid thermal annealing, interlayer annealing, laser annealing, or microwave annealing. Preferably, rapid thermal annealing is used, for example, annealing at 500°C to 750°C for 1 to 10 minutes, to obtain a perovskite phase thin film with excellent piezoelectric properties, but the temperature and time are not limited to those specified.

[0111] The second major step is to fabricate the piezoelectric drive structure for the fan and pump, such as... Figure 13 As shown, it mainly includes the following 7 sub-steps:

[0112] First, the patterning of the upper electrode layer can be achieved using various microfabrication techniques, including but not limited to: wet etching, reactive ion etching (RIE), ion beam etching (IBE), lift-off, laser etching or laser ablation, and electron beam lithography or electron beam etching. Preferably, front-side photolithography combined with ion beam etching (IBE) is used to pattern the upper electrode layer. A mask layer with a predetermined pattern is formed through photolithography, and then the electrode material in the unprotected areas is removed using ion beam directional etching, thereby obtaining the upper electrode layer with the desired pattern. This method has advantages such as strong etching directionality, high edge precision, and a wide range of applicable materials, and is particularly suitable for the microstructure processing of noble metal and inert metal electrodes.

[0113] Second, the patterning of the piezoelectric material layer can be achieved using etching techniques including, but not limited to, RIE, IBE, dry etching, or laser etching. Preferably, hot phosphoric acid wet etching is used to pattern the piezoelectric material layer to form the piezoelectric actuation region that meets the design requirements. During this etching process, the electrode layer in the exposed area is partially removed or exposed, thereby exposing the lower electrode pads and facilitating subsequent electrode lead-out and electrical connection operations.

[0114] Third, the patterning of the lower electrode layer can be achieved using etching techniques including, but not limited to, wet etching, RIE, lift-off processes, laser etching, or electron beam etching. Preferably, the lower electrode layer is patterned using the same IBE technique as the upper electrode layer to obtain the predetermined electrode structure.

[0115] Fourth, the patterning of the transition layer can be achieved using etching techniques including, but not limited to, dry etching and wet etching. Preferably, for Ti, a dilute HF solution can be used for rapid wet etching or a Cl2 / BCl3-based dry etching solution can be used; for Cr, a dedicated Cr etching solution such as cerium ammonium nitrate can be used.

[0116] Fifth, the structural pattern transfer employs RIE technology, sequentially removing the SiO2 protective layer and the Si device layer until the SiO2 buried oxide layer is reached. Preferably, the etching atmosphere can be CF4, CHF3, SF6, O2, or a mixture thereof to achieve high selectivity and good etching rate control. In some embodiments, to avoid damage to the piezoelectric layer and electrode layer, segmented etching or low-power process parameters can be used to ensure structural integrity and surface quality.

[0117] Sixth, the back cavity is formed using deep reactive ion etching (DRIE) technology. The Si support layer and the SiO2 underlayer are sequentially etched from the back of the silicon wafer to form the underlying back cavity structure. Preferably, the DRIE process can employ the Bosch process mode to achieve high depth and high aspect ratio etching effects, ensuring a regular cavity morphology and high verticality. The back cavity is a movable space region that directly affects the device's performance.

[0118] Seventh, the structure release employs RIE technology to selectively remove the SiO2 buried oxide layer, thereby releasing the cantilever pump / fan structure. Preferably, to prevent adhesion or warping during the release process, a dry etching combined with critical point drying (CPD) process can be used for post-processing. Finally, a complete piezoelectric drive structure for the fan and pump is obtained.

[0119] This embodiment provides a detailed description of another fabrication process for the piezoelectric driving layer, such as... Figure 14 As shown. It mainly includes the following 9 sub-steps:

[0120] First, cleaning and preparation of the custom substrate 120 (as shown in 2a):

[0121] In some embodiments, a custom substrate 120 containing a pre-formed air duct structure is selected as the substrate. The custom substrate 120 may be a silicon substrate, a glass substrate, a quartz substrate, or a composite substrate thereof, with air ducts, cavities, or microchannel structures for gas flow pre-formed inside or on its surface, but is not limited to the above forms.

[0122] In some embodiments, the customized substrate 120 is ultrasonically cleaned sequentially with acetone, anhydrous ethanol, and deionized water to remove organic contaminants, particulate impurities, and processing residues from the substrate surface. After cleaning, it can be dried in a nitrogen atmosphere, for example, by heating at 80°C to 150°C for 10 to 30 minutes, to improve the cleanliness of the substrate surface and the consistency and adhesion of subsequent thin film deposition.

[0123] Second, silicon layer 121 deposition (as shown in 2b):

[0124] In some embodiments, a silicon layer 121 is deposited on the surface of a custom substrate 120 to serve as a functional or structural layer for subsequent microstructure fabrication.

[0125] In some embodiments, the silicon layer 121 may be polycrystalline silicon, amorphous silicon, or an epitaxial silicon layer, and its deposition method includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), or magnetron sputtering.

[0126] In some embodiments, the thickness of the silicon layer 121 is 100nm to 50μm, for example, 500nm, 1μm, 5μm, 10μm or 20μm, but is not limited to the above values.

[0127] Third, cavity structure etching (as shown in 2c):

[0128] In some embodiments, the deposited silicon layer 121 is subjected to photolithography and etching processes to form the back cavity structure of the device and to release the device.

[0129] In some embodiments, photoresist is first spin-coated onto the wafer, and then exposed and developed using a mask to form a photolithographic pattern corresponding to the cavity. The photolithographic pattern is used to define the cavity region, via location, or support frame boundary.

[0130] In some embodiments, dry etching may employ reactive ion etching (RIE) or deep reactive ion etching (DRIE) techniques. The etching atmosphere includes SF5, CF4, CHF3, or mixtures thereof. The etching depth and sidewall morphology can be adjusted according to the cavity structure requirements, but are not limited to the aforementioned process conditions. DRIE etching preferably employs the Bosch cycle process, achieving high depth and high verticality of the etched sidewalls through alternating etching and passivation. The etching depth can be controlled down to the SOI buried oxide layer, with a typical etching rate of 2 μm / min to 10 μm / min and a sidewall verticality better than 89°.

[0131] After etching, the photoresist is removed, preferably using an organic stripper (such as NMP or acetone) or oxygen plasma ashing to remove residues. It is then rinsed with deionized water and dried with nitrogen to obtain a cavity structure with a predetermined morphology.

[0132] Fourth, thin silicon wafer bonding (as shown in 2d):

[0133] In some embodiments, the thin silicon wafer is a composite structure wafer, which includes a lower silicon dioxide layer 122 and an upper silicon layer 123 from bottom to top. The lower silicon dioxide layer 122 is used to provide electrical insulation, bonding interface control, or stress buffering functions; the upper silicon layer 123 serves as a structural or functional layer, used to form the working area of ​​subsequent microstructures or devices.

[0134] In some embodiments, the thickness of the lower silicon dioxide layer 122 is 50nm to 2000nm, for example, 100nm, 300nm, 500nm or 1000nm, but not limited to the values ​​mentioned above; the thickness of the upper silicon layer 123 is 1μm to 200μm, for example, 5μm, 20μm, 50μm or 100μm, but not limited to the range mentioned above.

[0135] In some embodiments, before bonding the thin silicon wafer to the custom substrate 120, the surface of the lower silicon dioxide layer 122 of the thin silicon wafer and / or the bonding surface of the custom substrate 120 are subjected to surface pretreatment. The surface pretreatment includes, but is not limited to, cleaning, plasma activation, ozone treatment or chemical activation treatment, to improve the cleanliness and hydrophilicity of the bonding interface, thereby enhancing the bonding strength.

[0136] In some embodiments, the thin silicon wafer is bonded to the custom substrate 120 by direct bonding, including but not limited to silicon oxide-silicon oxide bonding or silicon-silicon oxide bonding; during the bonding process, pre-bonding is first performed at room temperature or low temperature, and then the interface bonding strength is improved by subsequent annealing treatment.

[0137] In some embodiments, the annealing temperature is 200°C to 1100°C, for example, 300°C, 500°C, 800°C, or 1000°C, and the annealing time is 10 min to 10 h, but is not limited to the parameter ranges. Annealing allows stable chemical bonds to form at the bonding interface, thereby achieving a strong bond between the thin silicon wafer and the custom substrate 120.

[0138] In some embodiments, the thin silicon wafer is precisely aligned with the custom substrate 120 during the bonding process using alignment marks to ensure the positional matching accuracy between subsequent microstructures or cavity structures and functional layers on the thin silicon wafer.

[0139] Fifth, thin film preparation (as shown in 2e):

[0140] In some embodiments, an insulating layer 124 is formed on the surface of the SOI wafer. The material of the insulating layer 124 may be one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), and hafnium oxide (HfO2).

[0141] In some embodiments, the insulating layer 124 can be formed by processes such as dry oxidation, wet oxidation, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sol-gel method or magnetron sputtering.

[0142] In some embodiments, the thickness of the insulating layer 124 is 10nm to 2000nm, for example, 50nm, 100nm, 200nm, 500nm or 1000nm, but is not limited to the values ​​mentioned above.

[0143] In some embodiments, a transition layer 125 is deposited on the insulating layer 124.

[0144] In some embodiments, the transition layer 125 includes at least one adhesion promoting and blocking material, such as titanium (Ti), chromium (Cr), nickel-chromium alloy (NiCr), etc., to improve the adhesion between the electrode and the substrate and prevent element diffusion during high-temperature processing.

[0145] In some embodiments, the transition layer 125 may further include a lattice matching and orientation control layer, such as lead titanate (PbTiO3, PT), strontium ruthenium oxide (SrRuO3, SRO), iridium oxide (IrO2), etc., to provide good lattice matching conditions for subsequent epitaxial or preferred orientation growth of piezoelectric thin films.

[0146] In some embodiments, the thickness of the transition layer 125 is 5nm to 500nm, for example, 10nm, 50nm, 100nm or 200nm, but is not limited to these values.

[0147] In some embodiments, a lower electrode layer 126 is deposited on the transition layer 125.

[0148] In some embodiments, the material of the lower electrode layer 126 is platinum (Pt), gold (Au), iridium (Ir), ruthenium (Ru), ruthenium oxide (RuO2), or an alloy thereof.

[0149] In some embodiments, the lower electrode layer 126 can be formed by physical vapor deposition (PVD), radio frequency magnetron sputtering, DC magnetron sputtering, reactive sputtering, pulsed laser deposition (PLD), or electron beam evaporation. Preferably, PVD sputtering technology is used to deposit a metal target on the substrate.

[0150] In some embodiments, the thickness of the lower electrode layer 126 is 20 nm to 500 nm, for example, 50 nm, 100 nm or 200 nm, but is not limited to these values.

[0151] In some embodiments, a piezoelectric thin film layer 127, also known as an electromechanical drive layer, is deposited on the lower electrode layer 126.

[0152] In some embodiments, the material of the electromechanical drive layer is one or more of lead zirconate titanate (PZT), aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead magnesium niobate (PMN), barium titanate (BaTiO3), shape memory alloy, polycrystalline silicon, or silicon nitride.

[0153] In some embodiments, the piezoelectric thin film layer 127 can be prepared by sputtering, pulsed laser deposition (PLD), sol-gel method, screen printing method, metal-organic chemical vapor deposition (MOCVD), aerosol deposition, solid-state reaction method, hot pressing sintering, mixed oxide method or chemical coprecipitation method.

[0154] Preferably, PVD technology is used to deposit a piezoelectric thin film layer 127 by radio frequency magnetron sputtering using a Pb-excess Pb1.2Zr0.52Ti0.48O3 target.

[0155] In some embodiments, the thickness of the electromechanical drive layer is 20nm to 10000nm, for example, 20nm, 100nm, 500nm, 1000nm, 5000nm or 10000nm, but is not limited to the values ​​mentioned above.

[0156] In some embodiments, an upper electrode layer 128 is deposited on the piezoelectric thin film layer 127.

[0157] In some embodiments, the material of the upper electrode layer 128 may be gold, platinum, iridium, aluminum, silver or ruthenium.

[0158] In some embodiments, the upper electrode layer 128 can be formed by methods such as physical vapor deposition (PVD), radio frequency magnetron sputtering, DC magnetron sputtering, reactive sputtering, pulsed laser deposition (PLD), or electron beam evaporation. Preferably, PVD sputtering is used.

[0159] In some embodiments, the thickness of the upper electrode layer 128 is 20nm to 1000nm, for example, 50nm, 100nm, 200nm or 500nm, but is not limited to these values.

[0160] In some embodiments, after the deposition of the upper electrode layer 128 is completed, the structure is heat-treated to promote the crystallization of the piezoelectric thin film and the formation of a perovskite crystal phase.

[0161] In some embodiments, the heat treatment method includes one or more of conventional furnace tube annealing, rapid thermal annealing (RTA), interlayer annealing, laser annealing, or microwave annealing.

[0162] Preferably, rapid thermal annealing (RTA) is used, for example, annealing at 500°C to 750°C for 1 to 10 minutes, to obtain a perovskite phase film with excellent piezoelectric properties, but not limited to the temperature and time mentioned above.

[0163] Sixth, the upper electrode layer 128 is patterned (as shown in 2f):

[0164] In some embodiments, the upper electrode layer 128 is graphically processed to define the geometric region of the upper electrode.

[0165] In some embodiments, photoresist is first spin-coated onto the surface of the upper electrode, and a predetermined electrode pattern is formed by exposure and development using a photomask. The photolithography process determines the exposure energy and development time based on the electrode linewidth and the required resolution. Subsequently, the electrode material not covered by the photoresist is removed using a dry etching or wet etching process. Dry etching can employ argon ion beam etching (IBE) or reactive ion etching (RIE), and the etching gas can be Ar, Cl2, O2, or a mixture thereof; wet etching can use an iodine / potassium iodide (I2 / KI) solution, aqua regia, or a hydrochloric acid system. Preferably, ion beam etching (IBE) is used to etch the upper electrode layer. After etching, the photoresist is removed by organic stripping solution or oxygen plasma ashing to obtain a clear upper electrode pattern with neat edges. Preferably, the etched sample is rinsed with deionized water and dried with nitrogen to reduce surface residues and contamination.

[0166] Seventh, patterning of the piezoelectric material layer (as shown in 2g):

[0167] In some embodiments, the piezoelectric thin film layer 127 is patterned to define the effective working area of ​​piezoelectric actuation.

[0168] In some embodiments, photoresist is first spin-coated onto the surface of the piezoelectric thin film layer 127, and a predetermined piezoelectric pattern is formed by mask exposure and development. The photolithography parameters can be optimized according to the piezoelectric layer thickness and film stress to prevent the photoresist from cracking or warping after development.

[0169] Subsequently, the piezoelectric thin film is patterned using wet etching. The etching solution can be a mixed solution containing hydrofluoric acid (HF), hydrochloric acid (HCl), nitric acid (HNO3), ethylenediaminetetraacetic acid (EDTA), or ammonia. The etching temperature can be controlled within the range of room temperature to 60°C to ensure etching rate and selectivity. After etching, photoresist residue is removed using organic solvents or oxygen plasma to obtain a piezoelectric structure layer with regular morphology and smooth edges. Preferably, low-temperature annealing (e.g., 300°C~400°C) can be performed to repair defects caused by etching and restore the piezoelectric activity of the film.

[0170] Eighth, the lower electrode layer 126 and the transition layer 125 are patterned (as shown in 2h):

[0171] In some embodiments, the lower electrode layer 126 and the transition layer 125 are patterned to form the electrode interconnection region and the electrical isolation structure.

[0172] In some embodiments, photoresist is first spin-coated onto the front side of the sample, and then exposed and developed using a mask to form a predetermined pattern. Subsequently, an etching process is used to remove the lower electrode material not covered by the photoresist, for example, dry etching using chlorine- or iodine-based reactive gases, or wet etching using aqua regia or a potassium iodide-iodine system. Preferably, the lower electrode layer is patterned using the same IBE technique as the upper electrode layer to obtain the predetermined electrode structure. Next, the underlying transition layer is etched, and the etching techniques used include, but are not limited to, dry etching and wet etching. Preferably, for Ti, a dilute HF solution can be used for rapid wet etching, or a Cl2 / BCl3-based dry etching method can be used; for Cr, a dedicated Cr etching solution such as cerium ammonium nitrate can be used. After etching, the photoresist is removed, and the sample is rinsed with deionized water and dried with nitrogen to obtain a lower electrode pattern structure with good adhesion and conductivity.

[0173] Ninth, structural pattern transfer and structural release (as shown in 2i):

[0174] In some embodiments, to realize the mechanical structure of the piezoelectric device, the pattern is transferred from the thin film layer to the silicon device layer.

[0175] In some embodiments, photoresist is first spin-coated onto the front side of the wafer and then exposed and developed to form a structural pattern. Subsequently, reactive ion etching (RIE) or deep reactive ion etching (DRIE) is used to sequentially remove the SiO2 protective layer and the silicon device layer, with the etching depth precisely controlled down to the SiO2 buried oxide layer (BOX) of the SOI wafer. Preferably, the RIE etching atmosphere may include a mixture of SF6, CHF3, CF4, or O2 gases to obtain high anisotropic etching characteristics and smooth sidewalls.

[0176] In some embodiments, to avoid damage to the piezoelectric layer and electrode layer, segmented etching or low-power process parameters can be used for processing to ensure structural integrity and surface quality.

[0177] In some embodiments, the SiO2 buried oxide layer is selectively removed using RIE technology, thereby releasing microstructures such as cantilever beams, diaphragms, fan blades, or pump chambers.

[0178] In some embodiments, a re-etching process (RIE) is used to remove the buried oxide layer. The etching atmosphere can be a CF4 / O2 or CHF3 / Ar mixture to achieve highly selective and low-damage release. Preferably, a critical point drying (CPD) process is combined during the release process to prevent the structure from sticking or warping due to surface tension.

[0179] In some embodiments, the photoresist is removed and the surface is cleaned to obtain the complete piezoelectric driven microstructure.

[0180] In the description of this application, the term "multiple" refers to two or more. Unless otherwise expressly defined, the terms "upper," "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "connection," "installation," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0181] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0182] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A three-dimensional integrated active heat dissipation structure, characterized in that, include: An upper cover layer, wherein an air inlet hole is provided on the upper cover layer; A fan and pump layer is disposed below the upper cover layer. The fan and pump layer includes an inlet pump array area, an outlet pump array area, and a fan array area located between the inlet pump array area and the outlet pump array area. At least one liquid cooling channel layer is disposed below the fan and pump layer, and a microchannel array is formed inside it; A high-power device layer is disposed below the at least one liquid-cooled flow channel layer; At least one heat spreader layer, the at least one heat spreader layer being disposed on at least one surface of the high-power device layer; At least one thermally conductive material layer is disposed between the high-power device layer and the heat spreader layer; A lower cover layer is disposed at the bottom of the entire structure; The fan array region is used to drive the airflow through the air inlet of the upper cover plate layer, and the pump inlet array region and the pump outlet array region are used to drive the coolant to circulate within the at least one liquid cooling channel layer. The microchannel array is provided with a turbulence-enhancing structure to strengthen turbulence, and the cross-sectional shape of the microchannel array is rectangular, trapezoidal, or needle-ribbed. The upper cover layer is also provided with auxiliary microchannels on its interior or lower surface; The two ends of the auxiliary microchannel are in fluid communication with the inlet and outlet pump array areas of the fan and pump layer, respectively, and are connected in parallel with the microchannel array in the at least one liquid cooling channel layer to form an internal circulation liquid cooling loop that can be selectively opened and closed. The inlet and outlet pump array areas of the fan and pump layer are also provided with an external circulation interface for connecting to an external cooling circuit. The three-dimensional integrated active heat dissipation structure is configured to have two operating modes: In internal circulation mode, the external circulation interface is closed, and the cooling working fluid circulates in a closed loop formed by the microchannel array consisting of the auxiliary microchannel and the at least one liquid-cooled channel layer. In external circulation mode, the external circulation interface is opened and connected to the external liquid storage chamber, and the cooling working fluid circulates in the loop formed by the external liquid storage chamber and the microchannel array of the at least one liquid-cooled flow channel layer.

2. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, The at least one liquid-cooled flow channel layer includes an upper liquid-cooled flow channel layer and a lower liquid-cooled flow channel layer; The upper liquid cooling channel layer is disposed between the fan and pump layer and the high-power device layer; The lower liquid cooling channel layer is disposed between the high-power device layer and the lower cover plate layer.

3. The three-dimensional integrated active heat dissipation structure according to claim 2, characterized in that, The at least one heat spreader layer includes an upper heat spreader layer and a lower heat spreader layer; The upper heat spreader layer is disposed between the upper liquid cooling channel layer and the high-power device layer; The lower heat spreader layer is disposed between the high-power device layer and the lower liquid cooling channel layer; The at least one thermally conductive material layer includes an upper thermally conductive material layer and a lower thermally conductive material layer; The upper thermally conductive material layer is disposed between the high-power device layer and the upper heat spreader layer; The lower thermally conductive material layer is disposed between the high-power device layer and the lower heat spreader layer.

4. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, The liquid-cooled flow channel layer has a multi-level fluid channel structure, including: Liquid inlet channel, which is connected to the pump array area; The pump inlet main flow channel is connected to the liquid inlet channel and is used for equalizing and distributing the coolant. A microchannel array, wherein the microchannel array is connected to the main pump inlet channel through a plurality of microchannel inlets; The main outlet flow channel is used to collect the liquid after heat exchange through the microchannel array. The liquid outlet channel is connected to the main flow channel of the pump outlet and the pump outlet array area.

5. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, The heat spreader layer is a vacuum-sealed cavity structure, comprising: The heat spreader body has a closed vapor-liquid two-phase heat transfer space inside it. Working fluid, which is encapsulated within the vapor-liquid two-phase heat transfer space; A capillary wick structure is disposed inside the heat spreader body to achieve capillary reflux of liquid.

6. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, The high-power device layer includes: A high-power device array region, wherein a power device array is integrated in the high-power device array region; A packaging substrate is disposed below the high-power device array area to support the devices and conduct heat.

7. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, Also includes: A fan exhaust layer is disposed between the fan and pump layer and the at least one liquid cooling channel layer. The fan exhaust layer includes an inlet pump connection pipe, an outlet pump connection pipe, and a central airflow layer.

8. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, The fan and pump layer also includes: The electrical interconnection region is electrically connected to the upper and lower adjacent layers through a micro-bump interconnection process.

9. The three-dimensional integrated active heat dissipation structure according to claim 1, characterized in that, The fan units in the fan array region and / or the pump units in the pump inlet array region and pump outlet array region adopt a piezoelectric drive structure, the piezoelectric drive structure comprising: Substrate; An insulating layer formed on the substrate; A transition layer is formed on the insulating layer; A lower electrode layer is formed on the transition layer; A piezoelectric thin film layer is formed on the lower electrode layer; An upper electrode layer is formed on the piezoelectric thin film layer.

Images