Silicon photonic chip unclonable identity system, identity method and identity authentication method

Abstract

The application relates to the technical field of silicon optical chip hardware security, in particular to a silicon optical chip unclonable identification system, an identification method and an identity authentication method, which deeply plant the identity identification in the physical structure of the chip, integrally form and permanently fix the chip, and fundamentally eliminate the possibility of removal, tampering or destruction. The unique random resistance arrangement of the chip gives the chip an unclonable physical fingerprint, and realizes intrinsic anti-counterfeiting and traceability. At the hardware level, the scheme is only composed of a pure passive resistance array, an on-chip analog-to-digital conversion and a serial readout interface, the device structure is extremely simple, the chip area overhead is extremely small, and the scheme is perfectly compatible with the standard SOI silicon optical manufacturing process, does not require any special materials or customized processes, and has almost zero production cost. Through a standardized digital interface output, the scheme is easy to integrate with various host systems; meanwhile, the scheme is internally provided with a registration-free black box algorithm, does not require a production line registration step, can be used as soon as possible by downstream manufacturers, and greatly reduces the deployment threshold.

Description

Technical Field

[0001] This application relates to the field of silicon photonics chip hardware security technology, specifically to a silicon photonics chip non-cloning identification system, identification method, and identity authentication method. Background Technology

[0002] With the large-scale application of silicon photonics technology in high-end fields such as optical communication encryption, quantum communication, and military optoelectronic systems, chip authentication and anti-counterfeiting traceability have become core security requirements. However, high-end silicon photonics chips face four insurmountable identity constraints:

[0003] (1) No external physical labels (barcodes, QR codes, nameplates) shall be attached to the chip surface to avoid affecting optical coupling and heat dissipation;

[0004] (2) Surface treatment processes such as laser marking and etching are prohibited to prevent damage to the optical waveguide structure and optical performance;

[0005] (3) Most silicon photonics chips do not have integrated non-volatile memory units (FLASH / ROM) and cannot store digital identities;

[0006] (4) Traditional challenges - responsive electrical PUF circuits are complex, consume a lot of power, and are vulnerable to side-channel attacks, which cannot meet the requirements of high security level.

[0007] Existing technologies cannot simultaneously address the four constraints mentioned above. The industry urgently needs a silicon photonics chip physical-level identification technology that is embedded, natively generated, requires no external additional structures, and is permanently fixed in one piece. Summary of the Invention

[0008] In view of this, the purpose of this application is to provide a non-clonable identification system, identification method, and identity authentication method for silicon photonic chips to solve the problems in the background art.

[0009] To achieve the above objectives, this application adopts the following technical solution:

[0010] This application discloses a method for identifying non-cloningable silicon photonic chips, comprising the following steps:

[0011] SOI substrate;

[0012] A passive discrete resistor array formed on the SOI substrate, wherein the passive discrete resistor array is manufactured by actively amplifying the systematic gradient and random fluctuation of process parameters to introduce controllable process discreteness, thereby increasing the random distribution range of resistance values. The passive discrete resistor array does not contain non-volatile memory cells and programmable logic circuits. The contact holes between the impedance cells in the passive discrete resistor array and the substrate are not treated with a desiliconization mask layer.

[0013] An electrical readout interface is electrically connected to the passive discrete resistor array and is used to scan the electrical response of multiple impedance units in the passive discrete resistor array, convert the electrical response of the multiple impedance units into digital signals and output them to the outside of the chip, wherein the electrical response is determined based on the resistance value.

[0014] In one embodiment of this application, the method for determining the discreteness of the controllable process includes at least one of the following:

[0015] Set the impedance unit linewidth to the limit dimension of the photolithography process at the corresponding process node;

[0016] Set the exposure dose gradient across the entire wafer;

[0017] The reactive ion etching loading effect is utilized by the regional differences in the density of the resistor array.

[0018] Set the ion implantation dose gradient;

[0019] Set a rapid thermal annealing temperature gradient.

[0020] In one embodiment of this application, the electrical readout interface includes:

[0021] A serial communication interface is connected to an external host to receive read signals from the external host, wherein the read signals include row address signals and column address signals;

[0022] A row decoder is used to select a target row from the passive discrete resistor array based on the row address signal and connect one end of all impedance units in the target row to a common readout bus.

[0023] A column multiplexer is used to receive a column address signal, determine a target impedance unit in the target row according to the column address signal, and connect the other end of the target impedance unit to a sampling circuit.

[0024] The sampling and analog-to-digital conversion circuit is used to sample the target impedance unit through a voltage divider network composed of the target impedance unit and the on-chip reference resistor connected in series to obtain the voltage divider voltage; and to perform analog-to-digital conversion on the voltage divider voltage to obtain a digitized electrical response quantity.

[0025] The serial communication interface is also used to return the electrical response quantity to the external host.

[0026] In one embodiment of this application, returning the electrical response quantity to the external host includes:

[0027] The digital code is extracted from the data register of the analog-to-digital converter circuit based on a pre-built finite state machine, and the digital code is written into the on-chip first-in-first-out queue in priority order, wherein the depth of the first-in-first-out queue is greater than or equal to the column length of the passive discrete resistor array.

[0028] When the data acquisition of all column impedance units in a row is completed, the finite state machine sets the data ready flag to notify the external host to read the row data through the serial communication interface.

[0029] In one embodiment of this application, the sampling and analog-to-digital conversion circuit is an 8-bit to 16-bit successive approximation analog-to-digital converter.

[0030] In one embodiment of this application, the material of the impedance unit is selected from at least one of unsiliconized polysilicon, doped device silicon layer, TiN or TaN, and the contact hole between the impedance unit and the substrate is not treated with a desiliconization mask layer.

[0031] In one embodiment of this application, the serial communication interface is an I²C bus interface, an SPI bus interface, a UART bus interface, an SMBus bus interface, or a 1-Wire bus interface.

[0032] In one embodiment of this application, the linewidth of the impedance unit is greater than the lower limit of the minimum resolvable size of the photolithography process at the corresponding process node.

[0033] In one embodiment of this application, the size of the passive discrete resistor array is from 16×16 to 256×256.

[0034] This application also provides a method for identifying silicon photonic chips as unclonable, applied to the aforementioned silicon photonic chip unclonable identification system, comprising:

[0035] The original resistance array is obtained by splicing all the digital codes in the digital signal according to the preset scanning order.

[0036] The original resistance array is preprocessed to obtain a preprocessed array, wherein the preprocessing includes bad bit removal and normalization.

[0037] The preprocessed array is binarized based on a pre-built global fixed threshold to obtain the original bit string in the form of a binarized array;

[0038] The original bit string is stabilized and mapped to obtain the unique identification information of the silicon photonic chip.

[0039] In one embodiment of this application, the stabilization mapping process is error correction decoding or fuzzy extraction, or the stabilization mapping process is hash mapping or the SM3 national cryptographic algorithm.

[0040] In one embodiment of this application, the normalization process includes: dividing each effective resistance value by the average or median of all effective resistance values ​​of the chip.

[0041] In one embodiment of this application, the defective bit rejection includes: identifying and rejecting resistance values ​​that exceed the mean ± 3σ range as defective bits, wherein σ is the standard deviation of the defective bits.

[0042] This application also provides an identity authentication method, including:

[0043] During the registration phase, the target silicon photonic chip or its first identity information is extracted based on the silicon photonic chip non-cloning identification method described above, and the first identity information is stored in a secure database.

[0044] During the authentication phase, a second identity information of the target silicon photonic chip is extracted based on a silicon photonic chip non-cloning identification method as described above, and identity authentication is performed by comparing the first identity information and the second identity information.

[0045] In one embodiment of this application, the registration phase is performed during the wafer testing phase, and the first identity information is associated with and recorded with the physical coordinates of the chip on the wafer.

[0046] The beneficial effects of this application are as follows: The silicon photonics chip non-cloning identification system, identification method, and identity authentication method of this application deeply embed the identity identifier into the physical structure of the chip, making it integrally formed and permanently fixed with the chip, fundamentally eliminating the possibility of removal, tampering, or destruction. Its unique random resistance value arrangement gives the chip an unclonable physical fingerprint, achieving essential anti-counterfeiting and traceability. At the hardware level, this application consists only of a pure passive resistor array and an on-chip analog-to-digital converter and serial readout interface, with an extremely simple device structure, minimal chip area overhead, and perfect compatibility with standard SOI silicon photonics manufacturing processes, requiring no special materials or customized processes, resulting in almost zero mass production costs. At the system application level, this solution outputs through a standardized digital interface, making it easy to integrate with various host systems; at the same time, it has a built-in registration-free black-box algorithm, eliminating the need for production line registration steps, allowing downstream manufacturers to plug and play, significantly reducing the deployment threshold. This application combines permanence, anti-cloning, process compatibility, and ease of deployment, providing a systematic solution for the identity authentication of high-end silicon photonics chips. Attached Figure Description

[0047] The present application will be further described below with reference to the accompanying drawings and embodiments:

[0048] Figure 1 This is a structural diagram of a silicon photonic chip non-cloning identification system shown in one embodiment of this application;

[0049] Figure 2This is a schematic diagram of the active discrete manufacturing process in one embodiment of this application;

[0050] Figure 3 This is a schematic diagram of the electrical readout interface in one embodiment of this application;

[0051] Figure 4 This is a schematic flowchart of a method for identifying a silicon photonic chip as unclonable in one embodiment of this application;

[0052] Figure 5 This is an identity authentication method in one embodiment of this application. Detailed Implementation

[0053] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0054] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the layers related to this application and are not drawn according to the actual number, shape and size of the layers in the actual implementation. In the actual implementation, the form, number and proportion of each layer can be arbitrarily changed, and the layer layout may also be more complex.

[0055] Numerous details are explored in the following description to provide a more thorough explanation of embodiments of this application; however, it will be apparent to those skilled in the art that embodiments of this application may be practiced without these specific details.

[0056] Existing silicon photonic PUFs all rely on process deviations in the optical structure to generate identifiers, but this has significant limitations:

[0057] Silicon photonic moiré quasi-crystalline interferometer (PUF): It has a complex structure, occupies a large chip area, and only supports single-channel optical readout;

[0058] Reverse coupler (CDC) silicon photonics PUF: highly sensitive to process deviations, but with poor stability; temperature changes can easily cause label drift.

[0059] All-silicon multidimensional coded optical PUF (Nature Communications, 2024): integrates silicon metasurface and erbium-doped silicon quantum dots, with an information entropy of 2.32 bits / pixel, but requires additional quantum dot fabrication process and has poor compatibility with standard SOI silicon photonics process;

[0060] Reconfigurable silicon photonic PUF (Optics Letters, 2025): It utilizes the stochastic nonlinearity of silicon photonic neuromorphic computing with a cloning probability as low as 10⁻¹, but it relies on complex on-chip computing units and is very expensive.

[0061] Based on the above analysis, it can be seen that neither electronic chip resistive PUFs nor silicon photonic optical PUFs in the existing technology can simultaneously meet the four identity constraints of high-end silicon photonic chips:

[0062] Although the electronic chip resistor PUF meets the requirements of being unlabeled, uncoded, and without memory devices, its design carrier is a pure CMOS electronic chip, which cannot be natively integrated with the optical waveguides and thermo-optical devices of silicon photonics chips. Furthermore, its readout method is an analog pin or parallel interface, which does not meet the stringent limitations of silicon photonics chips on the number of pads and the surface area of ​​the chip.

[0063] While silicon photonic optical PUFs can be integrated into silicon photonic chips, they either require additional materials (such as erbium-doped silicon quantum dots) or complex computing units (such as neuromorphic computing), or they only support single-channel optical readout and are sensitive to ambient temperature, failing to meet the engineering requirements of low cost and high stability.

[0064] All existing PUF solutions require a registration process on the production line and the storage of auxiliary data or reference responses, which increases production costs and safety risks.

[0065] Therefore, the industry urgently needs a native identification solution for silicon photonic chips that can simultaneously meet the four constraints of "no external tags, no laser marking, no storage devices, and no complex PUF circuits," and is fully compatible with standard SOI silicon photonics processes, allowing for plug-and-play operation without registration. This invention is proposed precisely to address this need.

[0066] In terms of overall approach, this application breaks away from the traditional semiconductor industry design approach of "suppressing process errors." Instead, it takes the opposite approach by actively introducing and precisely controlling process discreteness to fabricate a purely passive discrete resistor array (impedance unit array) on the silicon photonics chip. The random resistance distribution of the impedance units generates a unique physical fingerprint. An analog-to-digital converter (ADC) and a serial communication interface are integrated on the silicon photonics chip. The resistance distribution of the resistor array is scanned, digitized, and output via the serial communication interface, allowing an external host to extract the chip's unique identifier using a registration-free black-box algorithm. This solution eliminates the need for physical tags, laser marking, storage devices, or traditional PUF circuits, is fully compatible with standard SOI silicon photonics manufacturing processes, and achieves a native, permanent, tamper-proof, and cloning-proof virtual identity for the silicon photonics chip.

[0067] Figure 1This is a structural diagram of a silicon photonic chip non-cloning identification system shown in one embodiment of this application, as follows: Figure 1 As shown, a silicon photonics chip non-cloning identification system of this application includes:

[0068] SOI substrate 110;

[0069] A passive discrete resistor array 120 is formed on the SOI substrate. During the manufacturing process, the passive discrete resistor array introduces controllable process discreteness by actively amplifying the systematic gradient and random fluctuation of process parameters, thereby increasing the random distribution range of resistance values. The passive discrete resistor array does not contain non-volatile memory cells or programmable logic circuits. The contact holes between the impedance cells in the passive discrete resistor array and the substrate are not treated with a desiliconization mask layer.

[0070] An electrical readout interface 130 is electrically connected to the passive discrete resistor array and is used to scan the electrical response of multiple impedance units in the passive discrete resistor array, convert the electrical response of the multiple impedance units into digital signals and output them to the outside of the chip, wherein the electrical response is determined based on the resistance value.

[0071] The following section will provide a detailed introduction to the aforementioned silicon photonics chip non-cloning identification system, based on its overall architecture, passive discrete resistor array manufacturing process, electrical readout interface structure, digital control and serial transmission logic, and electrical readout process.

[0072] (1) Overall architecture;

[0073] The aforementioned non-cloning identification system for silicon photonics chips integrates a purely passive resistor array unit on the SOI silicon photonics chip, and the overall architecture satisfies:

[0074] There are no non-volatile memory cells (FLASH / ROM / EEPROM).

[0075] There are no transistors, floating gate structures, or active devices (except for the readout circuitry);

[0076] No programmable circuitry or challenge-response logic;

[0077] It consists of only a number of independent impedance units (impedance units) connected by standard metal interconnects.

[0078] The row and column metal electrodes of the resistor array are electrically connected to the electrical readout interface, which includes an analog-to-digital converter (ADC) and a serial communication interface, used to scan and acquire the resistance distribution of each impedance unit, convert it into digital form, and output it to the outside of the chip.

[0079] The ADC and serial communication interface can be implemented using conventional analog-to-digital conversion and serial communication circuits in the art (such as successive approximation ADC, I²C slave interface or SPI slave interface), and the present invention does not limit its specific internal circuit structure.

[0080] Device selection guidelines: Impedance unit materials can be non-siliconized polysilicon, doped silicon, TiN, TaN, or other standard silicon photonics compatible materials; the array size is preferably 32×32 (1024 units), which can be flexibly adjusted between 16×16 and 256×256 according to the required number of elements; the metal interconnects use standard TiN / Ti / Al or Ti / Au processes. Contact holes do not use a silicid-block layer.

[0081] The aforementioned ion implantation gradient doping is performed outside the contact hole region that is not treated with a desiliconization mask layer. The two processes are independent of each other at the layout level and do not conflict with each other in terms of process.

[0082] (2) Manufacturing process of passive discrete resistor array;

[0083] Figure 2 This is a schematic diagram of the active discrete manufacturing process in one embodiment of this application, as shown below. Figure 2 As shown, by artificially relaxing the process control precision in specific areas and actively amplifying random process deviations, the inter-chip resistance dispersion is increased from the conventional ±5% to over ±30%. Specific process methods include:

[0084] S1: Forming a resistive material layer; S2: Actively introducing controllable process dispersion; S3: Patterning etching to form a resistive array; S4: Forming metal interconnects and PAD leads; wherein, the following five processes are applied in S2:

[0085] Limit linewidth design: Set the linewidth of the impedance unit to the limit size of the photolithography process (e.g., 180-220nm under the 180nm process node), and use the small linewidth fluctuations to cause a large random drift in the resistance value.

[0086] Wafer exposure dose gradient: A linear exposure dose gradient (gradient range ±5%~±10%) is set from the center to the edge of the entire wafer to create systematic differences in the size of resistor patterns on different chips;

[0087] Etching load effect control: By using non-uniform resistor array arrangement density (density variation range of 20%-80%), the load effect of RIE dry etching is used to create random differences in local etching rate.

[0088] Ion implantation gradient doping: By controlling the dose gradient (gradient range ±10%~±15%) and energy of ion implantation, a self-feedback random doping mode is constructed to enhance the resistance disorder.

[0089] Annealing temperature gradient: Introducing a wafer temperature gradient (gradient range ±20℃~±50℃) during rapid thermal annealing (RTA) further amplifies the random distribution of doping concentration and grain size.

[0090] Yield assurance: The selection of the above active discretization process parameters ensures that the linewidth of the impedance unit is still greater than the minimum resolvable size limit of the photolithography process (not less than 150nm for 180nm node), ensuring that each impedance unit in the array is not broken or short-circuited, and the yield is ≥95%; if necessary, redundant units can be set in the array and software shielding processing of skipping bad bits in rows and columns can be adopted.

[0091] The relationship between gradient parameters and discreteness:

[0092] The five process methods mentioned above contribute differently to the resistance dispersion, and the typical correspondence is shown in Table 1 (based on measured data from a 180nm SOI process platform):

[0093] Table 1. Contribution of different processes to resistance dispersion

[0094] process methods Typical parameter range Contribution to resistance dispersion Limit linewidth design Linewidth 180~220nm ±8%~±15% Exposure dose gradient ±5%~±10% ±5%~±10% Etching Loading Effect Density 20%–80% ±3%~±8% Ion implantation gradient ±10%~±15% ±8%~±12% Annealing temperature gradient ±20℃~±50℃ ±5%~±10%

[0095] After combining the above five methods, the inter-chip resistance dispersion can reach ±30%~±40%. When each parameter is within a given range, it can be guaranteed that the impedance unit will not be interrupted or short-circuited, and the yield rate is ≥95%. The above parameter range can be adjusted through the standard process menu on mainstream SOI silicon photonics process platforms (such as Tower PH18, GF 45SPCLO), without the need for additional special equipment.

[0096] (3) Electrical readout interface structure;

[0097] Figure 3 This is a schematic diagram of the electrical readout interface in one embodiment of this application, as shown below. Figure 3 As shown, the electrical readout interface 130 adopts a standard array readout architecture of row decoder + column multiplexer + single-channel SARADC, including:

[0098] The serial communication interface 310 is connected to an external host and is used to receive read signals from the external host, wherein the read signals include row address signals and column address signals;

[0099] The serial communication interface is an I²C bus interface, SPI bus interface, UART bus interface, SMBus bus interface, or 1-Wire bus interface.

[0100] Row decoder 320 is used to select a target row from the passive discrete resistor array based on the row address signal and connect one end of all impedance units in the target row to a common readout bus.

[0101] Specifically, the row decoder 320 is composed of standard CMOS transmission gates. Based on the row address signal sent by the external host through the serial interface, it selects a row of the resistor array and connects one end of all impedance units in that row to the common readout bus.

[0102] Column multiplexer 330 is used to receive column address signal, determine target impedance unit in target row according to column address signal, and connect the other end of target impedance unit to sampling circuit;

[0103] The column multiplexer 330 is composed of an NMOS switch array, which sequentially selects each column in the selected row and connects the other end of the selected impedance unit to the sampling circuit.

[0104] The sampling and analog-to-digital conversion circuit 340 is used to sample the target impedance unit through a voltage divider network composed of the target impedance unit and the on-chip reference resistor connected in series to obtain the voltage divider voltage; and to perform analog-to-digital conversion on the voltage divider voltage to obtain a digitized electrical response quantity.

[0105] In the sampling and analog-to-digital conversion circuit 340, each selected impedance unit is connected to an on-chip precision reference resistor. Forming a voltage divider network, the voltage divider voltage The data is fed into an on-chip 12-bit successive approximation analog-to-digital converter (SAR ADC) for quantization. The reference voltage for the ADC is provided by an on-chip bandgap reference source. For reference voltage, This represents the resistance value of the impedance unit. The value of the reference resistor.

[0106] The serial communication interface is also used to return the electrical response quantity to the external host. During the return process, the on-chip finite state machine (FSM) controls the row address increment, column gating switching and ADC sampling timing, and stores the digital resistance values ​​of each unit in row priority order into the output buffer, waiting for the external host to read them through the serial interface.

[0107] (4) Digital control and serial transmission logic;

[0108] In this application, during the process of returning the electrical response quantity to the external host, the digital resistance value converted by the ADC does not automatically appear on the serial interface. Instead, the data acquisition, temporary storage, and transmission are coordinated by the on-chip digital control logic (finite state machine, FSM), including:

[0109] (4-1) Extract digital codes from the data register of the analog-to-digital converter circuit based on a pre-built finite state machine, and write the digital codes into the on-chip first-in-first-out queue in priority order, wherein the depth of the first-in-first-out queue is greater than or equal to the column length of the passive discrete resistor array;

[0110] After each ADC conversion, the FSM reads a 12-bit digital code from the ADC's data register and writes it into the on-chip first-in-first-out queue (FIFO) or shift register in row priority order. The FIFO depth is at least the number of cells in one row of the array (e.g., a 32×32 array requires a depth of ≥32), ensuring that the entire row of data can be temporarily stored during column scanning and await serial transmission.

[0111] (4-2) When the data acquisition of all column impedance units in a row is completed, the finite state machine sets the data ready flag to notify the external host to read the row data through the serial communication interface.

[0112] Once a row of data has been acquired (or the entire array has been acquired), the FSM sets the "data ready" flag to notify the I²C / SPI slave interface that it can start sending.

[0113] (4-3) The external host sends a read command through the serial bus. The I²C / SPI slave interface retrieves data from the FIFO in sequence and sends it to the host in the standard protocol format (MSB first, 8-bit / 16-bit packing).

[0114] The above digital control logic is a standard digital circuit design that can be synthesized using hardware description languages ​​(Verilog / VHDL), requiring no more than 5,000 gates, and the increase in chip area is negligible.

[0115] The basic state transitions of the finite state machine include: upon receiving a read instruction in the idle state, entering the row acquisition state; in the row acquisition state, incrementing the row address and entering the column acquisition state; in the column acquisition state, sequentially selecting each column and triggering ADC conversion; after a single column of data is completed, returning to column acquisition until all columns of the row are acquired; after the entire row of data is acquired, setting the data ready flag and entering the transmit waiting state; and returning to the idle state after the external host has finished reading.

[0116] (5) Electrical readout process

[0117] After the chip is powered on normally, the electrical readout interface converts the resistance value of each impedance unit into a digital code in sequence through the on-chip ADC;

[0118] Concatenate all the numeric codes in row-major order to generate the original resistance value array;

[0119] The original resistance array is output to the external host via a serial communication interface.

[0120] To further simplify the chip deployment process and eliminate the production line registration step, this invention provides a registration-free black-box identity extraction algorithm. This algorithm takes the raw resistance array (i.e., the digital resistance values ​​of each unit output by the ADC) read after the chip is powered on as input and directly outputs the chip's unique identifier, without requiring any pre-stored auxiliary data or reference response.

[0121] Figure 4 This is a schematic flowchart of a method for identifying a silicon photonic chip as unclonable, as described in one embodiment of this application. Figure 4 As shown, this application also provides a method for identifying unclonable silicon photonic chips (a registration-free black-box identity extraction algorithm), applied to the aforementioned unclonable silicon photonic chip identification system, comprising:

[0122] S410, resistance input, concatenates all digital codes in the digital signal based on a preset scan order to obtain the original resistance value array;

[0123] The original digital resistance array R[0.N-1] of N impedance units;

[0124] S420, Preprocessing: The original resistance array is preprocessed to obtain a preprocessed array, wherein the preprocessing includes bad bit removal and normalization.

[0125] Specifically, it includes:

[0126] S420-1, the upper and lower limits of the normal range can be determined according to the statistical distribution of the effective resistance values ​​in the same batch of wafer testing. For example, the resistance value within the range of the mean ± 3σ is taken as the effective resistance value, and if it exceeds this range, it is judged as a bad bit.

[0127] S420-2, normalizes the remaining effective resistance values: divide each resistance value by the average (or median) of all effective resistance values ​​of the chip to eliminate the overall baseline drift caused by factors such as temperature and aging.

[0128] S430, Feature extraction and quantization encoding: The preprocessed array is binarized based on a pre-constructed global fixed threshold to obtain the original bit string in the form of a binarized array;

[0129] Specifically, the normalized resistance value is compared with a globally fixed threshold (e.g., 1.0, i.e., the average value itself):

[0130] Normalized resistance > threshold → encoded as "1";

[0131] If the normalized resistance value is less than or equal to the threshold, it is encoded as “0”.

[0132] Concatenate the binary codes of all valid bits in row-major order to generate the original bit string;

[0133] S440, Stabilization output: The original bit string is stabilized and mapped to obtain the unique identity information of the silicon photonic chip.

[0134] Perform error correction decoding (such as BCH) or hash mapping (such as SHA-256) on the original bit string to output a stable identity identifier of fixed length (such as 128 bits).

[0135] In one embodiment of this application, the stabilization mapping process is error correction decoding or fuzzy extraction, or the stabilization mapping process is hash mapping or the SM3 national cryptographic algorithm.

[0136] S450 outputs the identity identifier, and finally outputs the unique identifier (ID) of the chip.

[0137] The features of the above algorithm include:

[0138] No registration required: The chip does not require a registration process on the production line when it leaves the factory, and no auxiliary data or reference response needs to be stored;

[0139] High robustness: Normalization process eliminates overall baseline drift caused by temperature and aging, and defective bit removal ensures that abnormal cells do not affect the output;

[0140] Plug and play: Downstream manufacturers (such as optical module manufacturers) can integrate the algorithm into the MCU firmware of their products as a firmware library to achieve instant identity authentication of silicon photonic chips.

[0141] Confidential delivery: The algorithm can be delivered as a binary library, protecting core intellectual property rights.

[0142] Figure 5 This application provides an embodiment of an authentication method, such as... Figure 5 As shown, this application also provides an identity authentication method, including:

[0143] S510, during the registration phase, the target silicon photonic chip or the first identity information of the target silicon photonic chip is extracted based on the silicon photonic chip non-cloning identification method described above, and the first identity information is stored in the security database;

[0144] S520, during the authentication phase, the second identity information of the target silicon photonic chip is extracted based on a silicon photonic chip non-cloning identification method as described above, and identity authentication is performed by comparing the first identity information and the second identity information.

[0145] The registration and comparison logic for the aforementioned identity identifiers:

[0146] The unique identifier (ID) output by the black-box algorithm is the chip's physical fingerprint, which is not stored internally within the chip. Upon initial deployment, the external host reads the chip's output ID via a serial interface and records it in an external security database or a server's whitelist. During subsequent authentication attempts, the host reads the chip's current ID again and compares it with the pre-stored ID in the database: if they match, authentication succeeds; otherwise, authentication fails.

[0147] Since the ID is uniquely determined by the chip's physical structure and cannot be tampered with, there is no need to store any keys or auxiliary data inside the chip, which fundamentally solves the key storage problem caused by the lack of integrated non-volatile memory units (Flash / ROM) in silicon photonics chips.

[0148] Furthermore, this application can be fully registered at the wafer stage, with the communication pins of the serial communication interface (I²C / SPI) led out to the chip surface in the form of standard PADs on the chip layout. During the wafer testing (CP, ChipProbing) stage after wafer fabrication is completed, the testing equipment directly contacts the PADs through a probe card and sends a read command to the chip to read its unique identification (ID).

[0149] Since the ID can be obtained at the wafer stage, it can be associated with the chip's physical coordinates (row and column numbers) on the wafer to form a wafer-level identity map. This map can be used for:

[0150] Chips with abnormal IDs or those that cannot be reliably read before packaging are eliminated to avoid unnecessary packaging costs.

[0151] In subsequent chip mounting and assembly processes, the wafer origin and process batch of the chip are traced through ID.

[0152] Provides a wafer-level raw data foundation for system-level identity management.

[0153] The aforementioned wafer-level ID reading does not rely on chip packaging, nor does it require storing any keys or auxiliary data inside the chip, further reducing deployment costs.

[0154] The technical solution of the present invention effectively overcomes all the defects of the prior art and produces the following significant technical effects:

[0155] (1) Identity security: The identifier is embedded in the chip's physical structure, permanently fixed, and cannot be removed, tampered with, or destroyed;

[0156] (2) Anti-cloning capability: The random deviation of the active amplification process is unique, and there is no duplicate resistance value arrangement in the same batch of chips, so the probability of cloning is extremely low.

[0157] (3) Extremely simple device structure: pure passive resistor array, no complex PUF circuit, no active devices, and minimal layout footprint (<0.1mm²).

[0158] (4) On-chip ADC + serial interface readout: Supports standardized digital output, easy to integrate with various host systems, and the chip only requires a small number of pads (I²C: 4; SPI: 6).

[0159] (5) Process compatibility: It relies entirely on the standard SOI silicon photonics manufacturing process, without the need for additional special materials or customized processes, and the mass production cost is almost zero;

[0160] (6) Excellent environmental stability: The resistance value remains stable over a long period of time and is not affected by normal temperature and humidity, electromagnetic environment and long-term aging.

[0161] (7) No registration required, plug and play: Black-box algorithms do not require production line registration steps, and downstream manufacturers can directly integrate and use them, greatly reducing the deployment threshold.

[0162] Basis for quantitative estimation of technical effects:

[0163] Cloning probability estimation: For a 32×32 resistor array (1024 cells), under active discretization, the resistance value of each cell is randomly and independently distributed within the range of 10kΩ to 100MΩ. After normalization and quantization encoding, the effective entropy of each cell is not less than 0.95 bits / cell (based on the assumption that there is no significant correlation between adjacent resistance value distributions). Therefore, the total entropy... The cloning probability is approximately far below Even considering the potential inter-unit correlations (correlation coefficients) in actual processes. <0.1), the effective entropy is still not less than 850 bits, and the cloning probability is still less than .

[0164] Layout area estimation: For a 32×32 resistor array with a 2μm cell side length, the array area is approximately 64μm×64μm ≈ 0.004mm²; the peripheral circuit area for the row decoder, column multiplexer, and SARADC is approximately 0.01mm²~0.02mm²; the total chip area increment is <0.03mm². For a 64×64 array, the total chip area increment is <0.08mm². The above area estimation is based on the standard cell library of the 180nm process node; the actual area will further decrease as the process node shrinks.

[0165] Resistance dispersion verification: At the 180nm process node, by setting the polysilicon resistor linewidth to 180nm (the lithography limit), and with an exposure dose gradient of ±8%, an ion implantation dose gradient of ±12%, and an annealing temperature gradient of ±30℃, a chip-to-chip resistance dispersion of ≥±30% can be achieved on a standard SOI silicon photonics platform (actual measurement data comes from a statistical sample of test chips on the same process platform, with a sample size of ≥100 chips / batch). Under conventional process control (without active dispersion measures), the batch-to-batch dispersion is approximately ±5%~±8%, and this invention improves the dispersion by approximately 4~6 times.

[0166] Reliability analysis:

[0167] The ADC, digital control logic (FSM), and serial communication interface added in this invention are all mature semiconductor IPs, and their impact on the overall reliability of the chip is minimal.

[0168] ADC Reliability: SARADC is a mature, mass-produced IP with extensive production verification across automotive (-40℃~125℃) and industrial (-40℃~85℃) temperature ranges. In this solution, the ADC is only powered on briefly (milliseconds) during certification, not continuously, resulting in extremely slow aging. The ADC's reference voltage temperature drift (typically <50ppm / ℃) is canceled out in the normalization algorithm, not affecting PUFID stability. The ADC's signal-to-noise ratio (>70dB) far exceeds the quantization requirements of resistor arrays, and noise will not cause bit flips.

[0169] FSM reliability: Extremely small digital control logic size (<5000 gates), extremely low operating frequency (ADC sampling rate <1MHz, serial interface rate <400kHz), ample timing margin, and no timing convergence risk. Automatic reset is possible under abnormal conditions via a watchdog timer.

[0170] Serial interface reliability: I²C / SPI are standard digital interfaces with decades of mass production verification history. In this solution, the chip always acts as a slave and will not actively initiate communication, eliminating the risk of bus contention. Signal integrity is excellent during low-speed communication (standard mode 100kHz / 400kHz).

[0171] Overall failure rate: The additional failure rate increment of the above circuit modules is <0.1%, which has no significant impact on the overall reliability of the chip.

[0172] Cost analysis:

[0173] Chip area cost: The total area increase for the ADC, FSM, and serial interface is approximately 0.021 mm² (SARADC approximately 0.015 mm², FSM + FIFO approximately 0.002 mm², I²C / SPI slave approximately 0.001 mm², row decoder + column MUX approximately 0.003 mm²), plus the 0.005 mm² of the resistor array itself, totaling approximately 0.026 mm². For a typical silicon photonics chip (area 10~50 mm²), the area increase accounts for <0.3%, and the cost increase is negligible.

[0174] Process cost: In the silicon photonics SOI process with CMOS option, ADC and digital logic are part of the standard process menu, requiring no additional photolithography layers or process steps, and there is no increase in mask cost.

[0175] Testing Costs: PUF functional testing can be integrated into the existing wafer testing (CP) process, with a single-chip testing time increase of <10ms and minimal increase in testing costs.

[0176] This application presents a non-cloning identification system, identification method, and authentication method for silicon photonics chips. The identification identifier is deeply embedded in the chip's physical structure, permanently fixed and integrally formed with the chip, fundamentally eliminating the possibility of removal, tampering, or destruction. Its unique random resistance arrangement gives the chip a non-cloning physical fingerprint, achieving essential anti-counterfeiting and traceability. At the hardware level, this application consists only of a pure passive resistor array, on-chip analog-to-digital converter, and serial readout interface. The device structure is extremely simple, with minimal chip area overhead, and it is perfectly compatible with standard SOI silicon photonics manufacturing processes, requiring no special materials or customized processes, resulting in near-zero mass production costs. At the system application level, this solution outputs through a standardized digital interface, facilitating integration with various host systems. Simultaneously, it incorporates a registration-free black-box algorithm, eliminating the need for production line registration steps, allowing downstream manufacturers to plug and play, significantly lowering the deployment threshold. This application combines permanence, anti-cloning properties, process compatibility, and ease of deployment, providing a systematic solution for the authentication of high-end silicon photonics chips.

[0177] In the above embodiments, although the present application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. The embodiments of the present application are intended to cover all such substitutions, modifications, and variations falling within the broad scope of the appended claims.

[0178] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A silicon photonics chip non-cloning identification system, characterized in that, include: SOI substrate; A passive discrete resistor array formed on the SOI substrate, wherein the passive discrete resistor array introduces controllable process discreteness by actively amplifying the systematic gradient and random fluctuation of process parameters during manufacturing, thereby increasing the random distribution range of resistance values. The passive discrete resistor array does not contain non-volatile memory cells or programmable logic circuits, and the contact holes between the impedance cells and the substrate in the passive discrete resistor array are not treated with a siliconization mask layer. The controllable process discreteness method includes at least one of the following: setting the impedance cell linewidth to the limit size of the photolithography process at the corresponding process node; setting an exposure dose gradient over the entire wafer; utilizing the reactive ion etching loading effect through regional differences in resistor array density; setting an ion implantation dose gradient; setting a rapid thermal annealing temperature gradient. An electrical readout interface is electrically connected to the passive discrete resistor array and is used to scan the electrical response of multiple impedance units in the passive discrete resistor array, convert the electrical response of the multiple impedance units into digital signals and output them to the outside of the chip, wherein the electrical response is determined based on the resistance value.

2. The silicon photonics chip non-cloning identification system according to claim 1, characterized in that, The electrical readout interface includes: A serial communication interface is connected to an external host to receive read signals from the external host, wherein the read signals include row address signals and column address signals; A row decoder is used to select a target row from the passive discrete resistor array based on the row address signal and connect one end of all impedance units in the target row to a common readout bus. A column multiplexer is used to receive a column address signal, determine a target impedance unit in the target row according to the column address signal, and connect the other end of the target impedance unit to a sampling circuit. The sampling and analog-to-digital conversion circuit is used to sample the target impedance unit through a voltage divider network composed of the target impedance unit and the on-chip reference resistor connected in series to obtain the voltage divider voltage; and to perform analog-to-digital conversion on the voltage divider voltage to obtain a digitized electrical response quantity. The serial communication interface is also used to return the electrical response quantity to the external host.

3. The silicon photonics chip non-cloning identification system according to claim 2, characterized in that, Returning the electrical response quantity to the external host includes: The digital code is extracted from the data register of the analog-to-digital converter circuit based on a pre-built finite state machine, and the digital code is written into the on-chip first-in-first-out queue in priority order, wherein the depth of the first-in-first-out queue is greater than or equal to the column length of the passive discrete resistor array. When the data acquisition of all column impedance units in a row is completed, the finite state machine sets the data ready flag to notify the external host to read the row data through the serial communication interface.

4. The silicon photonics chip non-cloning identification system according to claim 2, characterized in that, The sampling and analog-to-digital conversion circuit is an 8-bit to 16-bit successive approximation analog-to-digital converter.

5. A silicon photonics chip non-cloning identification system according to claim 1, characterized in that, The material of the impedance unit is selected from at least one of unsiliconized polysilicon, doped device silicon layer, TiN or TaN, and the contact hole between the impedance unit and the substrate is not treated with a desiliconization mask layer.

6. A silicon photonics chip non-cloning identification system according to claim 2, characterized in that, The serial communication interface is I. 2 C bus interface, SPI bus interface, UART bus interface, SMBus bus interface or 1Wire bus interface.

7. A silicon photonics chip non-cloning identification system according to claim 1, characterized in that, The linewidth of the impedance unit is greater than the lower limit of the minimum resolvable size of the photolithography process at the corresponding process node.

8. A silicon photonic chip non-cloning identification system according to claim 1, characterized in that, The size of the passive discrete resistor array ranges from 16×16 to 256×256.

9. A method for identifying the non-cloning nature of silicon photonic chips, applied to the non-cloning nature identification system for silicon photonic chips as described in claim 1, characterized in that, include: The original resistance array is obtained by splicing all the digital codes in the digital signal according to the preset scanning order. The original resistance array is preprocessed to obtain a preprocessed array, wherein the preprocessing includes bad bit removal and normalization. The preprocessed array is binarized based on a pre-built global fixed threshold to obtain the original bit string in the form of a binarized array; The original bit string is stabilized and mapped to obtain the unique identification information of the silicon photonic chip.

10. A method for identifying the non-cloning nature of a silicon photonic chip according to claim 9, characterized in that, The stabilization mapping process is either error correction decoding or fuzzy extraction, or it is either hash mapping or the SM3 national cryptographic algorithm.

11. The method for identifying a silicon photonic chip as unclonable according to claim 9, characterized in that, The normalization process includes dividing each effective resistance value by the average or median of all effective resistance values ​​of the chip.

12. The method for identifying a silicon photonic chip as described in claim 10, characterized in that, The defective bit removal includes: identifying and removing resistance values ​​that exceed the mean ± 3σ range as defective bits, where σ is the standard deviation of the defective bit.

13. An identity authentication method, characterized in that, include: During the registration phase, the target silicon photonic chip or the first identity information of the target silicon photonic chip is extracted based on the silicon photonic chip non-cloning identification method as described in claim 9, and the first identity information is stored in a secure database; During the authentication phase, the second identity information of the target silicon photonic chip is extracted based on the silicon photonic chip non-cloning identification method as described in claim 10, and identity authentication is performed by comparing the first identity information and the second identity information.

14. The identity authentication method according to claim 13, characterized in that, The registration phase is performed during the wafer testing phase, and the first identity information is associated with and recorded with the physical coordinates of the chip on the wafer.

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