Analog parallel intelligent conversation CPU and its control method

Abstract

The application discloses a kind of analog parallel intelligent conversation CPU and its control method.The CPU is constituted by parallel computing array using 32 completely independent analog operation channels, each channel is composed of 8 operational amplifiers in series, each operational amplifier is composed of 16 basic units, and each basic unit is composed of 4 transistors.A gate array is arranged at the front end, and the number of open gates and combinations are dynamically controlled according to the task size by the conversational logic reasoning instruction set.The application quantifies all human and social science knowledge, natural language logic and conversational reasoning rules into mathematical vectors, points, lines, circles, distances, angles, weights and switches, fully mathematizes the knowledge of liberal arts, and is directly executed by hardware.The application has the advantages of simple hardware, low power consumption and high parallel efficiency, and can realize human-like intelligent conversation and reasoning ability based on mathematical logic closed loop without big data training, deep learning stacking parameters or high-performance digital chips.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor integrated circuits, analog computing chips, artificial intelligence hardware, and natural language processing technology. Specifically, it relates to an intelligent conversational CPU based on an analog parallel array and its control method. Background Technology

[0002] Traditional central processing units (CPUs) generally adopt the von Neumann or Harvard architecture, and their core arithmetic logic unit (ALU) can only process digital signals. In practical applications, many input signals are analog signals, such as voltage signals, current signals, waveform amplitude signals, and light intensity signals output by sensors. These analog signals must be converted from analog to digital quantities by an analog-to-digital converter (ADC) before they can enter the CPU's ALU for processing. If an analog signal needs to be output, it must also be converted from digital to analog quantities by a digital-to-analog converter (DAC), forming a complete conversion path of "analog → digital → computation → digital → analog".

[0003] Existing digital CPUs have the following shortcomings when processing intelligent tasks such as natural language, conversation, and reasoning: Statistical fitting relies on large-scale datasets, resulting in high power consumption and significant latency. Unable to truly understand the logical relationships, relying solely on brute-force matching based on computing power; The hardware structure is fixed and cannot flexibly adapt to different task scales. Digital matrix multiplication and instruction pipeline architecture are essentially unrelated to the structure of biological neurons.

[0004] This invention is proposed to solve the above-mentioned problems. Summary of the Invention

[0005] I. Purpose of the Invention This invention provides a simulated parallel intelligent conversational CPU and its control method, which refines humanities knowledge into mathematical problems and executes them directly through simulated parallel array hardware, thereby achieving human-like intelligent conversational and reasoning capabilities based on mathematical logic closed loops without the need for big data. Technical solution

[0006] The present invention adopts the following technical solution: (a) Hardware Architecture The entire chip integrates 32 completely independent analog computing channels; Each channel consists of 8 operational amplifiers connected in series; Each operational amplifier consists of 16 basic analog units; Each basic analog unit consists of 4 transistors; The front end of the 32-channel system is equipped with a gate circuit array, with one gate corresponding to each channel. The gate circuits are controlled by the conversational logic reasoning instruction set within the digital control unit; An analog domain feedback network is set between the output and input terminals.

[0007] (II) Control Methods The conversational logic reasoning instruction set dynamically determines the number and combination of gates in the gate array based on the task size: Task type, number of doors opened, channel working status Lightweight tasks (simple question and answer, switch judgment): 1-2 channels of low-power single-channel computation. Medium-level tasks (multi-turn dialogue, semantic understanding): 8-16 channels of medium-parallel collaboration. Heavy-duty tasks (complex inference, voice / video, radar) require 32-way fully parallel computing. (III) Core Innovation: Mathematicalization of Humanities Knowledge The essential innovation of this invention lies in: quantifying all humanities and social science knowledge, natural language logic, and conversational reasoning rules into mathematical vectors, points, lines, circles, distances, angles, weights, and switches, thus achieving the complete mathematization of humanities knowledge. A sentence or conversation context can be broken down into points and vectors in a multidimensional mathematical space. Logical judgment → transformed into distance between points, vector angle, and closed-loop integrity; The response strategy is transformed into a mathematical weight comparison and a channel gate opening / closing decision. Output → Reverse conversion of mathematical calculation results into natural language.

[0008] Chatting is no longer about guessing words or probability matching, but a rigorous closed loop of mathematical operations. Beneficial effects

[0009] Compared with the prior art, the present invention has the following beneficial effects: The hardware is extremely simple and can be mass-produced: there are approximately 17,600 transistors in total, far fewer than in a digital CPU, and it can be manufactured using common and mature processes without the need for EUV lithography machines. High parallel efficiency: 32 independent channels can operate simultaneously, with adaptive task size opening and no instruction pipeline bottleneck; Extremely low power consumption: Analog parallel computing is inherently low power consumption, with no high-frequency clock and no data transfer; True brain-like intelligence: 32 channels correspond to neurons, feedback networks correspond to memory, and gate circuits + instruction sets correspond to decision-making; The core technology is not replicable: the hardware can be made public, but the transformation rules of "liberal arts → mathematics" and the "door-knocking software logic" are unique to the patent holder and cannot be imitated by others; Universally applicable to all scenarios: It can be used in intelligent voice, chatbots, industrial detection, radar signal processing, waveform imaging, health monitoring, etc. Attached Figure Description

[0010] Figure 1 This is a block diagram of the overall structure of the parallel intelligent session CPU of this invention. Figure 2 This is a topology diagram of the operational amplifier array of the present invention. Figure 3 This is an architectural diagram of the logic control center and gate circuit array of the present invention. Figure 4 This is the schematic diagram of the 3.3V / 5V dual-voltage compatible circuit of the present invention. Figure 5 This is a schematic diagram of the simulated domain feedback network connection of the present invention.

Claims

1. Claim 1: A simulated parallel intelligent session CPU, characterized in that, include: A parallel computing array consisting of 32 completely independent analog computing channels; Each analog computing channel consists of 8 operational amplifiers connected in series. Each operational amplifier consists of 16 basic analog units, and each basic analog unit consists of 4 transistors. A gate array is used to control the selection and shutdown of each operation channel; A conversational logic reasoning instruction set, running on the digital control unit, is used to dynamically determine the number and combination of gates in the gate array based on the task size. An analog domain feedback network, connected between the output and input, is used to implement closed-loop logic judgment and short-term memory.

2. Claim 2: A simulated parallel intelligent session CPU according to claim 1, characterized in that: The 32 computing channels have no cross-connections, no data forwarding, and no timing dependencies. Each channel independently completes all analog calculations from input to output.

3. Claim 3: A simulated parallel intelligent session CPU according to claim 1, characterized in that: The gate array only performs channel switching control and does not participate in any calculations; the number and combination of open gates are dynamically determined by the conversational logic reasoning instruction set according to the task scale. Light task: Knock on 1-2 doors; Medium task: Knock on 8-16 doors; Heavy mission: Knock on all 32 doors.

4. Claim 4: A simulated parallel intelligent session CPU according to claim 1, characterized in that: The core logic of the conversational logic reasoning instruction set is to quantify humanities and social science knowledge, natural language logic, and conversational reasoning rules into mathematical vectors, points, lines, circles, distances, angles, weights, and switches, thereby realizing the complete mathematicalization of humanities knowledge and enabling direct execution by hardware.

5. Claim 5: A simulated parallel intelligent session CPU according to claim 1, characterized in that: The analog domain feedback network is composed of a resistor / capacitor array, and the feedback coefficient can be adjusted to realize the closed-loop influence of the output on the input, thus forming a hardware-level short-term memory and learning capability.

Images