Wafer defect detection and chip verification integrated closed-loop management method

Abstract

The application relates to the technical field of quality control, and discloses a wafer defect detection and chip verification integrated closed-loop control method, which comprises the following steps: acquiring optical detection data and electron beam detection data of a wafer; performing multi-scale fusion processing on the two kinds of data to generate a wafer defect comprehensive characterization atlas; constructing a defect-chip correlation matrix based on the atlas and chip layout information; calculating the cumulative defect influence value of each chip functional area based on the matrix and the defect characteristics of each defect to generate a chip verification priority list; performing hierarchical verification according to the priority list and generating a defect calibration signal based on the verification result; and feeding back the defect calibration signal to the multi-scale fusion processing link to dynamically optimize and adjust the fusion parameters, so that a closed-loop control is formed. Through multi-modal data fusion and closed-loop feedback optimization, the wafer defect detection and chip verification linkage are realized, and the accuracy of defect detection and the pertinence of chip verification are improved.

Description

Technical Field

[0001] This invention relates to the field of quality control technology, and in particular to an integrated closed-loop control method for wafer defect detection and chip verification. Background Technology

[0002] In semiconductor manufacturing, wafer defect detection is a crucial step in ensuring chip yield. Currently, wafer defect detection primarily employs single-modal methods such as optical inspection or electron beam inspection. Optical inspection equipment generates image data by collecting reflected and scattered light signals from the wafer surface, enabling rapid acquisition of macroscopic defect distribution information, such as scratches and large particle contamination. However, its ability to detect microscopic defects such as missing patterns, bridging, and tiny particles is limited. Electron beam inspection equipment scans the wafer surface with a focused electron beam and collects secondary electron signals to generate image data, accurately acquiring detailed information about microscopic defects. However, its detection speed is slower and it is difficult to cover the entire wafer surface. The detection data from these two modalities are independent, lacking effective data fusion methods, resulting in incomplete information and limited detection accuracy in single-modal inspection results.

[0003] For a long time, wafer defect detection results and chip verification have been independent processes. Defect information detected on the wafer surface is only used to determine wafer pass / fail status and is not effectively utilized to guide the prioritization and execution strategies of subsequent chip verification. Chip verification typically employs random sampling or full coverage to perform indiscriminate verification of all functional areas. This approach leads to a waste of resources as a large amount of verification resources are used for functional areas unaffected or only slightly affected by defects. Furthermore, functional areas severely affected by defects may not be selected for timely verification, posing a risk of missed detections. In addition, the defect detection parameters in existing technologies are fixed once set and cannot be adjusted and optimized based on subsequent chip verification results. This prevents continuous improvement in detection accuracy, keeping the false positive and false negative rates at a similar level, which is insufficient to meet the ever-increasing demands for detection accuracy in the semiconductor manufacturing industry. Therefore, improving the collaborative management efficiency of wafer defect detection and chip verification has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides an integrated closed-loop management method for wafer defect detection and chip verification to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides an integrated closed-loop management method for wafer defect detection and chip verification, comprising: S1, acquire optical inspection data and electron beam inspection data of the wafer; S2, perform multi-scale fusion processing on the optical detection data and the electron beam detection data to generate a comprehensive characterization map of wafer defects; S3. Based on the comprehensive characterization map of wafer defects and chip layout information, construct a defect-chip correlation matrix that reflects the spatial correlation between each defect on the wafer surface and each functional area of ​​the chip. S4. Based on the defect-chip correlation matrix and the defect characteristics of each defect, calculate the cumulative defect impact value of each chip functional area, and generate a chip verification priority list based on the cumulative defect impact value. S5, perform hierarchical verification of the chip functional areas according to the chip verification priority list, and generate a defect calibration signal based on the hierarchical verification results; S6, the defect calibration signal is fed back to the multi-scale fusion processing stage, and the fusion parameters of the multi-scale fusion processing are dynamically optimized and adjusted to form a closed-loop control.

[0006] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention constructs a defect-chip correlation matrix to establish a quantitative mapping relationship between dispersed defects on the wafer surface and various functional areas of the chip, thereby achieving a quantitative assessment of the impact of wafer defects on chip functional areas. Based on the correlation matrix and the defect propagation analysis algorithm, the cumulative defect impact value of each chip functional area is calculated, which can accurately identify the most severely affected functional areas and generate a chip verification priority list. This allows chip verification to focus on high-risk areas, avoiding blind verification and missed verification, significantly improving the targeting and efficiency of chip verification, and shortening the chip verification cycle.

[0007] 2. This invention introduces a closed-loop feedback mechanism from chip verification to multi-scale fusion processing. It uses newly identified defect information and false alarm defect information confirmed in the hierarchical verification results as calibration signals to incrementally and dynamically optimize the fusion weights in the high-frequency detail layer weighted fusion strategy. This mechanism enables wafer defect detection to continuously learn from chip verification results, continuously optimize the fusion parameters of multi-modal detection data, achieve iterative improvement in defect detection accuracy, reduce the defect false alarm rate and the defect missed rate, and form a virtuous cycle in which wafer defect detection and chip verification promote each other and continuously optimize. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating an integrated closed-loop control method for wafer defect detection and chip verification provided in an embodiment of the present invention. The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0009] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0010] This application provides an integrated closed-loop management method for wafer defect detection and chip verification. The executing entity of this integrated closed-loop management method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the integrated closed-loop management method for wafer defect detection and chip verification can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0011] Reference Figure 1 The diagram shown is a flowchart illustrating an integrated closed-loop management method for wafer defect detection and chip verification according to an embodiment of the present invention. In this embodiment, the integrated closed-loop management method for wafer defect detection and chip verification includes: S1, acquire optical inspection data and electron beam inspection data of the wafer; In this embodiment of the invention, acquiring the optical inspection data and electron beam inspection data of the wafer includes: Optical inspection data is obtained by scanning the surface of the wafer using optical inspection equipment; Electron beam inspection data is obtained by scanning the surface of the wafer using an electron beam inspection device.

[0012] It should be noted that the optical inspection device and the electron beam inspection device are two inspection devices based on different principles. The optical inspection device generates image data by collecting reflected and scattered light signals from the wafer surface, which is used to reflect the macroscopic defect distribution information of the wafer surface, such as larger defects such as scratches and large particle contamination. Electron beam inspection equipment scans the wafer surface with a focused electron beam and collects secondary electron signals to generate image data, which reflects the microscopic defect details of the wafer surface, such as pattern missing, bridging, and tiny particles. By acquiring detection data from two modes simultaneously, macroscopic and microscopic information can be complemented in subsequent multi-scale fusion processing, improving the comprehensiveness and accuracy of defect detection.

[0013] Furthermore, the optical detection data is optical scanning image data, and the electron beam detection data is electron beam scanning image data. During the acquisition process, the optical detection device and the electron beam detection device scan the same area of ​​the same wafer to ensure that the detection data of the two modes have a corresponding relationship in spatial position, thereby providing a spatially aligned data basis for subsequent multi-scale fusion processing.

[0014] S2, perform multi-scale fusion processing on the optical detection data and the electron beam detection data to generate a comprehensive characterization map of wafer defects; In this embodiment of the invention, the step of performing multi-scale fusion processing on the optical detection data and the electron beam detection data to generate a comprehensive characterization map of wafer defects includes: The optical detection data and the electron beam detection data are respectively subjected to Laplacian pyramid decomposition to obtain their respective high-frequency detail layer sequences and low-frequency base layers; For each high-frequency detail layer at each scale, a weighted fusion strategy based on fusion weights is used to fuse them, resulting in a fused high-frequency detail layer sequence. The low-frequency base layer is fused using an averaging strategy to obtain a fused low-frequency base layer. The fused high-frequency detail layer sequence and the fused low-frequency base layer are reconstructed using a Laplace pyramid to generate the comprehensive characterization map of wafer defects.

[0015] It should be noted that Laplacian pyramid decomposition is a multi-scale image decomposition method used to decompose an image into sub-images at multiple scales from high frequency to low frequency. The high-frequency detail layer reflects the image's edge, texture, and other detailed information, while the low-frequency base layer reflects the image's overall contour and gray-level distribution information. Setting the number of decomposition layers to 3 layers can preserve enough scale detail information while avoiding the problem of excessive computation due to too many layers.

[0016] Furthermore, a weighted fusion strategy based on fusion weights is applied to the high-frequency detail layers at each scale. Specifically, at the same pixel location, the pixel value of the high-frequency detail layer of the optical detection data at that scale is multiplied by the fusion weight of the optical detection data, and then the pixel value of the high-frequency detail layer of the electron beam detection data at that scale is multiplied by the fusion weight of the electron beam detection data to obtain the fused pixel value at that location. The sum of the fusion weights of the optical detection data and the electron beam detection data is 1. Initially, both the fusion weights of the optical detection data and the electron beam detection data are set to 0.5, indicating that the two modes contribute equally to the high-frequency detail fusion. The corresponding mathematical expression of the algorithm is as follows: ; In the formula, Indicates the first The high-frequency detail layer after layer fusion at the pixel location pixel values, Indicates the optical detection data number High-frequency detail layer at pixel location pixel values, Indicates the electron beam detection data. High-frequency detail layer at pixel location pixel values, Indicates the fusion weights of optical detection data. The weights represent the fusion weights of the electron beam detection data, and ; The initial values ​​for the fusion weights of optical detection data and electron beam detection data are both 0.5.

[0017] Furthermore, an averaging strategy is adopted for the low-frequency base layer fusion. Specifically, at the same pixel position, the low-frequency base layer pixel value of the optical detection data and the low-frequency base layer pixel value of the electron beam detection data are added together and then divided by 2 to obtain the fused pixel value at that position. The averaging strategy can retain the overall defect distribution information shared by the two modes and avoid distortion of the fusion result due to noise interference from a single mode.

[0018] Furthermore, the Laplacian pyramid reconstruction process is as follows: starting from the top layer, the high-frequency detail layer of the current layer is added to the low-frequency base layer of the previous layer after upsampling to obtain the fused image of the current layer, until the original image size is reconstructed, and finally the comprehensive characterization map of the wafer defects is obtained; the upsampling operation involved in the reconstruction process is: enlarging the image size to the size of the previous layer, and interpolating and filling the newly added pixels.

[0019] S3. Based on the comprehensive characterization map of wafer defects and chip layout information, construct a defect-chip correlation matrix that reflects the spatial correlation between each defect on the wafer surface and each functional area of ​​the chip. In this embodiment of the invention, the step of constructing a defect-chip correlation matrix reflecting the spatial correlation between various defects on the wafer surface and various functional areas of the chip based on the comprehensive characterization map of wafer defects and chip layout information includes: The defect feature vector of each defect is extracted from the comprehensive characterization map of the wafer defects. The defect feature vector includes the defect location coordinates, defect area, defect grayscale mean, defect shape factor and defect type. Obtain chip layout information, which includes the position coordinates and area range of each chip functional region on the wafer; The defect feature vector of each defect is spatially associated with the chip layout information. For each defect, the chip functional area where the defect location coordinates are located is determined, and the association relationship between each defect and the corresponding chip functional area is determined to construct a defect-chip association matrix.

[0020] It should be noted that the defect feature vector of each defect is extracted from the comprehensive characterization map of wafer defects. Specifically, the connected domains of each defect are identified from the comprehensive characterization map of wafer defects by an image segmentation algorithm. The corresponding feature parameters are extracted for the connected domains of each defect. The defect position coordinates are the center pixel coordinates of the defect connected domains, and the unit is micrometers. The defect area is the total number of pixels contained in the defect connected region multiplied by the actual area of ​​a single pixel, in square micrometers. The defect grayscale mean is the average grayscale value of all pixels within the defect's connected domain, used to characterize the brightness of the defect.

[0021] Furthermore, the defect feature vector also includes a defect shape factor, which is calculated by dividing the square of the perimeter of the defect connected domain by four times the defect area. It is used to describe the complexity of the defect shape. The closer the value of the defect shape factor is to 1, the closer the defect shape is to a circle. The larger the value, the more irregular the defect shape is.

[0022] Furthermore, the method for obtaining chip layout information is as follows: the position coordinates and area of ​​each chip functional region on the wafer are parsed from the chip layout design file. The position coordinates of each chip functional region are the center coordinates of that functional region, and the area is defined by the polygonal area enclosed by the boundary vertex coordinate sequence of that functional region. Chip functional areas include, but are not limited to, storage areas, logic operation areas, input / output areas, and analog circuit areas.

[0023] Furthermore, the defect type is determined as follows: a rule-based classification method is used to categorize the defects based on the defect shape factor and the mean gray value extracted from the defect feature vector. If the defect shape factor is greater than the first shape threshold and the defect grayscale mean is less than the first grayscale threshold, it is determined to be a scratch defect; the first shape threshold is 3.0 and the first grayscale threshold is 80. Scratch defects usually have the characteristics of irregular shape and low grayscale value. If the defect shape factor is less than the second shape threshold and the defect grayscale mean is greater than the second grayscale threshold, it is determined to be a particle defect. The second shape threshold is 1.5 and the second grayscale threshold is 180. Particle defects usually have the characteristics of being close to a circle in shape and having a high grayscale value. If the average gray value of the defect is less than the third gray value threshold and the defect area is greater than the area threshold, it is determined to be an embedded defect. The third gray value threshold is 60, and the area threshold is 100 square micrometers. Embedded defects are usually dark-colored defects with a large area. If it does not fall into any of the above three categories, it is determined to be a graphic missing defect; The mean grayscale value is an integer value between 0 and 255, and the defect shape factor is a dimensionless coefficient. Each threshold is obtained by statistically analyzing sample data of labeled defect types in historical wafer inspections, and the quantile of the characteristic distribution of each type of defect is taken as the corresponding threshold.

[0024] In this embodiment of the invention, the specific method for constructing the defect-chip correlation matrix is ​​as follows: Create a matrix where rows are determined by the total number of defects detected in the wafer defect comprehensive characterization map, and columns are determined by the total number of functional regions on the chip layout; For each defect, iterate through each chip functional area and determine whether the location coordinates of the current defect fall within the range of the current chip functional area. If yes, assign the value 1 to the element corresponding to the i-th defect and the i-th functional area in the defect-chip association matrix; otherwise, assign the value 0.

[0025] It should be noted that the mathematical expression for the defect-chip correlation matrix is: ; ; in, Indicates the first The first defect and the first The values ​​representing the relationships between the functional regions of each chip. Indicates the first The coordinates of the defect location. Indicates the first The range of each chip's functional area. This represents the total number of defects detected in the comprehensive defect characterization map of the wafer. This represents the total number of functional areas on the chip layout.

[0026] Furthermore, through the defect-chip correlation matrix, a direct quantitative mapping relationship can be established between the defects scattered on the wafer surface and the functional areas of the chip. This allows subsequent steps to determine which defects affect each functional area of ​​the chip based on the correlation matrix, thereby providing a data foundation for prioritizing chip verification based on defect impact.

[0027] S4. Based on the defect-chip correlation matrix and the defect characteristics of each defect, calculate the cumulative defect impact value of each chip functional area, and generate a chip verification priority list based on the cumulative defect impact value. In this embodiment of the invention, calculating the cumulative defect impact value of each chip functional region based on the defect-chip correlation matrix and the defect characteristics of each defect includes: Traverse each chip functional region in the defect-chip association matrix. For the current chip functional region, obtain all associated defects in the defect-chip association matrix corresponding to the current functional region, and obtain the defect area and defect type weight of each associated defect. Based on the correlation relationships in the defect-chip correlation matrix, the defect area of ​​each associated defect, the defect type weight, and the distance from the defect center to the center of the chip functional area, the cumulative defect impact value of the current chip functional area is calculated.

[0028] It should be noted that the cumulative defect impact value is used to quantify the overall impact of wafer surface defects on each chip functional area. The larger the cumulative defect impact value, the more severe the negative impact of defects on the chip functional area, and the more likely it is to be verified during the chip verification process. When obtaining the defect area and defect type weight of each associated defect, the defect area is extracted from the defect feature vector; the defect type weight is set according to the type of defect, and different types of defects have different degrees of influence on the chip functional area; the weight of scratch defects is set to 0.8, the weight of particle defects is set to 0.5, the weight of embedding defects is set to 1.0, and the weight of pattern missing defects is set to 0.9.

[0029] Furthermore, when calculating the cumulative defect impact value of each chip functional region, a defect propagation analysis algorithm is used. For the i-th chip functional region, its cumulative defect impact value is equal to the sum of the weighted impact values ​​of all defects that are related to that functional region. The weighted impact value of each defect is jointly determined by the defect area, defect type weight, and distance attenuation factor from the defect center to the center of the chip functional region. The specific algorithm expression is as follows: ; In the formula, Indicates the first The cumulative defect impact value of each chip functional area This represents the total number of defects detected in the comprehensive defect characterization map of the wafer. The defect-chip correlation matrix represents the first... The first defect and the first The association values ​​for the functional areas of each chip are set to 1, indicating that an association exists, and 0, indicating that no association exists. Indicates the first The defect area of ​​each defect. Indicates the first Defect type weights for each defect. Indicates the first The defect location coordinates of the first defect and the second defect The Euclidean distance between the position coordinates of each chip functional area. This represents a standardized area reference value, set at 1 square micrometer. This represents the distance attenuation coefficient, used to control the rate at which the impact of a defect decreases with increasing distance. Its value range is set from 0.01 to 0.1.

[0030] Furthermore, when the distance attenuation coefficient is large, the impact of the defect decreases rapidly with increasing distance, and only has a significant impact on functional areas close to the defect; when the distance attenuation coefficient is small, the impact of the defect decreases slowly with increasing distance, and still has a certain impact on functional areas far from the defect. The default value of the distance attenuation coefficient is 0.05.

[0031] Furthermore, by calculating the cumulative defect impact value of each chip functional area, the comprehensive impact of multiple defects dispersed on the wafer surface on the chip functional area is quantified into a single numerical index, enabling horizontal comparison of the degree of impact between different chip functional areas and providing a quantitative basis for the subsequent generation of a chip verification priority list.

[0032] In this embodiment of the invention, generating a chip verification priority list based on the cumulative defect impact value includes: Each chip functional area is sorted from largest to smallest according to the cumulative defect impact value to generate a chip verification priority list. The chip functional area with the larger the cumulative defect impact value in the chip verification priority list has a higher verification priority.

[0033] It should be noted that the chip verification priority list is used to guide the execution order of subsequent graded verifications. The sorting is in descending order, comparing the cumulative defect impact values ​​of all chip functional areas and arranging them from the maximum to the minimum. The chip functional area with the largest cumulative defect impact value is placed at the top of the list, indicating that this functional area is most severely affected by the defects and should be verified first during the chip verification process. The chip functional area with the smallest cumulative defect impact value is placed at the bottom of the list, indicating that this functional area is least affected by the defects and can be processed after the verification of high-priority areas is completed.

[0034] Furthermore, when two or more chip functional regions have the same cumulative defect impact value, they are sorted a second time according to the number of defects associated with these functional regions. Functional regions with more defects have higher priority to ensure that functional regions affected by more defects can be verified first.

[0035] Furthermore, the chip verification priority list is stored in the form of a data structure. Each element in the list contains the identification information of the chip's functional area and the corresponding cumulative defect impact value, which can be directly called and executed by subsequent graded verification steps.

[0036] S5, perform hierarchical verification of the chip functional areas according to the chip verification priority list, and generate a defect calibration signal based on the hierarchical verification results; In this embodiment of the invention, the step of performing graded verification of the chip functional areas according to the chip verification priority list includes: According to the chip verification priority list, each chip functional area is verified sequentially from high priority to low priority to obtain the actual defect location and actual defect type of each chip functional area.

[0037] It should be noted that the execution order of the graded verification strictly follows the chip verification priority list, that is, the chip functional areas with the largest cumulative defect impact value are verified first, ensuring that the most severely affected functional areas are detected and confirmed first. The graded verification adopts a batch execution method. In each batch, only a few chip functional areas with the highest current priority are verified. After the verification of the batch is completed, the defect calibration signal is updated according to the verification results, and then the next batch of verification begins. The graded verification method can reasonably allocate verification resources, avoid the waste of resources caused by indiscriminate verification of all functional areas, and at the same time, it can gradually optimize the verification strategy of subsequent batches during the verification process.

[0038] Furthermore, the actual defect location is the specific coordinate location of the defect within the functional area of ​​the chip; the actual defect types include scratch defects, particle defects, embedding defects, pattern missing defects, and bridging defects. After obtaining the actual defect location and actual defect type, they are compared with the defect location and defect type of the corresponding area recorded in the wafer defect comprehensive characterization map. If a defect actually exists but is not recorded in the map, the defect is marked as newly added defect information; if a defect is recorded in the map but not actually confirmed, the defect is marked as false alarm defect information, providing a data basis for the subsequent generation of defect calibration signals.

[0039] In this embodiment of the invention, generating a defect calibration signal based on the graded verification results includes: The actual defect location and type are compared with the corresponding defect location and type recorded in the wafer defect comprehensive characterization map; If a defect actually exists but is not recorded in the wafer defect comprehensive characterization map, then the current defect will be marked as newly added defect information; If a defect is recorded in the comprehensive characterization map of the wafer defect but is not actually confirmed, the current defect will be marked as a false alarm defect. The newly added defect information and the false alarm defect information are combined into a defect calibration signal.

[0040] It should be noted that the defect calibration signal is used to record the difference information between the comprehensive characterization map of the wafer defects found during the graded verification process and the actual detection results, as the basis for subsequent optimization and adjustment of the fusion parameters in the multi-scale fusion processing stage; the defect calibration signal contains two types of information: newly added defect information and false alarm defect information.

[0041] Furthermore, when comparing the actual defect location and the actual defect type with the corresponding defect location and defect type recorded in the wafer defect comprehensive characterization map item by item, if no defect is recorded in the wafer defect comprehensive characterization map at a certain actual defect location, the defect is determined to be a missed detection result of the wafer defect comprehensive characterization map, the defect is marked as newly added defect information, and its defect location and defect type are recorded; if no defect is found in actual verification at a certain defect location recorded in the wafer defect comprehensive characterization map, the defect is determined to be a false detection result of the wafer defect comprehensive characterization map, the defect is marked as false alarm defect information, and its defect location and defect type are recorded.

[0042] Furthermore, both the newly added defect information and the false alarm defect information are stored in a correspondence between pixel position coordinates and defect types. Each newly added defect or false alarm defect corresponds to a pixel position coordinate and a defect type identifier at that position. The defect calibration signal packages these two types of information into structured data for subsequent steps to read and use.

[0043] S6, the defect calibration signal is fed back to the multi-scale fusion processing stage, and the fusion parameters of the multi-scale fusion processing are dynamically optimized and adjusted to form a closed-loop control.

[0044] In this embodiment of the invention, feeding back the defect calibration signal to the multi-scale fusion processing stage and dynamically optimizing and adjusting the fusion parameters of the multi-scale fusion processing to form a closed-loop control includes: Acquire defect calibration signals to determine the pixel positions corresponding to newly added defect information and falsely reported defect information; Based on the newly added defect information and false alarm defect information at each pixel location, the fusion weight of the optical detection data in the high-frequency detail layer weighted fusion strategy is incrementally adjusted to obtain the adjusted fusion weight. The adjusted fusion weights are applied to the high-frequency detail layer fusion processing of the next wafer multimodal inspection data to form a closed-loop control.

[0045] It should be noted that both newly added defect information and false alarm defect information in the defect calibration signal are stored using the correspondence between pixel position coordinates and defect types. The pixel position corresponding to newly added defect information indicates that the wafer defect comprehensive characterization map has missed detections at that location, and the fusion weight of the corresponding modal data at that location needs to be increased in subsequent fusion processing so that the defect information at that location can be more completely preserved in the fusion result. The pixel position corresponding to false alarm defect information indicates that the wafer defect comprehensive characterization map has false detections, and the fusion weight of the corresponding modal data at that location needs to be decreased in subsequent fusion processing to reduce false alarms.

[0046] Furthermore, when incrementally adjusting the fusion weights, an incremental update algorithm for fusion parameters is employed. For each pixel location, based on whether there are newly added defects or false alarms at that location, the net adjustment amount of the fusion weights of the optical inspection data is calculated, and the fusion weights at that pixel location are updated. The incremental update formula for the fusion weights of the optical inspection data is as follows: ; In the formula, This indicates the updated optical detection data at the pixel position. The fusion weight, This indicates the position of the optical detection data at the pixel location before the update. The fusion weight, Indicates the learning rate. Indicates pixel position The new defect indication signal at this pixel location is set to 1 if a new defect exists at that pixel location, and 0 otherwise. Indicates pixel position The false alarm defect indication signal at the pixel location is set to 1 if a false alarm defect exists at that pixel location, and 0 otherwise. The learning rate controls the step size of each adjustment. The default value is 0.05, and the range is 0.01 to 0.1.

[0047] Furthermore, the fusion weight of the electron beam detection data at the pixel position is automatically determined based on the fusion weight of the optical detection data, ensuring that the sum of the fusion weights of the two modes is 1. The corresponding update formula is as follows: ; in, This indicates the updated electron beam detection data at the pixel position. The fusion weight, This indicates the updated optical detection data at the pixel position. The fusion weight.

[0048] Furthermore, the learning rate is used to control the magnitude of each feedback adjustment. The larger the learning rate, the greater the impact of a single adjustment on the fusion weights and the faster the convergence speed, but it may lead to overshoot. The smaller the learning rate, the smaller the impact of a single adjustment on the fusion weights and the smoother the convergence process, but the slower the convergence speed.

[0049] Furthermore, the adjusted fusion weights are applied to the multi-scale fusion processing of the next wafer multimodal inspection data. Specifically, when performing Laplace pyramid decomposition and reconstruction on the optical inspection data and electron beam inspection data of the next batch of wafers, the updated fusion weights are used to replace the initial fusion weights in the high-frequency detail layer fusion strategy. This allows the fusion results of the high-frequency detail layer to be adaptively adjusted according to historical verification results, thereby continuously optimizing the accuracy and comprehensiveness of defect detection and realizing integrated closed-loop management of wafer defect detection and chip verification.

[0050] In the several embodiments provided by this invention, it should be understood that the disclosed method can be implemented in other ways.

[0051] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0052] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence is the theory, method, and technology that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A closed-loop control method integrating wafer defect detection and chip verification, characterized in that, The method includes: S1, acquire optical inspection data and electron beam inspection data of the wafer; S2, perform multi-scale fusion processing on the optical detection data and the electron beam detection data to generate a comprehensive characterization map of wafer defects; S3. Based on the comprehensive characterization map of wafer defects and chip layout information, construct a defect-chip correlation matrix that reflects the spatial correlation between each defect on the wafer surface and each functional area of ​​the chip. S4. Based on the defect-chip correlation matrix and the defect characteristics of each defect, calculate the cumulative defect impact value of each chip functional area, and generate a chip verification priority list based on the cumulative defect impact value. S5, perform hierarchical verification of the chip functional areas according to the chip verification priority list, and generate a defect calibration signal based on the hierarchical verification results; S6, the defect calibration signal is fed back to the multi-scale fusion processing stage, and the fusion parameters of the multi-scale fusion processing are dynamically optimized and adjusted to form a closed-loop control.

2. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, Acquire optical inspection data and electron beam inspection data of the wafer, including: Optical inspection data is obtained by scanning the surface of the wafer using optical inspection equipment; Electron beam inspection data is obtained by scanning the surface of the wafer using an electron beam inspection device.

3. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, The optical detection data and the electron beam detection data are subjected to multi-scale fusion processing to generate a comprehensive characterization map of wafer defects, including: The optical detection data and the electron beam detection data are respectively subjected to Laplacian pyramid decomposition to obtain their respective high-frequency detail layer sequences and low-frequency base layers; For each high-frequency detail layer at each scale, a weighted fusion strategy based on fusion weights is used to fuse them, resulting in a fused high-frequency detail layer sequence. The low-frequency base layer is fused using an averaging strategy to obtain a fused low-frequency base layer. The fused high-frequency detail layer sequence and the fused low-frequency base layer are reconstructed using a Laplace pyramid to generate the comprehensive characterization map of wafer defects.

4. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, Based on the comprehensive characterization map of wafer defects and chip layout information, a defect-chip correlation matrix is ​​constructed to reflect the spatial correlation between various defects on the wafer surface and various functional areas of the chip, including: The defect feature vector of each defect is extracted from the comprehensive characterization map of the wafer defects. The defect feature vector includes the defect location coordinates, defect area, defect grayscale mean, defect shape factor and defect type. Obtain chip layout information, which includes the position coordinates and area range of each chip functional region on the wafer; The defect feature vector of each defect is spatially associated with the chip layout information. For each defect, the chip functional area where the defect location coordinates are located is determined, and the association relationship between each defect and the corresponding chip functional area is determined to construct a defect-chip association matrix.

5. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 4, characterized in that, The specific method for constructing the defect-chip correlation matrix is ​​as follows: Create a matrix where rows are determined by the total number of defects detected in the wafer defect comprehensive characterization map, and columns are determined by the total number of functional regions on the chip layout; For each defect, iterate through each chip functional area and determine whether the location coordinates of the current defect fall within the range of the current chip functional area. If yes, assign the value 1 to the element corresponding to the i-th defect and the i-th functional area in the defect-chip association matrix; otherwise, assign the value 0.

6. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, Based on the defect-chip correlation matrix and the defect characteristics of each defect, the cumulative defect impact value for each chip functional region is calculated, including: Traverse each chip functional region in the defect-chip association matrix. For the current chip functional region, obtain all associated defects in the defect-chip association matrix corresponding to the current functional region, and obtain the defect area and defect type weight of each associated defect. Based on the correlation relationships in the defect-chip correlation matrix, the defect area of ​​each associated defect, the defect type weight, and the distance from the defect center to the center of the chip functional area, the cumulative defect impact value of the current chip functional area is calculated.

7. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, A chip verification priority list is generated based on the cumulative defect impact value, including: Each chip functional area is sorted from largest to smallest according to the cumulative defect impact value to generate a chip verification priority list. The chip functional area with the larger the cumulative defect impact value in the chip verification priority list has a higher verification priority.

8. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, The chip functional areas are graded and verified according to the chip verification priority list, including: According to the chip verification priority list, each chip functional area is verified sequentially from high priority to low priority to obtain the actual defect location and actual defect type of each chip functional area.

9. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, Defect calibration signals are generated based on the graded verification results, including: The actual defect location and type are compared with the corresponding defect location and type recorded in the wafer defect comprehensive characterization map; If a defect actually exists but is not recorded in the wafer defect comprehensive characterization map, the current defect will be marked as newly added defect information. If a defect is recorded in the comprehensive characterization map of the wafer defect but has not actually been confirmed, the current defect will be marked as a false alarm defect. The newly added defect information and the false alarm defect information are combined into a defect calibration signal.

10. The integrated closed-loop control method for wafer defect detection and chip verification as described in claim 1, characterized in that, The defect calibration signal is fed back to the multi-scale fusion processing stage, and the fusion parameters of the multi-scale fusion processing are dynamically optimized and adjusted to form a closed-loop control, including: Acquire defect calibration signals to determine the pixel positions corresponding to newly added defect information and falsely reported defect information; Based on the newly added defect information and false alarm defect information at each pixel location, the fusion weight of the optical detection data in the high-frequency detail layer weighted fusion strategy is incrementally adjusted to obtain the adjusted fusion weight. The adjusted fusion weights are applied to the high-frequency detail layer fusion processing of the next wafer multimodal inspection data to form a closed-loop control.

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