PD radar multi-pulse parallel filtering method based on GPU wide bit memory access mechanism

Abstract

The application discloses a PD radar multi-pulse parallel filtering method based on a GPU wide-bit memory access mechanism and belongs to the technical field of radar signal processing.The method is characterized in that a special shared memory area is configured for each thread block in GPU kernel function calculation; the high-bandwidth, low-delay characteristics of the shared memory and the shared mechanism among multiple threads are utilized to preload distance-pulse data to be filtered and Doppler filter group coefficients into the shared memory, convert frequent global memory reading into on-chip shared memory access at high speed, and significantly improve the data throughput rate; according to the dimension structure of the distance-pulse matrix, the thread grid architecture of the GPU is configured, and parallel filtering calculation of multi-pulse radar echo data is realized; the parallel acceleration calculation potential of the GPU hardware architecture is fully utilized, the radar signal processing time is significantly shortened, and the engineering demand of the radar system for large-throughput, high-real-time signal processing is met.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism. Background Technology

[0002] Pulse Doppler (PD) radar is a coherent radar system that detects targets based on the Doppler effect. It detects the target's range and velocity by transmitting a highly stable coherent pulse train and utilizing the Doppler frequency shift of the target's echo. In existing PD radar signal processing workflows, Moving Target Detection (MTD) is a common target detection method. However, the aforementioned signal processing algorithms have the following technical problems:

[0003] In existing PD radar MTD processing, the Doppler filter bank is typically designed based on the Discrete Fourier Transform (DFT) principle and is mostly implemented using the Fast Fourier Transform (FFT) algorithm to reduce computational load. However, FFT-based Doppler filter banks not only require channels to be uniformly spaced in the frequency domain, but also have high sidelobe levels, causing stationary clutter energy to leak into adjacent low-speed Doppler channels through the sidelobes. Although windowing can improve the main-to-sidelobe ratio, this operation introduces the adverse consequence of main lobe broadening, affecting the signal processing algorithm's detection performance for low-speed, weak targets. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problems of the prior art and provide a PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism.

[0005] The technical problem addressed by this invention is solved as follows:

[0006] A parallel filtering method for multi-pulse PD radar based on GPU wide-bit memory access mechanism includes the following steps:

[0007] Step 1: Obtain the range-pulse matrix after pulse compression processing of the radar echo signal; obtain the coefficient matrix of the Doppler filter bank; initialize the filter output matrix;

[0008] Step 2: Allocate physical storage space in the global video memory of the GPU device for the distance-pulse matrix, the Doppler filter bank coefficient matrix, and the filter output matrix, respectively, and denot them as the first input video memory area, the second input video memory area, and the output video memory area;

[0009] Step 3: Configure the thread grid for GPU parallel computing based on the dimension of the distance-pulse matrix, and configure two shared memory areas for each thread block in the thread grid;

[0010] Step 4: Perform parallel computation of GPU kernel functions based on the configured GPU thread grid. Utilize the shared memory area of ​​the GPU in the multi-threaded block sharing mechanism and wide-bit memory access mechanism to realize the multiplication operation between the second input memory area and the first input memory area. The operation result is the filter output matrix stored in the output memory area, thus completing the parallel filtering of the multi-pulse radar.

[0011] Furthermore, in step 1, the distance-pulse matrix The dimension is , and These represent the number of radar echo pulses and the number of range gates, respectively; the Doppler filter bank coefficient matrix. The dimension is , The order of the coefficient matrix of the Doppler filter bank; Pulse count of radar echo signal Numerical values ​​are equal; filter output matrix The dimension is .

[0012] Furthermore, in step 2, the first input video memory area Used to store distance-pulse matrix The size is the distance-pulse matrix. Consistent; Second input video memory area Used to store the coefficient matrix of the Doppler filter bank. The size of the Doppler filter bank coefficient matrix Consistent; Output memory area Used to store the filter output matrix The size is the same as the filter output matrix. Consistent.

[0013] Furthermore, in step 2, a cache-first technique is used to allocate physical storage space for the first input video memory area, the second input video memory area, and the output video memory area.

[0014] Furthermore, in step 3, the global number of threads is set to [value] in the distance unit dimension. The thread block size is set to The number of thread blocks is In the impulse dimension, the global thread count is set to... The thread block size is set to The number of thread blocks is M is a positive integer power of 2; allocate the first shared memory area for each thread block. Second shared memory area Their sizes are all .

[0015] Furthermore, the specific process of step 4 is as follows:

[0016] Step 4-1: Record the index number of the thread block as... , , , This indicates rounding up; the local thread number within the thread block is denoted as . , , Initialize the current loop count i to 1, and initialize the cache register for each thread. ;

[0017] Step 4-2: For the i-th iteration, for the thread block... Threads in Thread From the first input video memory area middle Starting at the location, two distance-pulse matrix complex data are read and stored in the first shared memory area. of Location, from the second input video memory area of Starting at the specified location, the complex data of the coefficients of two Doppler filter banks is read and stored in the second shared memory area. of At this location; perform inter-thread synchronization, completing the first shared memory area of ​​the current iteration of the loop. Second shared memory area Assigning a value;

[0018] Step 4-3, for thread blocks Threads in For the first shared memory area Second shared memory area implement The result of the double complex number multiplication and addition operation is saved to the current thread's cache register. middle;

[0019] Step 4-4: Determine if the condition is met. If the conditions are met, the cache register will be... Assign to the output video memory area of At the correct position; otherwise, set i = i + 1 and return to step 4-2.

[0020] Furthermore, in step 4-3, , No. The specific process of the second complex number multiplication and addition operation is as follows:

[0021] Step 4-3-1, from the first shared memory area of At the location, two distance-pulse matrix complex data are loaded into the first local register. In the middle, from the second shared memory area of The complex data of the Doppler filter bank coefficients is loaded into the second local register at the specified location. Middle; Second Local Register With the first local register Perform dot product operations on complex numbers, and add the results of the dot product operations to the cache register. middle;

[0022] Step 4-3-2, from the first shared memory area Shared memory At the location, two distance-pulse matrix complex data are loaded into the first local register. In the middle, from the second shared memory area of The complex data of the Doppler filter bank coefficients is loaded into the second local register at the specified location. Middle; Second Local Register With the first local register Perform dot product operations on complex numbers, and add the results of the dot product operations to the cache register. middle.

[0023] Furthermore, in step 4-3, the second local register With the first local register The specific steps for performing a dot product operation on complex numbers are as follows:

[0024] Record the first local register , and The first local register The real and imaginary parts of the complex data of the first distance-pulse matrix. and First local register The real and imaginary parts of the complex data of the second distance-pulse matrix are defined; the third local register is defined. Define the fourth local register. , For the second local register The real part of the complex data of the coefficients of the middle Doppler filter bank; define the fifth local register. , For the second local register The imaginary part of the complex data of the coefficients of the middle Doppler filter bank; defining the complex multiplication coefficient vector register. ;renew ,renew ,renew As the result of the dot product operation on complex numbers.

[0025] The beneficial effects of this invention are:

[0026] (1) It supports the reconstruction of the coefficient matrix of the Doppler filter bank and has strong engineering adaptability;

[0027] This invention decouples the generation of the Doppler filter bank coefficient matrix from the filtering calculation, enabling dynamic reconstruction of the filter bank. It allows for flexible adjustment of the Doppler channel response based on radar operating mode and target environment, expanding scene adaptability. Furthermore, this invention allows for independent design of the amplitude-frequency characteristics of each channel, improving the detection performance of low-speed, weak targets.

[0028] (2) By utilizing GPU shared memory and wide-bit memory access mechanism, the processing time of radar signals can be shortened;

[0029] This invention transforms frequent global video memory reads into high-speed access to on-chip storage resources through shared memory and wide-bit memory access mechanisms, effectively overcoming storage access bottlenecks. Simultaneously, it configures a GPU thread grid architecture specifically according to the distance-pulse matrix dimension structure to achieve parallel filtering calculations of multi-pulse echo data, ensuring precise matching between computing resources and data dimensions. The synergistic effect of these two technologies significantly shortens radar signal processing time, meeting the engineering requirements of radar systems for high throughput and high real-time performance. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating the method described in this invention;

[0031] Figure 2 This is a schematic diagram of thread grid allocation for GPU parallel computing according to the method described in this invention.

[0032] Figure 3 This is a schematic diagram illustrating the reading of the shared memory area in the method described in this invention;

[0033] Figure 4 This is a schematic diagram of the double complex number multiplication and addition operation in the method described in this invention. Detailed Implementation

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0035] This embodiment provides a PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism, and its flowchart is shown below. Figure 1 As shown, it includes the following steps:

[0036] Step 1: Initialize radar echo data and filter bank parameters

[0037] The range-pulse matrix obtained after pulse compression processing of the radar echo signal , dimension , and These represent the number of radar echo pulses and the number of range gates, respectively, with the basic unit being float2, used to represent the real and imaginary parts; the Doppler filter bank coefficient matrix is ​​then obtained. , dimension , The order of the Doppler filter bank coefficient matrix is ​​represented by the float2 unit, which is used to represent the real and imaginary parts respectively. In actual radar echo signal processing, the order of the Doppler filter bank coefficient matrix is... Pulse count of radar echo signal equal;

[0038] Initialize the filter output matrix , dimension The basic unit is float2, which is used to represent the real part and the imaginary part, respectively.

[0039] Step 2: GPU-based hardware resource allocation

[0040] Physical storage space is dynamically allocated in the global video memory on the GPU device side. Specifically, this physical storage space includes: a space for storing the distance-pulse matrix. First input video memory area The allocation size is the same as Consistent; used to store the coefficient matrix of the Doppler filter bank. Second input video memory area , allocation size and Consistency; and the output memory area used to store the filter output matrix. The allocation size is the same as Consistent.

[0041] The distance-pulse matrix in the CPU's main memory is copied via a memory copy interface called by the CPU. With the coefficient matrix of the Doppler filter bank Copy to each and In this process, data migration between heterogeneous computing platforms is completed, providing a data-ready state for subsequent parallel accelerated computing.

[0042] In step 2, to further accelerate the parallel computing speed of the GPU, in the video memory area... , and The storage strategy employs a cache-first approach, sequentially determining whether the remaining available capacity of the on-chip storage resources meets the storage capacity required for the currently allocated video memory area according to a preset priority order. The video memory area to be allocated includes a first input video memory area, a second input video memory area, and an output video memory area. If the conditions are met, the currently allocated video memory area is allocated to the free physical space of the on-chip storage resources; otherwise, it is allocated to off-chip storage resources. In this example, the on-chip storage resource is on-chip static random access memory (SRAM). As described above, the Doppler filter bank coefficient matrix with higher reuse rates and the distance-pulse matrix to be processed by the current thread block are preferentially allocated to the on-chip SRAM. When the GPU executes kernel functions, the core computing unit directly reads data from the on-chip SRAM at high speed. This reduces the memory access latency caused by frequent access to slow off-chip storage resources, effectively improving the speed of GPU kernel function execution.

[0043] Step 3: Thread grid allocation based on GPU parallel computing

[0044] Based on the distance-pulse matrix obtained in step 1 The CPU calculates and configures the low-level scheduling parameters for the GPU kernel functions. Specifically, such as... Figure 2 As shown, the total number of global work items is determined based on the row and column dimensions of the matrix, and a thread grid for parallel computing is constructed, including a two-dimensional index space and work groups, and on-chip shared memory is dynamically configured for each work group;

[0045] Furthermore, in step 3,

[0046] In the distance unit dimension, the number of global threads is set to... and set the thread block size to The number of thread blocks is In the impulse dimension, the global thread count is set to... and set the thread block size to The number of thread blocks is M is a positive integer power of 2, and in this implementation, it is taken as 32;

[0047] Allocate the first shared memory area for each thread block Second shared memory area Their sizes are all The basic unit is float2.

[0048] Step 4: GPU-based parallel algorithm execution process

[0049] Based on the configured two-dimensional thread grid of the GPU, GPU kernel function calculations are performed to realize the second input memory area. and the first input video memory area The core of the matrix multiplication operation is to utilize the shared memory of the GPU in multi-threaded blocks and the wide-bit memory access mechanism to achieve fast computation of the matrix multiplication algorithm. The specific details are as follows:

[0050] Step 4-1, the index number of the thread block is , , ceil indicates rounding up; the local thread number within a thread block is... , , Initialize the current loop count i to 1, and initialize the cache register for each thread. ;

[0051] Step 4-2: For the i-th iteration, for the thread block... Threads in Thread From the first input video memory area middle Starting at the location, two distance-pulse matrix complex data are read and stored in the first shared memory area. of Location, from the second input video memory area of Starting at the specified location, the complex data of the coefficients of two Doppler filter banks is read and stored in the second shared memory area. of At this location; perform inter-thread synchronization, completing the first shared memory area of ​​the current iteration of the loop. Second shared memory area Assigning a value;

[0052] Step 4-3, for thread blocks Threads in ,right and implement The result of the double complex number multiplication and addition operation is saved to the current thread's cache register. middle;

[0053] Step 4-4: Determine if the condition is met. If the conditions are met, the cache register will be... Assign to Otherwise, let i = i + 1 and return to step 4-2.

[0054] Furthermore, in step 4-3, for the first... The specific process of the second complex number multiplication and addition operation is as follows:

[0055] Step 4-3-1, from the first shared memory area of At the location, two distance-pulse matrix complex data are loaded into the first local register. In the middle, from the second shared memory area of The complex data of the Doppler filter bank coefficients is loaded into the second local register at the specified location. Middle; Second Local Register With the first local register Perform dot product operations on complex numbers, and add the results of the dot product operations to the cache register. middle;

[0056] Step 4-3-2, from the first shared memory area Shared memory At the location, two distance-pulse matrix complex data are loaded into the first local register. In the middle, from the second shared memory area of The complex data of the Doppler filter bank coefficients is loaded into the second local register at the specified location. Middle; Second Local Register With the first local register Perform dot product operations on complex numbers, and add the results of the dot product operations to the cache register. middle.

[0057] A diagram illustrating shared memory area reading is shown below. Figure 3 As shown in the diagram, the operation of multiplication and addition of two complex numbers is illustrated below. Figure 4 As shown.

[0058] In the above complex number multiplication and addition operation, the second local register With the first local register The specific steps for performing a dot product operation on complex numbers are as follows:

[0059] To fully utilize the SIMD4 architecture of the GPU and achieve high throughput, the double complex multiplication and addition operation is performed twice in instruction-level parallelism. Let the first local register be... , and First local register The real and imaginary parts of the complex data of the first distance-pulse matrix. and First local register The real and imaginary parts of the complex data of the second distance-pulse matrix are defined; the third local register is defined. Define the fourth local register. , For the second local register The real part of the complex data of the coefficients of the middle Doppler filter bank; define the fifth local register. , For the second local register The imaginary part of the complex data of the coefficients of the middle Doppler filter bank; defining the complex multiplication coefficient vector register. ;renew ,renew ,renew As the result of the dot product operation on complex numbers.

[0060] GPU-based parallel algorithm output: The host calls a memory copy interface to copy the filtering calculation results. Return to .

[0061] To verify the performance of the method described in this embodiment, tests were conducted on Doppler filter bank coefficient matrices of different orders and measured range-pulse matrices of different lengths. During the tests, the method described in this embodiment was compared with existing block matrix multiplication methods and conventional matrix multiplication methods. The conventional matrix multiplication method utilizes GPU parallel acceleration, but each element in the filtered output matrix still requires a complete multiplication-accumulation operation. The existing block matrix multiplication method divides the matrix to be multiplied into several sub-blocks, using these sub-blocks as basic units for GPU parallel acceleration, and does not employ a wide-bit memory access mechanism. Each set of parameters was repeated one hundred times, and the average execution time was taken. The computation time of the three methods and their proportion of the coherent processing interval (CPI) time in the radar were compared. The test results are as follows:

[0062] When the distance-pulse matrix is ​​4096×64 and the Doppler filter bank coefficient matrix is ​​64×64, the average time taken by the method described in this embodiment is 444 μs, the average time taken by the block matrix multiplication method is 1037 μs, and the average time taken by the conventional matrix multiplication method is 7440 μs. The time taken by the method described in this embodiment, the block matrix multiplication method, and the conventional matrix multiplication method are approximately 2.9%, 6.8%, and 48.6% of the CPI time, respectively. The speedup of the method described in this embodiment compared to the block matrix multiplication method and the conventional matrix multiplication method is approximately 2.3 times and 16.8 times, respectively.

[0063] When the distance-pulse matrix is ​​2048×128 and the Doppler filter bank coefficient matrix is ​​128×128, the average time of the method described in this embodiment is 896 μs, the average time of the block matrix multiplication method is 2052 μs, and the average time of the conventional matrix multiplication method is 63117 μs. The time consumption of the method described in this embodiment, the block matrix multiplication method, and the conventional matrix multiplication method are approximately 5.8%, 13.3%, and 408.6% of the CPI time, respectively. The speedup of the method described in this embodiment compared to the block matrix multiplication method and the conventional matrix multiplication method is approximately 2.3 times and 70.4 times, respectively.

[0064] When the distance-pulse matrix is ​​1536×256 and the Doppler filter bank coefficient matrix is ​​256×256, the average time of the method described in this embodiment is 2718 μs, the average time of the block matrix multiplication method is 6200 μs, and the average time of the conventional matrix multiplication method is 315875 μs. The time consumption of the method described in this embodiment, the block matrix multiplication method, and the conventional matrix multiplication method are approximately 17.7%, 40.4%, and 2057.0% of the CPI time, respectively. The speedup of the method described in this embodiment compared to the block matrix multiplication method and the conventional matrix multiplication method is approximately 2.3 times and 116.2 times, respectively.

[0065] When the distance-pulse matrix is ​​2048×256 and the Doppler filter bank coefficient matrix is ​​256×256, the average time taken by the method described in this embodiment is 3667 μs, the average time taken by the block matrix multiplication method is 8294 μs, and the average time taken by the conventional matrix multiplication method is 430214 μs. The time taken by the method described in this embodiment, the block matrix multiplication method, and the conventional matrix multiplication method are approximately 16.9%, 38.2%, and 1982.7% of the CPI time, respectively. The speedup of the method described in this embodiment compared to the block matrix multiplication method and the conventional matrix multiplication method is approximately 2.3 times and 117.3 times, respectively.

[0066] When the distance-pulse matrix is ​​768×512 and the Doppler filter bank coefficient matrix is ​​512×512, the average time taken by the method described in this embodiment is 5485 μs, the average time taken by the block matrix multiplication method is 17659 μs, and the average time taken by the conventional matrix multiplication method is 686024 μs. The time taken by the method described in this embodiment, the block matrix multiplication method, and the conventional matrix multiplication method are approximately 25.3%, 81.5%, and 3164.3% of the CPI time, respectively. The speedup of the method described in this embodiment compared to the block matrix multiplication method and the conventional matrix multiplication method is approximately 3.2 times and 125.1 times, respectively.

[0067] When the distance-pulse matrix is ​​2048×512 and the Doppler filter bank coefficient matrix is ​​512×512, the average time taken by the method described in this embodiment is 14763 μs, the average time taken by the block matrix multiplication method is 48716 μs, and the average time taken by the conventional matrix multiplication method is 1907578 μs. The time taken by the method described in this embodiment, the block matrix multiplication method, and the conventional matrix multiplication method are approximately 28.8%, 95.0%, and 3721.3% of the CPI time, respectively. The speedup of the method described in this embodiment compared to the block matrix multiplication method and the conventional matrix multiplication method is approximately 3.3 times and 129.2 times, respectively.

[0068] The test results above show that the method described in this embodiment has significant computational advantages under different matrix sizes. Specifically, compared to the block matrix multiplication method, the method described in this embodiment effectively reduces computation time, and the acceleration effect increases with the matrix size. Compared to the conventional matrix multiplication method, the time reduction of the method described in this embodiment is more significant, and the advantage becomes more pronounced with larger matrix sizes. Furthermore, the proportion of computation time of the method described in this embodiment to the coherent processing interval is low in all test scenarios, reserving sufficient time margin for processing stages such as pulse compression, constant false alarm rate detection, and angle calculation, thus meeting the real-time processing requirements of the system. In contrast, the block matrix multiplication method accounts for a large proportion of the CPI time, almost filling the entire CPI time under larger matrix sizes, making it difficult to leave time margin for subsequent processing stages; the conventional matrix multiplication method takes far longer than the CPI time, making it impossible to complete matrix multiplication within the CPI time. Therefore, the method described in this embodiment can meet the real-time requirements of the system while ensuring computational efficiency.

[0069] The method described in this invention abandons the traditional MTD processing framework. To meet the requirement of independent control of core software and hardware, this invention does not rely on commercial closed-source acceleration libraries from specific vendors. Instead, it is based on the open standard OpenCL (Open Computing Language) heterogeneous computing framework. The core algorithm has undergone deep low-level reconstruction and instruction-level optimization. This invention improves the local data reuse rate through a shared memory mechanism to reduce global read latency. It also utilizes the SIMD4 vectorized unit architecture and a memory mapping mechanism to encapsulate the radar echo matrix and filter coefficients into a wide-byte vector data structure, thereby enabling concurrent execution of radar multi-pulse echo data streams.

Claims

1. A multi-pulse parallel filtering method for PD radar based on GPU wide-bit memory access mechanism, characterized in that, Includes the following steps: Step 1: Obtain the range-pulse matrix of the radar echo signal after pulse compression processing; Obtain the coefficient matrix of the Doppler filter bank; Initialize the filter output matrix; Step 2: Allocate physical storage space in the global video memory of the GPU device for the distance-pulse matrix, the Doppler filter bank coefficient matrix, and the filter output matrix, respectively, and denot them as the first input video memory area, the second input video memory area, and the output video memory area; Step 3: Configure the thread grid for GPU parallel computing based on the dimension of the distance-pulse matrix, and configure two shared memory areas for each thread block in the thread grid; Step 4: Perform parallel computation of GPU kernel functions based on the configured GPU thread grid. Utilize the shared memory area of ​​the GPU in the multi-threaded block sharing mechanism and wide-bit memory access mechanism to realize the multiplication operation between the second input memory area and the first input memory area. The operation result is the filter output matrix stored in the output memory area, thus completing the parallel filtering of the multi-pulse radar.

2. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 1, characterized in that, In step 1, the distance-pulse matrix The dimension is , and These represent the number of radar echo pulses and the number of range gates, respectively; the Doppler filter bank coefficient matrix. The dimension is , The order of the coefficient matrix of the Doppler filter bank; Doppler filter bank coefficient matrix order Pulse count of radar echo signal Numerical values ​​are equal; filter output matrix The dimension is .

3. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 1, characterized in that, In step 2, the first input video memory area Used to store distance-pulse matrix The size is the distance-pulse matrix. Consistent; Second input video memory area Used to store the coefficient matrix of the Doppler filter bank. The size of the Doppler filter bank coefficient matrix Consistent; Output memory area Used to store the filter output matrix The size is the same as the filter output matrix. Consistent.

4. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 1, characterized in that, In step 2, a cache-first technique is used to allocate physical storage space for the first input video memory area, the second input video memory area, and the output video memory area.

5. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 1, characterized in that, In step 3, the global number of threads is set to [value] in the distance unit dimension. The thread block size is set to The number of thread blocks is In the impulse dimension, the global thread count is set to... The thread block size is set to The number of thread blocks is M is a positive integer power of 2; allocate the first shared memory area for each thread block. Second shared memory area Their sizes are all .

6. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 5, characterized in that, The specific process of step 4 is as follows: Step 4-1: Record the index number of the thread block as... , , , This indicates rounding up; the local thread number within the thread block is denoted as . , , ; Initialize the current loop count i to 1, and initialize the cache register for each thread. ; Step 4-2: For the i-th iteration, for the thread block... Threads in Thread From the first input video memory area middle Starting at the location, two distance-pulse matrix complex data are read and stored in the first shared memory area. of Location, from the second input video memory area of Starting at the specified location, the complex data of the coefficients of two Doppler filter banks is read and stored in the second shared memory area. of At this location; perform inter-thread synchronization, completing the first shared memory area of ​​the current iteration of the loop. Second shared memory area Assigning a value; Step 4-3, for thread blocks Threads in For the first shared memory area Second shared memory area implement The result of the double complex number multiplication and addition operation is saved to the current thread's cache register. middle; Step 4-4: Determine if the condition is met. If the conditions are met, the cache register will be... Assign to the output video memory area of At the correct position; otherwise, set i = i + 1 and return to step 4-2.

7. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 6, characterized in that, In step 4-3, , No. The specific process of the second complex number multiplication and addition operation is as follows: Step 4-3-1, from the first shared memory area of At the location, two distance-pulse matrix complex data are loaded into the first local register. In the middle, from the second shared memory area of The complex data of the Doppler filter bank coefficients is loaded into the second local register at the specified location. Middle; Second Local Register With the first local register Perform dot product operations on complex numbers, and add the results of the dot product operations to the cache register. middle; Step 4-3-2, from the first shared memory area Shared memory At the location, two distance-pulse matrix complex data are loaded into the first local register. In the middle, from the second shared memory area of The complex data of the Doppler filter bank coefficients is loaded into the second local register at the specified location. Middle; Second Local Register With the first local register Perform dot product operations on complex numbers, and add the results of the dot product operations to the cache register. middle.

8. The PD radar multi-pulse parallel filtering method based on GPU wide-bit memory access mechanism according to claim 6, characterized in that, In step 4-3, the second local register With the first local register The specific steps for performing a dot product operation on complex numbers are as follows: Record the first local register , and First local register The real and imaginary parts of the complex data of the first distance-pulse matrix. and The first local register The real and imaginary parts of the complex data of the second distance-pulse matrix are defined; the third local register is defined. Define the fourth local register. , For the second local register The real part of the complex data of the coefficients of the middle Doppler filter bank; define the fifth local register. , For the second local register The imaginary part of the complex data of the coefficients of the middle Doppler filter bank; defining the complex multiplication coefficient vector register. ;renew ,renew ,renew As the result of the dot product operation on complex numbers.

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