Display panel and display device

Abstract

The application discloses a display panel and a display device, and belongs to the technical field of display. The display panel provided by the application comprises a substrate, a plurality of sub-pixels, an encapsulation layer and a first anti-static structure. The first anti-static structure is located in at least two first sub-regions and a second sub-region in a non-display area, and is used for accessing a ground end in a driving circuit board through a binding area. In this way, the first anti-static structure can block the downward conduction of the charges generated by static electricity and the lateral conduction in the direction of the display area. In the case that the first anti-static structure has conductivity, the charges can be conducted to the ground end along the first anti-static structure after being conducted to the first anti-static structure, so that the static electricity is released. Therefore, the first anti-static structure can avoid the opening of the transistors in the gate driving circuit and the pixel driving circuit caused by the charges generated by static electricity, thereby avoiding the abnormal opening of the light-emitting device, ensuring the normal display of the display panel and improving the reliability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Display panels that use organic light-emitting diodes (OLEDs) to achieve display functions are called OLED display panels. Due to their high color gamut, thinness, and flexibility, they have become the mainstream display structure. OLED display devices typically include: an OLED display panel and a cover glass plate located on one side of the OLED display panel's display surface.

[0003] During the use of OLED display devices, static electricity may accumulate on the surface of the cover glass, which may cause some light-emitting devices in the OLED display panel to turn on abnormally, resulting in phenomena such as greening, thus affecting the normal use of the OLED display device. Summary of the Invention

[0004] This application provides a display panel and a display device. It can solve the problem of poor reliability in existing display panels. The technical solution is as follows: On one hand, a display panel is provided, characterized in that the display panel has a display area and a non-display area, the non-display area being distributed around the display area; the display panel includes: Substrate; Multiple sub-pixels are located on one side of the substrate and are distributed at least within the display area; An encapsulation layer is located on the side of the plurality of sub-pixels that faces away from the substrate; A first antistatic structure is located within the non-display area and distributed around the display area, and the first antistatic structure is conductive; The non-display area includes: two first partitions distributed on both sides of the display area in a first direction, and a second partition and a third partition distributed on both sides of the display area in a second direction; the third partition has a bonding area inside, which is used to electrically connect with the driving circuit board; the first anti-static structure is located at least in the two first partitions and the second partition, and is used to connect to the ground terminal in the driving circuit board through the bonding area.

[0005] Optionally, the first antistatic structure is located on the side of the substrate facing the plurality of sub-pixels; The first antistatic structure and the conductive structure in the sub-pixel are disposed in the same layer and are made of the same material.

[0006] Optionally, the sub-pixel includes: a pixel driving circuit and a light-emitting device, wherein the light-emitting device is located on the side of the pixel driving circuit away from the substrate, and a first electrode in the light-emitting device is electrically connected to the pixel driving circuit; the pixel driving circuit has a plurality of transistors; Wherein, the first anti-static structure is disposed in the same layer as the gate of the transistor and is made of the same material, and / or, the first anti-static structure is disposed in the same layer as the active layer of the transistor and is made of the same material, and / or, the first anti-static structure is disposed in the same layer as the source and drain of the transistor and is made of the same material, and / or, the first anti-static structure is disposed in the same layer as the first electrode in the light-emitting device and is made of the same material.

[0007] Optionally, the first antistatic structure includes: two first blocking and dissipation sections, one second blocking and dissipation section, and two first grounding connection sections; the two first blocking and dissipation sections are respectively located within the two first partitions, the second blocking and dissipation section is located within the second partition, and the two first grounding connection sections are both located within the third partition; the first ends of the two first blocking and dissipation sections are respectively connected to the two ends of the second blocking and dissipation section, the second ends of the two first blocking and dissipation sections are respectively connected to the first ends of the two first grounding connection sections, and the second ends of the two first grounding connection sections are both used to connect to the grounding terminal in the drive circuit board through the bonding area.

[0008] Optionally, the first antistatic structure is integrated inside the substrate.

[0009] Optionally, for the first anti-static structure integrated inside the substrate, the first anti-static structure includes: two third blocking dissipation sections, one fourth blocking dissipation section, one fifth blocking dissipation section, and two second grounding connection sections; the two third blocking dissipation sections are respectively located within the two first partitions, the fourth blocking dissipation section is located within the second partition, and the fifth blocking dissipation section and the two second grounding connection sections are both located within the third partition; the first ends of the two third blocking dissipation sections are respectively connected to the two ends of the fourth blocking dissipation section, and the second ends of the two third blocking dissipation sections are respectively connected to the two ends of the fifth blocking dissipation section; the first ends of the two second grounding connection sections are both connected to the fifth blocking dissipation section, and the second ends of the two second grounding connection sections are both used to connect to the grounding terminal in the driving circuit board through the bonding area.

[0010] Optionally, there may be multiple first antistatic structures, which are distributed sequentially in a direction away from the display area in a direction parallel to the substrate.

[0011] Optionally, the display panel further includes: The second anti-static structure is distributed within the non-display area and corresponds to the first anti-static structure; the second anti-static structure includes: a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, and a fourth thin-film transistor; The drain of the first thin-film transistor is connected to the gate and to the corresponding first anti-static structure, and the source of the first thin-film transistor is connected to the drain of the second thin-film transistor. The drain of the second thin-film transistor is connected to the gate, and the source of the second thin-film transistor is connected to the data signal terminal; The drain of the third thin-film transistor is connected to the gate and to the data signal terminal, and the source of the third thin-film transistor is connected to the drain of the fourth thin-film transistor. The drain of the fourth thin-film transistor is connected to the gate, and the source of the fourth thin-film transistor is connected to the corresponding first anti-static structure.

[0012] Optionally, the second antistatic structure is located in the corner region between the second partition and the first partition, and / or the second antistatic structure is located in the corner region between the third partition and the first partition.

[0013] Optionally, the encapsulation layer includes: a first inorganic encapsulation layer; the display panel further includes: a driving circuit layer, wherein the pixel driving circuit in the sub-pixel is located within the driving circuit layer; the inorganic film layer of the driving circuit layer closest to the encapsulation layer is a target inorganic insulating layer; In the non-display area, the target inorganic insulating layer has a first through groove, the first inorganic encapsulation layer is in direct contact with the target inorganic insulating layer, and there is a portion of the first inorganic encapsulation layer located in the first through groove, the first inorganic encapsulation layer located in the first through groove is in direct contact with the groove sidewall of the first through groove.

[0014] Optionally, the target inorganic insulating layer has a plurality of first through-grooves arranged in a direction parallel to the substrate; the portion of the target inorganic insulating layer located between two adjacent first through-grooves is an inorganic insulating pillar; the driving circuit layer further includes: A first metal pillar is located on the side of the inorganic insulating pillar away from the substrate, and the first metal pillar protrudes from both sides of the inorganic insulating pillar in the width direction; the first inorganic encapsulation layer is in direct contact with the side of the first metal pillar away from the substrate, and is also in direct contact with the outer surface of the first metal pillar and the side of the first metal pillar facing the substrate. And / or, a second metal pillar located on the side of the inorganic insulating pillar facing the substrate, the second metal pillar protruding from both sides of the inorganic insulating pillar in the width direction; the first inorganic encapsulation layer is in direct contact with the side of the second metal pillar away from the substrate, and is in direct contact with the outer surface of the second metal pillar.

[0015] On the other hand, a display device is provided, characterized in that it includes: a power supply component, and a display panel electrically connected to the power supply component, wherein the display panel is any of the display panels described above. The beneficial effects of the technical solutions provided by the embodiments of this application include at least the following: Since the first anti-static structure is located in at least two first and second partitions within the non-display area and is used to connect to the ground terminal in the driver circuit board via the bonding area, the first anti-static structure can prevent the downward conduction of static-generated charges and the lateral conduction towards the display area. Furthermore, when the first anti-static structure is conductive, the charge, after being conducted to the first anti-static structure, can be conducted along the first anti-static structure to the ground terminal, thereby completing the static discharge. In this way, the first anti-static structure can prevent the static-generated charges from causing the transistors in the gate drive circuit and pixel drive circuit to turn on, thereby preventing abnormal turn-on of the light-emitting devices, ensuring normal display of the display panel, and improving the reliability of the display panel. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a partial structural schematic diagram of a display device provided in an embodiment of this application; Figure 2 This is a partial top view of a display panel provided in an embodiment of this application; Figure 3 yes Figure 2 A schematic cross-sectional view of the display panel at AA' is shown; Figure 4 This is a partial top view of another display panel provided in an embodiment of this application; Figure 5 This is a partial structural schematic diagram of another display device provided in an embodiment of this application; Figure 6 This is a partial structural schematic diagram of another display device provided in the embodiments of this application; Figure 7This is a partial structural schematic diagram of another display device provided in an embodiment of this application; Figure 8 This is a partial top view of another display panel provided in the embodiments of this application; Figure 9 This is a partial structural schematic diagram of another display device provided in an embodiment of this application; Figure 10 This is a partial top view of another display panel provided in the embodiments of this application; Figure 11 This is a partial top view of another display panel provided in the embodiments of this application; Figure 12 This is a partial structural schematic diagram of another display device provided in an embodiment of this application; Figure 13 This is a partial top view of another display panel provided in the embodiments of this application; Figure 14 This is a partial structural diagram of a display panel provided in an embodiment of this application; Figure 15 This is a schematic diagram of a second antistatic structure provided in an embodiment of this application; Figure 16 This is a schematic diagram of another second antistatic structure provided in the embodiments of this application; Figure 17 This is a partial structural diagram of another display panel provided in an embodiment of this application; Figure 18 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application; Figure 19 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application; Figure 20 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application; Figure 21 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] Please refer to Figure 1 , Figure 1 This is a partial structural schematic diagram of a display device provided in an embodiment of this application. The display device 00 may include: a display panel 000, and a cover glass 10 located on one side of the display surface of the display panel 000.

[0020] Please refer to Figure 2 and Figure 3 , Figure 2 This is a partial top view of a display panel provided in an embodiment of this application. Figure 3 yes Figure 2 The diagram shows a cross-sectional view of the display panel at AA'. The display panel 000 may include a substrate 100, a driving circuit layer 200, and an encapsulation layer 300. The driving circuit layer 200 may include a pixel driving circuit P1 located in the display area 001 and a gate driving circuit P2 located in the non-display area 002. Both the pixel driving circuit P1 and the gate driving circuit P2 have transistors T. The display panel 000 also includes a light-emitting device F, distributed within the display area 001 and electrically connected to the pixel driving circuit P1. The pixel driving circuit P1 drives the light-emitting device F to emit light, thereby realizing the display function of the display panel 000.

[0021] like Figure 1 As shown, when static electricity exists on the surface of the cover glass 10, the charge generated by the static electricity will be conducted downwards at the frame, i.e., the non-display area 002 of the display device 00, to the substrate 100 of the display panel 000, and then laterally from the substrate 100 towards the display area 001. For example, negative charges conducted to the area below the transistor T in the gate driving circuit P2 will be conducted upwards, causing the transistor T to turn on abnormally. Similarly, negative charges conducted to the area below the transistor T in the pixel driving circuit P1 will be conducted upwards, causing the transistor T to turn on abnormally, thus causing some of the light-emitting devices F in the display panel 000 to turn on abnormally. Among these, the green light-emitting device F has the lowest start-up current; therefore, under the influence of static electricity, the display panel 000 is prone to defects such as greening, thereby affecting the normal display of the display panel 000.

[0022] Therefore, this application provides a display panel that can reduce the impact of static electricity on the display panel and improve the reliability of the display panel.

[0023] Please refer to Figures 3-5 , Figure 4 This is a partial top view of another display panel provided in an embodiment of this application. Figure 5 This is a partial structural diagram of another display device provided in an embodiment of this application. The display panel 000 provided in this embodiment of the application has a display area 001 and a non-display area 002, with the non-display area 002 distributed around the display area 001. The display panel 000 may include: Substrate 100.

[0024] Multiple sub-pixels are located on one side of the substrate 100 and are distributed at least within the display area 001. Here, the sub-pixels may include a pixel driving circuit P1 and a light-emitting device F, wherein the light-emitting device F is located on the side of the pixel driving circuit P1 opposite to the substrate 100 and is electrically connected to the pixel driving circuit P1.

[0025] The encapsulation layer 300 is located on the side of the multiple sub-pixels away from the substrate 100, and is used to protect the multiple sub-pixels from moisture erosion from the external environment.

[0026] The first antistatic structure 400 is located within the non-display area 002 and distributed around the display area 001. The first antistatic structure 400 is conductive.

[0027] The non-display area 002 includes two first partitions Q1 distributed on both sides of the display area 001 in the first direction X, and a second partition Q2 and a third partition Q3 distributed on both sides of the display area 001 in the second direction Y. The third partition Q3 has a bonding area Q31 inside, which is used for electrical connection with the driving circuit board PCB. The first anti-static structure 400 is located at least in the two first partitions Q1 and the second partition Q2, and is used to connect to the ground terminal in the driving circuit board PCB through the bonding area Q31.

[0028] In this way, the first anti-static structure 400 can block the downward conduction of static-generated charges and the lateral conduction towards the display area 001. Furthermore, when the first anti-static structure 400 is conductive, the charges, after being conducted to the first anti-static structure 400, can be conducted along the first anti-static structure 400 to the grounding terminal, thereby completing the static discharge. Therefore, the first anti-static structure 400 can prevent the static-generated charges from causing the transistors T in the gate driving circuit P2 and the pixel driving circuit P1 to turn on, thereby preventing the abnormal turn-on of the light-emitting device F and ensuring the normal display of the display panel 000.

[0029] In summary, the display panel provided in this application includes: a substrate, multiple sub-pixels, an encapsulation layer, and a first anti-static structure. The first anti-static structure is located in at least two first and second partitions within the non-display area and is used to connect to a ground terminal in the driving circuit board via a bonding area. Thus, the first anti-static structure can block the downward conduction of static-generated charges and the lateral conduction towards the display area. Furthermore, when the first anti-static structure is conductive, the charge, after being conducted to the first anti-static structure, can be conducted along the first anti-static structure to the ground terminal, thereby completing the static discharge. Therefore, the first anti-static structure can prevent static-generated charges from causing the transistors in the gate driving circuit and pixel driving circuit to turn on, thereby preventing abnormal turn-on of the light-emitting devices, ensuring normal display of the display panel, and improving the reliability of the display panel.

[0030] It should be noted that, as Figure 4 As shown, the gate driving circuit P2 of the display panel 000 can be located within the two first partitions Q1 of the non-display area 002. The display panel 000 may also include a first power signal line and a second power signal line (not shown in the figure) located in the non-display area 002. The potential of the power signal loaded on the first power signal line is higher than the potential of the power signal loaded on the second power signal line. That is, the first power signal line can be a high-level power signal line, and the second power signal line can be a low-level power signal line. The first power signal line can be used to apply a high-level power signal to each pixel driving circuit P1, and the second power signal line can be used to apply a low-level power signal to each pixel driving circuit P1. To prevent the charge generated by static electricity from affecting the gate driving circuit P2, the first power signal line, and the second power signal line, the first anti-static structure 400 can be located within the non-display area 002, and on the side of the gate driving circuit P2, the first power signal line, and the second power signal line away from the display area 001.

[0031] like Figure 5 As shown, in some embodiments, the first antistatic structure 400 may be located on the side of the substrate 100 facing the plurality of sub-pixels.

[0032] The first antistatic structure 400 is disposed in the same layer as the conductive structure in the sub-pixel and is made of the same material.

[0033] In this way, without adding any new process steps, the reliability of the display panel can be improved while saving the manufacturing cost of the display panel.

[0034] like Figure 3 As shown, the first electrode 501 in the light-emitting device F is electrically connected to the pixel driving circuit P1. The pixel driving circuit P1 has multiple transistors T.

[0035] The first anti-static structure 400 may be disposed in the same layer as the gate G of the transistor T and made of the same material, and / or the first anti-static structure 400 may be disposed in the same layer as the active layer Act of the transistor T and made of the same material, and / or the first anti-static structure 400 may be disposed in the same layer as the source S and drain D of the transistor T and made of the same material, and / or the first anti-static structure 400 may be disposed in the same layer as the first electrode 501 in the light-emitting device F and made of the same material.

[0036] Specifically, the pixel driving circuit P1 is located within the driving circuit layer 200 in the display panel 000. The display panel 000 may also include: a first electrode layer 500, a pixel definition layer 600, a light-emitting layer 700, and a second electrode layer 800 located on the side of the driving circuit layer 200 away from the substrate 100. The first electrode layer 500, the pixel definition layer 600, the light-emitting layer 700, and the second electrode layer 800 are stacked in a direction away from the substrate 100 and are located at least within the display area 001.

[0037] The first electrode layer 500 may include a plurality of separately disposed first electrodes 501, which may be electrically connected to a plurality of pixel driving circuits P1. In some embodiments, the first antistatic structure 400 described above may also be included. In this case, the first antistatic structure 400 may include a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer stacked together. The first and third sub-conductive layers may be transparent conductive materials, such as indium tin oxide (ITO), and the second sub-conductive layer may be a metallic conductive material, such as silver (Ag).

[0038] The pixel definition layer 600 may have multiple pixel openings K, which may correspond to multiple first electrodes 501, and the orthogonal projection of the pixel opening K on the substrate 100 is located within the orthogonal projection of the corresponding first electrode 501 on the substrate 100.

[0039] Both the light-emitting layer 700 and the second electrode layer 800 have portions located within the pixel opening K.

[0040] Thus, for a pixel opening K, the first electrode 501 corresponding to this pixel opening K, as well as the portion of the light-emitting layer 700 and the second electrode layer 800 located within this pixel opening K, can form a light-emitting device F.

[0041] The pixel driving circuit P1 may include at least two transistors T and at least one storage capacitor.

[0042] The storage capacitor may include a first capacitor electrode C1 and a second capacitor electrode C2 disposed opposite to each other. The transistor T may include an active layer Act, a gate G, a source S, and a drain D. The active layer Act may be insulated from the gate G, and both the source S and the drain D may be connected to the active layer Act. The source S may be electrically connected to a data line, and the drain D may be electrically connected to the first electrode 501 of the light-emitting device F. Here, the drain D may be electrically connected to the first electrode 501 by direct connection, or, as... Figure 3As shown, the drain D can be electrically connected to the first electrode 501 via the transfer electrode Z. The transfer electrode can be a single-layer structure or a multi-layer structure. For example, in the case of a double-layer structure, the transfer electrode may include a first sub-transfer electrode and a second sub-transfer electrode stacked together.

[0043] When the drain D is electrically connected to the first electrode 501 through a single-layer transition electrode Z, the driving circuit layer 200 may include: a semiconductor layer, a first gate insulating layer 201, a first gate layer, a second gate insulating layer 202, a second gate layer, a dielectric layer 203, a first source-drain layer, a first planarization layer 204, an interlayer dielectric layer 205, a second source-drain layer, and a second planarization layer 206, all stacked on the substrate 100.

[0044] The semiconductor layer may include the active layer Act in the transistor T. In some embodiments, it may also include the first antistatic structure 400 described above.

[0045] The first gate layer may include a gate G in the transistor T and a first capacitor electrode C1 in the storage capacitor. In some embodiments, it may also include the first antistatic structure 400 described above. In this case, the first antistatic structure 400 may include molybdenum.

[0046] The second gate layer may include a second capacitor electrode C2 in a storage capacitor. In some embodiments, it may also include the first antistatic structure 400 described above. In this case, the first antistatic structure 400 may include molybdenum.

[0047] The first source-drain layer may include the source (S) and drain (D) of the transistor T. In some embodiments, it may also include the first antistatic structure 400 described above. In this case, the first antistatic structure 400 may include a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer stacked together, wherein the first and third sub-conductive layers may include titanium, and the second sub-conductive layer may include aluminum.

[0048] The second source / drain layer may include a transition electrode Z. In some embodiments, it may also include the first antistatic structure 400 described above. In this case, the first antistatic structure 400 may include a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer stacked together, wherein the first and third sub-conductive layers may include titanium, and the second sub-conductive layer may include aluminum.

[0049] like Figure 6 As shown, Figure 6This is a partial structural schematic diagram of another display device provided in an embodiment of this application. When the first antistatic structure 400 is disposed in the same layer as at least two of the aforementioned film layers and is made of the same material, the first antistatic structure 400 disposed in the same layer as different film layers and made of the same material can be multiple independent first antistatic structures 400. This improves the charge blocking effect of the first antistatic structure 400 and increases the electrostatic discharge path, accelerating electrostatic discharge. Alternatively, as... Figure 7 As shown, Figure 7 This is a partial structural schematic diagram of another display device provided in an embodiment of this application. Multiple first antistatic structures 400, disposed on the same layer as different film layers and made of the same material, can be in contact with each other. For example, Figure 7 One of the first antistatic structures 400 is disposed on the same layer as the second gate layer and made of the same material, while the other first antistatic structure 400 is disposed on the same layer as the first source-drain layer and made of the same material. The orthographic projections of the two first antistatic structures 400 located on different layers on the substrate 100 can overlap. The dielectric layer 203 located between the second gate layer and the first source-drain layer can have a second through-groove V2 located between the two first antistatic structures 400, so that the two first antistatic structures 400 can be contacted through the second through-groove V2 in at least a partial area. This can reduce the resistance of the first antistatic structure 400 and further accelerate the electrostatic discharge.

[0050] like Figure 4 and Figure 8 As shown, Figure 8 This is a partial top view of another display panel structure provided in this application embodiment. The first anti-static structure 400 may include: two first blocking and dissipating sections 401, one second blocking and dissipating section 402, and two first grounding connection sections L1. The two first blocking and dissipating sections 401 are respectively located in two first partitions Q1, the second blocking and dissipating section 402 is located in a second partition Q2, and the two first grounding connection sections L1 are both located in a third partition Q3. The first ends of the two first blocking and dissipating sections 401 are respectively connected to the two ends of the second blocking and dissipating section 402, and the second ends of the two first blocking and dissipating sections 401 are respectively connected to the first ends of the two first grounding connection sections L1. The second ends of the two first grounding connection sections L1 are both used to connect to the grounding terminal in the driver circuit board PCB through the bonding area Q31.

[0051] In this way, the first anti-static structure 400 located on the side of the substrate 100 facing multiple sub-pixels can be prevented from affecting the signal traces in the third partition Q3 of the driving circuit layer 200, thereby improving the yield of the display panel 000.

[0052] Please refer to Figure 9 , Figure 9This is a partial structural schematic diagram of another display device provided in an embodiment of this application. In some embodiments, the first antistatic structure 400 may also be integrated inside the substrate 100. In this case, the material of the first antistatic structure 400 may be similar to that in the above embodiments, and will not be described again here.

[0053] For example, the substrate 100 in the display panel 000 may include a first sub-substrate 101, a first buffer layer 102, a second sub-substrate 103, and a second buffer layer 104 stacked along the direction close to the sub-pixel.

[0054] The first antistatic structure 400 may be located between the first sub-substrate 101 and the first buffer layer 102, and / or, the first antistatic structure 400 may be located between the first buffer layer 102 and the second sub-substrate 103, and / or, the first antistatic structure 400 may be located between the second sub-substrate 103 and the second buffer layer 104, and / or, the first antistatic structure 400 may be located on the side of the second buffer layer 104 away from the second sub-substrate 103 and in direct contact with the second buffer layer 104.

[0055] Please refer to Figure 10 , Figure 10 This is a partial top view of another display panel structure provided in this application embodiment. For the first anti-static structure 400 integrated inside the substrate 100, the first anti-static structure 400 may include: two third blocking and dissipation sections 403, one fourth blocking and dissipation section 404, one fifth blocking and dissipation section 405, and two second grounding connection sections L2. The two third blocking and dissipation sections 403 are respectively located within two first partitions Q1, the fourth blocking and dissipation section 404 is located within a second partition Q2, and the fifth blocking and dissipation section 405 and the two second grounding connection sections L2 are both located within a third partition Q3. The first ends of the two third blocking and dissipation sections 403 are respectively connected to both ends of the fourth blocking and dissipation section 404, and the second ends of the two third blocking and dissipation sections 403 are respectively connected to both ends of the fifth blocking and dissipation section 405. The first ends of the two second grounding connection sections L2 are both connected to the fifth blocking and dissipation section 405, and the second ends of the two second grounding connection sections L2 are both used to connect to the ground terminal in the driver circuit board PCB through the bonding area Q31.

[0056] Thus, since the first anti-static structure 400 is integrated inside the substrate 100, the fifth blocking and dissipation section 405 will not affect the signal traces in the driving circuit layer 200. At the same time, the fifth blocking and dissipation section 405 can further block the charge generated by static electricity from being laterally conducted to the display area 001 in the third partition Q3, thereby further improving the reliability of the display panel 000.

[0057] Please refer to Figure 11 and Figure 12 , Figure 11 This is a partial top view of another display panel provided in the embodiments of this application. Figure 12 This is a partial structural schematic diagram of another display device provided in an embodiment of this application. In any of the above embodiments, the number of first antistatic structures 400 can be multiple. In a direction parallel to the substrate 100, the multiple first antistatic structures 400 can be sequentially distributed in a direction away from the display area 001. For example, as shown... Figure 12 As shown, there are two first antistatic structures 400, which can be located in the same layer. For example, both first antistatic structures 400 are located between the second sub-substrate 103 and the second buffer layer 104, and are distributed sequentially along the direction away from the display area 001. This improves the blocking effect of the first antistatic structure 400 on laterally conducted charges, increases the electrostatic discharge path, and accelerates electrostatic discharge.

[0058] Please refer to Figure 13 and Figure 14 , Figure 13 This is a partial top view of another display panel provided in the embodiments of this application. Figure 14 This is a partial structural diagram of a display panel provided in an embodiment of this application. In any of the above embodiments, the display panel 000 may further include: The second anti-static structure 900 is located within the non-display area 002 and corresponds to the first anti-static structure 400. Please refer to [reference needed]. Figure 15 , Figure 15 This is a schematic diagram of a second antistatic structure provided in an embodiment of this application. The second antistatic structure 900 may include: a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, and a fourth thin-film transistor T4.

[0059] In this configuration, the drain D of the first thin-film transistor T1 is connected to the gate G and to the corresponding first anti-static structure 400, thereby connecting to the ground terminal GND; the source S of the first thin-film transistor T1 is connected to the drain D of the second thin-film transistor T2.

[0060] The drain D of the second thin-film transistor T2 is connected to the gate G, and the source S of the second thin-film transistor T2 is connected to the data signal terminal Data.

[0061] The drain D of the third thin-film transistor T3 is connected to the gate G and connected to the data signal terminal Data. The source S of the third thin-film transistor T3 is connected to the drain D of the fourth thin-film transistor T4.

[0062] The drain D of the fourth thin-film transistor T4 is connected to the gate G, and the source S of the fourth thin-film transistor T4 is connected to the corresponding first anti-static structure 400, thereby connecting to the ground terminal GND.

[0063] In this way, not only can the first antistatic structure 400 block the static charge generated on the surface of the cover glass 10, but also, for the static charge that the first antistatic structure 400 fails to block, this part of the static charge will accumulate at the data signal line in the drive circuit layer 200 during the conduction process. By setting the second antistatic structure 900, on the one hand, the thin film transistor T in the second antistatic structure 900 can consume part of the charge during the operation process. On the other hand, the second antistatic structure 900 is connected to the first antistatic structure 400, so that the remaining charge can be released again through the grounded first antistatic structure 400.

[0064] like Figure 16 As shown, Figure 16 This is a schematic diagram of another second antistatic structure provided in the embodiments of this application. In some embodiments, the second antistatic structure 900 may further include: a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, and an eighth thin-film transistor T8.

[0065] In this configuration, the drain D of the fifth thin-film transistor T5 is connected to the gate G and to the first power voltage terminal VGH, and the source S of the fifth thin-film transistor T5 is connected to the drain D of the sixth thin-film transistor T6.

[0066] The drain D of the sixth thin-film transistor T6 is connected to the gate G, and the source S of the sixth thin-film transistor T6 is connected to the data signal terminal Data.

[0067] The drain D of the seventh thin-film transistor T7 is connected to the gate G and connected to the data signal terminal Data. The source S of the seventh thin-film transistor T7 is connected to the drain D of the eighth thin-film transistor T8.

[0068] The drain D of the eighth thin-film transistor T8 is connected to the gate G, and the source S of the eighth thin-film transistor T8 is connected to the second power voltage terminal VGL.

[0069] In this way, for the static charge accumulated at the data signal lines in the driving circuit layer 200, on the one hand, the number of thin film transistors T in the second antistatic structure 900 increases, which can consume more charge during operation; on the other hand, the electrostatic discharge path can be increased, thereby accelerating the electrostatic discharge.

[0070] In this configuration, the first anti-static structure 400 in the display panel 000 can be connected to the first power voltage terminal VGH instead of the ground terminal in the driver circuit board PCB. In this way, the drain D of the fifth thin-film transistor T5 can be electrically connected to the first power voltage terminal VGH via the first anti-static structure 400. Similarly, the first anti-static structure 400 in the display panel 000 can also be connected to the second power voltage terminal VGL. In this way, the source S of the eighth thin-film transistor T8 can be electrically connected to the second power voltage terminal VGL via the first anti-static structure 400.

[0071] It should be noted that each thin-film transistor T in the second antistatic structure 900 can be an N-type transistor or a P-type transistor.

[0072] For example, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4 are P-type transistors.

[0073] When positive charge accumulates at the data signal terminal Data, the voltage at the data signal terminal Data serves as the source voltage of the second thin-film transistor T2. When it is greater than or equal to the absolute value of the threshold voltages of the second thin-film transistor T2 and the first thin-film transistor T1, the second thin-film transistor T2 and the first thin-film transistor T1 are turned on, discharging the positive charge to the ground (that is, conducting the positive charge to the grounded first anti-static structure 400 and completing the electrostatic discharge).

[0074] When negative charge accumulates at the data signal terminal Data, the voltage at the data signal terminal Data serves as the gate voltage of the third thin-film transistor T3. When it is less than or equal to the threshold voltages of the third thin-film transistor T3 and the fourth thin-film transistor T4, the third thin-film transistor T3 and the fourth thin-film transistor T4 are turned on, discharging the negative charge to the ground.

[0075] Alternatively, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4 are N-type transistors.

[0076] When negative charge accumulates at the data signal terminal Data, the voltage at the data signal terminal Data serves as the source voltage of the second thin-film transistor T2. When its absolute value is greater than or equal to the threshold voltages of the second thin-film transistor T2 and the first thin-film transistor T1, the second thin-film transistor T2 and the first thin-film transistor T1 are turned on, discharging the negative charge to the ground.

[0077] When positive charge accumulates at the data signal terminal Data, the voltage at the data signal terminal Data serves as the gate voltage of the third thin-film transistor T3. When it is greater than or equal to the threshold voltages of the third thin-film transistor T3 and the fourth thin-film transistor T4, the third thin-film transistor T3 and the fourth thin-film transistor T4 are turned on, discharging the positive charge to the ground.

[0078] The working principles of the fifth thin-film transistor T5 to the eighth thin-film transistor T8 are similar to those described above, and will not be repeated here.

[0079] In this way, by setting multiple thin-film transistors T, both positive and negative charges generated by static electricity can be dissipated.

[0080] like Figure 13 As shown, the second antistatic structure 900 may be located in the corner region between the second partition Q2 and the first partition Q1, and / or, the second antistatic structure 900 may be located in the corner region between the third partition Q3 and the first partition Q1.

[0081] The thin-film transistor in the second antistatic structure 900 can be disposed on the same layer as the transistor in the pixel driving circuit P1 and made of the same material.

[0082] like Figure 3 and Figure 17 As shown, Figure 17 This is a partial structural diagram of another display panel provided in the embodiments of this application. The encapsulation layer 300 in the display panel 000 may include: a first inorganic encapsulation layer 301, and the inorganic film layer of the driving circuit layer 200 closest to the encapsulation layer 300 is the target inorganic insulating layer M.

[0083] In the non-display area 002, the target inorganic insulating layer M has a first through groove V1, the first inorganic encapsulation layer 301 is in direct contact with the target inorganic insulating layer M, and there is a portion of the first inorganic encapsulation layer 301 located in the first through groove V1. The first inorganic encapsulation layer 301 located in the first through groove V1 is in direct contact with the sidewall of the first through groove V1.

[0084] This allows for the formation of an interlocking structure between the first inorganic encapsulation layer 301 and the target inorganic insulating layer M, increasing the contact area between them. This enhances the bonding force between the two layers, reduces the probability of layer separation, ensures the encapsulation effect of the encapsulation layer 300, and ultimately improves the reliability of the display panel 000. Furthermore, it eliminates the need for additional film layer processes, thus saving costs.

[0085] For example, the target inorganic insulating layer M can be an interlayer dielectric layer 205, which can be an inorganic film layer made of silicon nitride or silicon oxynitride material.

[0086] like Figure 18 and Figure 19 As shown, Figure 18 This is a partial structural diagram of another display panel provided in an embodiment of this application. Figure 19 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application. The target inorganic insulating layer M has a plurality of first through-holes V1 arranged in a direction parallel to the substrate 100. The portion of the target inorganic insulating layer M located between two adjacent first through-holes V1 is an inorganic insulating pillar N. The driving circuit layer 200 in the display panel 000 may further include: A first metal pillar Z1 is located on the side of the inorganic insulating pillar N facing away from the substrate 100. The first metal pillar Z1 protrudes from both sides of the inorganic insulating pillar N in the width direction. The first inorganic encapsulation layer 301 is in direct contact with the side of the first metal pillar Z1 facing away from the substrate 100, and is also in direct contact with the outer surface of the first metal pillar Z1 and the side of the first metal pillar Z1 facing the substrate 100.

[0087] And / or, a second metal pillar Z2 is located on the side of the inorganic insulating pillar N facing the substrate 100, with the second metal pillar Z2 protruding from both sides of the inorganic insulating pillar N in the width direction. The first inorganic encapsulation layer 301 is in direct contact with the side of the second metal pillar Z2 away from the substrate 100, and is also in direct contact with the outer surface of the second metal pillar Z2.

[0088] This helps to further enhance the bonding force between the first inorganic encapsulation layer 301 and the target inorganic insulating layer M, reduce the probability of film separation, ensure the encapsulation effect of the encapsulation layer 300, and thus improve the reliability of the display panel 000.

[0089] The first metal pillar Z1 can be disposed in the same layer and made of the same material as the transition electrode Z, that is, it is located in the second source-drain layer; the second metal pillar Z2 can be disposed in the same layer and made of the same material as the source S and drain D in the transistor T, that is, it is located in the first source-drain layer. In this way, no additional film layer process is required, which helps to save costs.

[0090] Alternatively, the first metal pillar Z1 and / or the second metal pillar Z2 can also be made of other metal materials with a certain resistance, such as molybdenum.

[0091] In this embodiment, the multiple first through-slots V1 of the target inorganic insulating layer M can be located in the first partition Q1 and the second partition Q2 of the non-display area 002, so as to avoid affecting the signal traces located in the third partition Q3 of the driving circuit layer 200 and improve the yield of the display panel 000.

[0092] like Figure 20 As shown, Figure 20This is a partial structural diagram of another display panel provided in an embodiment of this application. The display panel 000 may further include: a blocking dam 1000, located within the non-display area 002 and distributed around the display area 001. The number of blocking dams 1000 can be one or more. For example, the number of blocking dams 1000 can be two, namely a first blocking dam 1001 and a second blocking dam 1002, with the second blocking dam 1002 located on the side of the first blocking dam 1001 away from the display area 001.

[0093] The encapsulation layer 300 in the display panel 000 may further include: an organic encapsulation layer 302 and a second inorganic encapsulation layer 303 located on the side of the first inorganic encapsulation layer 301 away from the substrate 100. The organic encapsulation layer 302 is located in the area enclosed by the first barrier dam 1001. On the side of the first barrier dam 1001 away from the display area 001, the second inorganic encapsulation layer 303 is in direct contact with the first inorganic encapsulation layer 301 to ensure that the first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 can wrap the organic encapsulation layer 302.

[0094] In a direction parallel to the substrate 100, the first through groove V1 may be located on the side of the first barrier dam 1001 facing the display area 001, and / or the first through groove V1 may be located on the side of the second barrier dam 1002 away from the display area 001, and / or the first through groove V1 may be located between two adjacent barrier dams 1000.

[0095] It should be noted that, in some embodiments where the display panel 000 includes a second antistatic structure 900 and the target inorganic insulating layer M has a first through-hole V1, such as... Figure 21 As shown, Figure 21 This is a partial structural schematic diagram of another display panel provided in the embodiments of this application. In the direction parallel to the substrate 100, the first through groove V1 can be located between the second antistatic structure 900 and the display area 001, or the orthogonal projection of the first through groove V1 on the substrate 100 can overlap with the orthogonal projection of at least a portion of the thin film transistors T in the second antistatic structure 900 on the driving back plate.

[0096] Further, refer to Figure 16 and Figure 21When the driving circuit layer 200 further includes a first metal pillar Z1 and / or a second metal pillar Z2, the drain D of the first thin-film transistor T1 in the second anti-static structure 900 can be electrically connected to the corresponding first anti-static structure 400 and to the first metal pillar Z1 and / or the second metal pillar Z2, and / or, the source S of the fourth thin-film transistor T4 can be electrically connected to the corresponding first anti-static structure 400 and to the first metal pillar Z1 and / or the second metal pillar Z2, and / or, the drain D of the fifth thin-film transistor T5 can be connected to the first power voltage terminal VGH and to the first metal pillar Z1 and / or the second metal pillar Z2, and / or, the source S of the eighth thin-film transistor T8 can be connected to the second power voltage terminal VGL and to the first metal pillar Z1 and / or the second metal pillar Z2. For example, as... Figure 21 As shown, the drain D of the first thin-film transistor T1 in the second antistatic structure 900 can be electrically connected to the corresponding first antistatic structure 400 and to the second metal pillar Z2.

[0097] In this way, on the one hand, it is conducive to further release of static charge, and on the other hand, the heat generated by the second antistatic structure 900 when it is working can be conducted to the first metal pillar Z1 and / or the second metal pillar Z2. During the process of water vapor in the external environment eroding from the edge of the display panel 000 to the display area 001, the water vapor will be heated at the first metal pillar Z1 and / or the second metal pillar Z2 and will retreat back to the edge of the display panel 000, thereby reducing the probability of the sub-pixels in the display panel 000 being eroded by water vapor and improving the reliability of the display panel 000.

[0098] like Figure 21 As shown, in some embodiments, the display panel 000 may further include a glass substrate 1100 located on the side of the substrate 100 opposite to the driving circuit layer 200.

[0099] It should be noted that the display panel 000 provided in this application can be an OLED display panel, or it can be a QLED display panel that uses quantum dot light-emitting diodes (QLED) to achieve the display function, or it can be a QD-OLED display panel that uses quantum dot organic light-emitting diodes (QD-OLED) to achieve the display function. This application does not impose any limitations on this.

[0100] In summary, the display panel provided in this application includes: a substrate, multiple sub-pixels, an encapsulation layer, and a first anti-static structure. The first anti-static structure is located in at least two first and second partitions within the non-display area and is used to connect to a ground terminal in the driving circuit board via a bonding area. Thus, the first anti-static structure can block the downward conduction of static-generated charges and the lateral conduction towards the display area. Furthermore, when the first anti-static structure is conductive, the charge, after being conducted to the first anti-static structure, can be conducted along the first anti-static structure to the ground terminal, thereby completing the static discharge. Therefore, the first anti-static structure can prevent static-generated charges from causing the transistors in the gate driving circuit and pixel driving circuit to turn on, thereby preventing abnormal turn-on of the light-emitting devices, ensuring normal display of the display panel, and improving the reliability of the display panel.

[0101] This application also provides a display device 00, which includes: a power supply component and a display panel 000 electrically connected to the power supply component. The display panel 000 may include any of the display panels 000 given above. The display device 00 may be any product or component with display function, such as a mobile phone, tablet computer, television, advertising machine, display screen, digital photo frame, etc.

[0102] like Figure 12 As shown, the display device 00 may further include: a polarizer 20, an optical adhesive layer 30, and a cover glass 10 stacked on one side of the display surface of the display panel 000, and a support layer 40 located on the back side of the display panel 000, where the back side of the display panel 000 refers to the side opposite to the display surface. (Reference) Figure 4 and Figure 12 The bonding area Q31 of the display panel 000 and the driving circuit board PCB are bent to the back of the display panel 000, and the driving circuit board PCB is bonded to the support layer 40 and grounded. The display device 00 may also include a light-shielding ink layer 50 located between the optical adhesive layer 30 and the cover glass 10, distributed in the non-display area 002 and surrounding the display area 001.

[0103] This application also provides a method for manufacturing a display device 00, used to manufacture the aforementioned display device 00. The manufacturing method may include: Step S100: Forming a substrate.

[0104] Here, the substrate 100 may include a first sub-substrate 101, a first buffer layer 102, a second sub-substrate 103, and a second buffer layer 104 stacked together. When the first antistatic structure 400 is integrated inside the substrate 100, step S100 further includes forming the first antistatic structure 400.

[0105] Step S200: A driving circuit layer is formed on the side of the second buffer layer away from the first sub-substrate.

[0106] Step S300: Form multiple light-emitting devices on the side of the driving circuit layer away from the substrate.

[0107] Step S400: Form an encapsulation layer on the side of the light-emitting device away from the substrate.

[0108] Step S500: Module bonding and assembly.

[0109] Here, module bonding assembly may include: flexible circuit board (FPC) bonding, polarizer 20 bonding, support layer 40 bonding, and cover glass 10 bonding, etc.

[0110] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0111] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0112] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a non-display area, the non-display area being distributed around the display area; the display panel includes: Substrate; Multiple sub-pixels are located on one side of the substrate and are distributed at least within the display area; An encapsulation layer is located on the side of the plurality of sub-pixels that faces away from the substrate; A first antistatic structure is located within the non-display area and distributed around the display area, and the first antistatic structure is conductive; The non-display area includes: two first partitions distributed on both sides of the display area in a first direction, and a second partition and a third partition distributed on both sides of the display area in a second direction; the third partition has a bonding area inside, which is used to electrically connect with the driving circuit board; the first anti-static structure is located at least in the two first partitions and the second partition, and is used to connect to the ground terminal in the driving circuit board through the bonding area.

2. The display panel according to claim 1, characterized in that, The first antistatic structure is located on the side of the substrate facing the plurality of sub-pixels; The first antistatic structure and the conductive structure in the sub-pixel are disposed in the same layer and are made of the same material.

3. The display panel according to claim 2, characterized in that, The sub-pixel includes a pixel driving circuit and a light-emitting device, wherein the light-emitting device is located on the side of the pixel driving circuit away from the substrate, and the first electrode of the light-emitting device is electrically connected to the pixel driving circuit; the pixel driving circuit has a plurality of transistors; Wherein, the first anti-static structure is disposed in the same layer as the gate of the transistor and is made of the same material, and / or, the first anti-static structure is disposed in the same layer as the active layer of the transistor and is made of the same material, and / or, the first anti-static structure is disposed in the same layer as the source and drain of the transistor and is made of the same material, and / or, the first anti-static structure is disposed in the same layer as the first electrode in the light-emitting device and is made of the same material.

4. The display panel according to claim 2, characterized in that, The first antistatic structure includes: two first blocking and dissipation sections, one second blocking and dissipation section, and two first grounding connection sections; the two first blocking and dissipation sections are respectively located within the two first partitions, the second blocking and dissipation section is located within the second partition, and the two first grounding connection sections are both located within the third partition; the first ends of the two first blocking and dissipation sections are respectively connected to the two ends of the second blocking and dissipation section, the second ends of the two first blocking and dissipation sections are respectively connected to the first ends of the two first grounding connection sections, and the second ends of the two first grounding connection sections are both used to connect to the grounding terminal in the drive circuit board through the bonding area.

5. The display panel according to any one of claims 1-4, characterized in that, The first antistatic structure is integrated inside the substrate.

6. The display panel according to claim 5, characterized in that, For the first anti-static structure integrated inside the substrate, the first anti-static structure includes: two third blocking dissipation sections, one fourth blocking dissipation section, one fifth blocking dissipation section, and two second grounding connection sections; the two third blocking dissipation sections are respectively located within the two first partitions, the fourth blocking dissipation section is located within the second partition, and the fifth blocking dissipation section and the two second grounding connection sections are both located within the third partition; the first ends of the two third blocking dissipation sections are respectively connected to the two ends of the fourth blocking dissipation section, and the second ends of the two third blocking dissipation sections are respectively connected to the two ends of the fifth blocking dissipation section; the first ends of the two second grounding connection sections are both connected to the fifth blocking dissipation section, and the second ends of the two second grounding connection sections are both used to connect to the grounding terminal in the driving circuit board through the bonding area.

7. The display panel according to any one of claims 1-4, 6, characterized in that, The number of the first antistatic structures is multiple, and the multiple first antistatic structures are distributed sequentially in a direction away from the display area in a direction parallel to the substrate.

8. The display panel according to any one of claims 1-4, 6, characterized in that, The display panel also includes: The second anti-static structure is distributed within the non-display area and corresponds to the first anti-static structure; the second anti-static structure includes: a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, and a fourth thin-film transistor; The drain of the first thin-film transistor is connected to the gate and to the corresponding first anti-static structure, and the source of the first thin-film transistor is connected to the drain of the second thin-film transistor. The drain of the second thin-film transistor is connected to the gate, and the source of the second thin-film transistor is connected to the data signal terminal; The drain of the third thin-film transistor is connected to the gate and to the data signal terminal, and the source of the third thin-film transistor is connected to the drain of the fourth thin-film transistor. The drain of the fourth thin-film transistor is connected to the gate, and the source of the fourth thin-film transistor is connected to the corresponding first anti-static structure.

9. The display panel according to claim 8, characterized in that, The second antistatic structure is located in the corner region between the second partition and the first partition, and / or the second antistatic structure is located in the corner region between the third partition and the first partition.

10. The display panel according to any one of claims 1-4, 6, and 9, characterized in that, The encapsulation layer includes: a first inorganic encapsulation layer; the display panel further includes: a driving circuit layer, wherein the pixel driving circuit in the sub-pixel is located within the driving circuit layer; the inorganic film layer closest to the encapsulation layer in the driving circuit layer is a target inorganic insulating layer. In the non-display area, the target inorganic insulating layer has a first through groove, the first inorganic encapsulation layer is in direct contact with the target inorganic insulating layer, and there is a portion of the first inorganic encapsulation layer located in the first through groove, the first inorganic encapsulation layer located in the first through groove is in direct contact with the groove sidewall of the first through groove.

11. The display panel according to claim 10, characterized in that, The target inorganic insulating layer has a plurality of first through-grooves arranged in a direction parallel to the substrate; The portion of the target inorganic insulating layer located between two adjacent first through slots is an inorganic insulating pillar; the driving circuit layer further includes: A first metal pillar is located on the side of the inorganic insulating pillar away from the substrate, and the first metal pillar protrudes from both sides of the inorganic insulating pillar in the width direction; the first inorganic encapsulation layer is in direct contact with the side of the first metal pillar away from the substrate, and is also in direct contact with the outer surface of the first metal pillar and the side of the first metal pillar facing the substrate. And / or, a second metal pillar located on the side of the inorganic insulating pillar facing the substrate, the second metal pillar protruding from both sides of the inorganic insulating pillar in the width direction; the first inorganic encapsulation layer is in direct contact with the side of the second metal pillar away from the substrate, and is in direct contact with the outer surface of the second metal pillar.

12. A display device, characterized in that, include: A power supply component, and a display panel electrically connected to the power supply component, wherein the display panel is the display panel according to any one of claims 1-11.

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