Wafer stack structure, manufacturing method thereof, and electronic device
Patent Information
- Application Number
- CN202510371795.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2026-10-02
AI Technical Summary
然而，后续的硅衬底减薄工艺受到切割宽度的影响，晶圆的边缘可能出现厚度急剧变化、甚至掉边的情况，导致芯片中某些膜层的图形异常，影响芯片的可靠性和电学性能
[0017]由于在制作工艺过程中，第一晶圆和第二晶圆的边缘容易发生破碎(peeling)、甚至掉边等现象，涉及的金属层的层数越多、洗边宽度越宽，第一晶圆和第二晶圆边缘的破碎、掉边现象越严重。将第一晶圆和第二晶圆进行绑定时，在键合过程中第一晶圆和第二晶圆边缘可能会出现弱连接、甚至无法连接等异常。为了使第一晶圆和第二晶圆的边缘更加平整，提高芯片的良率和可靠性，可以采用切割(trim)工艺对第一晶圆和第二晶圆的边缘进行切割。
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Figure CN122872178A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a wafer stacking structure, its fabrication method, and electronic equipment. Background Technology
[0002] With the continuous evolution of chip technology, it is gradually moving towards multi-dimensional stacking. Multi-dimensional stacking can achieve high-speed, high-density interconnection of chips, and has received widespread attention and application in recent years. However, the original thickness of silicon substrates is difficult to meet the performance requirements of multi-dimensional stacked chips. Excessively thick silicon substrates will affect the interconnection density, heat dissipation efficiency, and reliability of the chips. Therefore, silicon substrate thinning has gradually become one of the key steps in chip manufacturing.
[0003] During the manufacturing process, wafer edges are prone to peeling and even chipping. The more metal layers involved and the wider the edge washing width, the more severe the peeling and chipping. When bonding multiple wafers, weak connections or even failures to connect may occur at the wafer edges during bonding. Furthermore, as the number of wafers stacked increases, the peeling and chipping become increasingly severe. To make the wafer edges smoother and improve chip yield and reliability, a trimming process is used to trim the wafer edges. However, subsequent silicon substrate thinning processes are affected by the trimming width, and the wafer edges may experience drastic thickness changes or even chipping, leading to abnormal patterns in certain film layers within the chip and affecting chip reliability and electrical performance. Summary of the Invention
[0004] This application provides a wafer stacking structure, its fabrication method, and an electronic device to improve the reliability and electrical performance of chips.
[0005] In a first aspect, embodiments of this application provide a wafer stacking structure, which may include a first wafer, a second wafer, and a dielectric layer. The first wafer and the second wafer are stacked, with the dielectric layer covering at least a portion of the side surface of the second wafer. The surface of the dielectric layer away from the first wafer in a first direction is flush with the surface of the second wafer away from the first wafer. The first direction is the thickness direction of the wafer stacking structure. Due to process errors and other reasons, in this embodiment, the flush alignment of the dielectric layer and the surface of the second wafer away from the first wafer in the first direction means that they are substantially flush within a certain error range. The fabricated wafer stacking structure has a structure with multiple chips. By dividing the wafer stacking structure, multiple independent chip stacking structures can be obtained.
[0006] In the technical solution provided in this application embodiment, during the fabrication of the wafer stacking structure, a dielectric layer is deposited at the edge of the wafer to compensate for edge breakage and chipping. This allows for effective control of the total thickness variation during subsequent silicon substrate thinning processes by adjusting relevant parameters. Consequently, the risk of defocusing during photolithography is reduced, and deviations in critical dimensions at the center and edge positions are effectively minimized. This improves the electrical performance and reliability of the wafer stacking structure, and consequently, enhances the electrical performance and reliability of the chip stacking structure obtained through dicing.
[0007] During the fabrication process, a dielectric layer is deposited at the edge of the second wafer, covering the surface edge of the second wafer and extending to its side. The dielectric layer may completely cover the side of the second wafer, or it may cover only a portion of its side. During the thinning process, as the silicon substrate of the second wafer is thinned, the dielectric layer at the surface edge of the second wafer is also thinned. Therefore, in the resulting wafer stack structure, the dielectric layer is flush with the surface of the second wafer on the side furthest from the first wafer in the first direction, resulting in better flatness of the wafer stack structure.
[0008] In one possible implementation, the first and second wafers may include structures such as a silicon substrate and a metal layer. The silicon substrate serves to support the metal layer, and by setting circuit structures in the metal layer, the chip can achieve corresponding functions. The wafer stacking structure in this embodiment may also include a bonding layer and an insulating layer. Adjacent wafers can be bonded together through the bonding layer and the insulating layer. The bonding layer may include conductive materials such as metal, and serves to electrically connect the two adjacent wafers. The insulating layer serves to insulate, support, and adhere. Of course, adjacent wafers can also be connected in other ways, which are not limited here.
[0009] In one possible implementation, the projection of the dielectric layer in the first direction can surround the projection of the second wafer. During the fabrication process, a dielectric layer can be deposited around the edge of the second wafer, thus providing better compensation for edge breakage and chipping.
[0010] In some embodiments of this application, during the deposition of the dielectric layer, the dielectric layer may also extend to the side surface of the first wafer, thus covering at least a portion of the side surface of the first wafer. Alternatively, the dielectric layer may completely cover the side surface of the first wafer.
[0011] In the manufacturing process, to make the wafer edges smoother and improve chip yield and reliability, a trimming process can be used to cut the wafer edges. During the trimming process, the wafer is typically trimmed downwards from the surface of the second wafer to at least a portion of the first wafer. This is because the fabrication of a wafer stack typically involves multiple different processes. To ensure the wafer radius meets the requirements of each process device, the trimming process can cut from the surface of the wafer to its interior, without cutting to the bottom, thus maintaining the overall wafer radius. Consequently, a recess is formed on the side of the resulting wafer stack. Specifically, the first wafer may include a first portion and a second portion distributed along a first direction, with the second portion located between the first portion and the second wafer. The edge of the second portion is flush with the edge of the second wafer, while the edge of the first portion protrudes beyond the edge of the second portion, forming a recess on the side of the wafer stack. It is understood that, due to process errors and other factors, in this embodiment, "the edge of the second portion is flush with the edge of the second wafer" means that the edge of the second portion is substantially flush with the edge of the second wafer within a certain error range.
[0012] In a specific configuration, the dielectric layer can be positioned in a recessed area on the side of the wafer stacking structure, meaning the dielectric layer can cover a portion of the second wafer and a portion of the second portion. This allows for a more stable position of the dielectric layer. Since the dielectric layer is generally thin—for example, less than 1 mm—the surface of the dielectric layer on the side furthest from the second wafer in the second direction generally will not extend beyond the side of the first portion, and the second direction is perpendicular to the first direction.
[0013] In one possible implementation, the dielectric layer may include silicon dioxide (SiO2) or silicon nitride (SiN). During the silicon substrate thinning process, the total thickness change of the wafer can be controlled by adjusting the etching selectivity ratio between the silicon substrate and the dielectric layer. Of course, in some cases, the dielectric layer may also include other insulating dielectric materials, which is not limited here.
[0014] In this embodiment, the wafer stacking structure includes a first wafer and a second wafer as an example. In specific implementation, the wafer stacking structure may also include more wafers, and a dielectric layer may be provided on the side of other wafers to compensate for problems such as breakage and edge chipping at the wafer edges.
[0015] Secondly, embodiments of this application also provide a method for fabricating a wafer stacked structure. The method for fabricating a wafer stacked structure provided in embodiments of this application may include:
[0016] Step 1: Provide a first wafer and a second wafer in a stacked configuration. The first wafer and the second wafer can be bonded together through a bonding layer and an insulating layer. The bonding layer may include conductive materials such as metals, and it serves to electrically connect components in the first wafer and the second wafer. The insulating layer serves to provide insulation, support, and adhesion. Of course, the first wafer and the second wafer can also be connected in other ways, which are not limited here.
[0017] During the manufacturing process, the edges of the first and second wafers are prone to peeling and even chipping. The more metal layers involved and the wider the edge washing width, the more severe the peeling and chipping issues become. When bonding the first and second wafers, weak connections or even failures to connect may occur at their edges during the bonding process. To make the edges of the first and second wafers smoother and improve chip yield and reliability, a trimming process can be used to trim the edges of the first and second wafers.
[0018] In the fabrication of wafer stacking structures, multiple different processes are typically involved. To ensure that the wafer radius meets the requirements of each process device, the dicing process can cut from the surface of the second wafer to the interior of the first wafer, without cutting to the bottom of the first wafer, thus maintaining the overall wafer radius. This creates a recess at the edge of the first and second wafers.
[0019] Step 2: Deposit a dielectric layer at the edge of the second wafer, such that the dielectric layer covers the surface edge of the second wafer away from the first wafer and at least a portion of the side surface of the second wafer. Exemplarily, the dielectric layer can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other methods, and the dielectric layer can be made of materials such as silicon dioxide (SiO2) or silicon nitride (SiN).
[0020] In one possible implementation, the dielectric layer can be configured to surround the edge of the second wafer. In practice, the dielectric layer can be formed within the recess formed by the edges of the first and second wafers; that is, the dielectric layer can cover the side of the second wafer and a portion of the side of the first wafer, thus ensuring a relatively stable position of the dielectric layer. Since the dielectric layer is generally thin—for example, less than 1 mm—the surface of the dielectric layer on the side furthest from the second wafer in the second direction generally will not extend beyond the side of the lower half of the first wafer.
[0021] Step 3: Thin the surface of the second wafer away from the first wafer, so that the surface of the dielectric layer away from the first wafer in a first direction is flush with the surface of the second wafer away from the first wafer; wherein, the first direction is the direction from the first wafer to the second wafer. The first and second wafers may include a silicon substrate, and step 3 actually involves thinning the silicon substrate in the second wafer. During the thinning process, the total thickness change of the second wafer can be controlled by adjusting the etching selectivity ratio between the silicon substrate and the dielectric layer. In this embodiment, the dielectric layer is set as a silicon-containing compound, which facilitates the adjustment of the etching selectivity ratio between the silicon substrate and the dielectric layer.
[0022] In one possible implementation, chemical mechanical polishing (CMP) can be used to polish the surface of the second wafer furthest from the first wafer. The selectivity ratio of the silicon substrate to the dielectric layer can be adjusted using the polishing slurry in CMP, and the total thickness change of the second wafer can be controlled by combining this with pressure adjustment parameters in CMP. In another possible implementation, wet etching can be used to etch the surface of the second wafer furthest from the first wafer. The selectivity ratio of the silicon substrate to the dielectric layer can be adjusted using chemical reagents in wet etching and by adjusting the rate at which the chemical reagents are sprayed from the nozzle. In practical applications, either CMP or wet etching can be used to thin the second wafer, or a combination of both can be used, depending on the specific requirements.
[0023] After completing the fabrication processes for interconnect layers, redistribution layers, and other films, the wafer stack structure is divided to obtain multiple chip stack structures. The first chip in the chip stack structure is obtained by cutting the first wafer, and the second chip is obtained by cutting the second wafer.
[0024] In the fabrication method provided in this application embodiment, a dielectric layer is deposited at the edge of the second wafer to compensate for edge breakage and chipping, thereby reducing the etching impact on the edge of the second wafer during subsequent thinning processes. Furthermore, during the subsequent thinning process, the total thickness variation can be effectively controlled by adjusting relevant parameters, thereby reducing the risk of defocusing during photolithography. This effectively reduces the deviation of critical dimensions at the center and edge positions, improving the electrical performance and reliability of the wafer stacking structure, and consequently, enhancing the electrical performance and reliability of the chip stacking structure obtained through dicing.
[0025] In some embodiments of this application, before cutting the edges of the first and second wafers using a dicing process in step one above, the fabrication method further includes: using a mechanical grinding process to grind the surface of the second wafer away from the first wafer. This allows for a significant reduction in the thickness of the silicon substrate in the second wafer.
[0026] In some other embodiments of this application, after step one and before step two, the fabrication method may further include: using a chemical mechanical polishing process to polish the surface of the second wafer away from the first wafer. In this way, by thinning the second wafer through multiple thinning processes, the total thickness variation of the wafer can be adjusted in a timely manner, resulting in better electrical performance and reliability of the fabricated wafer.
[0027] In this embodiment, single-sided thinning of a wafer is taken as an example, that is, thinning is performed only on the surface of the second wafer away from the first wafer. In specific implementation, the surface of the first wafer away from the second wafer can also be thinned. The specific implementation method can be referred to the above description, and the repeated parts will not be described again.
[0028] In the embodiments of this application, the fabrication process of the first wafer and the second wafer is used as an example for explanation. In specific implementation, when more wafers need to be stacked, the implementation method of this application can be referred to. Repeated parts will not be described again.
[0029] Thirdly, embodiments of this application also provide an electronic device, which may include: a chip stacking structure and a circuit board, wherein the chip stacking structure is electrically connected to the circuit board. The chip stacking structure may be obtained by dividing any of the wafer stacking structures described in the first aspect above; or, the chip stacking structure may be obtained by dividing a wafer stacking structure fabricated by any of the manufacturing methods described in the second aspect above. Attached Figure Description
[0030] Figure 1 This is a schematic diagram illustrating the thickness change of a wafer during the silicon substrate thinning process.
[0031] Figure 2 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;
[0032] Figure 3 This is a top view of the wafer stacking structure provided in an embodiment of this application;
[0033] Figure 4 for Figure 3 A schematic diagram of the cross-section at the dashed line BB';
[0034] Figure 5 for Figure 3 A schematic diagram of another cross-section at the dashed line BB';
[0035] Figure 6 This is a schematic diagram of the chip stacking structure in an embodiment of this application;
[0036] Figure 7 for Figure 3 A schematic diagram of another cross-section at the dashed line BB';
[0037] Figure 8 A flowchart illustrating the fabrication method of the wafer stacking structure provided in this application embodiment;
[0038] Figure 9 A schematic diagram of the structure corresponding to each step in the manufacturing method provided in the embodiments of this application;
[0039] Figure 10 This is another structural schematic diagram corresponding to each step in the manufacturing method provided in the embodiments of this application.
[0040] Figure label:
[0041] 100 - Electronic device; 101 - Chip stacking structure; 102 - Circuit board; 103 - Wafer stacking structure; 21 - First chip; W11 - First part; W12 - Second part; 22 - Second chip; 23 - Dielectric layer; 24 - Bonding layer; 25 - Insulating layer; F1 - First direction; F2 - Second direction; W1 - First wafer; W2 - Second wafer; W3 - Third wafer. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.
[0043] It should be noted that the accompanying drawings in this application are for illustrative purposes only and do not represent actual scale. The same reference numerals in the accompanying drawings denote the same or similar structures, and therefore, repeated descriptions of them will be omitted.
[0044] The terms describing position and direction described in this application, such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," are illustrative examples based on the orientation or positional relationships shown in the accompanying drawings. They are merely for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Changes may be made as needed, and all changes are included within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0045] Multi-dimensional stacking enables high-speed, high-density interconnects between chips, and has received widespread attention and application in recent years. However, the original thickness of the silicon substrate is insufficient to meet the performance requirements of multi-dimensional stacked chips; excessively thick silicon substrates can negatively impact interconnect density, heat dissipation efficiency, and reliability. Therefore, silicon substrate thinning has gradually become a critical step in chip fabrication. Considering both cost and quality, processes such as grinding, chemical mechanical polishing (CMP), and wet etching are commonly used to thin the silicon substrate.
[0046] To improve chip manufacturing efficiency, wafers are typically used as the base material. Through multiple processes such as photolithography, etching, and bonding, a structure containing multiple chips is fabricated within the wafer. Then, the wafer is diced to obtain multiple independent stacked chip structures. The silicon substrate is the silicon material layer within the wafer that forms the basis for chip construction; it provides structural support and the foundation for the chip's electrical characteristics.
[0047] During the manufacturing process, wafer edges are prone to peeling and even chipping. The more metal layers involved and the wider the edge washing width, the more severe the peeling and chipping. When bonding multiple wafers, weak connections or even failures to connect may occur at the wafer edges during bonding. Furthermore, as the number of wafers stacked increases, the peeling and chipping become increasingly severe. To make the wafer edges smoother and improve chip yield and reliability, a trimming process is required to trim the wafer edges. However, during subsequent silicon substrate thinning processes, the trimming width can affect the wafer edges, causing abrupt changes in thickness, chipping, or even preventing wafer fabrication. For example, during silicon substrate thinning using chemical mechanical polishing, the pressure control capability in the edge region is affected by the trimming width, making the wafer edges, especially areas beyond 145mm, highly susceptible to chipping, or exhibiting abrupt changes in local thickness (THK) at region transitions. Figure 1 This is a schematic diagram illustrating the thickness change of a wafer during the silicon substrate thinning process, as shown below. Figure 1 As shown, the horizontal axis represents the radial position along the wafer, and the vertical axis represents the wafer thickness. Figure 1 Curve L1 represents the wafer thickness at different locations after mechanical grinding, curve L2 represents the wafer thickness at different locations after chemical mechanical polishing, and curve L3 represents the wafer thickness at different locations after wet etching. Taking the sequential thinning of a silicon substrate through mechanical grinding, chemical mechanical polishing, and wet etching as an example, from... Figure 1 It is evident that the thickness at the wafer edge changes drastically after chemical mechanical polishing (CMP) and wet etching. In subsequent photolithography processes, leveling operations cannot fully compensate for the broken and chipped areas at the wafer edge, causing defocusing during patterning and resulting in abnormal patterns in certain film layers within the chip, affecting its reliability and electrical performance. Therefore, controlling the total thickness variation (TTV) during silicon thinning is crucial.
[0048] Based on this, embodiments of this application provide a wafer stacking structure, its fabrication method, and an electronic device. The technical solution of this application, by improving the structure and fabrication method of the wafer stacking structure, can effectively control the total thickness change during the silicon substrate thinning process, reducing the risk of defocusing during photolithography. This effectively reduces the deviation of the critical dimension (CD) at the center and edge positions, improving the electrical performance and reliability of the wafer stacking structure. Furthermore, it can improve the electrical performance and reliability of the chip stacking structure obtained after dicing. The chip stacking structure in the embodiments of this application can be various types of chips, such as artificial intelligence (AI) chips and high bandwidth memory (HBM) chips. The chip stacking structure in the embodiments of this application can be applied to various types of electronic devices, such as mobile phones, tablets, laptops, smart wearable devices, and other terminal devices, or smart TVs, smart door locks, smart home appliances, and other electronic devices.
[0049] Figure 2 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Figure 2 The left-hand side is a top view of the electronic device. Figure 2 The right side of the image shows a top view of the electronic device, with a cross-sectional view at the dashed line AA'. (See image below.) Figure 2 As shown, the electronic device 100 provided in this application embodiment may include: a chip stacking structure 101 and a circuit board 102, wherein the chip stacking structure 101 and the circuit board 102 are electrically connected. Figure 2 The example shown is a mobile phone. When the electronic device 100 is another device, the position, shape, and size of the chip stacking structure 101 and the circuit board 102 in the electronic device 100 can be reasonably set according to actual needs.
[0050] Figure 3 This is a top view of the wafer stacking structure provided in an embodiment of this application. Figure 4 for Figure 3 A schematic diagram of the cross-section at the dashed line BB', as shown below. Figure 3 and Figure 4 As shown, the wafer stacking structure 103 provided in this embodiment may include: a first wafer W1, a second wafer W2, and a dielectric layer 23. The first wafer W1 and the second wafer W2 are stacked, and the dielectric layer 23 covers at least a portion of the side surface of the second wafer W2. The surface of the dielectric layer 23 on the side away from the first wafer W1 in the first direction F1 (e.g., Figure 4 As indicated by the middle arrow S1, the surface of the second wafer W2 on the side away from the first wafer W1 is flush with the surface of the second wafer W2. Here, the first direction F1 is the thickness direction of the wafer stacking structure 103. Due to process errors and other reasons, in this embodiment, the flush alignment of the dielectric layer 23 and the surface of the second wafer W2 on the side away from the first wafer W1 in the first direction F1 means that they are essentially flush within a certain error range.
[0051] In the technical solution provided in this application embodiment, during the fabrication of the wafer stacked structure 103, a dielectric layer 23 is deposited at the edge of the wafer to compensate for edge breakage and chipping. This allows for effective control of the total thickness variation during the subsequent silicon substrate thinning process by adjusting relevant parameters. Consequently, the risk of defocusing during the photolithography process is reduced, and the deviation of critical dimensions at the center and edge positions is effectively reduced. This improves the electrical performance and reliability of the wafer stacked structure 103, and further enhances the electrical performance and reliability of the chip stacked structure obtained by dicing.
[0052] During the fabrication process, a dielectric layer 23 is deposited at the edge of the wafer. The dielectric layer 23 covers the surface edge of the second wafer W2 and extends to the side surface of the second wafer W2. The dielectric layer 23 can completely cover the side surface of the second wafer W2; or, the dielectric layer 23 can cover a portion of the side surface of the second wafer W2. During the thinning process, when the silicon substrate of the second wafer W2 is thinned, the dielectric layer 23 at the surface edge of the second wafer W2 is also thinned. Therefore, in the fabricated wafer stack structure 103, the surface S1 of the dielectric layer 23 is basically flush with the surface of the second wafer W2 on the side away from the first wafer W1, which can improve the flatness of the wafer stack structure 103.
[0053] In one possible implementation, the first wafer W1 and the second wafer W2 may include structures such as a silicon substrate and a metal layer. The silicon substrate can serve to support the metal layer, and by setting circuit structures in the metal layer, the chip can realize corresponding functions. The wafer stacking structure 103 in this embodiment may also include a bonding layer 24 and an insulating layer 25, with adjacent wafers (e.g., Figure 4The first wafer W1 and the second wafer W2 in the process can be bonded together through a bonding layer 24 and an insulating layer 25. The bonding layer 24 may include conductive materials such as metal, and the bonding layer 24 can serve to electrically connect the two adjacent wafers. The insulating layer 25 can serve to insulate, support, and adhere. Of course, the two adjacent wafers can also be connected in other ways, which are not limited here.
[0054] In one possible implementation, continue to refer to Figure 3 and Figure 4 In the first direction F1, the projection of the dielectric layer 23 can surround the projection of the second wafer W2. During the fabrication process, a dielectric layer 23 can be deposited around the edge of the second wafer W2, thus providing better compensation for edge breakage and chipping.
[0055] In some embodiments of this application, during the deposition of the dielectric layer 23, the dielectric layer 23 may also extend to the side surface of the first wafer W1, thus the dielectric layer 23 may also cover at least a portion of the side surface of the first wafer W1. The dielectric layer 23 may cover a portion of the side surface of the first wafer W1; or, the dielectric layer 23 may completely cover the side surface of the first wafer W1.
[0056] In the manufacturing process, to make the wafer edges smoother and improve chip yield and reliability, a trimming process can be used to cut the wafer edges. During the trimming process, the wafer is typically trimmed downwards from the surface of the second wafer W2 to at least a portion of the first wafer W1. This is because the fabrication of the wafer stack structure 103 usually involves multiple different processes. To ensure the wafer radius meets the requirements of each process device, the trimming process can cut from the surface of the wafer to its interior, without cutting to the bottom, thus maintaining the overall wafer radius. Consequently, a recess is formed on the side of the fabricated wafer stack structure 103. Specifically, the first wafer W1 may include a first portion W11 and a second portion W12 distributed along a first direction F1, with the second portion W12 located between the first portion W11 and the second wafer W2. The edge of the second portion W12 is flush with the edge of the second wafer W2, and the edge of the first portion W11 protrudes beyond the edge of the second portion W12, thus forming a recess on the side of the wafer stack structure 103. It is understandable that, due to process errors and other reasons, in the embodiments of this application, the fact that the edge of the second part W12 is flush with the edge of the second wafer W2 means that the edge of the second part W12 is basically flush with the edge of the second wafer W2 within a certain error range.
[0057] In a specific configuration, the dielectric layer 23 can be positioned in a recessed area on the side of the wafer stacking structure 103, meaning the dielectric layer 23 can cover a portion of the second wafer W2 and a portion of the second part W12. This allows for a more stable position of the dielectric layer 23. Since the dielectric layer 23 is generally thin—for example, less than 1 mm—the surface of the dielectric layer 23 on the side furthest from the second wafer W2 in the second direction F2 (e.g., Figure 4 As indicated by the middle arrow S2, it generally does not extend beyond the side of the first part W11, and the second direction F2 is perpendicular to the first direction F1.
[0058] In one possible implementation, the dielectric layer 23 may include silicon dioxide (SiO2) or silicon nitride (SiN). During the thinning process of the silicon substrate, the total thickness change of the wafer can be controlled by adjusting the etching selectivity ratio of the silicon substrate to the dielectric layer 23. Of course, in some cases, the dielectric layer 23 may also include other insulating dielectric materials, which is not limited here.
[0059] exist Figure 4 In the wafer stacking structure shown, the edges of dielectric layer 23 are relatively flat. In other cases, such as... Figure 5 As shown, Figure 5 for Figure 3 Another cross-sectional view at the dashed line BB' shows that in the actual process, after the dielectric layer 23 is formed, after multiple steps such as silicon substrate thinning, photolithography, etching, and cleaning, the dielectric layer 23 may experience a certain degree of wear. This wear may occur within the dielectric layer 23. Figure 5 The pits, holes, etc. shown.
[0060] Figure 6 This is a schematic diagram of the chip stacking structure in an embodiment of this application, as shown below. Figure 6 As shown, using wafers as the base material, after multiple processes such as photolithography, etching, and bonding, a wafer stack structure with multiple chips is obtained. Then, by dividing the wafer stack structure, multiple independent chip stack structures 101 can be obtained.
[0061] In this embodiment, the wafer stacking structure includes a first wafer and a second wafer as an example. In specific implementation, the wafer stacking structure may also include more wafers, and a dielectric layer may be provided on the side of other wafers to compensate for problems such as breakage and edge chipping at the wafer edges. Figure 7 for Figure 3 Another cross-sectional diagram at the dashed line BB' is shown below. Figure 7As shown, the wafer stacking structure 103 provided in this embodiment may further include a third wafer W3 located between the first wafer W1 and the second wafer W2, and the dielectric layer 23 may further cover at least a portion of the side surface of the third wafer W3. During the fabrication process, the third wafer W3 can be bonded to the first wafer W1 firstly, and the dielectric layer 23 can be deposited at the surface edge of the third wafer W3 to thin the surface of the third wafer W3 away from the first wafer W1. Then, the second wafer W2 is bonded to the third wafer W3, and the dielectric layer 23 is deposited at the surface edge of the second wafer W2 to thin the surface of the second wafer W2 away from the first wafer W1, resulting in... Figure 7 The structure is shown. In this embodiment, the first wafer W1 can be the bottom wafer in the wafer stacking structure 103, and the second wafer W2 can be the top wafer in the wafer stacking structure 103. In specific configurations, more wafers can be placed between the first wafer W1 and the second wafer W2. Specific implementations can be found in the description of this embodiment, and repetitions will not be repeated. Of course, in some cases, more wafers can be placed below the first wafer W1 or above the second wafer W2; this is not limited here.
[0062] Based on the same technical concept, this application also provides a method for fabricating a wafer stacking structure. Figure 8 This is a flowchart illustrating the fabrication method of the wafer stacking structure provided in the embodiments of this application. Figure 9 The following are schematic diagrams illustrating the structural steps corresponding to each step in the manufacturing method provided in the embodiments of this application: Figure 8 and Figure 9 As shown in the embodiments of this application, the method for fabricating a wafer stacked structure may include:
[0063] S301, reference Figure 9 In (1), a first wafer W1 and a second wafer W2 are provided in a stacked configuration. In this embodiment, the second wafer W2 is shown above the first wafer W1. The first wafer W1 and the second wafer W2 can be bonded together through a bonding layer 24 and an insulating layer 25. The bonding layer 24 may include conductive materials such as metal, and the bonding layer 24 can electrically connect the components in the first wafer W1 and the second wafer W2. The insulating layer 25 can provide insulation, support, and adhesion. Of course, the first wafer W1 and the second wafer W2 can also be connected in other ways, which are not limited here.
[0064] During the fabrication of the various film layers in the first wafer W1 and the second wafer W2, the edges of the first wafer W1 and the second wafer W2 are prone to peeling or even chipping. The more metal layers involved and the wider the edge washing width, the more severe the peeling and chipping phenomena become. When bonding the first wafer W1 and the second wafer W2, weak connections or even failure to connect may occur at the edges during the bonding process. To make the edges of the first wafer W1 and the second wafer W2 smoother and improve the chip yield and reliability, a trimming process can be used to trim the edges of the first wafer W1 and the second wafer W2 to obtain... Figure 9 The structure shown in (2) is as follows. For example, the cutting width of the cutting process can be around 2mm or 3mm. The cutting width can be reasonably set according to the specific dimensions of the first wafer W1 and the second wafer W2. There is no limitation here.
[0065] In the fabrication of wafer stacking structures, multiple different processes are typically involved. To ensure the wafer radius meets the requirements of each process device, during the dicing process, the wafer can be cut from the surface of the second wafer W2 to the interior of the first wafer W1, without cutting to the bottom of the first wafer W1, thus maintaining the overall wafer radius. This creates a recess (such as...) at the edges of the first wafer W1 and the second wafer W2. Figure 9 (As indicated by arrow Q in the image).
[0066] S302, reference Figure 9 In step (3), a dielectric layer 23 is deposited at the edge of the second wafer W2, such that the dielectric layer 23 covers the surface edge of the second wafer W2 away from the first wafer W1 and covers at least a portion of the side surface of the second wafer W2. Exemplarily, the dielectric layer 23 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other methods, and the dielectric layer 23 can be made of materials such as silicon dioxide (SiO2) or silicon nitride (SiN).
[0067] In one possible implementation, the dielectric layer 23 can be configured to surround the edge of the second wafer W2. In a specific implementation, the dielectric layer 23 can be formed within the recess formed by the edges of the first wafer W1 and the second wafer W2, meaning the dielectric layer 23 can cover the side surface of the second wafer W2 and the upper half of the side surface of the first wafer W1. This makes the position of the dielectric layer 23 relatively stable. Since the thickness of the dielectric layer 23 is generally thin—for example, less than 1 mm—the surface of the dielectric layer 23 on the side away from the second wafer W2 in the second direction F2 generally will not extend beyond the lower half of the side surface of the first wafer W1. The second direction F2 is perpendicular to the first direction F1.
[0068] S303, reference Figure 9 In step (4), the surface of the second wafer W2 away from the first wafer W1 is thinned so that the surface of the dielectric layer 23 away from the first wafer W1 in the first direction F1 is flush with the surface of the second wafer W2 away from the first wafer W1; wherein, the first direction F1 is the direction from the first wafer W1 to the second wafer W2. The first wafer W1 and the second wafer W2 may include a silicon substrate. Step S303 actually involves thinning the silicon substrate in the second wafer W2, and during the thinning process of the silicon substrate of the second wafer W2, the dielectric layer 23 at the edge of the surface of the second wafer W2 is also thinned. During the thinning process, the total thickness change of the second wafer W2 can be controlled by adjusting the etching selectivity ratio of the silicon substrate and the dielectric layer 23.
[0069] In one possible implementation, a chemical mechanical polishing (CMP) process can be used to polish the surface of the second wafer W2 away from the first wafer W1. The selectivity ratio of the silicon substrate to the dielectric layer 23 can be adjusted using the polishing slurry in the CMP process, and the total thickness change of the second wafer W2 can be controlled by combining this with pressure adjustment parameters in the CMP process. In another possible implementation, a wet etching process can be used to etch the surface of the second wafer W2 away from the first wafer. The selectivity ratio of the silicon substrate to the dielectric layer 23 can be adjusted using the chemical reagents in the wet etching process, and the total thickness change of the second wafer W2 can be controlled by combining this with adjusting the rate at which the chemical reagents are sprayed from the nozzle. In practical applications, either chemical mechanical polishing (CMP) or wet etching can be used to thin the second wafer W2; alternatively, a combination of CMP and wet etching can be used. CMP can be performed first, followed by wet etching, or vice versa. In specific implementation, the thinning process and its order can be chosen appropriately based on actual needs; no further restrictions are imposed here.
[0070] After completing the fabrication processes for interconnect layers, redistribution layers, and other films, the wafer stack structure is divided to obtain multiple independent chip stack structures. The resulting chip stack structures can be arranged as follows: Figure 6 As shown, the first chip 21 in the chip stack structure 101 is cut from the first wafer W1, and the second chip 22 is cut from the second wafer W2.
[0071] In the fabrication method provided in this application embodiment, a dielectric layer 23 is deposited at the edge of the second wafer W2 to compensate for edge breakage and chipping, thereby reducing the etching impact on the edge of the second wafer W2 during subsequent thinning processes. Furthermore, during the subsequent thinning process, the total thickness variation can be effectively controlled by adjusting relevant parameters, thereby reducing the risk of defocusing during photolithography. This effectively reduces the deviation of critical dimensions at the center and edge positions, improving the electrical performance and reliability of the wafer stacking structure, and consequently, enhancing the electrical performance and reliability of the chip stacking structure obtained through dicing.
[0072] In some embodiments of this application, reference continues to be made to... Figure 8 and Figure 9 In step S301 above, before cutting the edges of the first wafer and the second wafer using a cutting process, the fabrication method further includes: using a mechanical grinding process to grind the surface of the second wafer W2 away from the first wafer W1. This allows for a significant reduction in the thickness of the silicon substrate in the second wafer W2.
[0073] Figure 10 This is another structural schematic diagram corresponding to each step in the manufacturing method provided in the embodiments of this application, and... Figure 9 The difference in the steps shown is that, in Figure 10 In the steps shown, the edges of the first wafer W1 and the second wafer W2 are cut to obtain... Figure 10 After the structure shown in (2) above, refer to Figure 10 In (3), before depositing the dielectric layer, the surface of the second wafer W2 away from the first wafer W1 can be thinned. For example, a chemical mechanical polishing process can be used to polish the surface of the second wafer W2 away from the first wafer W1. Then, refer to... Figure 10 In step (4), a dielectric layer 23 is deposited at the edge of the thinned second wafer W2; refer to Figure 10 In step (5), the surface of the second wafer W2 on the side away from the first wafer W1 is thinned again. Figure 10 The steps shown in (1), (2), (4) and (5) can be referred to Figure 9The corresponding descriptions and implementations are as follows, and repetitions will not be repeated. That is to say, after step S301 and before step S302, one or more thinning processes can be added. In this way, by thinning the second wafer W2 through multiple thinning processes, the total thickness change of the wafer can be adjusted in a timely manner, resulting in better electrical performance and reliability of the fabricated wafer.
[0074] In this embodiment, single-sided thinning of a wafer is taken as an example, that is, thinning is performed only on the surface of the second wafer W2 away from the first wafer W1. In specific implementation, the surface of the first wafer W1 away from the second wafer W2 can also be thinned. The specific implementation method can refer to the above description, and the repeated parts will not be repeated. Furthermore, in this embodiment, the fabrication process of the first wafer W1 and the second wafer W2 is used as an example for explanation. In specific implementation, when more wafers need to be stacked, a dielectric layer can also be deposited on the surface edge of the wafer before thinning. The implementation method of this application can be referred to, and the repeated parts will not be repeated.
[0075] In some embodiments of this application, the chip stacking structure in these embodiments can be Figure 4 or Figure 5 The wafer stacking structure shown is obtained by segmentation, for example, it can be... Figure 6 The chip stacking structure shown; or, the chip stacking structure in the embodiments of this application can be made of Figure 8 The wafer stack structure fabricated by the method shown is obtained by segmentation.
[0076] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0077] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.
Claims
1. A wafer stacking structure, characterized in that, include: First wafer, second wafer, and dielectric layer; The first wafer and the second wafer are stacked together; The dielectric layer covers at least a portion of the side surface of the second wafer; The surface of the dielectric layer away from the first wafer in a first direction is flush with the surface of the second wafer away from the first wafer; wherein, the first direction is the thickness direction of the wafer stacking structure.
2. The wafer stacking structure as described in claim 1, characterized in that, The dielectric layer also covers at least a portion of the side surface of the first wafer.
3. The wafer stacking structure as described in claim 2, characterized in that, The first wafer includes: a first portion and a second portion distributed along the first direction, wherein the second portion is located between the first portion and the second wafer; The edge of the second portion is flush with the edge of the second wafer, and the edge of the first portion protrudes beyond the edge of the second portion to form a recess on the side of the wafer stack structure; The dielectric layer is disposed in a recessed position on the side of the wafer stacking structure.
4. The wafer stacking structure according to any one of claims 1 to 3, characterized in that, Also includes: A third wafer located between the first wafer and the second wafer; The dielectric layer also covers at least a portion of the side surface of the third wafer.
5. The wafer stacking structure according to any one of claims 1 to 4, characterized in that, In the first direction, the projection of the dielectric layer surrounds the projection of the second wafer.
6. The wafer stacking structure according to any one of claims 1 to 5, characterized in that, The dielectric layer comprises silicon dioxide or silicon nitride.
7. A method for fabricating a wafer stacked structure, characterized in that, include: A first wafer and a second wafer are provided in a stacked configuration, and the edges of the first wafer and the second wafer are cut using a dicing process; A dielectric layer is deposited at the edge of the second wafer such that the dielectric layer covers the surface edge of the second wafer away from the first wafer and covers at least a portion of the side surface of the second wafer; The surface of the second wafer away from the first wafer is thinned so that the surface of the dielectric layer away from the first wafer in a first direction is flush with the surface of the second wafer away from the first wafer; wherein, the first direction is the direction from the first wafer to the second wafer.
8. The manufacturing method as described in claim 7, characterized in that, Before the edges of the first wafer and the second wafer are cut using a cutting process, the fabrication method further includes: The surface of the second wafer away from the first wafer is ground using a mechanical grinding process.
9. The manufacturing method as described in claim 7 or 8, characterized in that, The thinning of the surface of the second wafer away from the first wafer specifically includes: A chemical mechanical polishing process is used to polish the surface of the second wafer on the side away from the first wafer; And / or, a wet etching process is used to etch the surface of the second wafer away from the first wafer.
10. The manufacturing method according to any one of claims 7 to 9, characterized in that, After the edges of the first wafer and the second wafer are cut using a dicing process and before the dielectric layer is formed, the fabrication method further includes: A chemical mechanical polishing process is used to polish the surface of the second wafer on the side away from the first wafer.
11. An electronic device, characterized in that, include: A chip stacking structure and a circuit board, wherein the chip stacking structure is electrically connected to the circuit board; The chip stacking structure is obtained by dividing the wafer stacking structure as described in any one of claims 1 to 6; or, the chip stacking structure is obtained by dividing the wafer stacking structure manufactured by the manufacturing method as described in any one of claims 7 to 10.