FDTD electromagnetic simulation acceleration method and system based on decoupling of cpu and gpu functions

Abstract

The application belongs to the cross field of computer aided engineering and electromagnetic field calculation, and relates to a CPU and GPU function decoupling cooperative FDTD electromagnetic simulation acceleration method and system. In view of the problems of large grid scale, large time step number, high communication overhead and the like existing in high-speed interconnection wire harness, antenna array and electromagnetic compatibility analysis, the application does not adopt the traditional space domain decomposition, but from three dimensions of calculation characteristics, communication mode and preprocessing flow, through GPU kernel level optimization, CPU and GPU functional asymmetric decoupling, processing based on Ping-Pong double buffering and multi-hardware heterogeneous flow mechanism and preprocessing cooperation and normalization on the input CAD geometric model, the GPU calculation resource utilization is improved, the CPU / GPU data exchange overhead is reduced, and the overall execution efficiency of large-scale FDTD electromagnetic simulation is improved, so that the electromagnetic simulation is accelerated.

Description

Technical Field

[0001] This invention belongs to the interdisciplinary field of computer-aided engineering and electromagnetic field calculation, and relates to an accelerated method and system for ultra-large-scale FDTD electromagnetic simulation, especially an accelerated method and system for FDTD electromagnetic simulation with decoupled and coordinated functions of CPU and GPU. Background Technology

[0002] Finite-difference time-domain (FDTD) methods are a widely used technique for full-wave time-domain solution in numerical analysis of complex electromagnetic fields. When using FDTD methods for electromagnetic simulations, due to the large scale of the simulations, acceleration is necessary. Current mainstream solutions for accelerating electromagnetic simulations mainly include the following categories: 1. Parallel approach based on multi-core CPUs. This typically involves using OpenMP or MPI to partition the 3D Yee mesh, with multiple CPUs updating the electromagnetic field in parallel. While simple to implement, this approach is limited by the computing power of a single CPU core and memory bandwidth, resulting in limited scalability for extremely large-scale models.

[0003] 2. Single-GPU-based parallel solutions. These solutions typically map the Yee mesh to GPU memory, with the GPU handling the temporal updates. Their advantage lies in high computational throughput, but they are still limited by GPU memory capacity. Furthermore, the boundary conditions and material updates often involve numerous conditional branches, which can easily lead to warp divergence and reduced execution efficiency. The adaptability of a single-GPU architecture is also relatively limited for tasks such as multi-port logic processing and frequency domain transformations.

[0004] 3. Traditional CPU-GPU Spatial Domain Decomposition Hybrid Scheme. This type of scheme is a common approach in existing heterogeneous acceleration. It typically divides the overall mesh into multiple sub-regions, with the GPU and CPU each responsible for computation in their respective sub-regions, synchronizing boundary data at each time step. Its limitations mainly lie in the frequent synchronization required between the CPU and GPU, resulting in significant PCIe communication overhead. In multi-port scenarios, boundary switching and latency may be further amplified, leading to unstable acceleration gains or even negative gains in some operating conditions.

[0005] 4. Multi-GPU Domain Decomposition Schemes in Commercial Software. Some commercial electromagnetic simulation software uses multi-GPU spatial partitioning to improve the computational power of large-scale models. While this approach can extend the parallel capabilities of a single machine, the data exchange and synchronization logic between GPUs is relatively complex, and it typically focuses more on mesh partitioning and load distribution, while still lacking sufficient support for port logic processing, CPU-GPU functional collaboration, and the linkage between preprocessing and solving.

[0006] In summary, the existing technologies have the following shortcomings in solving large-scale FDTD: (1) In the single-GPU implementation, there are many conditional branches and discontinuous memory access modes, which easily lead to warp divergence and reduce memory merging efficiency; (2) The CPU-GPU hybrid scheme based on spatial domain decomposition has frequent data exchange and synchronization waiting at the port and PML boundary, making it difficult to obtain stable acceleration benefits; (3) The preprocessing stage does not make sufficient use of the regularization of the CAD / STEP geometric model, resulting in an increase in singular meshes and irregular boundaries, which in turn increases the warp divergence and memory access overhead in the solution stage.

[0007] Therefore, based on the above analysis, there is an urgent need for a new method and system for accelerating ultra-large-scale FDTD electromagnetic simulation. Summary of the Invention

[0008] To address the problems existing in the prior art, this invention proposes an FDTD electromagnetic simulation acceleration method and system that decouples and coordinates the functions of CPU and GPU. This method can improve the utilization of GPU computing resources, reduce CPU / GPU data exchange overhead, and improve the overall execution efficiency of large-scale FDTD electromagnetic simulation, thereby accelerating electromagnetic simulation.

[0009] To achieve the above objectives, the present invention provides the following technical solution: A method for accelerating FDTD electromagnetic simulation by decoupling and coordinating the functions of CPU and GPU, characterized by the following steps: S1: For the input CAD geometric model, calculate the minimum mesh step size based on the FDTD global objective. Model regularization and topology repair are performed to obtain a normalized geometric model suitable for FDTD mesh generation; S2: Perform GPU kernel-level optimizations on the Yee mesh field variables to form a regular field to advance the computation path; S3: Collect the hardware and software characteristic parameters of the current simulation task online, and obtain the port and frequency domain post-processing overhead characteristics, geometric topology non-uniformity characteristics and memory pressure characteristics respectively. Normalize each characteristic and construct a dimensionless decoupling metric. Based on the dimensionless decoupling metric and the preset decoupling threshold, determine whether to adopt the pure GPU exclusive iteration mode or the CPU and GPU functional asymmetric decoupling mode. S4: When adopting the functional asymmetric decoupling mode of CPU and GPU, the rule field advancement task is allocated to the GPU according to the task calculation characteristics, and the port, monitoring point and frequency domain post-processing tasks are allocated to the CPU. Through device-side double buffering, host-side corresponding buffering, and asynchronous calculation flow and data transmission flow, the GPU rule field calculation of the current time step is partially or completely overlapped with the local data transmission and CPU logic processing of the previous time step.

[0010] Preferably, in step S1, the minimum grid step size of the FDTD global target is... ,in, yes Directional grid step size, yes Directional grid step size, yes Directional grid step size.

[0011] Preferably, the model normalization and topology repair of the input CAD geometric model in step S1 specifically includes: S11: Perform adaptive filling of sub-mesh holes; S12: Perform topological smoothing on local singular sharp corners; S13: Perform equivalent degradation treatment on the thin sheet structure; S14: Perform topological non-manifold feature repair and surface stitching.

[0012] Preferably, step S2 specifically includes: S21: Perform separate storage of field variables: Create 6 independent one-dimensional arrays for the six field components of the Yee grid and store them separately; S22: 3D coordinate flattening and pre-calculated coordinate recovery: Linearize the 3D coordinates of the Yee mesh into a 1D index and assign a 1D global ID to the GPU thread; when the thread needs 3D coordinates, the 3D coordinates are recovered based on the pre-stored mesh dimension parameters and product constants; S23: 128-byte memory alignment: The one-dimensional array used to store Yee grid field variables is aligned to a 128-byte boundary, and the tail space that is insufficient to align to the boundary is padded to improve the efficiency of merged memory access for consecutive threads; S24: Shared memory sliding window cache: preloads the neighborhood data required for Yee grid computing into the GPU high-speed on-chip shared memory in batches, and reuses the neighborhood data by sliding the window. S25: Multi-kernel differential path splitting: Processing logic with different computation paths is split into multiple relatively independent GPU computing kernels, so that the target mesh area corresponding to the same computing kernel has a more consistent computation path, thereby reducing thread bundle branch divergence.

[0013] Preferably, step S3 specifically includes: S31: Obtain port and frequency domain post-processing overhead characteristics by acquiring the number of acquisition ports, online FFT points, and excitation type. ; Calculate the degree of discreteness of mesh cell size to obtain the geometric topological non-uniformity characteristics. The memory pressure characteristic is obtained by calculating the ratio of the video memory required by the current task to the available video memory of the GPU. ,in, This represents the physical video memory space required for the current simulation task. This represents the actual physical video memory available to the GPU; S32: Normalize the features respectively, and construct a dimensionless decoupling metric. : ; In the formula, The weights are non-negative and satisfy the following conditions: ; S33: In At that time, a pure GPU-exclusive iteration mode was adopted; At that time, an asymmetric decoupling mode for CPU and GPU functions is adopted, wherein, This is the preset decoupling threshold.

[0014] Preferably, when using the pure GPU-exclusive iteration mode, the simulation task is mainly based on regular field updates, and the CPU-side post-processing overhead is extremely light. When using the CPU and GPU functional asymmetric decoupling mode, the simulation task is divided into functional tasks according to the computing power characteristics. That is, the GPU is responsible for Yee field advancement, PML updates and other regular high-throughput tasks, while the CPU is responsible for port excitation, waveguide mode integration, monitoring point data processing, FFT and S-parameter post-processing. The CPU and GPU exchange local port, monitoring point or cross-section sampling data, without performing periodic full host-device backhaul on the core Yee field array.

[0015] Preferably, when performing step S4, three parallel execution entities are set up: a GPU computation stream, a GPU asynchronous data transfer stream, and a host multi-threaded processing queue. Device Buffer A and Device Buffer B are set up on the GPU side, and corresponding page-locking Host Buffer A and Host Buffer B are set up on the CPU side. The GPU computation stream is used to execute Yee grid rule field iteration, the GPU asynchronous data transfer stream is used for local data transfer across the PCIe bus, and the host multi-threaded processing queue is used for port field data post-processing. Device Buffer A and Device Buffer B alternately handle data snapshots of adjacent time steps. When the communication and CPU post-processing path time exceeds the GPU computation path time, the Host Buffer circular queue depth is increased according to the critical path cost model.

[0016] Furthermore, this invention also provides an FDTD electromagnetic simulation acceleration system with decoupled and coordinated CPU and GPU functions, characterized by comprising: a pre-processing linkage module, a GPU kernel-level optimization module, a decoupling determination module, and a heterogeneous pipelined execution module; the pre-processing linkage module is used to determine the minimum grid step size based on the FDTD global target. The input CAD geometric model is model regularized and topologically repaired to obtain a standardized geometric model suitable for FDTD mesh generation. The GPU kernel-level optimization module is used to perform GPU kernel-level optimization on the Yee mesh field variables to form a regular field advancement calculation path. The decoupling determination module is used to collect the hardware and software characteristic parameters of the current simulation task online, and obtain the port and frequency domain post-processing overhead characteristics, geometric topology non-uniformity characteristics, and memory pressure characteristics, respectively. Each feature is normalized and a dimensionless decoupling metric is constructed. Based on the dimensionless decoupling metric and the preset decoupling threshold, it is determined whether to adopt a pure GPU exclusive iteration mode or a CPU and GPU functional asymmetric decoupling mode. The heterogeneous pipeline execution module is used to allocate the regular field advancement task to the GPU and the port, monitoring point, and frequency domain post-processing tasks to the CPU according to the task calculation characteristics when adopting the CPU and GPU functional asymmetric decoupling mode. Through device-side double buffering, host-side corresponding buffering, and asynchronous calculation flow and data transmission flow, the GPU regular field calculation in the current time step is partially or completely overlapped with the local data transmission and CPU logic processing in the previous time step.

[0017] Furthermore, this invention also provides an FDTD electromagnetic simulation acceleration device with decoupled and coordinated CPU and GPU functions, characterized in that it includes: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the FDTD electromagnetic simulation acceleration method described above, which decouples and coordinates CPU and GPU functions. Finally, the present invention also provides a computer-readable storage medium having a computer program stored thereon, characterized in that, when the program is executed by a processor, it implements the steps of the FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions as described above.

[0018] Compared with the prior art, the FDTD electromagnetic simulation acceleration method and system of CPU and GPU functional decoupling and coordination of the present invention has one or more of the following beneficial technical effects: 1. In terms of single-GPU solving, optimizations such as SoA storage, one-dimensional flattening, pre-computed coordinate recovery, Shared Memory adaptive sliding window, and Multi-kernel differential path splitting significantly reduce the performance loss caused by warp divergence and non-merged memory access, improve the utilization of GPU computing resources, and enable the pure GPU iterative mode to achieve significant acceleration under the same grid size.

[0019] 2. In terms of CPU-GPU hybrid acceleration, this invention no longer adopts the traditional spatial domain decomposition, but performs functional decoupling based on computational characteristics. The regular field advancement task is mainly assigned to the GPU, and the high branch logic task is assigned to the CPU, thereby reducing data synchronization and thread waiting at the port and PML boundary, and improving the overall efficiency and stability of the hybrid mode.

[0020] 3. In terms of preprocessing and solution collaboration, this invention reduces the data transfer cost from preprocessing to the solution stage through model normalization, double-buffered asynchronous transmission, and CUDAStream pipeline mechanism, reduces the additional overhead of singular meshes and irregular boundaries on the solver, and improves the scalability of the overall process.

[0021] In summary, this invention can simultaneously improve single-machine computing power utilization, heterogeneous collaboration efficiency, and end-to-end execution efficiency in complex 3D electromagnetic simulation scenarios, and is suitable for high-performance implementation of large-scale FDTD solving tasks. Attached Figure Description

[0022] Figure 1 This is a flowchart of the FDTD electromagnetic simulation acceleration method for decoupling and coordinating CPU and GPU functions according to the present invention; Figure 2 This is a schematic diagram of the FDTD electromagnetic simulation acceleration system with decoupled and coordinated CPU and GPU functions according to the present invention. Figure 3 This is a structural block diagram of the FDTD electromagnetic simulation acceleration device with decoupled and coordinated CPU and GPU functions according to the present invention.

[0023] Where 11: memory; 12: processor. Detailed Implementation

[0024] Before detailing any embodiment of the invention, it should be understood that the invention, in its application, is not limited to the details of the construction and arrangement of the components set forth in the following description or illustrated in the following figures. The invention can have other embodiments and can be practiced or carried out in various ways. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered limiting. The use of “comprising” or “having” and variations thereof in this invention is intended to cover the items set forth below and their equivalents, as well as any additional items. Unless otherwise specified or limited, the terms “installation,” “connection,” “support,” and “linkage,” and variations thereof are used broadly and cover both direct and indirect installation, connection, support, and linking. Moreover, “connection” and “linkage” are not limited to physical or mechanical connections or links. Furthermore, firstly, in the disclosure of this invention, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the invention. Secondly, the term "a" should be understood as "at least one" or "one or more," that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple. The term "a" should not be construed as a limitation on the quantity.

[0025] This invention addresses the full-wave numerical analysis needs of complex three-dimensional electromagnetic structures. It tackles common problems in high-speed interconnect harnesses, antenna arrays, and electromagnetic compatibility analysis, such as large mesh sizes, numerous time steps, and high communication overhead. Instead of traditional spatial domain decomposition, it constructs a four-layer architecture—hardware optimization, functional decoupling, asynchronous pipeline, and preprocessing collaboration—based on computational characteristics, communication modes, and preprocessing procedures. This improves GPU computing resource utilization, reduces CPU / GPU data exchange overhead, and enhances the overall execution efficiency of large-scale FDTD electromagnetic simulations, thereby accelerating electromagnetic simulation.

[0026] Figure 1 A flowchart of the FDTD electromagnetic simulation acceleration method based on the decoupling and coordination of CPU and GPU functions according to the present invention is shown. Figure 1 As shown, the FDTD electromagnetic simulation acceleration method of CPU and GPU functional decoupling and coordination according to the present invention includes the following steps: S1: Preprocessing.

[0027] The input CAD geometric model is normalized and its topology is repaired to standardize the geometric model.

[0028] Specifically, let the minimum grid step size of the global objective in FDTD (Finite-Difference Time-Domain) be... During preprocessing, the minimum grid step size of the global target in the FDTD is used. The input CAD geometric model undergoes model normalization and topology repair to standardize the geometric model. The FDTD global target minimum mesh step size is specified here. In the formula, yes Directional grid step size, yes Directional grid step size, yes Directional grid step size.

[0029] The preprocessing specifically includes: 1. Perform adaptive filling of sub-mesh holes.

[0030] To perform adaptive filling of sub-mesh holes, the holes requiring adaptive filling must first be identified. In this invention, the identification mechanism for sub-mesh holes is as follows: traverse all closed inner boundary loops of the input CAD geometric model and calculate the maximum diagonal dimension of the loop bounding box. When satisfied Time (where the correction factor) The value range is [0.5, 1.5], with a default value of 1.0). This value indicates that the hole is an unresolvable electromagnetic singularity, i.e., a hole that needs to be adaptively filled.

[0031] After identifying the small hole requiring adaptive filling, it is adaptively filled. In this invention, during adaptive filling, the base surface topology to which the loop belongs is extracted, and surface stitching and geometric repair operators are invoked to generate a continuous filling surface to eliminate the small hole, avoiding the generation of local minima during mesh generation. The adaptive filling method used in this invention does not rely on manual interaction, but is implemented through an automated geometric reconstruction engine based on topological boundary search and parameter domain projection, specifically including the following four standardized core execution steps: (1) Automatic identification and extraction of topological boundary loops.

[0032] First, a non-manifold edge and boundary search is performed. During the search, the input local 3D solid or shell is traversed, and the intersection edges of all geometric faces are extracted. By counting the frequency of each edge being shared by adjacent faces, open boundary edges with a shared face count of 1 are selected.

[0033] Next, topological loop construction is performed. Specifically, topological tracing is performed along these open boundary edges, automatically combining and constructing closed geometric boundary loops.

[0034] Finally, feature size filtering is performed. Specifically, the 3D tight bounding boxes of all discrete vertices of the loop are calculated, and their maximum diagonal physical dimensions are extracted. When the aforementioned conditions are met... During the judgment process, this circuit is latched as the target small hole circuit to be repaired. .

[0035] (2) Reverse derivation of the topology of the reference plane and mapping of the parameter domain.

[0036] First, the baseline is determined. Specifically, this involves reverse retrieval and the target loop. Known geometric surfaces around which direct topological adjacency occurs If the surrounding adjacent surfaces belong to the same analytical surface (such as the same plane, cylindrical surface, or conical surface), then the mathematical analytical equation of that analytical surface is directly extracted as the reference surface. .

[0037] Secondly, non-analytical freeform surface fitting (spline approximation) is performed. Specifically, if the surrounding adjacent surfaces are complex non-uniform rational B-spline freeform surfaces, the control vertices and tangent vectors of the adjacent surface edges are extracted, and a local least squares curvature reconstruction algorithm is used to inversely extrapolate and fit a virtual base surface covering the area of ​​the small hole. .

[0038] Finally, coordinate system projection mapping is performed ( Specifically, the coordinates of the target aperture loop in three-dimensional space are... Inverse projection onto the fitting reference plane Two-dimensional parameter space In the middle, a two-dimensional closed curve boundary is formed within the parameter domain. .

[0039] (3) The geometric repair operator generates the filling surface online.

[0040] First, parametric domain surface trimming and inversion are performed. Specifically, on the reference plane... Within the two-dimensional parameter space, with closed curve boundaries This serves as the clipping boundary. Since the goal here is to fill the hole rather than remove it, a topology inversion operation is performed to... Internal parameter area Activate, as the parameter domain of the new fill surface.

[0041] Then, perform 3D repair surface mapping ( Specifically, the filled area within the parameter domain. Through the base surface equation Mapping back to 3D physical space, a completely new 3D geometric patch entity is instantiated online, namely, the filled surface. The filling surface intersects with the surrounding adjacent surfaces at the boundary. Reached (Continuous tangent) or The geometric smoothness (continuous curvature) ensures the physical continuity of the electromagnetic field as it passes through the cut surface.

[0042] (4) Implement global manifold reconstruction.

[0043] First, perform tolerance stitching. The newly generated fill surface... Adjacent surfaces of the original model There may be minute physical gaps at physical boundaries due to floating-point precision. Tolerance stitching can be performed by calling the topology stitching operator, and a boundary stitching tolerance threshold can be set. .

[0044] Secondly, vertex sharing and edge merging are performed. The topology stitching operator operates along the loop. Forcibly filling the surface The corresponding open boundary edges of the original model are geometrically merged, and the two sets of discontinuous boundary vertices are merged into the same set of shared vertex pointers, thus reconstructing the local topological adjacency matrix.

[0045] Finally, the manifold shell is output. After stitching, the filling surface is... It was formally incorporated into the topology tree structure of the original model. The original non-closed shell with small holes was successfully regularized into a continuous, pore-free standard watertight manifold geometry.

[0046] 2. Perform topological smoothing on local singular sharp corners.

[0047] To perform topological smoothing of local singular sharp corners, it is first necessary to identify the local singular sharp corners that require topological smoothing. In this invention, the identification mechanism for local singular sharp corners is as follows: calculate the angle θ between the normal vectors of any two adjacent geometric faces of the 3D model at their common intersection line. When the angle θ between the normal vectors of the two faces at their common intersection line satisfies... (default When a certain condition is met, it is determined to be a local singular sharp corner that requires topological smoothing.

[0048] After identifying the local singular sharp corners that require topological smoothing, topological smoothing processing is necessary. In this invention, the strategy for topological smoothing is to perform local fillet or chamfering fine-tuning on the edge, forcibly correcting its radius of curvature to: ,in, This eliminates local irregular meshing caused by local singular sharp corners, preventing the global time step from being forced to compress due to excessively low Courant stability condition (CFL) during time-domain advancement.

[0049] 3. Perform equivalent degradation treatment on the thin sheet structure.

[0050] For the equivalent degradation treatment of thin sheet structures, based on the thin sheet material properties, frequency range and corresponding electromagnetic equivalent boundary conditions, a boundary model corresponding to the original three-dimensional structure is selected from the PEC boundary, impedance boundary or equivalent lossy thin film boundary; two-dimensional degradation is performed only when the equivalent model meets the preset error tolerance.

[0051] To perform equivalent degradation of thin-sheet structures, it is first necessary to identify the thin-sheet structures that require equivalent degradation. In this invention, the identification mechanism for thin-sheet structures is as follows: for solid shell models, extract the local thickness feature dimensions between opposite surfaces. ,when Time (default) = 0.8), if the three-dimensional solid mesh is continued, the mesh in the Z direction will be extremely dense. Therefore, it is considered to be a thin sheet structure that needs equivalent degradation treatment.

[0052] After identifying the thin sheet structure that requires equivalent degradation, it needs to be subjected to equivalent degradation. In this invention, the strategy for equivalent degradation is as follows: strip away the three-dimensional features of the entity, degrade it to a two-dimensional zero-thickness geometry, and output the boundary attribute labels of "Perfect Conductor (PEC) Thin Sheet" or "Equivalent Lossy Thin Film" to the solver. The solver then directly uses the field quantity jump conditions on / below the two-dimensional surface to advance the process, eliminating the need for explicit three-dimensional mesh generation.

[0053] 4. Repair and stitch the topological non-manifold features.

[0054] To repair topological non-manifold features and stitch surfaces, it is first necessary to identify the topological non-manifold features to be repaired and the surfaces to be stitched. In this invention, the identification mechanism for the topological non-manifold features to be repaired and the surfaces to be stitched is as follows: Traverse the CAD geometric model after the above three steps, retrieving all isolated edges not shared by more than two solid faces, and non-manifold vertices with abnormal topological connectivity. When a spatial gap distance between isolated edge pairs is detected... Time (of which) The free tolerance coefficient, with a value range of ([0.1, 0.5]), activates the adaptive surface extension and topology stitching operators, forcibly closing the open boundary and reconstructing it into a solid geometry with strict watertightness. Activating the adaptive surface extension and topology stitching operators ensures that during subsequent Yee mesh voxelization and splitting, electromagnetic "leakage fields" or mesh leakage will not occur due to topological tearing, thus guaranteeing the stable, branchless operation of the solver kernel's multi-kernel structure from the source.

[0055] The specific implementation mechanism of the activated surface adaptive extension and topology stitching operator is to achieve fully automatic normalization through four explicit hard-core steps: constructing a topological adjacency graph, extrapolating the curvature of the boundary tangent, spatial interactive clipping, and vertex remelting. The specific process is as follows: (1) Accurate identification of topological non-manifold features and isolated edges.

[0056] First, construct the B-Rep topological adjacency matrix. Specifically, first transform the boundary representation (B-Rep) of the 3D mesh geometric model into an adjacency graph structure in graph theory, where nodes represent topological vertices, edges represent topological edges, and faces represent geometric faces.

[0057] Next, non-manifold vertex identification is performed. Specifically, in a standard manifold entity, the faces surrounding a vertex must form a single, topologically closed conical entity domain. If a vertex is found to be shared by two or more face tiles that are not connected at their edges (e.g., two cones apex-to-apex), then that vertex is marked as a non-manifold singularity. By performing a topological splitting operator at this point, the vertex pointer is copied and adjacent faces are physically isolated, degenerating it into two independent local topologies of the manifold.

[0058] Finally, isolated edge retrieval is performed. Specifically, the number of times each topological edge is shared by a surface is counted, and the sharing count is recorded. An edge is defined as an open isolated edge, which is formed by two edges that are physically closest in space, have a tangent angle less than a preset threshold, and satisfy the spatial gap condition. The isolated edge is locked as the opposing edge pair to be stitched. ).

[0059] (2) Mathematical solution of the adaptive extension operator for surfaces.

[0060] When facing When dealing with physical gaps, in order to prevent the surface from being severely distorted and deformed due to forced pulling, curvature extrapolation is performed using local calculus features.

[0061] First, perform inverse extrapolation of the boundary curvature. Specifically, for the left edge... Retrieve the parent surface from discrete sampling points on the surface. Extract the first derivative (tangent vector T) and second derivative (curvature tensor K) of the surface at the edge.

[0062] Secondly, higher-order continuity extrapolation is performed. Specifically, if the parent surface is a plane or a first-order analytic surface, the extension operator directly extrapolates the physical gap span outward along the domain of the analytic equation. If the parent surface is a complex spline free surface, the extension operator passes through... (Continuous tangent) or (Curvature continuity) boundary constraints, reconstruct control vertex weights, and extend outward tangentially a distance along the edge normal direction.

[0063] Similarly, the right edge The corresponding parent surface also undergoes synchronous extrapolation.

[0064] (3) Spatial clipping and differentiation of intersection lines.

[0065] First, spatial intersection operations are performed. Specifically, the virtual transition geometric patches extrapolated from both sides overlap in physical space. The geometric intersection equation is called to analytically solve for the precise analytical intersection line of the two extrapolated surface patches in three-dimensional space. .

[0066] Then, redundant faces are removed. Specifically, this is done using the intersection line. As a novel topological boundary, the parametric domain of the extrapolated surfaces on both sides is pruned to remove any suspended, invalid fragment surfaces. This results in a precisely fitting group of transitional closed surfaces that converges above the original topological tear. .

[0067] (4) The topological stitching operator realizes rigorous watertightness reconstruction.

[0068] The newly generated closed surface group still has a very small physical gap with the original model at the floating-point level, and structural re-fusion is necessary.

[0069] First, tolerance vertex remelting is performed. Specifically, starting along the new boundary, the patch is... The outer topological edge and the opposite edge pair of the original model ( Forced merging is performed, combining two sets of boundary vertex pointers that are independent in physical address into a single physical memory pointer.

[0070] Then, a manifold state machine change is performed. Specifically, after stitching, the previously broken topology is successfully reconstructed into a connected graph. When traversing all topological edges, it is confirmed that the count of their shared faces is strictly equal to 2. When ), it means that the non-manifold structure that originally had topological tears and open boundaries has been completely reconstructed into a standard manifold solid geometry with strict watertightness.

[0071] S2: GPU kernel-level optimization.

[0072] GPU kernel-level optimizations are performed to improve GPU computing resource utilization, enabling a significant acceleration of the pure GPU iterative mode under the same grid size.

[0073] In this invention, by flattening the Yee grid and material coefficients in one dimension and performing optimal alignment according to the 128-byte boundary, and combining the Shared Memory sliding window cache and the Multi-kernel differential path splitting mechanism, the warp divergence caused by condition judgment is reduced, thereby improving the throughput efficiency of the FDTD time-domain advancement stage.

[0074] The specific implementation of GPU kernel-level optimization is as follows: 1. Field variable separate storage (SoA storage).

[0075] For the six field components of the Yee mesh ( This invention stores data centrally by attribute, directly creating 6 independent one-dimensional arrays ( [] [] [] [] [] []) separates the storage, rather than packaging the data "by spatial point". The reason is that in scientific computing using the finite-difference time-domain (FDTD) method, it is often necessary to update all points simultaneously. This invention uses a separate one-dimensional array for continuous memory arrangement, which perfectly meets the requirements of GPU vectorized reading, enables efficient merged memory access, ensures that the data blocks loaded into the cache are fully utilized by the current computing kernel, and maximizes the utilization of memory access bandwidth.

[0076] 2. 3D coordinate flattening and pre-calculated coordinate restoration.

[0077] First, perform forward flattening: 3D coordinates -> 1D indexing. Specifically, for the Yee mesh size... Define a row-major linear mapping: That is, finish first. Axis (innermost layer) ), and then walk to the end Axis (middle layer) ), and finally walked to the end Shaft (outermost layer) In this way, the three-dimensional coordinates of each point in the Yee mesh can be obtained. Each of these points is flattened into a one-dimensional index, so that any point in the three-dimensional space corresponds to an absolute position in the one-dimensional array.

[0078] Next, GPU thread allocation is performed: a one-dimensional linear unique identifier. Specifically, the GPU launches a total of parallel threads equal to the total number of points in the Yee grid, and each thread is assigned a one-dimensional global ID. Thus, each thread can directly handle the one-dimensional index of the absolute position corresponding to the position ID in the one-dimensional array and the one-dimensional global ID.

[0079] Finally, pre-calculation optimization and reverse recovery are performed: one-dimensional index -> three-dimensional coordinates. Specifically, the thread needs to reverse recover the three-dimensional coordinates when updating the physics field. To avoid the GPU repeatedly executing expensive division and modulo instructions billions of times within its internal threads, this invention pre-calculates the operations on the CPU side. The product is stored in a constant. In the context of GPU threads needing to access 3D coordinates, constants can be called directly. and based on constants The one-dimensional index is disassembled to recover the three-dimensional coordinates, thereby saving a lot of redundant instruction overhead at the hardware level.

[0080] 3.128-byte memory alignment.

[0081] In one NVIDIA GPU-based implementation, the one-dimensional array used to store Yee grid field variables is address-aligned to 128-byte boundaries and padded at the end of the array as necessary to improve the layout of continuous thread access to continuous data regions.

[0082] When adjacent threads access addresses that are continuous and meet the corresponding alignment conditions, the degree of merging of global video memory access can be improved, reducing additional memory access transactions caused by addresses crossing memory transaction boundaries, thereby improving video memory bandwidth utilization.

[0083] The 128-byte alignment method is a preferred implementation, and the actual alignment boundary can be adjusted according to the GPU hardware architecture, compilation environment, and memory access granularity.

[0084] 4. Shared memory sliding window cache.

[0085] The neighborhood data required for Yee grid computing is preloaded in batches into the high-speed on-chip shared memory of the GPU, and the cached data is reused in a window sliding manner to avoid frequent access to slow global video memory, reduce memory access latency, and improve the speed of electromagnetic field iteration calculation.

[0086] The extremely high latency of GPU global memory access is the biggest performance bottleneck in GPU electromagnetic field FDTD simulation. By using a shared memory sliding window cache, GPU threads can first move a large block of adjacent grid data from global memory to high-speed on-chip shared memory in batches. During thread computation, the data is read from the nearest high-speed on-chip shared memory. After calculating a window region, the sliding window loads the next batch of neighboring data, and so on.

[0087] Updating a single field point in the Yee grid depends on the field values ​​of its six neighboring grids. If each thread repeatedly reads global memory directly, it results in numerous repetitive, discrete, and high-latency memory accesses. This invention employs a shared memory sliding window, preloading all adjacent grid data within a computation window into high-speed shared memory. All threads within this window access adjacent grid data via on-chip high-speed SRAM, resulting in virtually no waiting latency. This significantly improves cache / shared memory hit rate and avoids frequent accesses to slow global memory.

[0088] 5. Multi-kernel differential path splitting.

[0089] For the FDTD update process, which contains multiple different computation paths, different processing logics are split into multiple relatively independent GPU computing cores according to the computation type. This makes the target mesh region processed by the same computing core have a more consistent computation path, thereby reducing the divergence of thread bundle branches caused by the difference in execution paths of different threads and improving parallel execution efficiency.

[0090] For example, electric field update kernel, magnetic field update kernel, absorption boundary update kernel and local data reduction kernel can be set separately and combined and scheduled according to the computational needs of the current time step.

[0091] Through optimizations such as separate storage of field variables, coordinate linearization, aligned storage, shared memory sliding window, and differential calculation path splitting, the memory access continuity and thread execution consistency during the rule field advancement phase are improved, thereby reducing the computational overhead of single-step rule field advancement.

[0092] S3: Decoupling determination based on multidimensional feature parameters.

[0093] At the same time, based on the dimensionless decoupling metric, it is determined whether to perform pure GPU-exclusive iteration or to perform functional asymmetric decoupling between CPU and GPU.

[0094] To achieve a dynamic balance between GPU-exclusive computing efficiency and heterogeneous parallel collaboration overhead throughout the entire time-domain process, this invention first performs a decoupling determination based on multi-dimensional feature parameters during initialization and at each key time step, specifically including: 1. Collect multidimensional feature parameters.

[0095] The software and hardware characteristic parameters of the current simulation task are collected online, mainly including: (1) (Port and frequency domain post-processing overhead factors).

[0096] It is a comprehensive overhead coefficient used to quantify the computational load and memory access pressure on the CPU caused by port excitation and fast Fourier transform frequency domain post-processing in electromagnetic simulation. The larger the value, the higher the computing power consumption.

[0097] In this invention, the port and the frequency domain post-processing overhead factor satisfy a logarithmic step relationship. In other words, the structure consists of two parts: the logarithmic overhead caused by the number of ports. And the computational power correction coefficient resulting from the number of sampling points in the Fast Fourier Transform (FFT). .

[0098] It is the port logarithmic step term, using the natural logarithm. Characterized by the non-linear overhead of increasing the number of ports, where the number of ports doubles linearly. The increase is only slight, which aligns with the actual computing power growth pattern of multi-port matrix operations and multi-source superposition, and avoids overestimating the pressure brought by the ports. This refers to the number of ports, specifically the number of excitation ports in the electromagnetic simulation, such as waveguide ports, S-parameter measurement ports, and antenna feed ports. The overhead increases logarithmically with the number of ports: the more ports there are, the more computationally intensive the mode integration and multi-excitation superposition becomes, following a logarithmic step relationship.

[0099] These are adaptive correction coefficients to reduce the computational burden of online frequency domain analysis and complex excitation calculations. When performing online Fast Fourier Transform (FFT) frequency domain processing, the initial boundary is set using a baseline FFT number of points (e.g., 1024 points). In online frequency domain analysis, for every doubling of the number of FFT sampling points, The value is linearly increased by 0.2 to accurately quantify the branch prediction and memory access ladder pressure on the host (CPU) caused by waveguide mode integration and non-uniform excitation spectrum weighting.

[0100] (2) (Geometric topological non-uniformity characteristics).

[0101] This represents a quantitative index of the non-uniformity of the mesh density distribution in the entire computational domain after computation by the adaptive meshing operator and normalization during simulation preprocessing. It is used for evaluating the computational load in electromagnetic simulations. If it is an ideal uniform mesh, with all elements having the same volume, then... If the structure is complex, with sharp corners / thin layers / high-frequency skin effect forcing local refinement, and the mesh size varies greatly, then... The value has increased significantly.

[0102] (3) (Virtual memory physical boundary characteristics).

[0103] This represents the physical memory space required for the current electromagnetic simulation. Compared to the actual available physical video memory of the GPU The ratio. In This indicates that the GPU has sufficient actual available physical video memory, and the electromagnetic simulation can be fully loaded and solved using a single card; This indicates that the GPU's physical video memory is fully loaded, which can easily trigger video memory overflow and memory swapping to system memory, resulting in a sharp drop in computing power; This indicates that the physical video memory of a single GPU is insufficient, and strategies such as multi-GPU memory sharding, model block solving, and matrix compression must be enabled.

[0104] 2. Construct a dimensionless decoupling metric.

[0105] The dimensionless decoupling metric is a normalized dimensionless comprehensive pressure metric. The heterogeneous scheduling engine compares it with a preset threshold. In comparison, among them The value can be preset according to the hardware platform, task scale, and target throughput requirements, with a preferred value range of 0.8 to 1.0. In this invention, a dimensionless decoupling metric is constructed. The explicit mathematical expression for is defined as follows: ; In the formula, The weights are non-negative and satisfy the following conditions: .

[0106] 3. Policy routing control branch determination.

[0107] Dimensionless decoupling metrics Essentially, it's the ratio of the potential post-processing communication pressure on the host side to the baseline throughput capacity of the pure rule-based field update on the device side. The heterogeneous scheduling engine uses this ratio as the routing driver, setting the dynamic balance critical point for hardware and software resource efficiency as... : (1) Pure GPU-exclusive iteration mode: when < At this time, the GPU performs rule-based field advancement and necessary stimulus loading, while the CPU mainly performs scheduling and lightweight management, without initiating continuous local asynchronous data pipelines.

[0108] (2) Functional asymmetric decoupling mode: when ≥ When the system switches to a functional asymmetric decoupling mode, processing paths are allocated according to the type of computational task: the GPU is responsible for high-throughput calculations such as Yee field propulsion, PML updates, and material updates; the CPU is responsible for FFT frequency domain transformation, port mode integration, excitation signal generation, monitoring point caching, S-parameter calculation, and other high-branch post-processing tasks. This functional partitioning does not depend on dividing the Yee mesh into CPU subdomains and GPU subdomains.

[0109] S4: Execution based on double buffering and heterogeneous hardware streams.

[0110] When performing functional asymmetric decoupling between CPU and GPU, the Ping-Pong double buffer and multi-hardware heterogeneous flow mechanism are used for processing. While the GPU processes the data of the current time step, the data transmission of the next buffer and the CPU logic processing of the previous buffer are executed asynchronously, realizing the overlap of computation and communication.

[0111] Specifically, when switching to the functional asymmetric decoupling mode of CPU and GPU, an asynchronous collaborative pipeline based on Ping-Pong double buffer (Buffer A / Buffer B) and multiple hardware heterogeneous streams (CUDA Stream) is launched at the hardware level to reduce the impact of cross-bus transport on the overall execution time, and a dynamic cost model is introduced to achieve steady-state control in the entire time domain.

[0112] 1. Heterogeneous parallel hardware streams and physical buffer configuration.

[0113] In the underlying hardware space, during the initialization phase, three parallel execution entities and a double-buffered queue are configured and bound: (1) Stream_Compute (GPU Computation Stream): A computing unit that exclusively uses the GPU and is dedicated to executing the Yee Mesh Electromagnetic Field Iteration Kernel.

[0114] (2) Stream_Copy (GPU Transport Stream): Drives the GPU's independent asynchronous copy engine, implicitly performing data transfer across the PCIe bus without blocking the computation stream.

[0115] (3) Host CPU (host multi-threaded cluster): Through a non-blocking event verification mechanism, it digests the backed-back port field data locally and performs waveguide integration and FFT post-processing.

[0116] (4) Buffer A / Buffer B physical pair: two physical address-aligned buffers allocated in video memory, with rolling latch time step snapshots.

[0117] 2. Flow-line sequential rolling advancement mechanism.

[0118] Taking any consecutive time step as an example, the overlapping state machine executes the following closed-loop timing sequence: (1) Current time step .

[0119] Computational flow control: Stream_Compute locks Buffer A and executes at full speed for the current time step. Global Yee grid electromagnetic field iteration.

[0120] Flow control: Parallel locking of Buffer B, holding the previous time step The discrete port snapshots calculated by the GPU are asynchronously transferred to the CPU.

[0121] Host-side flow control: Host-side CPU threads are activated in parallel to perform high-point FFT and pattern integration on the historical port data ready in main memory. At this time, the GPU computation time for the current step ( PCIe transfer time ( ) and CPU processing time ( It achieves partial or complete time overlap on the timeline.

[0122] (2) Next time step . After crossing the step size boundary, an asynchronous handshake instruction is issued, and the hardware roles of the buffers are swapped. Stream_Compute switches to Buffer B for computation; Stream_Copy switches to Buffer A for data transfer. Step data; CPU synchronously transitions and processes the data just transmitted back. Step data.

[0123] 3. Negative feedback closed-loop fine-tuning mechanism based on pipeline cost.

[0124] To ensure that the pipeline does not experience scheduling delays or state machine deadlocks when faced with extreme conditions (such as a sudden increase in CPU processing and PCIe transmission time due to high-point online FFT), dynamic weights and negative feedback mechanisms are introduced.

[0125] (1) End-to-end execution time.

[0126] The end-to-end execution time of a single time step is determined by the critical path of the heterogeneous pipeline, and its edge cost equation is explicitly expressed as follows:

[0127] in, This represents the GPU core field update time in step n (after underlying optimization in step one). This represents the asynchronous PCIe transfer time across the bus in step n-1. This represents the CPU port logic and frequency domain post-processing time at step n-1. This indicates the minimal handshake synchronization overhead during buffer flipping.

[0128] (2) Dynamic flow line depth control.

[0129] Real-time monitoring of congestion tolerance indicators; when it is determined that a communication and post-processing bottleneck period has been entered (i.e. When this happens, the pipeline depth is automatically and adaptively calculated and expanded. :

[0130] By allowing CPU logic processing to lag behind GPU computation steps appropriately, the pipeline depth is increased, ensuring that the GPU computing cores can continue to advance.

[0131] (3) Smoothing estimation and oscillation suppression.

[0132] To avoid severe oscillations in the scheduling module caused by single-step burst communication, an exponential moving average (EMA) is used to smoothly estimate the transient latency characteristics.

[0133] This mechanism ensures that cross-bus communication and computational overhead are effectively masked. Scheduling decisions are based on smoothed cost metrics. By implementing dynamic weight updates, system oscillations caused by frequent mode switching can be completely avoided over a time-domain period of tens of thousands of steps.

[0134] Furthermore, in this invention, the preprocessing parameters for subsequent simulation tasks can be adjusted based on performance data collected during operation. When the PCIe cross-bus asynchronous transmission time, CPU post-processing time, or GPU computation time is detected to continuously deviate from the preset target range, the corresponding performance deviation is formed into preprocessing feedback parameters. After the current simulation task ends or during the next model reconstruction and re-meshing, the geometric regularization parameters are adjusted based on these preprocessing feedback parameters. The geometric regularization parameters include at least one of the following: pinhole recognition threshold, sharp corner repair threshold, thin-film equivalent threshold, and topology stitching tolerance. This reduces irregular geometric features in the subsequent simulation model and the resulting irregular meshes and local data exchange overhead, enabling the preprocessing parameters to be iteratively optimized based on historical performance.

[0135] Figure 2 A schematic diagram of the electromagnetic simulation acceleration system of the present invention, which decouples and coordinates the functions of the CPU and GPU, is shown. Figure 2 As shown, the FDTD electromagnetic simulation acceleration system of the present invention, which decouples and coordinates CPU and GPU functions, includes: 1. Pre-processing linkage module.

[0136] The preprocessing linkage module is used to perform model regularization and topology repair on the input CAD geometric model in order to standardize the geometric model.

[0137] 2. GPU kernel-level optimization module.

[0138] The GPU kernel-level optimization module is used to perform GPU kernel-level optimization to improve the utilization of GPU computing resources.

[0139] 3. Decoupling determination module based on multidimensional feature parameters.

[0140] The decoupling determination module based on multidimensional feature parameters is used to collect the software and hardware feature parameters of the current simulation task online and construct a dimensionless decoupling metric based on the collected software and hardware feature parameters. At the same time, based on the dimensionless decoupling metric, it determines whether to perform pure GPU-exclusive iteration or functional asymmetric decoupling between CPU and GPU.

[0141] 4. Execution module based on double buffering and multi-hardware heterogeneous streams.

[0142] The execution module based on double buffering and multi-hardware heterogeneous flow is used to process CPU and GPU functional asymmetric decoupling based on Ping-Pong double buffering and multi-hardware heterogeneous flow mechanism. While the GPU processes the data of the current time step, it asynchronously executes the data transmission of the next buffer and the CPU logic processing of the previous buffer, realizing the overlap of computation and communication.

[0143] Furthermore, this invention also provides an FDTD electromagnetic simulation acceleration device with decoupled and coordinated CPU and GPU functions. For example... Figure 3 As shown, the CPU and GPU functional decoupling and collaborative FDTD electromagnetic simulation acceleration device of the present invention includes: a memory 11 for storing one or more programs; one or more processors 12; when the one or more programs are executed by the one or more processors 12, the one or more processors 12 implement the CPU and GPU functional decoupling and collaborative FDTD electromagnetic simulation acceleration method of the present invention. Finally, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the FDTD electromagnetic simulation acceleration method for decoupling and coordinating CPU and GPU functions in the present invention.

[0144] The computer-readable storage medium includes both permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. As defined in this invention, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0145] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0146] The steps of the methods or algorithms described in conjunction with the embodiments disclosed in this invention can be implemented in hardware, software modules executed by a processor, or a combination of both. The software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention based on the concept of the present invention, without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for accelerating FDTD electromagnetic simulation by decoupling and coordinating the functions of CPU and GPU, characterized in that, Includes the following steps: S1: For the input CAD geometric model, calculate the minimum mesh step size based on the FDTD global objective. Model regularization and topology repair are performed to obtain a normalized geometric model suitable for FDTD mesh generation; S2: Perform GPU kernel-level optimizations on the Yee mesh field variables to form a regular field to advance the computation path; S3: Collect the hardware and software characteristic parameters of the current simulation task online, and obtain the port and frequency domain post-processing overhead characteristics, geometric topology non-uniformity characteristics and memory pressure characteristics respectively. Normalize each characteristic and construct a dimensionless decoupling metric. Based on the dimensionless decoupling metric and the preset decoupling threshold, determine whether to adopt the pure GPU exclusive iteration mode or the CPU and GPU functional asymmetric decoupling mode. S4: When adopting the functional asymmetric decoupling mode of CPU and GPU, the rule field advancement task is allocated to the GPU according to the task calculation characteristics, and the port, monitoring point and frequency domain post-processing tasks are allocated to the CPU. Through device-side double buffering, host-side corresponding buffering, and asynchronous calculation flow and data transmission flow, the GPU rule field calculation of the current time step is partially or completely overlapped with the local data transmission and CPU logic processing of the previous time step.

2. The FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions according to claim 1, characterized in that, In step S1, the minimum grid step size of the FDTD global target ,in, yes Directional grid step size, yes Directional grid step size, yes Directional grid step size.

3. The FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions according to claim 2, characterized in that, The specific steps of model normalization and topology repair of the input CAD geometric model in step S1 include: S11: Perform adaptive filling of sub-mesh holes; S12: Perform topological smoothing on local singular sharp corners; S13: Perform equivalent degradation treatment on the thin sheet structure; S14: Perform topological non-manifold feature repair and surface stitching.

4. The FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions according to claim 1, characterized in that, Step S2 specifically includes: S21: Perform separate storage of field variables: Create 6 independent one-dimensional arrays for the six field components of the Yee grid and store them separately; S22: 3D coordinate flattening and pre-calculated coordinate recovery: Linearize the 3D coordinates of the Yee mesh into a 1D index and assign a 1D global ID to the GPU thread. When the thread needs 3D coordinates, the 3D coordinates are recovered according to the pre-stored mesh dimension parameters and product constants. S23: 128-byte memory alignment: The one-dimensional array used to store Yee grid field variables is aligned to a 128-byte boundary, and the tail space that is insufficient to align to the boundary is padded to improve the efficiency of merged memory access for consecutive threads; S24: Shared memory sliding window cache: preloads the neighborhood data required for Yee grid computing into the GPU high-speed on-chip shared memory in batches, and reuses the neighborhood data by sliding the window. S25: Multi-kernel differential path splitting: Processing logic with different computation paths is split into multiple relatively independent GPU computing kernels, so that the target grid region corresponding to the same computing kernel has a more consistent computation path, thereby reducing thread bundle branch divergence.

5. The FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions according to claim 1, characterized in that, Step S3 specifically includes: S31: Obtain port and frequency domain post-processing overhead characteristics by acquiring the number of acquisition ports, online FFT points, and excitation type. ; Calculate the degree of discreteness of mesh cell size to obtain the geometric topological non-uniformity characteristics. The memory pressure characteristic is obtained by calculating the ratio of the video memory required by the current task to the available video memory of the GPU. ,in, This represents the physical video memory space required for the current simulation task. This represents the actual physical video memory available to the GPU; S32: Normalize the features respectively, and construct a dimensionless decoupling metric. : ； In the formula, The weights are non-negative and satisfy the following conditions: ; S33: In At that time, a pure GPU-exclusive iteration mode was adopted; At that time, an asymmetric decoupling mode for CPU and GPU functions is adopted, wherein, This is the preset decoupling threshold.

6. The FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions according to claim 5, characterized in that, When using the pure GPU-exclusive iteration mode, the simulation task mainly involves regular field updates, and the CPU-side post-processing overhead is extremely light. When using the CPU and GPU functional asymmetric decoupling mode, the simulation task is divided into functional tasks according to the computing power characteristics. That is, the GPU is responsible for Yee field advancement, PML updates and other regular high-throughput tasks, while the CPU is responsible for port excitation, waveguide mode integration, monitoring point data processing, FFT and S-parameter post-processing. The CPU and GPU exchange local port, monitoring point or cross-section sampling data, without performing periodic full host-device backhaul on the core Yee field array.

7. The FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions according to claim 1, characterized in that, When performing step S4, three parallel execution entities are set up: GPU computation stream, GPU asynchronous data transfer stream, and host multi-threaded processing queue. Device Buffer A and Device Buffer B are set up on the GPU side, and corresponding page-locked Host Buffer A and Host Buffer B are set up on the CPU side. The GPU computation stream is used to execute Yee grid rule field iteration, the GPU asynchronous data transfer stream is used for local data transfer across the PCIe bus, and the host multi-threaded processing queue is used for port field data post-processing. Device Buffer A and Device Buffer B alternately handle data snapshots of adjacent time steps. When the communication and CPU post-processing path time exceeds the GPU computation path time, the Host Buffer circular queue depth is increased according to the critical path cost model.

8. A CPU and GPU functionally decoupled and collaborative FDTD electromagnetic simulation acceleration system, characterized in that, include: The module includes a pre-processing linkage module, a GPU kernel-level optimization module, a decoupling and determination module, and a heterogeneous pipeline execution module. The preprocessing linkage module is used to determine the minimum grid step size based on the global target of FDTD. The input CAD geometric model is model regularized and topologically repaired to obtain a standardized geometric model suitable for FDTD mesh generation. The GPU kernel-level optimization module is used to perform GPU kernel-level optimization on the Yee mesh field variables to form a regular field advancement calculation path. The decoupling determination module is used to collect the hardware and software characteristic parameters of the current simulation task online, and obtain the port and frequency domain post-processing overhead characteristics, geometric topology non-uniformity characteristics, and memory pressure characteristics, respectively. Each feature is normalized and a dimensionless decoupling metric is constructed. Based on the dimensionless decoupling metric and the preset decoupling threshold, it is determined whether to adopt a pure GPU exclusive iteration mode or a CPU and GPU functional asymmetric decoupling mode. The heterogeneous pipeline execution module is used to allocate the regular field advancement task to the GPU and the port, monitoring point, and frequency domain post-processing tasks to the CPU according to the task calculation characteristics when adopting the CPU and GPU functional asymmetric decoupling mode. Through device-side double buffering, host-side corresponding buffering, and asynchronous calculation flow and data transmission flow, the GPU regular field calculation in the current time step is partially or completely overlapped with the local data transmission and CPU logic processing in the previous time step.

9. An FDTD electromagnetic simulation acceleration device with decoupled and coordinated CPU and GPU functions, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the FDTD electromagnetic simulation acceleration method of decoupling and cooperating CPU and GPU functions as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the FDTD electromagnetic simulation acceleration method with decoupled and coordinated CPU and GPU functions as described in any one of claims 1-7.

Images