Display device

Abstract

The application provides a display device, which comprises a display panel, the display panel comprising a pixel driving circuit and a light emitting device, the pixel driving circuit comprising a driving transistor, a compensation module and a first reset module, the compensation module being electrically connected with one of a source electrode and a drain electrode of the driving transistor and a gate electrode of the driving transistor, and the first reset module being electrically connected with a reset voltage input end and the gate electrode of the driving transistor. The compensation module comprises a first compensation transistor and a second compensation transistor connected in series, and the first reset module comprises a first reset transistor and a second reset transistor connected in series. The display panel further comprises a gate driving circuit, the gate driving circuit comprising an output control module and a voltage stabilizing module, and the voltage stabilizing module being electrically connected with the output control module and a fourth power voltage input end. The application reduces the leakage current of the internal node through the double-gate structure and the voltage stabilizing module, and improves the display quality of the display device.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices include a display panel, which includes pixels and gate driving circuitry. Each pixel includes a light-emitting device and a pixel driving circuitry. The pixel driving circuitry is used to control the light emission of the light-emitting device, and the gate driving circuitry is used to generate a scan signal to control the operating timing of the pixel driving circuitry.

[0003] To improve the display uniformity of display devices, existing technologies typically add a node reset module or a threshold voltage compensation module to the pixel driving circuit. The node reset module resets the gate node of the driving transistor to a preset voltage before the start of the driving cycle to eliminate voltage residue from the previous frame. The threshold voltage compensation module compensates for the threshold voltage offset of the driving transistor to reduce brightness unevenness between different pixels caused by differences in the threshold voltage of the driving transistor. Furthermore, in driving circuits using hybrid pulse width modulation (PWM) and pulse amplitude modulation (PAM), the PWM module needs to be electrically connected to the gate node of the driving transistor to control the emission time. The gate driving circuit includes multiple cascaded shift register units, each including an output control module and multiple internal nodes. The output control module controls the signal output at the output terminal based on the voltage state of the internal nodes.

[0004] However, in pixel driving circuits and gate driving circuits, internal nodes typically need to be electrically connected to the source or drain of multiple transistors. Since leakage current still exists in the transistor's off state, the presence of multiple leakage paths exacerbates the voltage instability of these internal nodes. Specifically, the voltage of the gate node driving the transistor in the pixel driving circuit leaks through the leakage paths. This leakage causes the driving current output by the driving transistor to deviate from the expected value. This deviation causes a shift in the brightness of the light-emitting device, resulting in poor display uniformity of the display panel. Simultaneously, leakage in the internal nodes of the gate driving circuit causes a voltage shift in that node. This shift affects the operating state of the output control module, leading to abnormal signal waveforms at the output. These leakage problems in internal nodes ultimately result in low display quality for the display device.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display device that aims to improve the display quality of the display device.

[0007] This application provides a display device, which includes a display panel, a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a driving transistor, a compensation module and a first reset module. The compensation module is electrically connected to one of the source and drain of the driving transistor and the gate of the driving transistor. The first reset module is electrically connected to a reset voltage input terminal and the gate of the driving transistor.

[0008] In the above-mentioned display device, the compensation module includes a first compensation transistor and a second compensation transistor. One of the source and drain of the first compensation transistor is electrically connected to one of the source and drain of the driving transistor. The other of the source and drain of the first compensation transistor is electrically connected to one of the source and drain of the second compensation transistor. The other of the source and drain of the second compensation transistor is electrically connected to the gate of the driving transistor.

[0009] In the above-mentioned display device, the first reset module includes a first reset transistor and a second reset transistor. One of the source and drain of the first reset transistor is electrically connected to the reset voltage input terminal, and the other of the source and drain of the first reset transistor is electrically connected to one of the source and drain of the second reset transistor. The other of the source and drain of the second reset transistor is electrically connected to the gate of the driving transistor.

[0010] In the above-mentioned display device, the first reset module includes a first reset transistor, a second reset transistor, and a second storage capacitor. One of the source and drain of the first reset transistor is electrically connected to the reset voltage input terminal, the other of the source and drain of the first reset transistor is electrically connected to the first plate of the second storage capacitor, one of the source and drain of the second reset transistor is electrically connected to the second plate of the second storage capacitor, and the other of the source and drain of the second reset transistor is electrically connected to the gate of the driving transistor.

[0011] In the aforementioned display device, the pixel driving circuit further includes a voltage regulator module, which includes a first voltage regulator transistor and a second voltage regulator transistor. One of the source and drain of the first voltage regulator transistor is electrically connected to a reference voltage input terminal, and the other of the source and drain of the first voltage regulator transistor is electrically connected to the second plate of the second storage capacitor. One of the source and drain of the second voltage regulator transistor is electrically connected to the reference voltage input terminal, and the other of the source and drain of the second voltage regulator transistor is electrically connected to the first plate of the second storage capacitor.

[0012] In the above-described display device, the gate of the first reset transistor is electrically connected to the scan signal input terminal, and the gate of the second reset transistor is electrically connected to the scan signal input terminal; the gate of the first Zener transistor is electrically connected to the reset control signal input terminal, and the gate of the second Zener transistor is electrically connected to the reset control signal input terminal.

[0013] In the above-mentioned display device, the reset control signal input terminal is configured to input an effective level in a first stage, and the scan signal input terminal is configured to input an effective level in a second stage, wherein the first stage is earlier than the second stage.

[0014] In the above-described display device, the voltage at the reset voltage input terminal is lower than the voltage at the reference voltage input terminal.

[0015] In the above-described display device, the gate of the first compensation transistor is electrically connected to the first scan signal input terminal, and the gate of the second compensation transistor is electrically connected to the first scan signal input terminal.

[0016] In the above-mentioned display device, the pixel driving circuit further includes a pulse width modulation module, a light emission control module, and an isolation transistor; the pulse width modulation module is electrically connected to the light emission control module, the light emission control module is electrically connected to one of the source and drain of the isolation transistor, and the other of the source and drain of the isolation transistor is electrically connected to the gate of the driving transistor; the gate of the isolation transistor is electrically connected to a third power supply voltage input terminal.

[0017] In the above-described display device, the isolation transistor is configured to be in a closed state when the voltage at the gate of the driving transistor is less than or equal to the sum of the absolute values ​​of the voltage at the third power supply voltage input terminal and the threshold voltage of the isolation transistor.

[0018] In the aforementioned display device, the pixel driving circuit further includes a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a third reset transistor, and a first storage capacitor; one of the source and drain of the data writing transistor is electrically connected to a data signal input terminal, and the other of the source and drain of the data writing transistor is electrically connected to the other of the source and drain of the driving transistor; one of the source and drain of the first light-emitting control transistor is electrically connected to a first power supply voltage input terminal, and the other of the source and drain of the first light-emitting control transistor is electrically connected to the other of the source and drain of the driving transistor. The other is electrically connected; one of the source and drain of the second light-emitting control transistor is electrically connected to one of the source and drain of the driving transistor, and the other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device; the first plate of the first storage capacitor is electrically connected to the first power supply voltage input terminal, and the second plate of the first storage capacitor is electrically connected to the gate of the driving transistor; one of the source and drain of the third reset transistor is electrically connected to the second reset voltage input terminal, and the other of the source and drain of the third reset transistor is electrically connected to the anode of the light-emitting device.

[0019] This application also provides a display device, the display device including a display panel, the display panel including a gate driving circuit, the gate driving circuit including an output control module and a voltage regulator module, the output control module being electrically connected to a signal output terminal and a fourth power supply voltage input terminal, and the voltage regulator module being electrically connected to the output control module and the fourth power supply voltage input terminal.

[0020] In the aforementioned display device, the output control module includes a first output control transistor, a second output control transistor, and a first capacitor. One of the source and drain of the first output control transistor is electrically connected to the signal output terminal, and the other of the source and drain of the first output control transistor is electrically connected to the first plate of the first capacitor. One of the source and drain of the second output control transistor is electrically connected to the second plate of the first capacitor, and the other of the source and drain of the second output control transistor is electrically connected to the fourth power supply voltage input terminal. The gate of the first output control transistor is electrically connected to a first node, and the gate of the second output control transistor... The voltage regulator module includes a first voltage regulator transistor and a second voltage regulator transistor. One of the source and drain of the first voltage regulator transistor is electrically connected to the first plate of the first capacitor, and the other of the source and drain of the first voltage regulator transistor is electrically connected to the fourth power supply voltage input terminal. One of the source and drain of the second voltage regulator transistor is electrically connected to the second plate of the first capacitor, and the other of the source and drain of the second voltage regulator transistor is electrically connected to the fourth power supply voltage input terminal. The gate of the first voltage regulator transistor is electrically connected to the control signal input terminal, and the gate of the second voltage regulator transistor is electrically connected to the control signal input terminal.

[0021] In the above-mentioned display device, the gate driving circuit further includes a third output control transistor, the gate of which is electrically connected to the second node, one of the source and drain of which is electrically connected to the clock signal input terminal, and the other of the source and drain of which is electrically connected to the signal output terminal.

[0022] In the above-mentioned display device, the gate driving circuit further includes a second capacitor and a third capacitor. The first plate of the second capacitor is electrically connected to the second node, the second plate of the second capacitor is electrically connected to the signal output terminal, the first plate of the third capacitor is electrically connected to the first node, and the second plate of the third capacitor is electrically connected to the fourth power supply voltage input terminal.

[0023] The technical solution of this application establishes a dual-gate structure in the compensation module, connecting the first and second compensation transistors in series. This creates two levels of isolation between the gate of the driving transistor and either its source or drain, reducing leakage current along this path during threshold voltage compensation. Since the total leakage current of the two transistors connected in series is much smaller than that of a single transistor, the voltage stability of the driving transistor's gate after the compensation phase is improved. This reduces the offset of the driving current output by the driving transistor, suppresses brightness shift in the light-emitting device, and enhances the display uniformity of the display panel.

[0024] The technical solution of this application establishes a dual-gate structure in the first reset module, connecting the first and second reset transistors in series. This creates two levels of isolation between the reset voltage input terminal and the gate of the driving transistor, reducing leakage current in this path after the reset phase. Since the gate of the driving transistor typically remains at a low potential after reset, while the reset voltage input terminal typically provides a low-level voltage, the potential difference between the two drives leakage current from the gate of the driving transistor to the reset voltage input terminal. The dual-gate structure, by increasing the series connection of the off-state leakage impedances of the two transistors, significantly reduces the total leakage current in this leakage path. This ensures the stability of the gate voltage of the driving transistor during the light-emitting phase, improves the brightness stability of the light-emitting device, and enhances the display quality of the display device.

[0025] The technical solution of this application, in a first reset module including a second storage capacitor, uses a voltage regulator module to charge the voltages of both the first and second plates of the second storage capacitor to the voltage of the reference voltage input terminal before the reset phase begins, thus initializing the voltage difference across the second storage capacitor to zero. During the reset phase, after the first and second reset transistors are turned on, the voltage at the reset voltage input terminal is transmitted to the first plate of the second storage capacitor through the first reset transistor. This voltage jump is transmitted to the second plate through the coupling effect of the second storage capacitor. This transmission causes a corresponding voltage jump at the gate of the driving transistor, achieving the reset of the driving transistor's gate. In the holding phase after the reset phase ends, the first and second reset transistors are turned off, as are the first and second voltage regulator transistors. Due to the pre-charging effect of the voltage regulator module, both the first and second plates of the second storage capacitor are maintained near the voltage of the reference voltage input terminal. Even if there is off-state leakage in the first and second reset transistors, the voltage of both plates of the second storage capacitor is pre-charged to the reference voltage. This pre-charging forms a voltage stabilizing effect on the intermediate node of the leakage path, reduces the potential difference between the two ends of the leakage path, further reduces the leakage current, further improves the voltage stability of the gate of the driving transistor, and further improves the display quality of the display device.

[0026] The technical solution of this application adds a first capacitor between the first and second output control transistors of the output control module in the gate drive circuit through a voltage regulator module. The first and second voltage regulator transistors charge the voltage across the first capacitor to the voltage of the fourth power supply voltage input terminal at a specific time, thus initializing the voltage difference across the first capacitor to zero. During the output control phase, because the first capacitor is pre-charged to the same voltage in the leakage paths of the first and second output control transistors, this pre-charging provides voltage regulation at the intermediate node of the leakage path, reducing leakage current and improving the voltage stability of the first node. This suppresses abnormal signal waveforms at the signal output terminal, improves the output signal quality of the gate drive circuit, and enhances the display quality of the display device. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0028] Figure 2 A circuit diagram of a pixel in a first embodiment of the display device provided in this application.

[0029] Figure 3 A circuit diagram of a pixel in a second embodiment of the display device provided in this application.

[0030] Figure 4 Timing diagram of a second embodiment of the display device provided in this application.

[0031] Figure 5 A circuit diagram of a pixel in a third embodiment of the display device provided in this application.

[0032] Figure 6 A circuit diagram of a pixel in a fourth embodiment of the display device provided in this application.

[0033] Figure 7 A circuit diagram of the gate driving circuit in the fifth embodiment of the display device provided in this application. Detailed Implementation

[0034] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0036] The technical solutions of different embodiments of this application can be combined with each other.

[0037] In this application, the threshold voltage of a transistor refers to the minimum voltage difference between the gate and source required for the transistor to transition from the off state to the on state. For a P-type transistor, the threshold voltage is negative; for an N-type transistor, the threshold voltage is positive.

[0038] The display devices provided in the embodiments of this application may be, for example, organic light-emitting diode (OLED) display devices, mini light-emitting diode (Mini-LED) display devices, or micro light-emitting diode (Micro-LED) display devices. The embodiments of this application are described using organic light-emitting diode display devices as an example.

[0039] like Figure 1 As shown, the display device provided in the embodiments of this application includes a display panel (organic light-emitting diode display panel DP), a timing controller TCON, and a source driver chip SDIC. The organic light-emitting diode display panel DP includes a gate driver circuit GOA, multiple gate lines GL, multiple light-emitting control signal lines EM, multiple data lines DL, multiple first power lines VDD, multiple second power lines VSS, and multiple pixel units PX. The multiple pixel units are arranged in an array. The timing controller TCON is electrically connected to the source driver chip SDIC, and the timing controller TCON processes the received image data and control signals and outputs them to the source driver chip SDIC. The source driver chip SDIC is electrically connected to the multiple data lines DL, and the source driver chip SDIC converts the received image data into data signals and applies them to the multiple data lines DL. The gate driver circuit GOA is electrically connected to the multiple gate lines GL and the multiple light-emitting control signal lines EM, and the gate driver circuit GOA outputs scan signals and light-emitting control signals to the multiple gate lines GL and the multiple light-emitting control signal lines EM. Multiple gate lines GL extend along a first direction, and multiple data lines DL extend along a second direction, intersecting the first and second directions. Multiple pixel units PX are arranged in an array, each pixel unit PX being electrically connected to a corresponding gate line GL, a light emission control signal line EM, a data line DL, a first power supply line VDD, and a second power supply line VSS. Each pixel unit PX includes a pixel driving circuit and a light-emitting device. The pixel driving circuit provides a driving current to the light-emitting device based on the data signal provided by the data line DL and the control signal provided by the gate line GL and the light emission control signal line EM, thereby controlling the light emission of the light-emitting device.

[0040] In various embodiments of this application, the light-emitting device is an organic light-emitting diode (OLED). In other embodiments, the light-emitting device is also a quantum dot OLED, a micro OLED, or an inorganic OLED.

[0041] Example 1 like Figure 2 As shown, an embodiment of this application provides a display device, which includes a display panel and a plurality of pixels. Each pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit provides a driving current to the light-emitting device to control the light emission of the light-emitting device.

[0042] The pixel driving circuit includes a driving transistor TA3, a compensation module, a first reset module, a data writing transistor TA2, a first light-emitting control transistor TA1, a second light-emitting control transistor TA5, a third reset transistor TA7, and a first storage capacitor CA1.

[0043] The gate of driving transistor TA3 is electrically connected to node G, one of the source and drain of driving transistor TA3 is electrically connected to node B, and the other of the source and drain of driving transistor TA3 is electrically connected to node A. Driving transistor TA3 provides driving current to the light-emitting device according to the voltage of node G.

[0044] The gate of data writing transistor TA2 is electrically connected to the first scan signal input terminal PAM(n), which is used to input the control signal PAM(n). One of the source and drain of data writing transistor TA2 is electrically connected to the data signal input terminal Data, and the other of the source and drain of data writing transistor TA2 is electrically connected to the other of the source and drain of driving transistor TA3, i.e., electrically connected to node A. During the data writing phase, a valid level is input to the first scan signal input terminal PAM(n), and data writing transistor TA2 is turned on. The voltage at the data signal input terminal Data is applied to node A through data writing transistor TA2. Here, the term "valid level" refers to the level that enables the transistor to conduct.

[0045] The compensation module is electrically connected to one of the source and drain terminals of the driving transistor TA3, as well as the gate of the driving transistor TA3. The compensation module includes a first compensation transistor TA4_1 and a second compensation transistor TA4_2. The gate of the first compensation transistor TA4_1 is electrically connected to the first scan signal input terminal PAM(n), and one of the source and drain terminals of the first compensation transistor TA4_1 is electrically connected to one of the source and drain terminals of the driving transistor TA3, i.e., electrically connected to node B. The other of the source and drain terminals of the first compensation transistor TA4_1 is electrically connected to one of the source and drain terminals of the second compensation transistor TA4_2. The gate of the second compensation transistor TA4_2 is electrically connected to the first scan signal input terminal PAM(n), and the other of the source and drain terminals of the second compensation transistor TA4_2 is electrically connected to the gate of the driving transistor TA3, i.e., electrically connected to node G. The first compensation transistor TA4_1 and the second compensation transistor TA4_2 are connected in series between node B and node G, forming a threshold voltage compensation path together. During the threshold voltage compensation phase, the first scan signal input terminal PAM(n) receives an active level, and both the first compensation transistor TA4_1 and the second compensation transistor TA4_2 are simultaneously turned on. Nodes B and G are connected, and the gate of the driving transistor TA3 is connected to either its source or drain. The driving transistor TA3 is in a diode-connected state, and the voltage at node G is adjusted to compensate for the threshold voltage of the driving transistor TA3. During the hold and emission phases, the first scan signal input terminal PAM(n) receives an inactive level, and both the first compensation transistor TA4_1 and the second compensation transistor TA4_2 are simultaneously turned off, breaking the electrical connection between node B and node G. Here, the term "inactive level" refers to a level that cannot turn on the transistor, i.e., a level that can turn the transistor off.

[0046] The first reset module is electrically connected to the reset voltage input terminal ViG and the gate of the driving transistor TA3. The first reset module includes a first reset transistor TA6_1 and a second reset transistor TA6_2. The gate of the first reset transistor TA6_1 is electrically connected to the second scan signal input terminal PAM(n-1), which is used to input the control signal PAM(n-1). One of the source and drain of the first reset transistor TA6_1 is electrically connected to the reset voltage input terminal ViG, and the other of the source and drain of the first reset transistor TA6_1 is electrically connected to one of the source and drain of the second reset transistor TA6_2. The gate of the second reset transistor TA6_2 is electrically connected to the second scan signal input terminal PAM(n-1), and the other of the source and drain of the second reset transistor TA6_2 is electrically connected to the gate of the driving transistor TA3, i.e., electrically connected to node G. The first reset transistor TA6_1 and the second reset transistor TA6_2 are connected in series between the reset voltage input terminal ViG and node G, forming the node reset path together. During the reset phase, the second scan signal input terminal PAM(n-1) receives an active level, and both the first reset transistor TA6_1 and the second reset transistor TA6_2 are simultaneously turned on. The voltage at the reset voltage input terminal ViG is applied to node G through the first reset transistor TA6_1 and the second reset transistor TA6_2, and the voltage at node G is reset to the voltage at the reset voltage input terminal ViG. During the hold and illumination phases, the second scan signal input terminal PAM(n-1) receives an inactive level, and both the first reset transistor TA6_1 and the second reset transistor TA6_2 are simultaneously turned off, breaking the electrical connection between node G and the reset voltage input terminal ViG.

[0047] The gate of the first light-emitting control transistor TA1 is electrically connected to the light-emitting control signal input terminal EM. One of the sources and drains of the first light-emitting control transistor TA1 is electrically connected to the first power supply voltage input terminal VDD. The other of the sources and drains of the first light-emitting control transistor TA1 is electrically connected to the other of the sources and drains of the driving transistor TA3, i.e., electrically connected to node A. The gate of the second light-emitting control transistor TA5 is electrically connected to the light-emitting control signal input terminal EM. One of the sources and drains of the second light-emitting control transistor TA5 is electrically connected to the other of the sources and drains of the driving transistor TA3, i.e., electrically connected to node B. The other of the sources and drains of the second light-emitting control transistor TA5 is electrically connected to the anode of the light-emitting device, i.e., electrically connected to node C. During the light-emitting stage, the light-emitting control signal input terminal EM inputs an effective level, and the first light-emitting control transistor TA1 and the second light-emitting control transistor TA5 are turned on simultaneously. The first power supply voltage input terminal VDD, node A, driving transistor TA3, node B, node C and the light-emitting device form a current path. The driving transistor TA3 outputs a driving current according to the voltage of node G. The driving current flows through the light-emitting device and drives the light-emitting device to emit light.

[0048] The first plate of the first storage capacitor CA1 is electrically connected to the first power supply voltage input terminal VDD, and the second plate of the first storage capacitor CA1 is electrically connected to the gate of the driving transistor TA3, i.e., electrically connected to node G. The first storage capacitor CA1 is used to store the voltage of node G and maintain the voltage stability of node G during the holding and emission phases.

[0049] The gate of the third reset transistor TA7 is electrically connected to the control signal input terminal Discharge. One of the sources and drains of the third reset transistor TA7 is electrically connected to the second reset voltage input terminal ViA, and the other of the sources and drains of the third reset transistor TA7 is electrically connected to the anode of the light-emitting device, i.e., electrically connected to node C. The third reset transistor TA7 is used to reset node C during the reset phase, resetting the voltage at the anode of the light-emitting device to the voltage at the second reset voltage input terminal ViA.

[0050] The anode of the light-emitting device is electrically connected to node C, and the cathode of the light-emitting device is electrically connected to the second power supply voltage input terminal VSS. The light-emitting device is an organic light-emitting diode.

[0051] In this embodiment, all transistors in the pixel driving circuit are P-type transistors. For a P-type transistor, the transistor is turned on when the difference between the gate voltage and the source voltage is greater than or equal to the threshold voltage; the transistor is turned off when the difference between the gate voltage and the source voltage is less than the threshold voltage. The threshold voltage of a P-type transistor is negative. For a P-type transistor, the transistor is turned on when the gate voltage is lower than the source voltage. In this embodiment, the effective level is low, and the ineffective level is high.

[0052] The embodiments of this application improve the leakage current problem of node G by connecting a first compensation transistor TA4_1 and a second compensation transistor TA4_2 in series on the threshold voltage compensation path, and connecting a first reset transistor TA6_1 and a second reset transistor TA6_2 in series on the node reset path. Specifically, when both the first compensation transistor TA4_1 and the second compensation transistor TA4_2 are in the off state, the threshold voltage compensation path is blocked by two transistors connected in series, the total leakage impedance on the threshold voltage compensation path increases, and the leakage current is suppressed by the two transistors. Compared with the case of only a single compensation transistor, the leakage current is significantly reduced. Similarly, when both the first reset transistor TA6_1 and the second reset transistor TA6_2 are in the off state, the node reset path is blocked by two transistors connected in series, the leakage current on the node reset path is effectively suppressed, the leakage current from node G to the reset voltage input terminal ViG is significantly reduced, the voltage stability of node G is improved, the brightness stability of the light-emitting device is improved, and the display uniformity of the display device is improved.

[0053] Example 2 like Figure 3 and Figure 4 As shown, an embodiment of this application provides another display device that further improves the leakage problem of node G based on embodiment one.

[0054] The difference from Embodiment 1 is that the first reset module further includes a second storage capacitor CA2, and the pixel driving circuit further includes a voltage regulator module. The voltage regulator module includes a first voltage regulator transistor TA8_1 and a second voltage regulator transistor TA8_2.

[0055] The second storage capacitor CA2 is disposed between the first reset transistor TA6_1 and the second reset transistor TA6_2. Specifically, one of the source and drain of the first reset transistor TA6_1 is electrically connected to the reset voltage input terminal ViG, and the other of the source and drain of the first reset transistor TA6_1 is electrically connected to the first plate of the second storage capacitor CA2. One of the source and drain of the second reset transistor TA6_2 is electrically connected to the second plate of the second storage capacitor CA2, and the other of the source and drain of the second reset transistor TA6_2 is electrically connected to the gate of the driving transistor TA3, that is, electrically connected to node G.

[0056] The voltage regulator module is electrically connected to the first reset module and the reference voltage input terminal Vref. The gate of the first Zener transistor TA8_1 is electrically connected to the reset control signal input terminal RST. One of the source and drain of the first Zener transistor TA8_1 is electrically connected to the reference voltage input terminal Vref, and the other of the source and drain of the first Zener transistor TA8_1 is electrically connected to the second plate of the second storage capacitor CA2. The gate of the second Zener transistor TA8_2 is electrically connected to the reset control signal input terminal RST. One of the source and drain of the second Zener transistor TA8_2 is electrically connected to the reference voltage input terminal Vref, and the other of the source and drain of the second Zener transistor TA8_2 is electrically connected to the first plate of the second storage capacitor CA2.

[0057] In this embodiment, path 1 is formed between the first reset transistor TA6_1 and the second reset transistor TA6_2. Path 1 starts from node G, passes through the second reset transistor TA6_2, the second storage capacitor CA2, and the first reset transistor TA6_1 in sequence, and points to the reset voltage input terminal ViG. Path 2 is formed between the second reset transistor TA6_2 and the first Zener transistor TA8_1. Path 2 starts from node G, passes through the second reset transistor TA6_2 and the first Zener transistor TA8_1 in sequence, and points to the reference voltage input terminal Vref.

[0058] The voltage at the reset voltage input terminal ViG is lower than the voltage at the reference voltage input terminal Vref. During the holding phase, the voltage difference between node G and the reset voltage input terminal ViG is less than the voltage difference between node G and the reference voltage input terminal Vref. The leakage driving force of path 1 is lower than the original leakage driving force between node G and the reset voltage input terminal ViG, and the leakage current of path 1 decreases.

[0059] like Figure 4 As shown, the operation of the pixel driving circuit includes the first stage S1, the second stage S2, the third stage S3, and the fourth stage S4.

[0060] In the first stage S1, the reset control signal input terminal RST is active, meaning the reset control signal RST jumps to a low level, and the first Zener transistor TA8_1 and the second Zener transistor TA8_2 are turned on. The voltage at the reference voltage input terminal Vref is applied to the second plate of the second storage capacitor CA2 through the first Zener transistor TA8_1, and the voltage at the reference voltage input terminal Vref is applied to the first plate of the second storage capacitor CA2 through the second Zener transistor TA8_2. The voltages at the first and second plates of the second storage capacitor CA2 are both set to the voltage at the reference voltage input terminal Vref, and the voltage difference between the two plates of the second storage capacitor CA2 is initialized to zero. In the first stage S1, the control signal PAM(n-1), the control signal PAM(n), and the light emission control signal EM are all kept at a high level, while the first reset transistor TA6_1, the second reset transistor TA6_2, the data writing transistor TA2, the first compensation transistor TA4_1, the second compensation transistor TA4_2, the first light emission control transistor TA1, and the second light emission control transistor TA5 are all in the off state.

[0061] In the second stage S2, the reset control signal input terminal RST receives an invalid level, meaning the reset control signal RST remains high, and the first Zener transistor TA8_1 and the second Zener transistor TA8_2 are turned off. The second scan signal input terminal PAM(n-1) receives an active level, meaning the control signal PAM(n-1) is low, and the first reset transistor TA6_1 and the second reset transistor TA6_2 are turned on. The voltage at the reset voltage input terminal ViG is applied to the first plate of the second storage capacitor CA2. The voltage at the first plate of the second storage capacitor CA2 jumps from the voltage at the reference voltage input terminal Vref to the voltage at the reset voltage input terminal ViG. The voltage jump is the difference between the voltage at the reset voltage input terminal ViG and the voltage at the reference voltage input terminal Vref. This voltage jump is transmitted to the second plate of the second storage capacitor CA2 through capacitive coupling, causing a corresponding voltage jump at the second plate of the second storage capacitor CA2. The jump is the same as the voltage jump of the first plate of the second storage capacitor CA2. The voltage of the second plate of the second storage capacitor CA2 is transmitted to node G through the second reset transistor TA6_2, causing a voltage jump at node G and resetting node G. In the second stage S2, the control signal PAM(n) and the light emission control signal EM remain at a high level.

[0062] In the third stage S3, the control signal PAM(n-1) returns to a high level, and the first reset transistor TA6_1 and the second reset transistor TA6_2 are turned off. The first scan signal input terminal PAM(n) receives an effective level, i.e., the control signal PAM(n) is at a low level, and the data writing transistor TA2, the first compensation transistor TA4_1, and the second compensation transistor TA4_2 are turned on. The voltage of the data signal input terminal Data is applied to node A through the data writing transistor TA2, and the voltage of node A is set to the voltage of the data signal input terminal Data. At the same time, nodes B and G are turned on, and the gate of the driving transistor TA3 is connected to one of its source and drain terminals, putting the driving transistor TA3 in a diode-connected state. The voltage of node G is adjusted to compensate for the threshold voltage of the driving transistor TA3. In the third stage S3, the reset control signal RST, the control signal PAM(n-1), and the light emission control signal EM remain at a high level.

[0063] In the fourth stage S4, the control signal PAM(n) returns to a high level, the data writing transistor TA2, the first compensation transistor TA4_1, and the second compensation transistor TA4_2 are turned off, and the voltage of node G is maintained by the first storage capacitor CA1. The light emission control signal input terminal EM receives an effective level, i.e., the light emission control signal EM is at a low level, and the first light emission control transistor TA1 and the second light emission control transistor TA5 are turned on. The first power supply voltage input terminal VDD, node A, driving transistor TA3, node B, node C, and the light-emitting device form a current path. The driving transistor TA3 outputs a driving current according to the voltage of node G, and the driving current flows through the light-emitting device, driving the light-emitting device to emit light. In the fourth stage S4, the reset control signal RST, the control signal PAM(n-1), and the control signal PAM(n) are all kept at a high level.

[0064] During the holding and light-emitting periods of the fourth stage S4, both the first reset transistor TA6_1 and the second reset transistor TA6_2 are in the off state, as are the first Zener transistor TA8_1 and the second Zener transistor TA8_2. Even if there is leakage current in the first reset transistor TA6_1 and the second reset transistor TA6_2, since one of the source and drain of the first Zener transistor TA8_1 is electrically connected to the reference voltage input terminal Vref, and one of the source and drain of the second Zener transistor TA8_2 is also electrically connected to the reference voltage input terminal Vref, the voltage at the reference voltage input terminal Vref remains constant. Therefore, the first Zener transistor TA8_1 and the second Zener transistor TA8_2 provide voltage regulation for the second plate and the first plate of the second storage capacitor CA2. Specifically, if path 1 exhibits a leakage tendency, meaning the charge at node G leaks to the reset voltage input terminal ViG through the second reset transistor TA6_2, the second plate of the second storage capacitor CA2, the first plate of the second storage capacitor CA2, and the first reset transistor TA6_1, the voltage at the second plate of the second storage capacitor CA2 and the voltage at the first plate of the second storage capacitor CA2 will change slightly. Since one of the source and drain of the first Zener transistor TA8_1 is electrically connected to the reference voltage input terminal Vref, and the other of the source and drain of the first Zener transistor TA8_1 is electrically connected to the second plate of the second storage capacitor CA2, the presence of the first Zener transistor TA8_1 constrains the voltage at the reference voltage input terminal Vref, thus suppressing voltage changes at the second plate of the second storage capacitor CA2. Similarly, the presence of the second Zener transistor TA8_2 suppresses voltage changes at the first plate of the second storage capacitor CA2. The voltage between the second plate of the second storage capacitor CA2 and the first plate of the second storage capacitor CA2 remains relatively stable. The degree to which the voltage of the second plate of the second storage capacitor CA2 affects the voltage of node G through the second reset transistor TA6_2 is greatly reduced, and the leakage problem of node G is improved.

[0065] Similarly, if there is a leakage tendency in path 2, that is, the charge of node G leaks to the reference voltage input terminal Vref through the second reset transistor TA6_2 and the first Zener transistor TA8_1, since the voltage of the reference voltage input terminal Vref is constant and the voltage of the reset voltage input terminal ViG is lower than the voltage of the reference voltage input terminal Vref, the leakage driving force of path 2 is less than the leakage driving force of path 1, and the leakage current of path 2 is less than the leakage current of path 1.

[0066] The embodiments of this application further improve the leakage problem of node G by placing a second storage capacitor CA2 between the first reset transistor TA6_1 and the second reset transistor TA6_2, and by adding a first Zener transistor TA8_1 and a second Zener transistor TA8_2. The presence of the first Zener transistor TA8_1 and the second Zener transistor TA8_2 ensures that the voltage of the two plates of the second storage capacitor CA2 remains relatively stable during the holding and light-emitting phases. Even if leakage current exists in the first reset transistor TA6_1 and the second reset transistor TA6_2, the voltage variation of the plates of the second storage capacitor CA2 is suppressed. This improves the voltage stability of node G, enhances the brightness stability of the light-emitting device, and improves the display uniformity of the display device.

[0067] Example 3 like Figure 5 As shown, the pixel driving circuit of the display device provided in this embodiment adds a pulse width modulation module (PWM), a light emission control module (LEC), and an isolation transistor (TAC) to the pixel driving circuit of embodiment one.

[0068] To achieve more precise and stable grayscale control, a pulse width modulation (PWM) module was added to the original pulse amplitude modulation (PWM) module. The PWM module is electrically connected to the light emission control module (LEC). The PWM module outputs a pulse width modulation signal, and the pulse width of the signal determines the emission time of the light-emitting device.

[0069] like Figure 5 As shown, the pixel driving circuit also includes an isolation transistor TAC. The gate of the isolation transistor TAC is electrically connected to the third power supply voltage input terminal VGL. One of the source and drain of the isolation transistor TAC is electrically connected to the light-emitting control module LEC, and the other of the source and drain of the isolation transistor TAC is electrically connected to the gate of the driving transistor TA3, i.e., electrically connected to node G. The isolation transistor TAC is a P-type transistor. The light-emitting control module LEC is electrically connected to the pulse width modulation module PWM. The light-emitting control module LEC is electrically connected to the gate of the driving transistor TA3 through the isolation transistor TAC. The light-emitting control module LEC controls the voltage of the gate of the driving transistor TA3 according to the pulse width modulation signal to control the light-emitting time of the light-emitting device.

[0070] The isolation transistor TAC is used to automatically turn off when the voltage at node G drops below a preset threshold, thereby blocking the leakage path between node G and the pulse width modulation module (PWM) and preventing the voltage of node G from leaking out through the PWM module. Specifically, the gate of the isolation transistor TAC is electrically connected to the third power supply voltage input terminal VGL, which outputs a constant low-level signal. Under normal conditions, the isolation transistor TAC is in the on state, and node G is connected to the light emission control module LEC. When the voltage at node G drops to a level less than or equal to the sum of the absolute values ​​of the voltage at the third power supply voltage input terminal VGL and the threshold voltage of the isolation transistor TAC (i.e., when the voltage at node G is less than or equal to VGL + |Vth|), the voltage difference between the gate, source, and drain of the isolation transistor TAC is less than the threshold voltage of the isolation transistor TAC. The conduction condition of the isolation transistor TAC is no longer met, and the isolation transistor TAC automatically turns off. After the isolation transistor TAC is turned off, the electrical connection between node G and the light emission control module LEC is cut off, the leakage path between node G and the pulse width modulation module PWM is blocked, the voltage of node G will not continue to leak out through the pulse width modulation module PWM, the voltage of node G is maintained near VGL+|Vth|, and the voltage stability of node G is guaranteed.

[0071] Since the isolation transistor TAC is a P-type transistor, its threshold voltage is negative. When the potentials of the source and drain of the isolation transistor TAC drop to less than or equal to VGL + |Vth|, the isolation transistor TAC meets the turn-off condition, i.e., Vgs is less than Vth, and the isolation transistor TAC is in the off state. The turn-off of the isolation transistor TAC blocks the leakage path, preventing the potential of node G from being further pulled down by the pulse width modulation module PWM.

[0072] In other embodiments, the isolation transistor TAC is an N-type transistor. For an N-type transistor, the transistor is turned on when the difference between the gate voltage and the source voltage is greater than the threshold voltage; the transistor is turned off when the difference between the gate voltage and the source voltage is less than or equal to the threshold voltage. When the isolation transistor TAC is an N-type transistor, the gate of the isolation transistor TAC is electrically connected to the third power supply voltage input terminal VGH, and the third power supply voltage input terminal VGH outputs a constant high-level signal. Under normal circumstances, the isolation transistor TAC is in the on state, and node G is connected to the light-emitting control module LEC. When the voltage of node G rises to a level greater than or equal to the voltage of the third power supply voltage input terminal VGH minus the threshold voltage of the isolation transistor TAC, that is, when the voltage of node G is greater than or equal to VGH-Vth, the voltage difference between the gate, source, and drain of the isolation transistor TAC is less than or equal to the threshold voltage of the isolation transistor TAC, the on-condition of the isolation transistor TAC is no longer met, and the isolation transistor TAC is automatically turned off. After the isolation transistor TAC is turned off, the electrical connection between node G and the light emission control module LEC is cut off, the leakage path between node G and the pulse width modulation module PWM is blocked, the voltage of node G will not continue to leak out through the pulse width modulation module PWM, the voltage of node G is maintained near VGH-Vth, and the voltage stability of node G is guaranteed.

[0073] The embodiments of this application, by adding an isolation transistor TAC, effectively control the leakage path between node G and the pulse width modulation module PWM in a pixel driving circuit with hybrid pulse width modulation and pulse amplitude modulation. Under different pulse width modulation modes, the influence of the leakage path between node G of pixel units at different gray levels and the pulse width modulation module PWM is suppressed, the consistency of brightness performance at different gray levels is improved, and the display uniformity of the display device is enhanced.

[0074] Example 4 like Figure 6 As shown, the pixel driving circuit of the display device provided in this embodiment integrates the technical solutions of Embodiment 2 and Embodiment 3, and adds a pulse width modulation module (PWM), a light emission control module (LEC), and an isolation transistor (TAC) on the basis of Embodiment 2.

[0075] The gate of the isolation transistor TAC is electrically connected to the third power supply voltage input terminal VGL. One of the source and drain of the isolation transistor TAC is electrically connected to the light-emitting control module LEC, and the other of the source and drain of the isolation transistor TAC is electrically connected to the gate of the driving transistor TA3, i.e., electrically connected to node G. The isolation transistor TAC is a P-type transistor. The working principle of the isolation transistor TAC is the same as that of the isolation transistor TAC in Embodiment 3.

[0076] In this embodiment, the pixel driving circuit includes both the technical solution of improving the leakage current of node G through the second storage capacitor CA2, the first Zener transistor TA8_1 and the second Zener transistor TA8_2 in embodiment 2, and the technical solution of blocking the leakage current path between node G and pulse width modulation module PWM through the isolation transistor TAC in embodiment 3.

[0077] The embodiments of this application, through the comprehensive application of the above-described technical solutions, achieve a more comprehensive improvement in the voltage stability of node G. On the node reset path, the series connection of the first reset transistor TA6_1 and the second reset transistor TA6_2, along with the cooperation of the second storage capacitor CA2 with the first Zener transistor TA8_1 and the second Zener transistor TA8_2, suppresses leakage current from node G to the reset voltage input terminal ViG. On the threshold voltage compensation path, the series connection of the first compensation transistor TA4_1 and the second compensation transistor TA4_2 suppresses leakage current from node G to node B. On the connection path with the pulse width modulation module PWM, the isolation transistor TAC blocks the leakage path between node G and the pulse width modulation module PWM. The leakage problem of node G is effectively suppressed on multiple paths, significantly improving the voltage stability of node G, significantly improving the brightness stability of the light-emitting device, and significantly improving the display uniformity of the display device.

[0078] Example 5 like Figure 7 As shown, an embodiment of this application provides a display device, which includes a display panel and a gate driving circuit GOA.

[0079] The gate drive circuit GOA includes an input and control module 701, an output control module 702, and a voltage regulator module 703.

[0080] The input and control module 701 is electrically connected to the first node P, the second node Q, the fourth power supply voltage input terminal VGH, and the fifth power supply voltage input terminal VGL. The input and control module 701 includes a first input transistor TB10, a second input transistor TB11, a third input transistor TB12, a fourth input transistor TB13, a pull-down transistor TB9, a first reset transistor TB8, a second reset transistor TB7, and an isolation transistor TB6.

[0081] The gate of the first input transistor TB10 is electrically connected to the clock signal input terminal CK2. One of the sources and drains of the first input transistor TB10 is electrically connected to the signal input terminal Gin. The other of the sources and drains of the first input transistor TB10 is electrically connected to the third node R. The gate of the second input transistor TB11 is electrically connected to the third node R. One of the sources and drains of the second input transistor TB11 is electrically connected to the clock signal input terminal CK2. The other of the sources and drains of the second input transistor TB11 is electrically connected to the first node P. The gate of the third input transistor TB12 is electrically connected to the clock signal input terminal CK1. One of the sources and drains of the third input transistor TB12 is electrically connected to the other of the sources and drains of the fourth input transistor TB13. The other of the sources and drains of the third input transistor TB12 is electrically connected to the third node R. The gate of the fourth input transistor TB13 is electrically connected to the first node P. One of the sources and drains of the fourth input transistor TB13 is electrically connected to the fourth power supply voltage input terminal VGH. The gate of pull-down transistor TB9 is electrically connected to the clock signal input terminal CK2. One of the source and drain of pull-down transistor TB9 is electrically connected to the fifth power supply voltage input terminal VGL, and the other of the source and drain of pull-down transistor TB9 is electrically connected to the first node P. The gate of the first reset transistor TB8 is electrically connected to the second control signal input terminal CS. One of the source and drain of the first reset transistor TB8 is electrically connected to the fourth power supply voltage input terminal VGH, and the other of the source and drain of the first reset transistor TB8 is electrically connected to the first node P. The gate of the second reset transistor TB7 is electrically connected to the second control signal input terminal CS. One of the source and drain of the second reset transistor TB7 is electrically connected to the fourth power supply voltage input terminal VGH, and the other of the source and drain of the second reset transistor TB7 is electrically connected to the third node R. The gate of the isolation transistor TB6 is electrically connected to the fifth power supply voltage input terminal VGL. One of the source and drain of the isolation transistor TB6 is electrically connected to the third node R, and the other of the source and drain of the isolation transistor TB6 is electrically connected to the second node Q.

[0082] The output control module 702 is electrically connected to the signal output terminal Gout, the first node P, the second node Q, and the fourth power supply voltage input terminal VGH. The output control module 702 includes an output transistor TB1, a first output control transistor TB2, a second output control transistor TB3, a first capacitor CB3, a second capacitor CB1, and a third capacitor CB2.

[0083] The gate of output transistor TB1 is electrically connected to the second node Q. One of the source and drain of output transistor TB1 is electrically connected to the clock signal input terminal CK1, and the other of the source and drain of output transistor TB1 is electrically connected to the signal output terminal Gout. The first plate of the second capacitor CB1 is electrically connected to the second node Q, and the second plate of the second capacitor CB1 is electrically connected to the signal output terminal Gout.

[0084] The gate of the first output control transistor TB2 is electrically connected to the first node P. One of the source and drain of the first output control transistor TB2 is electrically connected to the signal output terminal Gout. The other of the source and drain of the first output control transistor TB2 is electrically connected to the first plate of the first capacitor CB3. The gate of the second output control transistor TB3 is electrically connected to the first node P. One of the source and drain of the second output control transistor TB3 is electrically connected to the second plate of the first capacitor CB3. The other of the source and drain of the second output control transistor TB3 is electrically connected to the fourth power supply voltage input terminal VGH. The first plate of the first capacitor CB3 is electrically connected to the other of the source and drain of the first output control transistor TB2. The second plate of the first capacitor CB3 is electrically connected to the source and drain of the second output control transistor TB3. The first plate of the third capacitor CB2 is electrically connected to the first node P. The second plate of the third capacitor CB2 is electrically connected to the fourth power supply voltage input terminal VGH.

[0085] The voltage regulator module 703 is electrically connected to the output control module 702 and the fourth power supply voltage input terminal VGH. The voltage regulator module 703 includes a first Zener transistor TB4 and a second Zener transistor TB5. The gate of the first Zener transistor TB4 is electrically connected to the first control signal input terminal CL. One of the source and drain of the first Zener transistor TB4 is electrically connected to the fourth power supply voltage input terminal VGH, and the other of the source and drain of the first Zener transistor TB4 is electrically connected to the first plate of the first capacitor CB3. The gate of the second Zener transistor TB5 is electrically connected to the first control signal input terminal CL. One of the source and drain of the second Zener transistor TB5 is electrically connected to the fourth power supply voltage input terminal VGH, and the other of the source and drain of the second Zener transistor TB5 is electrically connected to the second plate of the first capacitor CB3.

[0086] In this embodiment, the first input transistor TB10, the second input transistor TB11, the third input transistor TB12, the fourth input transistor TB13, the pull-down transistor TB9, the first reset transistor TB8, the second reset transistor TB7, and the isolation transistor TB6 in the input and control module 701 are all P-type transistors. Similarly, the output transistor TB1, the first output control transistor TB2, and the second output control transistor TB3 in the output control module 702 are all P-type transistors. Furthermore, the first voltage regulator transistor TB4 and the second voltage regulator transistor TB5 in the voltage regulator module 703 are both P-type transistors. The fourth power supply voltage input terminal VGH is a high-level signal input terminal, and the fifth power supply voltage input terminal VGL is a low-level signal input terminal.

[0087] The working cycle of the gate drive circuit GOA includes an initialization phase, a signal input phase, an output phase, and a reset phase.

[0088] During the initialization phase, the first control signal input terminal CL receives an active level, turning on the first Zener transistor TB4 and the second Zener transistor TB5. The voltage at the fourth power supply voltage input terminal VGH is applied to the first plate of the first capacitor CB3 through the first Zener transistor TB4, and the voltage at the fourth power supply voltage input terminal VGH is applied to the second plate of the first capacitor CB3 through the second Zener transistor TB5. Both the voltage at the first and second plates of the first capacitor CB3 are charged to the voltage at the fourth power supply voltage input terminal VGH, and the voltage difference across the first capacitor CB3 is initialized to zero. Subsequently, the first control signal input terminal CL receives an inactive level, turning off the first Zener transistor TB4 and the second Zener transistor TB5.

[0089] During the signal input phase, the start signal is input to the signal input terminal Gin, and the clock signal input terminal CK2 receives an active level. The first input transistor TB10 is turned on, and the start signal is transmitted to the third node R through the first input transistor TB10, pulling the voltage of the third node R low. The second input transistor TB11 is turned on, and the low-level signal from the clock signal input terminal CK2 is transmitted to the first node P through the second input transistor TB11, pulling the voltage of the first node P low. The isolation transistor TB6 is turned on, and the low-level signal from the third node R is transmitted to the second node Q, pulling the voltage of the second node Q low.

[0090] During the output phase, the voltage of the second node Q is low, the output transistor TB1 is turned on, and the low-level signal of the clock signal input terminal CK1 is transmitted to the signal output terminal Gout through the output transistor TB1. The signal output terminal Gout outputs a low-level signal. At this time, the clock signal input terminal CK2 inputs an invalid level, and the high-level signal of the clock signal input terminal CK2 is transmitted to the first node P through the second input transistor TB11. The voltage of the first node P is high, and the first output control transistor TB2 and the second output control transistor TB3 are turned off. During the output phase, even if there is leakage current in the first output control transistor TB2 and the second output control transistor TB3, since the first and second plates of the first capacitor CB3 have been pre-charged to the voltage of the fourth power supply voltage input terminal VGH during the initialization phase, although the first Zener transistor TB4 and the second Zener transistor TB5 are in the off state, the voltage of the first and second plates of the first capacitor CB3 is constrained by the pre-charge voltage. The voltage change of the first and second plates of the first capacitor CB3 is suppressed, the voltage stability of the first node P is improved, and the signal waveform quality of the signal output terminal Gout is improved.

[0091] During the reset phase, the second control signal input terminal CS receives a valid level, the first reset transistor TB8 and the second reset transistor TB7 are turned on, and the voltage of the fourth power supply voltage input terminal VGH is applied to the first node P through the first reset transistor TB8, resetting the voltage of the first node P to the voltage of the fourth power supply voltage input terminal VGH. The voltage of the fourth power supply voltage input terminal VGH is applied to the third node R through the second reset transistor TB7, resetting the voltage of the third node R to the voltage of the fourth power supply voltage input terminal VGH. After the output phase ends, when the clock signal input terminal CK2 receives a valid level, the pull-down transistor TB9 is turned on, and the voltage of the fifth power supply voltage input terminal VGL is applied to the first node P through the pull-down transistor TB9, pulling the voltage of the first node P down to the voltage of the fifth power supply voltage input terminal VGL.

[0092] The gate of isolation transistor TB6 is electrically connected to the fifth power supply voltage input terminal VGL. Under normal circumstances, isolation transistor TB6 is in the on state, and the third node R and the second node Q are connected. When the voltage of the third node R drops to less than or equal to the sum of the absolute values ​​of the voltage at the fifth power supply voltage input terminal VGL and the threshold voltage of isolation transistor TB6, the voltage difference between the gate, source, and drain of isolation transistor TB6 is less than the threshold voltage of isolation transistor TB6. Isolation transistor TB6 is automatically turned off, the electrical connection between the third node R and the second node Q is broken, and the leakage path between the third node R and the second node Q is blocked.

[0093] In various embodiments of this application, the transistors in the pixel driving circuit are all P-type transistors. The P-type transistors are fabricated using a low-temperature polysilicon process or an oxide semiconductor process. In other embodiments, the transistors in the pixel driving circuit are all N-type transistors, or some transistors in the pixel driving circuit are P-type transistors and some are N-type transistors. When the types of transistors are different, the polarity of the control signal is adjusted accordingly to achieve transistor turn-on and turn-off control.

[0094] In various embodiments of this application, the voltage at the fourth power supply voltage input terminal VDD is positive, and the voltage at the second power supply voltage input terminal VSS is negative or grounded. The voltage at the reset voltage input terminal ViG is negative and is used to reset node G. The voltage at the second reset voltage input terminal ViA is negative and is used to reset node C. The voltage at the reference voltage input terminal Vref is negative, and the voltage at the reset voltage input terminal ViG is lower than the voltage at the reference voltage input terminal Vref. The voltage at the third power supply voltage input terminal VGL is negative and is used to control the isolation transistor TAC.

[0095] The technical solution of this application establishes a dual-gate structure in the compensation module, where the first compensation transistor TA4_1 and the second compensation transistor TA4_2 are connected in series. This creates two levels of isolation between the gate of the driving transistor TA3 and either its source or drain, reducing leakage current in this path during threshold voltage compensation. Since the total leakage current of the two transistors connected in series is much smaller than that of a single transistor, the voltage stability of the gate of the driving transistor TA3 after the compensation stage is improved. This reduces the offset of the driving current output by the driving transistor TA3, suppresses brightness shift in the light-emitting device, and improves the display uniformity of the display panel.

[0096] The technical solution of this application establishes a dual-gate structure in the first reset module, where the first reset transistor TA6_1 and the second reset transistor TA6_2 are connected in series. This creates two levels of isolation between the reset voltage input terminal ViG and the gate of the driving transistor TA3, reducing the leakage current in this path after the reset phase. Since the gate of the driving transistor TA3 typically remains at a low potential after reset, while the reset voltage input terminal ViG typically provides a low-level voltage, the potential difference between the two drives leakage current from the gate of the driving transistor TA3 to the reset voltage input terminal ViG. The dual-gate structure, by increasing the series connection of the off-state leakage impedances of the two transistors, significantly reduces the total leakage current in this leakage path. This ensures the stability of the gate voltage of the driving transistor TA3 during the light-emitting phase, improves the brightness stability of the light-emitting device, and enhances the display quality of the display device.

[0097] The technical solution of this application, in a first reset module including a second storage capacitor CA2, uses a voltage regulator module to charge the voltages of both the first and second plates of the second storage capacitor CA2 to the voltage of the reference voltage input terminal Vref before the reset phase begins, thus initializing the voltage difference across the second storage capacitor CA2 to zero. During the reset phase, after the first reset transistor TA6_1 and the second reset transistor TA6_2 are turned on, the voltage at the reset voltage input terminal ViG is transmitted to the first plate of the second storage capacitor CA2 through the first reset transistor TA6_1. This voltage jump is transmitted to the second plate through the coupling effect of the second storage capacitor CA2. This transmission causes a corresponding voltage jump at the gate of the driving transistor TA3, achieving the reset of the gate of the driving transistor TA3. During the holding phase after the reset phase ends, the first reset transistor TA6_1 and the second reset transistor TA6_2 are turned off, as are the first voltage regulator transistor TA8_1 and the second voltage regulator transistor TA8_2. Due to the pre-charging effect of the voltage regulator module, both the first and second plates of the second storage capacitor CA2 are maintained near the voltage of the reference voltage input terminal Vref. Even if the first reset transistor TA6_1 and the second reset transistor TA6_2 have off-state leakage, the voltage of both plates of the second storage capacitor CA2 is pre-charged to the reference voltage. This pre-charging forms a voltage stabilizing effect on the intermediate node of the leakage path, reduces the potential difference between the two ends of the leakage path, further reduces the leakage current, further improves the voltage stability of the gate of the driving transistor TA3, and further improves the display quality of the display device.

[0098] The technical solution of this application adds a first capacitor CB3 between the first output control transistor TB2 and the second output control transistor TB3 in the gate drive circuit GOA through a voltage regulator module. The first voltage regulator transistor TB4 and the second voltage regulator transistor TB5 charge the voltage across the first capacitor CB3 to the voltage of the fourth power supply voltage input terminal VGH at specific times. This charging initializes the voltage difference across the first capacitor CB3 to zero. During the output control phase, because the first capacitor CB3 is pre-charged to the same voltage in the leakage path of the first output control transistor TB2 and the second output control transistor TB3, this pre-charging has a voltage stabilizing effect on the intermediate node of the leakage path, reducing leakage current, improving the voltage stability of the first node P, suppressing abnormal signal waveforms at the signal output terminal Gout, improving the output signal quality of the gate drive circuit GOA, and enhancing the display quality of the display device.

[0099] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a driving transistor, a compensation module, and a first reset module. The compensation module is electrically connected to one of the source and drain of the driving transistor and the gate of the driving transistor. The first reset module is electrically connected to a reset voltage input terminal and the gate of the driving transistor.

2. The display device according to claim 1, characterized in that, The compensation module includes a first compensation transistor and a second compensation transistor. One of the source and drain of the first compensation transistor is electrically connected to one of the source and drain of the driving transistor. The other of the source and drain of the first compensation transistor is electrically connected to one of the source and drain of the second compensation transistor. The other of the source and drain of the second compensation transistor is electrically connected to the gate of the driving transistor.

3. The display device according to claim 2, characterized in that, The first reset module includes a first reset transistor and a second reset transistor. One of the source and drain of the first reset transistor is electrically connected to the reset voltage input terminal. The other of the source and drain of the first reset transistor is electrically connected to one of the source and drain of the second reset transistor. The other of the source and drain of the second reset transistor is electrically connected to the gate of the driving transistor.

4. The display device according to claim 2, characterized in that, The first reset module includes a first reset transistor, a second reset transistor, and a second storage capacitor. One of the source and drain of the first reset transistor is electrically connected to the reset voltage input terminal, the other of the source and drain of the first reset transistor is electrically connected to the first plate of the second storage capacitor, one of the source and drain of the second reset transistor is electrically connected to the second plate of the second storage capacitor, and the other of the source and drain of the second reset transistor is electrically connected to the gate of the driving transistor.

5. The display device according to claim 4, characterized in that, The pixel driving circuit further includes a voltage regulator module, which includes a first voltage regulator transistor and a second voltage regulator transistor. One of the source and drain of the first voltage regulator transistor is electrically connected to a reference voltage input terminal, and the other of the source and drain of the first voltage regulator transistor is electrically connected to the second plate of the second storage capacitor. One of the source and drain of the second voltage regulator transistor is electrically connected to the reference voltage input terminal, and the other of the source and drain of the second voltage regulator transistor is electrically connected to the first plate of the second storage capacitor.

6. The display device according to claim 5, characterized in that, The gate of the first reset transistor is electrically connected to the scan signal input terminal, and the gate of the second reset transistor is electrically connected to the scan signal input terminal; The gate of the first Zener transistor is electrically connected to the reset control signal input terminal, and the gate of the second Zener transistor is electrically connected to the reset control signal input terminal.

7. The display device according to claim 6, characterized in that, The reset control signal input terminal is configured to input an effective level in the first stage, and the scan signal input terminal is configured to input an effective level in the second stage, wherein the first stage precedes the second stage.

8. The display device according to claim 5, characterized in that, The voltage at the reset voltage input terminal is lower than the voltage at the reference voltage input terminal.

9. The display device according to claim 2, characterized in that, The gate of the first compensation transistor is electrically connected to the first scan signal input terminal, and the gate of the second compensation transistor is electrically connected to the first scan signal input terminal.

10. The display device according to any one of claims 1 to 9, characterized in that, The pixel driving circuit also includes a pulse width modulation module, a light emission control module, and an isolation transistor; The pulse width modulation module is electrically connected to the light emission control module, the light emission control module is electrically connected to one of the source and drain of the isolation transistor, and the other of the source and drain of the isolation transistor is electrically connected to the gate of the driving transistor. The gate of the isolation transistor is electrically connected to the third power supply voltage input terminal.

11. The display device according to claim 10, characterized in that, The isolation transistor is configured to be in a closed state when the voltage at the gate of the driving transistor is less than or equal to the sum of the absolute values ​​of the voltage at the third power supply voltage input terminal and the threshold voltage of the isolation transistor.

12. The display device according to any one of claims 1 to 9, characterized in that, The pixel driving circuit also includes a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a third reset transistor, and a first storage capacitor. One of the source and drain of the data writing transistor is electrically connected to the data signal input terminal, and the other of the source and drain of the data writing transistor is electrically connected to the other of the source and drain of the driving transistor. One of the source and drain of the first light-emitting control transistor is electrically connected to the first power supply voltage input terminal, and the other of the source and drain of the first light-emitting control transistor is electrically connected to the other of the source and drain of the driving transistor. One of the source and drain of the second light-emitting control transistor is electrically connected to one of the source and drain of the driving transistor, and the other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device. The first plate of the first storage capacitor is electrically connected to the first power supply voltage input terminal, and the second plate of the first storage capacitor is electrically connected to the gate of the driving transistor. One of the source and drain of the third reset transistor is electrically connected to the second reset voltage input terminal, and the other of the source and drain of the third reset transistor is electrically connected to the anode of the light-emitting device.

13. A display device, characterized in that, The display device includes a display panel, the display panel includes a gate driving circuit, the gate driving circuit includes an output control module and a voltage regulator module, the output control module is electrically connected to a signal output terminal and a fourth power supply voltage input terminal, and the voltage regulator module is electrically connected to the output control module and the fourth power supply voltage input terminal.

14. The display device according to claim 13, characterized in that, The output control module includes a first output control transistor, a second output control transistor, and a first capacitor. One of the source and drain of the first output control transistor is electrically connected to the signal output terminal, and the other of the source and drain of the first output control transistor is electrically connected to the first plate of the first capacitor. One of the source and drain of the second output control transistor is electrically connected to the second plate of the first capacitor, and the other of the source and drain of the second output control transistor is electrically connected to the fourth power supply voltage input terminal. The gate of the first output control transistor is electrically connected to the first node, and the gate of the second output control transistor is electrically connected to the first node. The voltage regulator module includes a first voltage regulator transistor and a second voltage regulator transistor. One of the source and drain of the first voltage regulator transistor is electrically connected to the first plate of the first capacitor, and the other of the source and drain of the first voltage regulator transistor is electrically connected to the fourth power supply voltage input terminal. One of the source and drain of the second voltage regulator transistor is electrically connected to the second plate of the first capacitor, and the other of the source and drain of the second voltage regulator transistor is electrically connected to the fourth power supply voltage input terminal. The gate of the first voltage regulator transistor is electrically connected to the control signal input terminal, and the gate of the second voltage regulator transistor is electrically connected to the control signal input terminal.

15. The display device according to claim 14, characterized in that, The gate drive circuit further includes a third output control transistor, the gate of which is electrically connected to the second node, one of the source and drain of which is electrically connected to the clock signal input terminal, and the other of the source and drain of which is electrically connected to the signal output terminal.

16. The display device according to claim 15, characterized in that, The gate drive circuit further includes a second capacitor and a third capacitor. The first plate of the second capacitor is electrically connected to the second node, the second plate of the second capacitor is electrically connected to the signal output terminal, the first plate of the third capacitor is electrically connected to the first node, and the second plate of the third capacitor is electrically connected to the fourth power supply voltage input terminal.

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