LDO circuit

Abstract

The present specification relates to the technical field of circuit, and particularly relates to a LDO circuit. The LDO circuit comprises a comparison circuit, a switched capacitor circuit, a power tube and a coupling capacitor; the comparison circuit is used for comparing an output voltage of the power tube with a first reference voltage and a second reference voltage respectively according to a clock signal, generating a first control signal according to a comparison result of the output voltage and the first reference voltage, and generating a second control signal according to a comparison result of the output voltage and the second reference voltage; the switched capacitor circuit is used for adjusting a charge of the coupling capacitor according to the first control signal to increase the output voltage of the power tube when the output voltage is lower than the first reference voltage, and adjusting the charge of the coupling capacitor according to the second control signal to decrease the output voltage of the power tube when the output voltage is higher than the second reference voltage; and the coupling capacitor is connected with a control end of the power tube. The LDO circuit has higher stability.

Description

Technical Field

[0001] This specification relates to the field of circuit technology, and in particular to an LDO circuit. Background Technology

[0002] With the rapid development of electronic technology, LDO (Low Dropout Regulator) circuits have been widely used. For example, LDO circuits can be applied to power management chips to achieve voltage regulation.

[0003] Traditional LDO circuits are implemented using operational amplifiers. The load current often varies over a wide range, for example, fluctuating between 1µA and 100mA. This large fluctuation in load current causes a significant shift in the dominant pole of the LDO circuit. This shift may cause the dominant pole to move closer to the secondary pole of the operational amplifier, reducing the phase margin and affecting the stability of the LDO circuit. Summary of the Invention

[0004] This specification provides an LDO circuit with high stability.

[0005] This specification provides an LDO circuit, which includes a comparator circuit, a switched capacitor circuit, a power transistor, and a coupling capacitor. The comparator circuit is used to compare the output voltage of the power transistor with a first reference voltage and a second reference voltage according to a clock signal, generate a first control signal based on the comparison result of the output voltage and the first reference voltage, and transmit the first control signal to the switched capacitor circuit; and generate a second control signal based on the comparison result of the output voltage and the second reference voltage, and transmit the second control signal to the switched capacitor circuit; the second reference voltage is greater than the first reference voltage. The switched capacitor circuit is used to perform charge transfer on the coupling capacitor according to a first control signal to increase the output voltage of the power transistor when the output voltage is lower than the first reference voltage, and to perform charge transfer on the coupling capacitor according to a second control signal to decrease the output voltage of the power transistor when the output voltage is higher than the second reference voltage; the coupling capacitor is connected to the control terminal of the power transistor.

[0006] In some embodiments, the comparison circuit includes a first comparison circuit and a second comparison circuit; The first comparison circuit is used to compare the output voltage with the first reference voltage according to the clock signal, generate a first control signal according to the comparison result of the output voltage and the first reference voltage, and transmit the first control signal to the switched capacitor circuit. The second comparison circuit is used to compare the output voltage with the second reference voltage according to the clock signal, generate a second control signal according to the comparison result of the output voltage and the second reference voltage, and transmit the second control signal to the switched capacitor circuit.

[0007] In some embodiments, the first comparison circuit includes a first comparator and N inverters; N=1, the output of the first comparator is connected to the input of the inverter; or, N≥2, the N inverters are cascaded, and the output of the first comparator is connected to the input of the first inverter among the N inverters. The second comparison circuit includes a second comparator and M inverters; M=1, the output of the second comparator is connected to the input of the inverter; or, M≥2, the M inverters are cascaded, and the output of the second comparator is connected to the input of the first inverter among the M inverters.

[0008] In some embodiments, the first control signal includes a first reset signal and a first charge transfer signal; when N=1, the first reset signal is a signal generated by the first comparator, and the first charge transfer signal is a signal generated by the inverter; when N≥2, the first reset signal is a signal generated by the (N-1)th inverter among the N inverters, and the first charge transfer signal is a signal generated by the Nth inverter among the N inverters. The second control signal includes a second reset signal and a second charge transfer signal; when M=1, the second reset signal is a signal generated by the second comparator, and the second charge transfer signal is a signal generated by the inverter; when M≥2, the second reset signal is a signal generated by the (M-1)th inverter among the M inverters, and the second charge transfer signal is a signal generated by the Mth inverter among the M inverters.

[0009] In some embodiments, the switched capacitor circuit includes a first switched capacitor circuit and a second switched capacitor circuit. The first switched capacitor circuit is used to perform charge transfer on the coupling capacitor according to the first control signal, so as to increase the output voltage of the power transistor when the output voltage is lower than the first reference voltage; The second switched capacitor circuit is used to perform charge transfer on the coupling capacitor according to the second control signal, so as to reduce the output voltage of the power transistor when the output voltage is higher than the second reference voltage.

[0010] In some embodiments, the first switched capacitor circuit includes a first capacitor and a first switching circuit, the first switching circuit being configured to transfer charge between the first capacitor and the coupling capacitor according to a first control signal; the second switched capacitor circuit includes a second capacitor and a second switching circuit, the second switching circuit being configured to transfer charge between the second capacitor and the coupling capacitor according to a second control signal.

[0011] In some embodiments, the first switching circuit includes a first reset switch and a first charge transfer switch, the first end of the first capacitor is connected to the first end of the first reset switch and the first end of the first charge transfer switch respectively, the second end of the first capacitor and the second end of the first reset switch are connected to the low voltage end, and the second end of the first charge transfer switch is connected to the coupling capacitor. The first control signal includes a first reset signal and a first charge transfer signal. The first reset signal is used to control the opening and closing of the first reset switch to perform a reset operation on the first capacitor. The first charge transfer signal is used to control the opening and closing of the first charge transfer switch to transfer charge between the first capacitor and the coupling capacitor. The second switching circuit includes a second reset switch and a second charge transfer switch. The first end of the second capacitor is connected to the first end of the second reset switch and the first end of the second charge transfer switch, respectively. The second end of the second capacitor is connected to the low-voltage end, the second end of the second reset switch is connected to the high-voltage end, and the second end of the second charge transfer switch is connected to the coupling capacitor. The second control signal includes a second reset signal and a second charge transfer signal. The second reset signal is used to control the on / off state of the second reset switch to perform a reset operation on the second capacitor. The second charge transfer signal is used to control the on / off state of the second charge transfer switch to transfer charge between the second capacitor and the coupling capacitor.

[0012] In some embodiments, the power transistor is a P-type switching transistor, and the switched capacitor circuit is used to transfer charge out of the coupling capacitor according to a first control signal and transfer charge into the coupling capacitor according to a second control signal; or, the power transistor is an N-type switching transistor, and the switched capacitor circuit is used to transfer charge into the coupling capacitor according to a first control signal and transfer charge out of the coupling capacitor according to a second control signal.

[0013] In some embodiments, the first end of the power transistor is connected to a high-voltage terminal, and the second end of the power transistor is connected to an external capacitor. The second end of the power transistor is used to provide the output voltage.

[0014] In some embodiments, the LDO circuit further includes an enable transistor; The first end of the enable transistor and the first end of the power transistor are connected to the high-voltage end. The second end of the enable transistor is connected to the control end of the power transistor; The control terminal of the enable transistor is used to receive the enable signal; The second terminal of the power transistor is used to provide the output voltage.

[0015] In some embodiments, the comparison circuit includes a comparator; The comparator includes a first differential branch, a second differential branch, and a control transistor; The first differential branch is used to receive a first input voltage and adjust the potential of the first output node according to the first input voltage. The second differential branch is used to receive a second input voltage and adjust the potential of the second output node according to the second input voltage. The first output node and / or the second output node are used to output a signal that can characterize the comparison result between the first input voltage and the second input voltage. The control transistor is used to control the operating timing of the comparison circuit according to the clock signal.

[0016] In some embodiments, the first differential branch includes a first node reset circuit, a first latch, a first differential input transistor, and a first differential reset transistor, and the second differential branch includes a second node reset circuit, a second latch, a second differential input transistor, and a second differential reset transistor. The first node reset circuit is used to perform a potential reset on the first output node according to the clock signal; The second node reset circuit is used to perform a potential reset on the second output node according to the clock signal; The first differential input transistor is used to adjust the potential of the first output node according to the first input voltage; The second differential input transistor is used to adjust the potential of the second output node according to the second input voltage; The first latch transistor and the second latch transistor are cross-coupled to amplify the potential difference between the first output node and the second output node and to latch the potential of the first output node and the potential of the second output node. The first differential reset transistor is used to perform a potential reset on the first differential input transistor according to the clock signal; The second differential reset transistor is used to perform a potential reset on the second differential input transistor according to the clock signal.

[0017] The LDO circuit in this embodiment compares the output voltage with a first reference voltage and a second reference voltage. Based on the comparison result, it controls a switched capacitor circuit to transfer charge to the coupling capacitor, thereby dynamically adjusting the control terminal voltage of the power transistor and stabilizing the LDO circuit's output voltage between the first and second reference voltages. Since no operational amplifier is involved, the problem of dominant pole drift with load changes is avoided, enhancing stability. Furthermore, the LDO circuit in this embodiment uses a comparator circuit instead of an operational amplifier to adjust the control terminal voltage of the power transistor. Compared to an operational amplifier, the comparator circuit operates in a switching state, resulting in significantly lower static power consumption than an operational amplifier that requires continuous conduction. Moreover, the switched capacitor circuit can respond quickly to changes in output voltage without relying on the bandwidth of the operational amplifier to maintain response speed. Therefore, the LDO circuit can simultaneously achieve low power consumption and fast transient response. Additionally, the LDO circuit in this embodiment adjusts the control terminal voltage of the power transistor by adjusting the charge on the coupling capacitor. The adjustable range of the power transistor's control terminal voltage is no longer limited by the operational amplifier's output swing. In scenarios requiring high load current, there is no need to increase the size of the power transistor to improve load capacity, effectively reducing the size of the LDO circuit and chip area overhead. Therefore, the LDO circuit in the embodiments of this specification eliminates the operational amplifier found in traditional LDOs. While ensuring fast transient response, it avoids stability issues caused by dominant pole drift, and reduces power consumption and area cost, thus possessing significant performance advantages. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. The drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the functional structure of a traditional LDO circuit in related technologies; Figure 2 This is a functional structure diagram of the comparison circuit, coupling capacitor, and power transistor in the embodiments of this specification; Figure 3 This is a functional structure diagram of the switched capacitor circuit in the embodiments of this specification; Figure 4 This is a timing diagram of the LDO circuit in the embodiments of this specification; Figure 5 This is a schematic diagram of the functional structure of the comparator in the embodiments of this specification.

[0020] The following are the reference numerals used in the embodiments of this specification: 1. Comparator circuit; 11. First comparator circuit; 111. First comparator; 112. First inverter; 12. Second comparator circuit; 121. Second comparator; 122. Second inverter; 2. Switched capacitor circuit; 21. First switched capacitor circuit; 211. First capacitor; 212. First reset switch; 213. First charge transfer switch; 22. Second switched capacitor circuit; 221. Second capacitor; 222. Second reset switch; 223. Second charge transfer switch; 3. Power transistor; 4. Coupling capacitor; 5. Enable transistor. Detailed Implementation

[0021] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. The specific embodiments described herein are only used to explain this disclosure, and not to limit this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure are within the scope of protection of this disclosure. In addition, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0022] Figure 1A functional structure diagram of the aforementioned conventional LDO circuit is shown. This conventional LDO circuit may include an operational amplifier (OP), a power transistor (MP), a first resistor R1, a second resistor R2, and an external capacitor Cext. The power transistor MP can be a P-type switching transistor. The source of the power transistor MP is connected to the high-voltage terminal, the drain of the power transistor MP is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the low-voltage terminal. The gate of the power transistor MP is connected to the output terminal of the operational amplifier OP. The negative input terminal of the operational amplifier OP is connected to the reference voltage VBG, and the positive input terminal of the operational amplifier OP is connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2. The drain of the power transistor MP is used to provide the output voltage Vout of the LDO circuit. The drain of the power transistor MP is connected to the first terminal of the external capacitor Cext, and the second terminal of the external capacitor Cext is connected to the low-voltage terminal. The high-voltage terminal can be, for example, a power supply, and the low-voltage terminal can be, for example, ground. Thus, in the aforementioned conventional LDO circuit, the first resistor R1 and the second resistor R2 can form a series voltage divider feedback network. The voltage divider feedback network samples the output voltage Vout of the LDO circuit and transmits the sampled voltage to the positive input of the operational amplifier OP. The operational amplifier OP amplifies the difference between the sampled voltage and the reference voltage VBG, generating a control voltage and transmitting it to the gate of the power transistor MP. This control voltage can be used to change the conduction level of the power transistor MP, compensating for output voltage Vout fluctuations caused by changes in load current, thereby stabilizing the LDO circuit's output voltage Vout. An external capacitor Cext provides transient current to the load, reducing the ripple in the LDO's output voltage Vout.

[0023] The traditional LDO circuit described above is implemented using an operational amplifier. The power consumption of an operational amplifier is directly proportional to its bandwidth. To improve the response speed of the LDO circuit, the bandwidth of the operational amplifier needs to be increased. However, increasing the bandwidth of the operational amplifier will increase the power consumption of the LDO circuit. Therefore, the traditional LDO circuit described above cannot simultaneously achieve both high response speed and high power consumption. Furthermore, in practical applications, the load current often varies significantly. For example, the load current can fluctuate between 1µA and 100mA. This large fluctuation in load current can cause a significant shift in the dominant pole of the LDO circuit. This shift may cause the dominant pole to move closer to the secondary pole of the operational amplifier, resulting in a decrease in phase margin and thus affecting the stability of the LDO circuit. Additionally, the limited output swing of the operational amplifier restricts the adjustable range of the gate voltage of the power transistor (MP). For scenarios with large load currents, the size of the power transistor (MP) needs to be increased to ensure that the LDO circuit can provide sufficient load-driving capability, which will increase the size of the LDO circuit.

[0024] Please refer to the following: Figure 2 and Figure 3This specification provides an LDO (Low Dropout Regulator) circuit. The LDO circuit can provide a relatively stable output voltage Vout.

[0025] The LDO circuit may include a comparator circuit 1, a switched capacitor circuit 2, a power transistor 3, and a coupling capacitor 4. The comparator circuit 1 is connected to the switched capacitor circuit 2 and the power transistor 3. The switched capacitor circuit 2 is connected to the comparator circuit 1 and the power transistor 3. The power transistor 3 is connected to the comparator circuit 1, the switched capacitor circuit 2, and the coupling capacitor 4. The coupling capacitor 4 is connected to the power transistor 3.

[0026] Comparator circuit 1 can compare the output voltage Vout of power transistor 3 with the first reference voltage VRE1 and the second reference voltage VRE2 according to the clock signal clkc. It can generate a first control signal based on the comparison result of output voltage Vout and the first reference voltage VRE1, and transmit the first control signal to switched capacitor circuit 2. It can also generate a second control signal based on the comparison result of output voltage Vout and the second reference voltage VRE2, and transmit the second control signal to switched capacitor circuit 2. The second reference voltage VRE2 is greater than the first reference voltage VRE1. Coupling capacitor 4 is connected to the control terminal of power transistor 3. Switched capacitor circuit 2 can perform charge transfer on coupling capacitor 4 according to the first control signal, adjusting the charge of coupling capacitor 4 to adjust the control terminal voltage Vctrl of power transistor 3, thereby increasing the output voltage Vout of power transistor 3 when the output voltage Vout is lower than the first reference voltage VRE1; conversely, it can perform charge transfer on coupling capacitor 4 according to the second control signal, adjusting the charge of coupling capacitor 4 to adjust the control terminal voltage Vctrl of power transistor 3, thereby decreasing the output voltage Vout of power transistor 3 when the output voltage Vout is higher than the second reference voltage VRE2.

[0027] In the LDO circuit of this embodiment, the comparator circuit 1 compares the output voltage Vout with the first reference voltage VRE1 and the second reference voltage VRE2. Based on the comparison result, it controls the switched capacitor circuit 2 to adjust the charge of the coupling capacitor 4, thereby dynamically adjusting the control terminal voltage Vctrl of the power transistor 3, stabilizing the output voltage Vout of the LDO circuit between the first reference voltage VRE1 and the second reference voltage VRE2. Since no operational amplifier is involved, the problem of the dominant pole drifting with load changes is avoided, enhancing stability. Furthermore, in this embodiment, the LDO circuit uses the comparator circuit 1 instead of an operational amplifier to adjust the control terminal voltage Vctrl of the power transistor 3. Compared to an operational amplifier, the comparator circuit 1 operates in a switching state, resulting in significantly lower static power consumption than an operational amplifier that requires continuous conduction. Moreover, the switched capacitor circuit 2 can quickly respond to changes in the output voltage Vout within a clock cycle, without relying on the bandwidth of an operational amplifier to maintain response speed. Therefore, the LDO circuit can simultaneously achieve low power consumption and fast transient response. Additionally, in this embodiment, the LDO circuit adjusts the control terminal voltage Vctrl of the power transistor by adjusting the charge on the coupling capacitor 4. The adjustable range of the control terminal voltage Vctrl of power transistor 3 is no longer limited by the operational amplifier output swing. For example, the control terminal voltage Vctrl of power transistor 3 can be adjusted between 0 and the voltage at the high-voltage terminal avdd. In scenarios requiring large load current, there is no need to increase the size of the power transistor to improve load capacity, effectively reducing the size of the LDO circuit and chip area overhead. Therefore, the LDO circuit in the embodiments of this specification eliminates the operational amplifier in traditional LDOs, avoiding stability problems caused by dominant pole drift while ensuring fast transient response, and reducing power consumption and area cost, thus possessing significant performance advantages.

[0028] The aforementioned high-voltage terminal avdd can be, for example, a power supply, and the voltage of the aforementioned high-voltage terminal avdd can be, for example, the power supply voltage.

[0029] In some embodiments, the clock signal clkc can be a periodic signal. For example, the clock signal clkc can be a square wave signal. The clock signal clkc can be generated by a clock circuit. When the LDO circuit is located on the chip, the clock signal clkc can also be an internal clock signal of the chip. The clock signal clkc is used to periodically trigger a comparison between the output voltage Vout and the first reference voltage VRE1 and the second reference voltage VRE2, so as to periodically adjust the output voltage Vout, thereby stabilizing the output voltage Vout between the first reference voltage VRE1 and the second reference voltage VRE2. By periodically adjusting the output voltage Vout, the repeated oscillation of the output voltage Vout caused by uninterrupted continuous adjustment can be avoided, thereby improving the stability of the output voltage Vout.

[0030] The frequency of the clock signal clkc is related to the transient response speed of the LDO circuit. By adjusting the frequency of the clock signal clkc, the response speed of the LDO circuit can be adjusted, thereby adjusting the rate of change of the output voltage Vout. For example, the frequency of the clock signal clkc can be positively correlated with the response speed of the LDO circuit. The frequency of the clock signal clkc can be, for example, 50MHz, 100MHz, etc.

[0031] In some embodiments, the comparison circuit 1 may include a first comparison circuit 11 and a second comparison circuit 12.

[0032] The first comparator circuit 11 can compare the output voltage Vout with the first reference voltage VRE1 according to the clock signal clkc, and generate a first control signal based on the comparison result of the output voltage Vout and the first reference voltage VRE1. The first control signal can be transmitted to the switched capacitor circuit 2. The first comparator circuit 11 may include a first comparator 111 and N first inverters 112. The negative input terminal of the first comparator 111 can be connected to the second terminal of the power transistor 3 to receive the output voltage Vout. The positive input terminal of the first comparator 111 is used to receive the first reference voltage VRE1. N≥1 and N is an integer. When N=1, the output terminal of the first comparator 111 is connected to the input terminal of the first inverter 112. When N≥2, the N first inverters 112 are cascaded. The output terminal of the first comparator 111 is connected to the input terminal of the first of the N first inverters 112. The N first inverters 112 are used to shape the waveform of the output signal of the first comparator 111 and improve the driving capability of the first comparator circuit 11.

[0033] The second comparator circuit 12 can compare the output voltage Vout with the second reference voltage VRE2 according to the clock signal clkc, and generate a second control signal based on the comparison result of the output voltage Vout and the second reference voltage VRE2, and transmit the second control signal to the switched capacitor circuit 2. The second comparator circuit 12 may include a second comparator 121 and M second inverters 122. The positive input terminal of the second comparator 121 can be connected to the second terminal of the power transistor 3 to receive the output voltage Vout. The negative input terminal of the second comparator 121 is used to receive the second reference voltage VRE2. M≥1 and M is an integer. When M=1, the output terminal of the second comparator 121 is connected to the input terminal of the second inverter 122. When M≥2, the M second inverters 122 are cascaded. The output terminal of the second comparator 121 is connected to the input terminal of the first second inverter 122 among the M second inverters 122. The M second inverters 122 are used to shape the waveform of the output signal of the second comparator 121 and improve the driving capability of the second comparator circuit 12.

[0034] M and N can be the same or different. Figure 2 In this case, M=N=4.

[0035] In some embodiments, the first comparator 111 can receive a clock signal clkc, an output voltage Vout, and a first reference voltage VRE1; it can compare the output voltage Vout with the first reference voltage VRE1 according to the clock signal clkc; and it can generate a signal Q1 according to the comparison result between the output voltage Vout and the first reference voltage VRE1.

[0036] The clock signal clkc can switch between a first level and a second level. Signal Q1 can also switch between a first level and a second level. The first level is the active level, which can be, for example, a high level. The second level is the inactive level, which can be, for example, a low level. When the clock signal clkc is at the second level, the first comparator 111 performs a reset operation, and signal Q1 is at the second level. When the clock signal clkc is at the first level, the first comparator 111 performs a comparison operation between the output voltage Vout and the first reference voltage VRE1. When the output voltage Vout is lower than the first reference voltage VRE1, signal Q1 is at the first level; when the output voltage Vout is higher than the first reference voltage VRE1, signal Q1 is at the second level.

[0037] It should be noted that the clock signal clkc has a relatively high frequency. The clock signal clkc switches rapidly between the first level and the second level. When the output voltage Vout is lower than the first reference voltage VRE1, signal Q1 is a pulse signal; when the output voltage Vout is higher than the first reference voltage VRE1, signal Q1 remains at the second level.

[0038] In some embodiments, the second comparator 121 can receive a clock signal clkc, an output voltage Vout, and a second reference voltage VRE2; it can compare the output voltage Vout with the second reference voltage VRE2 according to the clock signal clkc; and it can generate a signal Q2 according to the comparison result between the output voltage Vout and the second reference voltage VRE2.

[0039] The clock signal clkc can switch between a first level and a second level. Signal Q2 can also switch between a first level and a second level. When the clock signal clkc is at the second level, the second comparator 121 performs a reset operation, and signal Q2 can be at the second level. When the clock signal clkc is at the first level, the second comparator 121 performs a comparison operation between the output voltage Vout and the second reference voltage VRE2. When the output voltage Vout is higher than the second reference voltage VRE2, signal Q2 is at the first level; when the output voltage Vout is lower than the second reference voltage VRE2, signal Q2 is at the second level.

[0040] It should be noted that the clock signal clkc has a relatively high frequency. The clock signal clkc switches rapidly between the first level and the second level. When the output voltage Vout is higher than the second reference voltage VRE2, signal Q2 is a pulse signal; when the output voltage Vout is lower than the second reference voltage VRE2, signal Q2 remains at the second level.

[0041] In some embodiments, coupling capacitor 4 can be connected to the control terminal of power transistor 3. The first terminal of coupling capacitor 4 can be connected to the control terminal of power transistor 3. The second terminal of coupling capacitor 4 can be connected to the low-voltage terminal AVSS. The low-voltage terminal AVSS can be, for example, ground.

[0042] Coupling capacitor 4 is used to adjust the control terminal voltage Vctrl of power transistor 3, thereby adjusting the output voltage Vout of power transistor 3. The amount of charge on coupling capacitor 4 is positively correlated with the control terminal voltage Vctrl. When the amount of charge stored in coupling capacitor 4 is large, the control terminal voltage Vctrl is high; when the amount of charge stored in coupling capacitor 4 is small, the control terminal voltage Vctrl is low. Therefore, by adjusting the amount of charge stored in coupling capacitor 4, the control terminal voltage Vctrl of power transistor 3 can be adjusted.

[0043] In some embodiments, the power transistor 3 can be a P-type switching transistor. For example, a P-type field-effect transistor (PMOS) can be used. The switched capacitor circuit 2 can transfer charge from the coupling capacitor 4 according to a first control signal, thereby reducing the amount of charge on the coupling capacitor 4 to lower the control terminal voltage Vctrl of the power transistor 3, thus increasing the output voltage Vout of the power transistor 3; or it can transfer charge into the coupling capacitor 4 according to a second control signal, thereby increasing the amount of charge on the coupling capacitor 4 to raise the control terminal voltage Vctrl of the power transistor 3, thus lowering the output voltage Vout of the power transistor 3. Figure 2 In the middle, power transistor 3 is a P-type switching transistor.

[0044] Of course, power transistor 3 can also be an N-type switching transistor. An N-type switching transistor could be, for example, an N-type field-effect transistor (NMOS). The switched capacitor circuit 2 can also transfer charge to coupling capacitor 4 according to the first control signal, increasing the control terminal voltage Vctrl of power transistor 3 by increasing the charge on coupling capacitor 4, thereby increasing the output voltage Vout of power transistor 3; or it can transfer charge out of coupling capacitor 4 according to the second control signal, decreasing the charge on coupling capacitor 4 by decreasing the control terminal voltage Vctrl of power transistor 3, thereby decreasing the output voltage Vout of power transistor 3.

[0045] The switched capacitor circuit 2 may include multiple energy storage capacitors. The switched capacitor circuit 2 can transfer the charge of the coupling capacitor 4 to a portion of the multiple energy storage capacitors, thereby reducing the charge amount of the coupling capacitor 4. The switched capacitor circuit 2 can also transfer the charge of another portion of the multiple energy storage capacitors to the coupling capacitor 4, thereby increasing the charge amount of the coupling capacitor 4.

[0046] In some embodiments, the switched capacitor circuit 2 may include a first switched capacitor circuit 21 and a second switched capacitor circuit 22.

[0047] The first switched capacitor circuit 21 can perform charge transfer on the coupling capacitor 4 according to the first control signal to adjust the control terminal voltage Vctrl of the power transistor 3, thereby increasing the output voltage Vout of the power transistor 3 when the output voltage Vout is lower than the first reference voltage VRE1. The first switched capacitor circuit 21 may include a first capacitor 211 and a first switching circuit. The first capacitor 211 can be an energy storage capacitor. The first switching circuit can transfer charge between the first capacitor 211 and the coupling capacitor 4 according to the first control signal to increase the output voltage Vout of the power transistor 3. As an example, the power transistor 3 can be a P-type switch. The first switching circuit can transfer charge from the coupling capacitor 4 to the first capacitor 211 according to the first control signal to decrease the control terminal voltage Vctrl of the power transistor 3, thereby increasing the output voltage Vout of the power transistor 3. As another example, the power transistor 3 can be an N-type switch. The first switching circuit can transfer charge from the first capacitor 211 to the coupling capacitor 4 according to the first control signal to increase the control terminal voltage Vctrl of the power transistor 3, thereby increasing the output voltage Vout of the power transistor 3.

[0048] The second switched capacitor circuit 22 can perform charge transfer on the coupling capacitor 4 according to the second control signal to adjust the control terminal voltage Vctrl of the power transistor 3, thereby reducing the output voltage Vout of the power transistor 3 when the output voltage Vout is higher than the second reference voltage VRE2. The second switched capacitor circuit 22 may include a second capacitor 221 and a second switching circuit. The second capacitor 221 can be an energy storage capacitor. The second switching circuit can transfer charge between the second capacitor 221 and the coupling capacitor 4 according to the second control signal to reduce the output voltage Vout of the power transistor 3. As an example, the power transistor 3 can be a P-type switch. The second switching circuit can transfer charge from the second capacitor 221 to the coupling capacitor 4 according to the second control signal to increase the control terminal voltage Vctrl of the power transistor 3, thereby reducing the output voltage Vout of the power transistor 3. As another example, the power transistor 3 can be an N-type switch. The second switching circuit can transfer charge from the coupling capacitor 4 to the second capacitor 221 according to the second control signal to reduce the control terminal voltage Vctrl of the power transistor 3, thereby reducing the output voltage Vout of the power transistor 3.

[0049] In some embodiments, the N first inverters 112 in the first comparator circuit 11 can generate a first control signal based on signal Q1. The first control signal may include a first reset signal and a first charge transfer signal. The phase difference between the first reset signal and the first charge transfer signal is a set value. The set value can be 180°. When N=1, the first reset signal is the signal generated by the first inverter 112, and the first charge transfer signal is signal Q1 generated by the first comparator 111. When N≥2, the first reset signal is the signal generated by the (N-1)th first inverter 112 out of the N first inverters 112, and the first charge transfer signal is the signal generated by the Nth first inverter 112 out of the N first inverters 112. The M second inverters 122 in the second comparator circuit 12 can generate a second control signal based on signal Q2. The second control signal may include a second reset signal and a second charge transfer signal. The phase difference between the second reset signal and the second charge transfer signal is the set value. When M=1, the second reset signal is the signal generated by the second inverter 122, and the second charge transfer signal is signal Q2 generated by the second comparator 121. When M≥2, the second reset signal is the signal generated by the (M-1)th second inverter 122 out of the M second inverters 122, and the second charge transfer signal is the signal generated by the Mth second inverter 122 out of the M second inverters 122. Figure 2 In this context, rst0 is the first reset signal, dn is the first charge transfer signal, rst1 is the second reset signal, and up is the second charge transfer signal.

[0050] The first switching circuit includes a first reset switch 212 and a first charge transfer switch 213. The first terminal of the first capacitor 211 is connected to the first terminals of both the first reset switch 212 and the first charge transfer switch 213. The second terminals of both the first capacitor 211 and the first reset switch 212 are connected to a low-voltage terminal AVSS. The low-voltage terminal AVSS can be, for example, ground. The second terminal of the first charge transfer switch 213 is connected to the control terminal of the power transistor 3 and the first terminal of the coupling capacitor 4. A first reset signal controls the on / off state of the first reset switch 212 to perform a reset operation on the first capacitor 211. A first charge transfer signal controls the on / off state of the first charge transfer switch 213 to transfer charge between the first capacitor 211 and the coupling capacitor 4. The phase difference between the first reset signal and the first charge transfer signal is set to alternately perform the reset operation and the charge transfer operation.

[0051] The first reset signal switches between a first level and a second level. The first charge transfer signal also switches between a first level and a second level. When the output voltage Vout is higher than the first reference voltage VRE1, the first reset signal is at the first level and the first charge transfer signal is at the second level. The first reset switch 212 is closed and the first charge transfer switch 213 is open. Both the first and second terminals of the first capacitor 211 are connected to the low-voltage terminal avss, and the connection between the first capacitor 211 and the coupling capacitor 4 is broken, thereby performing a reset operation on the first capacitor 211. By performing the reset operation, the first capacitor 211 can be kept in a state with less charge (for example, the first capacitor 211 can be discharged to reduce the amount of charge on the first capacitor 211), so that the amount of charge on the first capacitor 211 is lower than the amount of charge on the coupling capacitor 4. When the output voltage Vout is lower than the first reference voltage VRE1, the first reset signal is at the second level and the first charge transfer signal is at the first level. The first reset switch 212 is open and the first charge transfer switch 213 is closed. The first end of the first capacitor 211 is connected to the first end of the coupling capacitor 4, and the second end of the first capacitor 211 is connected to the low-voltage terminal avss. The connection between the first capacitor 211 and the coupling capacitor 4 is made conductive, thereby realizing the charge transfer operation on the first capacitor 211. By performing the charge transfer operation, the charge on the coupling capacitor 4 can be transferred to the first capacitor 211, reducing the amount of charge on the coupling capacitor 4, thereby reducing the control terminal voltage Vctrl of the power transistor 3.

[0052] The second switching circuit may include a second reset switch 222 and a second charge transfer switch 223. The first terminal of the second capacitor 221 is connected to both the first terminals of the second reset switch 222 and the second charge transfer switch 223. The second terminal of the second capacitor 221 can be connected to a low-voltage terminal avss, which may be ground. The second terminal of the second reset switch 222 can be connected to a high-voltage terminal avdd, which may be a power supply. The second terminal of the second charge transfer switch 223 is connected to the control terminal of the power transistor 3 and the first terminal of the coupling capacitor 4. A second reset signal controls the on / off state of the second reset switch 222 to perform a reset operation on the second capacitor 221. A second charge transfer signal controls the on / off state of the second charge transfer switch 223 to transfer charge between the second capacitor 221 and the coupling capacitor 4. The phase difference between the second reset signal and the second charge transfer signal is a set value, thus allowing the reset operation and charge transfer operation to be performed alternately.

[0053] The second reset signal switches between a first level and a second level. The second charge transfer signal also switches between a first level and a second level. When the output voltage Vout is lower than the second reference voltage VRE2, the second reset signal is at the first level and the second charge transfer signal is at the second level. The second reset switch 222 is closed and the second charge transfer switch 223 is open. The first terminal of the second capacitor 221 is connected to the high-voltage terminal avdd, and the second terminal of the second capacitor 221 is connected to the low-voltage terminal avss. The connection between the second capacitor 221 and the coupling capacitor 4 is broken, thereby performing a reset operation on the second capacitor 221. By performing the reset operation, the second capacitor 221 can be kept in a state with a higher charge (for example, by charging the second capacitor 221 to increase the amount of charge on the second capacitor 221), making the amount of charge on the second capacitor 221 higher than the amount of charge on the coupling capacitor 4. When the output voltage Vout is higher than the second reference voltage VRE2, the second reset signal is at the second level and the second charge transfer signal is at the first level. The second reset switch 222 is open and the second charge transfer switch 223 is closed. The first end of the second capacitor 221 is connected to the first end of the coupling capacitor 4, and the second end of the second capacitor 221 is connected to the low-voltage terminal avss. The connection between the second capacitor 221 and the coupling capacitor 4 is completed, thereby realizing the charge transfer operation on the second capacitor 221. By performing the charge transfer operation, the charge on the second capacitor 221 can be transferred to the coupling capacitor 4, increasing the charge of the coupling capacitor 4 and thus increasing the control terminal voltage Vctrl of the power transistor 3.

[0054] It should be noted that the first reset switch 212, the first charge transfer switch 213, the second reset switch 222, and the second charge transfer switch 223 mentioned above can all be analog switches. Analog switches can be controlled to turn on and off.

[0055] It should also be noted that, as mentioned earlier, when the output voltage Vout is lower than the first reference voltage VRE1, the signal Q1 generated by the first comparator 111 is at a first level. When the output voltage Vout is higher than the first reference voltage VRE1, the signal Q1 generated by the first comparator 111 is at a second level. Furthermore, when N≥2, the first reset signal is the signal generated by the (N-1)th first inverter 112 out of the N first inverters 112, and the first charge transfer signal is the signal generated by the Nth first inverter 112 out of the N first inverters 112. Therefore, when N≥2, N can be an even number. Thus, when the output voltage Vout is higher than the first reference voltage VRE1, the first reset signal can be at a first level and the first charge transfer signal is at a second level; when the output voltage Vout is lower than the first reference voltage VRE1, the first reset signal can be at a second level and the first charge transfer signal is at a first level.

[0056] It should also be noted that, as mentioned earlier, when the output voltage Vout is higher than the second reference voltage VRE2, the signal Q2 generated by the second comparator 121 is at the first level. When the output voltage Vout is lower than the second reference voltage VRE2, the signal Q2 generated by the second comparator 121 is at the second level. Furthermore, when M ≥ 2, the second reset signal is the signal generated by the (M-1)th second inverter 122 out of the M second inverters 122, and the second charge transfer signal is the signal generated by the Mth second inverter 122 out of the M second inverters 122. Therefore, when M ≥ 2, M can be an even number. Thus, when the output voltage Vout is lower than the second reference voltage VRE2, the second reset signal can be at the first level and the second charge transfer signal can be at the second level; when the output voltage Vout is higher than the second reference voltage VRE2, the second reset signal can be at the second level and the second charge transfer signal can be at the first level.

[0057] In some embodiments, an output voltage Vout lower than the first reference voltage VRE1 can mean that the output voltage Vout is less than the first reference voltage VRE1, or that the output voltage Vout is less than or equal to the first reference voltage VRE1. An output voltage Vout higher than the second reference voltage VRE2 can mean that the output voltage Vout is greater than the second reference voltage VRE2, or that the output voltage Vout is greater than or equal to the second reference voltage VRE2. The magnitudes of the first reference voltage VRE1 and the second reference voltage VRE2 can be preset. For example, the first reference voltage VRE1 can be 1.18V, and the second reference voltage VRE2 can be 1.22V. Since the LDO circuit can stabilize the output voltage Vout between the first reference voltage VRE1 and the second reference voltage VRE2, the ripple of the LDO circuit's output voltage Vout can be adjusted by adjusting the difference between the first reference voltage VRE1 and the second reference voltage VRE2. The magnitude of the ripple can be positively correlated with the difference between the first reference voltage VRE1 and the second reference voltage VRE2. When the difference is large, the ripple of the LDO circuit is large. When the difference is small, the ripple of the LDO circuit is small.

[0058] In some embodiments, the capacitance values ​​of coupling capacitor 4, first capacitor 211, and second capacitor 221 are related to the transient response speed of the LDO circuit. By adjusting the capacitance values ​​of coupling capacitor 4, first capacitor 211, and second capacitor 221, the transient response speed of the LDO circuit can be adjusted, thereby adjusting the rate of change of the output voltage Vout. For example, the capacitance values ​​of coupling capacitor 4, first capacitor 211, and second capacitor 221 are negatively correlated with the transient response speed of the LDO circuit.

[0059] In some embodiments, the LDO circuit may further include an external capacitor Cext. The first terminal of power transistor 3 is connected to the high-voltage terminal avdd. The second terminal of power transistor 3 is used to provide the output voltage Vout of the LDO circuit. The second terminal of power transistor 3 is connected to the external capacitor Cext. For example, the second terminal of power transistor 3 is connected to the first terminal of the external capacitor Cext, and the second terminal of the external capacitor Cext is connected to the low-voltage terminal avss. The external capacitor Cext is used to provide transient current to the load, reducing the ripple of the LDO's output voltage Vout.

[0060] Power transistor 3 can be a P-type switch. The first terminal of power transistor 3 is the source, the second terminal is the drain, and the control terminal is the gate. Alternatively, power transistor 3 can also be an N-type switch. The first terminal of power transistor 3 is the drain, the second terminal is the source, and the control terminal is the gate.

[0061] In some embodiments, the LDO circuit may further include an enable transistor 5. The first terminal of the enable transistor 5 and the first terminal of the power transistor 3 are connected to the high-voltage terminal avdd. The second terminal of the enable transistor 5 is connected to the control terminal of the power transistor 3. The control terminal of the enable transistor 5 is used to receive an enable signal en. The enable transistor 5 enables the LDO circuit, thus turning the voltage regulation function of the LDO circuit on and off. The enable signal en can switch between a first level and a second level. When the enable signal en is at the second level, the voltage regulation function is off. When the enable signal is at the first level, the voltage regulation function is on. The enable transistor 5 can be a P-type switch. The first terminal of the enable transistor 5 is the source, the second terminal of the enable transistor 5 is the drain, and the control terminal of the enable transistor 5 is the gate. Alternatively, the enable transistor 5 can also be an N-type switch. The first terminal of the enable transistor 5 is the drain, the second terminal of the enable transistor 5 is the source, and the control terminal of the enable transistor 5 is the gate.

[0062] In some embodiments, the load of the LDO circuit may include a capacitive load Cload and / or a resistive load Rload.

[0063] In some embodiments, Figure 4 It shows Figure 1 as well as Figure 2 The timing diagram of the LDO circuit shown is as follows. (The following is combined with...) Figure 4 The operating states of the LDO circuit described above are explained. Enable transistor 5 and power transistor 3 are P-type switches. When the enable signal en is low, enable transistor 5 is turned on, the control terminal of power transistor 3 is connected to the high-voltage terminal avdd, power transistor 3 is turned off, and the voltage regulation function of the LDO circuit is disabled. When the enable signal en is high, enable transistor 5 is turned off, and the voltage regulation function of the LDO circuit is enabled.

[0064] After the LDO circuit's voltage regulation function is enabled, the output voltage Vout is relatively low. The first reference voltage VREF1 is higher than the output voltage Vout. The signal Q1 output by the first comparator 111 is a pulse signal, as are the first charge transfer signal and the first reset signal, which are 180° out of phase. Because the first charge transfer signal and the first reset signal are pulse signals, the charge on coupling capacitor 4 can be transferred to the first capacitor 211 following the pulse signal, causing the control terminal voltage Vctrl of power transistor 3 to continuously decrease. When the control terminal voltage Vctrl of power transistor 3 decreases to a certain voltage threshold, power transistor 3 turns on. Power transistor 3 can then charge the load and the external capacitor Cext, causing the output voltage Vout to begin to rise.

[0065] When the output voltage Vout rises above the first reference voltage VREF1, the first charge transfer signal is low and the first reset signal is high. At this time, a reset operation is performed on the first capacitor 211 to keep it in a state with less charge. Meanwhile, the output voltage Vout is still below the second reference voltage VREF2, the second charge transfer signal is low and the second reset signal is high, allowing a reset operation to be performed on the second capacitor 221 to restore it to a state with more charge. Additionally, the power transistor 3 can continue to charge the load and the external capacitor Cext, and the output voltage Vout can continue to rise. When the output voltage Vout rises above the second reference voltage VREF2, the signal Q2 output by the second comparator 121 is a pulse signal. The second charge transfer signal and the second reset signal are also pulse signals, with a 180° phase difference. Because the second charge transfer signal and the second reset signal are pulse signals, the charge on the second capacitor 221 can be transferred to the coupling capacitor 4 following the pulse signal. The control terminal voltage Vctrl of the power transistor 3 increases, and the current flowing through the power transistor 3 decreases (or it is turned off). The current supplied by power transistor 3 is less than the current consumed by the load, and the output voltage Vout begins to decrease.

[0066] When the output voltage Vout drops below the first reference voltage VREF1, the signal Q1 output by the first comparator 111 is a pulse signal. The first charge transfer signal and the first reset signal are also pulse signals, with a 180° phase difference. Because the first charge transfer signal and the first reset signal are pulse signals, the charge on the coupling capacitor 4 can be transferred to the first capacitor 211 following the pulse signal. This reduces the control terminal voltage Vctrl of the power transistor 3, increasing the current flowing through the power transistor 3 (or causing it to conduct). The power transistor 3 charges the load and the external capacitor Cext, causing the output voltage Vout to begin to rise.

[0067] When the output voltage Vout rises above the second reference voltage VREF2, the signal Q2 output by the second comparator 121 becomes a pulse signal. The second charge transfer signal and the second reset signal are also pulse signals, with a 180° phase difference. Because the second charge transfer signal and the second reset signal are pulse signals, the charge on the second capacitor 221 can be transferred to the coupling capacitor 4 following the pulse signal. This causes the control terminal voltage Vctrl of the power transistor 3 to rise, and the current flowing through the power transistor 3 to decrease (or turn off). Since the current supplied by the power transistor 3 is less than the current consumed by the load, the output voltage Vout begins to decrease.

[0068] This cycle continues, allowing the output voltage Vout to stabilize between the first reference voltage VREF1 and the second reference voltage VREF2.

[0069] In some embodiments, the first comparator 111 and the second comparator 121 can be differential latch type dynamic comparators.

[0070] Please see Figure 5 The differential latch-type dynamic comparator may include a first differential branch, a second differential branch, and a control transistor 61. The first differential branch receives a first input voltage *vinn* and adjusts the potential of the first output node *op* according to *vinn*. The second differential branch receives a second input voltage *vinp* and adjusts the potential of the second output node *on* according to *vinp*. The first output node *op* and / or the second output node *on* output a signal characterizing the comparison result. The comparison result is the comparison between the first input voltage *vinn* and the second input voltage *vinp*. The first output node *op* and the second output node *on* may be connected to one or more inverters, which can generate signals characterizing the comparison result. Figure 5 In the circuit, the first output node op can be connected to inverter 66. The second output node on can be connected to three cascaded inverters, namely inverters 67, 68, and 69. Among the three cascaded inverters, the third inverter 69 can generate a signal Q that characterizes the comparison result. Control transistor 61 is used to control the timing of the comparison circuit according to the clock signal clkc. Control transistor 61 can be turned on or off by the clock signal clkc. When turned on, control transistor 61 provides a current path for the first and second differential branches. When turned off, control transistor 61 cuts off the current to the first and second differential branches to eliminate static power consumption.

[0071] The first input voltage vinn can be the aforementioned output voltage Vout, or the aforementioned first reference voltage VRE1, or the aforementioned second reference voltage VRE2. The second input voltage vinn can be the aforementioned output voltage Vout, or the aforementioned first reference voltage VRE1, or the aforementioned second reference voltage VRE2. The first input voltage vinn and the second input voltage vinn are different.

[0072] The first differential branch circuit may include a first node reset circuit, a first latch 631, a first differential input transistor 641, and a first differential reset transistor 651. The second differential branch circuit may include a second node reset circuit, a second latch 632, a second differential input transistor 642, and a second differential reset transistor 652. The first node reset circuit is used to perform a potential reset on the first output node op according to the clock signal clkc. The second node reset circuit is used to perform a potential reset on the second output node on according to the clock signal clkc. The first differential input transistor 641 is used to receive a first input voltage vinn and adjust the potential of the first output node op according to the first input voltage vinn. The second differential input transistor 642 is used to receive a second input voltage vimp and adjust the potential of the second output node on according to the second input voltage vimp. The first latch 631 and the second latch 632 are cross-coupled to amplify the potential difference between the first output node op and the second output node on and latch the potentials of the first output node op and the second output node on. The first differential reset transistor 651 is used to perform a potential reset on the first differential input transistor 641 according to the clock signal clkc. The second differential reset transistor 652 is used to perform a potential reset on the second differential input transistor 642 according to the clock signal clkc.

[0073] The first node reset circuit may include a first node reset transistor 621 and a second node reset transistor 622. The control terminal of the first node reset transistor 621 receives the clock signal clkc, and the control terminal of the second node reset transistor 622 is connected to the control terminal of the first latch transistor 631. The first terminals of the first node reset transistor 621 and the second node reset transistor 622 are connected to the high-voltage terminal avdd. The second terminals of the first node reset transistor 621 and the second node reset transistor 622 are connected to the first terminal of the first latch transistor 631. Therefore, the first node reset circuit adopts a dual-transistor parallel structure, resulting in lower on-resistance, faster output node reset speed, and compatibility with higher operating frequencies. The second terminal of the first latch transistor 631 is connected to the first terminal of the first differential input transistor 641. The control terminal of the first differential input transistor 641 can be the positive input terminal of a comparator, used to receive the first input voltage vinn. The second terminal of the first differential input transistor 641 is connected to the first terminal of the control transistor 61. The first terminal of the first differential reset transistor 651 is connected to the high-voltage terminal avdd. The control terminal of the first differential reset transistor 651 receives the clock signal clkc. The second terminal of the first differential reset transistor 651 is connected to the first terminal of the first differential input transistor 641. Therefore, the first differential reset transistor 651 can perform a potential reset on the first terminal of the first differential input transistor 641 according to the clock signal clkc.

[0074] The second node reset circuit may include a third node reset transistor 623 and a fourth node reset transistor 624. The control terminal of the fourth node reset transistor 624 receives the clock signal clkc, and the control terminal of the third node reset transistor 623 is connected to the control terminal of the second latch transistor 632. The first terminals of the third node reset transistor 623 and the fourth node reset transistor 624 are connected to the high-voltage terminal avdd. The second terminals of the third node reset transistor 623 and the fourth node reset transistor 624 are connected to the first terminal of the second latch transistor 632. Therefore, the second node reset circuit adopts a dual-transistor parallel structure, resulting in lower on-resistance, faster output node reset speed, and compatibility with higher operating frequencies. The second terminal of the second latch transistor 632 is connected to the first terminal of the second differential input transistor 642. The control terminal of the second differential input transistor 642 can be the negative input terminal of a comparator, used to receive the second input voltage vimp. The second terminal of the second differential input transistor 642 is connected to the first terminal of the control transistor 61. The first terminal of the second differential reset transistor 652 is connected to the high-voltage terminal avdd. The control terminal of the second differential reset transistor 652 receives the clock signal clkc. The second terminal of the second differential reset transistor 652 is connected to the first terminal of the second differential input transistor 642. Therefore, the second differential reset transistor 652 can perform a potential reset on the first terminal of the second differential input transistor 642 according to the clock signal clkc.

[0075] The first output node OP is connected to the second terminal of the second node reset transistor 622, the first terminal of the first latch transistor 631, the control terminal of the third node reset transistor 623, and the control terminal of the second latch transistor 632. The second output node ON is connected to the control terminal of the second node reset transistor, the control terminal of the first latch transistor 631, the second terminal of the third node reset transistor 623, and the first terminal of the second latch transistor 632. The control terminal of control transistor 61 is used to receive the clock signal clkc. The second terminal of control transistor 61 is connected to the low-voltage terminal AVSS.

[0076] The first node reset transistor 621, the second node reset transistor 622, the third node reset transistor 623, the fourth node reset transistor 624, the first differential reset transistor 651, and the second differential reset transistor 652 can be P-type switches. The first terminal of the P-type switch is the source, the second terminal is the drain, and the control terminal is the gate. The first latch transistor 631, the second latch transistor 632, the first differential input transistor 641, the second differential input transistor 642, and the control transistor 61 are N-type switches. The first terminal of the N-type switch is the drain, the second terminal is the source, and the control terminal is the gate.

[0077] The comparator described above is reset when the clock signal clkc is at the second level (low level), and the signal Q is at the second level. When the clock signal clkc is at the first level (high level), the voltage of the positive input terminal (e.g., the control terminal of the first differential input transistor 641) is compared with the voltage of the negative input terminal (the control terminal of the second differential input transistor 642). If the voltage of the positive input terminal is less than the voltage of the negative input terminal, the signal Q is low; if the voltage of the positive input terminal is greater than the voltage of the negative input terminal, the signal Q is high.

[0078] The comparator described above is driven by a unified clock signal clkc, resulting in simple timing logic and reduced design complexity for peripheral circuits. Furthermore, the symmetrical components in the two differential branches effectively suppress external common-mode noise, providing excellent anti-interference capabilities. The comparator uses a unified clock signal clkc to control the on / off state of each switch, generating operating current during comparison but ceasing to generate operating current after the comparison result is obtained. Since it does not require continuous conduction, it reduces unnecessary power consumption and has low static power consumption. Additionally, the comparator synchronously resets the latch node and differential input transistors in each operating cycle, clearing offset interference caused by residual potentials from the previous cycle, avoiding offset errors in the comparison result, and significantly improving comparison accuracy.

[0079] The functional units in the embodiments of this specification can be integrated into one processing unit, or each functional unit can exist physically separately, or two or more functional units can be integrated into one processing unit.

[0080] Those skilled in the art will understand that the descriptions of the various embodiments in this specification have different focuses, and parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, it is understood that those skilled in the art, after reading this specification, can conceive of any combination of some or all of the embodiments listed in this specification without creative effort, and such combinations are also within the scope of disclosure and protection of this specification.

[0081] Although this specification has been described through embodiments, those skilled in the art will understand that the above embodiments are merely illustrative of the core ideas of this specification. Those skilled in the art will appreciate that many variations and modifications are possible with this specification. It is intended that the appended claims encompass these variations and modifications without departing from the spirit of this specification.

Claims

1. An LDO circuit, characterized in that, This includes a comparator circuit, a switched capacitor circuit, a power transistor, and a coupling capacitor; The comparison circuit is used to compare the output voltage of the power transistor with a first reference voltage and a second reference voltage according to a clock signal, generate a first control signal based on the comparison result of the output voltage and the first reference voltage, and transmit the first control signal to the switched capacitor circuit; and generate a second control signal based on the comparison result of the output voltage and the second reference voltage, and transmit the second control signal to the switched capacitor circuit. The second reference voltage is greater than the first reference voltage; The switched capacitor circuit is used to perform charge transfer on the coupling capacitor according to a first control signal to increase the output voltage of the power transistor when the output voltage is lower than the first reference voltage, and to perform charge transfer on the coupling capacitor according to a second control signal to decrease the output voltage of the power transistor when the output voltage is higher than the second reference voltage; The coupling capacitor is connected to the control terminal of the power transistor.

2. The LDO circuit according to claim 1, characterized in that, The comparison circuit includes a first comparison circuit and a second comparison circuit; The first comparison circuit is used to compare the output voltage with the first reference voltage according to the clock signal, generate a first control signal according to the comparison result of the output voltage and the first reference voltage, and transmit the first control signal to the switched capacitor circuit. The second comparison circuit is used to compare the output voltage with the second reference voltage according to the clock signal, generate a second control signal according to the comparison result of the output voltage and the second reference voltage, and transmit the second control signal to the switched capacitor circuit.

3. The LDO circuit according to claim 2, characterized in that, The first comparison circuit includes a first comparator and N inverters; N=1, and the output of the first comparator is connected to the input of the inverter; Alternatively, N≥2, N inverters are cascaded, and the output of the first comparator is connected to the input of the first inverter among the N inverters; The second comparison circuit includes a second comparator and M inverters; M=1, and the output of the second comparator is connected to the input of the inverter; Alternatively, M ≥ 2, M inverters are cascaded, and the output of the second comparator is connected to the input of the first inverter among the M inverters.

4. The LDO circuit according to claim 3, characterized in that, The first control signal includes a first reset signal and a first charge transfer signal; when N=1, the first reset signal is a signal generated by the first comparator, and the first charge transfer signal is a signal generated by the inverter; when N≥2, the first reset signal is a signal generated by the (N-1)th inverter among the N inverters, and the first charge transfer signal is a signal generated by the Nth inverter among the N inverters. The second control signal includes a second reset signal and a second charge transfer signal; When M=1, the second reset signal is the signal generated by the second comparator, and the second charge transfer signal is the signal generated by the inverter; when M≥2, the second reset signal is the signal generated by the (M-1)th inverter among the M inverters, and the second charge transfer signal is the signal generated by the Mth inverter among the M inverters.

5. The LDO circuit according to claim 1, characterized in that, The switched capacitor circuit includes a first switched capacitor circuit and a second switched capacitor circuit. The first switched capacitor circuit is used to perform charge transfer on the coupling capacitor according to the first control signal, so as to increase the output voltage of the power transistor when the output voltage is lower than the first reference voltage; The second switched capacitor circuit is used to perform charge transfer on the coupling capacitor according to the second control signal, so as to reduce the output voltage of the power transistor when the output voltage is higher than the second reference voltage.

6. The LDO circuit according to claim 5, characterized in that, The first switched capacitor circuit includes a first capacitor and a first switching circuit, wherein the first switching circuit is used to transfer charge between the first capacitor and the coupling capacitor according to a first control signal; the second switched capacitor circuit includes a second capacitor and a second switching circuit, wherein the second switching circuit is used to transfer charge between the second capacitor and the coupling capacitor according to a second control signal.

7. The LDO circuit according to claim 6, characterized in that, The first switching circuit includes a first reset switch and a first charge transfer switch. The first end of the first capacitor is connected to the first end of the first reset switch and the first end of the first charge transfer switch, respectively. The second end of the first capacitor and the second end of the first reset switch are connected to the low voltage end. The second end of the first charge transfer switch is connected to the coupling capacitor. The first control signal includes a first reset signal and a first charge transfer signal. The first reset signal is used to control the opening and closing of the first reset switch to perform a reset operation on the first capacitor. The first charge transfer signal is used to control the opening and closing of the first charge transfer switch to transfer charge between the first capacitor and the coupling capacitor. The second switching circuit includes a second reset switch and a second charge transfer switch. The first end of the second capacitor is connected to the first end of the second reset switch and the first end of the second charge transfer switch, respectively. The second end of the second capacitor is connected to the low-voltage end, the second end of the second reset switch is connected to the high-voltage end, and the second end of the second charge transfer switch is connected to the coupling capacitor. The second control signal includes a second reset signal and a second charge transfer signal. The second reset signal is used to control the on / off state of the second reset switch to perform a reset operation on the second capacitor. The second charge transfer signal is used to control the on / off state of the second charge transfer switch to transfer charge between the second capacitor and the coupling capacitor.

8. The LDO circuit according to claim 1, characterized in that, The power transistor is a P-type switching transistor, and the switched capacitor circuit is used to transfer charge out of the coupling capacitor according to a first control signal and transfer charge into the coupling capacitor according to a second control signal; or, the power transistor is an N-type switching transistor, and the switched capacitor circuit is used to transfer charge into the coupling capacitor according to a first control signal and transfer charge out of the coupling capacitor according to a second control signal.

9. The LDO circuit according to claim 1, characterized in that, The first end of the power transistor is connected to the high-voltage terminal, and the second end of the power transistor is connected to an external capacitor. The second end of the power transistor is used to provide the output voltage.

10. The LDO circuit according to claim 1, characterized in that, The LDO circuit also includes an enable transistor; The first end of the enable transistor and the first end of the power transistor are connected to the high-voltage end. The second end of the enable transistor is connected to the control end of the power transistor; The control terminal of the enable transistor is used to receive the enable signal; The second terminal of the power transistor is used to provide the output voltage.

11. The LDO circuit according to claim 1, characterized in that, The comparison circuit includes a comparator; The comparator includes a first differential branch, a second differential branch, and a control transistor; The first differential branch is used to receive a first input voltage and adjust the potential of the first output node according to the first input voltage. The second differential branch is used to receive a second input voltage and adjust the potential of the second output node according to the second input voltage. The first output node and / or the second output node are used to output a signal that can characterize the comparison result between the first input voltage and the second input voltage. The control transistor is used to control the operating timing of the comparison circuit according to the clock signal.

12. The LDO circuit according to claim 11, characterized in that, The first differential branch includes a first node reset circuit, a first latch, a first differential input transistor, and a first differential reset transistor; the second differential branch includes a second node reset circuit, a second latch, a second differential input transistor, and a second differential reset transistor. The first node reset circuit is used to perform a potential reset on the first output node according to the clock signal; The second node reset circuit is used to perform a potential reset on the second output node according to the clock signal; The first differential input transistor is used to adjust the potential of the first output node according to the first input voltage; The second differential input transistor is used to adjust the potential of the second output node according to the second input voltage; The first latch transistor and the second latch transistor are cross-coupled to amplify the potential difference between the first output node and the second output node and to latch the potential of the first output node and the potential of the second output node. The first differential reset transistor is used to perform a potential reset on the first differential input transistor according to the clock signal; The second differential reset transistor is used to perform a potential reset on the second differential input transistor according to the clock signal.

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