Three-dimensional storage-computing integrated architecture and operation method
Patent Information
- Application Number
- CN202510551171.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2026-10-30
AI Technical Summary
[0003]本发明的目的在于提供一种三维存算一体架构及运算方法，用于解决现有存算一体架构的权值数据只能复用一次导致的计算次数多，计算效率低的问题
[0016]与现有技术相比，本发明提供的一种三维存算一体架构，包括：矩阵乘阵列、输入矩阵、权值矩阵以及存储单元；矩阵乘阵列为三维阵列；输入矩阵与矩阵乘阵列的第一输入端相连，权值矩阵与矩阵乘阵列的第二输入端相连；存储单元与所述矩阵乘阵列的输出端相连；矩阵乘阵列用于对输入矩阵和权值矩阵进行内外积混合运算；本申请的输入矩阵沿矩阵乘阵列的第一维度方向进行广播，可以使得输入数据与第一维度方向的所有权值数据分别进行计算，实现输入数据的多次复用，权值矩阵沿矩阵乘阵列的第二维度方向进行广播，可以使得权值数据与第二维度方向上的所有输入数据分别进行计算，实现权值数据的多次复用，且由于矩阵乘阵列为三维阵列，输入阵列的每个行向量或列向量中的每个数据都能够实现多次复用，权值矩阵的每个行向量或列向量的每个数据都能够实现多次复用。通过本申请的三维存算一体架构可以极大的减小计算次数，提高数据的计算效率，另外存储单元的设置能够实现对计算结果的存储。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of in-memory computing architecture technology, and in particular to a three-dimensional in-memory computing architecture and computing method. Background Technology
[0002] Traditional in-memory computing architectures typically employ a fixed-weight inner product architecture. Weight data is pre-stored and arranged within a storage array, and the input vector is loaded from the outside to perform multiplication and accumulation operations on the input vector and the weight data. Fixed weights minimize the overhead of accessing weight data caching. However, in this fixed-weight architecture, each time weight data is accessed, it is only used by the current input data, reused only once, and consumed after a single operation, unable to be used for subsequent inputs. The low reuse rate of weight data increases the overall computational complexity of the task, reducing computational efficiency. Summary of the Invention
[0003] The purpose of this invention is to provide a three-dimensional in-memory computing architecture and computing method to solve the problem of high computational frequency and low computational efficiency caused by the fact that the weight data of the existing in-memory computing architecture can only be reused once.
[0004] To achieve the above objectives, the present invention provides the following technical solution:
[0005] In a first aspect, the present invention provides a three-dimensional in-memory computing architecture, including: a matrix multiplication array, an input matrix, a weight matrix, and a storage unit;
[0006] The matrix multiplication array is a three-dimensional array; the input matrix is connected to the first input terminal of the matrix multiplication array, and the weight matrix is connected to the second input terminal of the matrix multiplication array; the storage unit is connected to the output terminal of the matrix multiplication array.
[0007] The matrix multiplication array is used to perform a mixed inner and outer product operation on the input matrix and the weight matrix; the input matrix is broadcast along the first dimension of the matrix multiplication array, and the weight matrix is broadcast along the second dimension of the matrix multiplication array;
[0008] The storage unit is used to store the output results of the matrix multiplication array.
[0009] Optionally, the storage unit consists of multiple IGZO dynamic accumulators, which are arranged in a two-dimensional planar array.
[0010] Optionally, the matrix multiplication array performs an outer product calculation on the first plane by taking the outer product of each column vector of the input matrix with each row vector of the weight matrix, and performs an inner product calculation on the third dimension by taking the inner product of each row vector of the input matrix with each column vector of the weight matrix; the first plane is the plane formed by the first dimension and the second dimension.
[0011] Optionally, the IGZO dynamic accumulator includes a first IGZO transistor, a second IGZO transistor, a third IGZO transistor, a fourth IGZO transistor, a first NMOS transistor, and a second NMOS transistor. The gate of the first IGZO transistor is connected to a clock signal, the drain of the first IGZO transistor is connected to the output terminal of the matrix multiplication array, the source of the first IGZO transistor is connected to the gate of the first NMOS transistor and the gate of the second IGZO transistor, the drain of the first NMOS transistor is connected to the source of the second IGZO transistor and the source of the third IGZO transistor, the drain of the second IGZO transistor is grounded, the gate of the third IGZO transistor is connected to the inverted signal of the clock signal, the drain of the third IGZO transistor is connected to the gate of the second NMOS transistor and the gate of the fourth IGZO transistor, the drain of the second NMOS transistor is connected to the source of the fourth IGZO transistor, and the drain of the fourth IGZO transistor is grounded.
[0012] Optionally, the matrix multiplication array includes multiple multiply-accumulate calculation units, which are arranged in a three-dimensional array. Each multiply-accumulate calculation unit is used to perform multiplication and accumulation calculations on corresponding input data and corresponding weight data. Each multiply-accumulate calculation unit includes a multiplier and an adder. The output of the multiplier is connected to the input of the adder. The first input of the multiplier is connected to the input matrix, the second input of the multiplier is connected to the weight matrix, the output of the adder is connected to the input of the corresponding IGZO dynamic accumulator, and the outputs of two adjacent multiply-accumulate calculation units are connected.
[0013] Optionally, the matrix multiplication array includes multiple CMOS transistors arranged in a three-dimensional array. The gates of the CMOS transistors are connected to the corresponding input data, the sources of the CMOS transistors are connected to the corresponding weight data, the drains of the CMOS transistors are connected to the input of the IGZO dynamic accumulator, and the drains of two adjacent CMOS transistors are connected together.
[0014] Optionally, the three-dimensional in-memory computing architecture further includes a weight storage array, which is connected to the input terminal of the amplifier circuit, and the output terminal of the amplifier circuit is connected to the weight matrix.
[0015] Optionally, the input matrix is used to convert input data into an input voltage signal, and the weight matrix is used to convert weight data into a weight voltage signal. The source current of the CMOS transistor is proportional to the product of the input voltage signal and the weight voltage signal.
[0016] Compared with existing technologies, this invention provides a three-dimensional in-memory computing architecture, comprising: a matrix multiplication array, an input matrix, a weight matrix, and a storage unit; the matrix multiplication array is a three-dimensional array; the input matrix is connected to the first input terminal of the matrix multiplication array, and the weight matrix is connected to the second input terminal of the matrix multiplication array; the storage unit is connected to the output terminal of the matrix multiplication array; the matrix multiplication array is used to perform mixed inner and outer product operations on the input matrix and the weight matrix; the input matrix of this application is broadcast along the first dimension of the matrix multiplication array, allowing the input data to be calculated separately with all the weight data in the first dimension, achieving multiple reuse of the input data; the weight matrix is broadcast along the second dimension of the matrix multiplication array, allowing the weight data to be calculated separately with all the input data in the second dimension, achieving multiple reuse of the weight data; and since the matrix multiplication array is a three-dimensional array, each data in each row or column vector of the input array can be reused multiple times, and each data in each row or column vector of the weight matrix can be reused multiple times. This three-dimensional in-memory computing architecture can greatly reduce the number of calculations and improve data computation efficiency; furthermore, the storage unit enables the storage of calculation results.
[0017] Secondly, the present invention also provides a computation method for a three-dimensional in-memory computing architecture, which is applied to a three-dimensional in-memory computing architecture, the three-dimensional in-memory computing architecture including a matrix multiplication array, an input matrix, a weight matrix and a storage unit; the matrix multiplication array is a three-dimensional array; the input matrix is connected to a first input terminal of the matrix multiplication array, the weight matrix is connected to a second input terminal of the matrix multiplication array; the storage unit is connected to the output terminal of the matrix multiplication array;
[0018] The input matrix and the weight matrix are subjected to a mixed inner and outer product operation to obtain the output result; the input matrix is broadcast along the first dimension of the matrix multiplication array, and the weight matrix is broadcast along the second dimension of the matrix multiplication array.
[0019] The output results are stored.
[0020] Optionally, before performing the mixed inner and outer product operation on the input matrix and the weight matrix, the method further includes:
[0021] The input data is mapped into the input matrix, the weight data is read from the weight storage array, and the weight data is mapped into the weight matrix.
[0022] Compared with the prior art, the beneficial effects of the computing method of the three-dimensional in-memory computing architecture provided by the present invention are the same as the beneficial effects of the three-dimensional in-memory computing architecture described in the above technical solution, and will not be repeated here. Attached Figure Description
[0023] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0024] Figure 1 This is a schematic diagram of an integrated memory-computation architecture in the prior art.
[0025] Figure 2 A schematic diagram of the three-dimensional in-memory computing architecture provided by the present invention;
[0026] Figure 3 The working principle diagram of the IGZO dynamic accumulator provided by this invention;
[0027] Figure 4 The circuit diagram of the IGZO dynamic accumulator provided by this invention;
[0028] Figure 5 A CMOS circuit diagram of the plane formed by the second and third dimensions of the matrix multiplication array provided by the present invention;
[0029] Figure 6 A CMOS circuit diagram of the plane formed by the first and second dimensions of the matrix multiplication array provided by the present invention;
[0030] Figure 7 A flowchart illustrating the computation method of the three-dimensional in-memory computing architecture provided by this invention.
[0031] Figure label:
[0032] 1-Input matrix, 2-Weight matrix, 3-Matrix multiplication array, 4-Weight storage array, 5-Storage cell, N1-First NMOS transistor, N2-Second NMOS transistor, G1-First IGZO transistor, G2-Second IGZO transistor, G3-Third IGZO transistor, G4-Fourth IGZO transistor. Detailed Implementation
[0033] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.
[0034] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0035] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.
[0036] Existing in-memory computing architectures include fixed-weight inner product architectures and fixed-output computation architectures. For example... Figure 1 As shown, in the fixed-weight structure, weight data such as W11, W12, W13, W21, W22, W23, W31, W32, and W33 are pre-stored and arranged inside the storage array. The input vector [X1, X2, X3] is externally loaded, and multiplication and accumulation operations are performed on the input vector and weight data. During calculation, the weight data can only be used by the current input data, resulting in low computational efficiency. The fixed-output computing architecture generally uses an external product calculation method. The NE array obtains the input data and weight data from the outside, stores the calculated product result in the NE array's register, and performs summation and accumulation internally within the NE array to avoid intermediate data transmission. However, due to the large number of CMOS transistors required by the static edge-triggered register, it results in significant area and power consumption overhead.
[0037] To address the aforementioned issues, this invention provides a three-dimensional in-memory computing architecture and computation method. It employs a hybrid inner and outer product approach to improve the reusability of weight data and uses a dynamic IGZO latch instead of a traditional register to reduce area and power consumption. The following is a detailed description.
[0038] See Figure 2 The present invention provides a three-dimensional in-memory computing architecture, characterized in that it includes: an input matrix 1, a weight matrix 2, a matrix multiplication array 3, a weight storage array 4, and a storage unit 5;
[0039] Matrix multiplication array 3 is a three-dimensional array; weight storage array 4 is connected to the input terminal of the amplifier circuit, and the output terminal of the amplifier circuit is connected to weight matrix 2. The amplifier circuit is used to read the weight data stored in weight storage array 4, and the weight data is mapped into the weight array. Input matrix 1 is connected to the first input terminal of matrix multiplication array 3, and weight matrix 2 is connected to the second input terminal of matrix multiplication array 3. Input matrix 1 is obtained by mapping external input data to the first input terminal of matrix multiplication array 3 in a preset order, and weight matrix 2 is obtained by mapping weight data to the second input terminal of matrix multiplication array 3 in a preset order. Both the first and second input terminals are arranged in the form of two-dimensional planar matrices. Storage unit 5 is connected to the output terminal of matrix multiplication array 3. Matrix multiplication array 3 is used to perform mixed inner and outer product operations on input matrix 1 and weight matrix 2. The data of input matrix 1 is broadcast along the first dimension of matrix multiplication array 3, and weight matrix 2 is broadcast along the second dimension of matrix multiplication array 3. Storage unit 5 is used to store the output result of matrix multiplication array 3. For example, x is the first dimension of the matrix multiplication array, y is the second dimension of the matrix multiplication array, and z is the third dimension of the matrix multiplication array. It should be noted that the first dimension is the perpendicular direction from the input matrix to the matrix multiplication array, the second dimension is the perpendicular direction from the weight matrix to the matrix multiplication array, and the third dimension is the perpendicular direction from the matrix multiplication array to the storage unit. The first, second, and third dimensions are all mutually perpendicular.
[0040] Specifically, matrix multiplication array 3 performs outer product calculations on each column vector of input matrix 1 with each row vector of the weight matrix in the first plane. Matrix multiplication array 3 then performs inner product calculations on each row vector of input matrix 1 with each column vector of weight matrix 2 in the third dimension. The inner product calculation requires less intermediate data storage, reducing register overhead. The outer product calculation allows for high data reuse, requiring less external data storage and access overhead. The first plane is the plane formed by the first and second dimensions. It can be understood that the first plane includes multiple planes.
[0041] The output of matrix multiplication by array is shown in formula (1):
[0042]
[0043] Among them, Y j Xi is the j-th output result of matrix multiplication of array, Wi is the i-th input data, and n is the total number of input data or weight data. The number of input data and weight data are the same.
[0044] In this application, the input matrix is broadcast along the first dimension of the matrix multiplication array, and the weight matrix is broadcast along the second dimension of the matrix multiplication array. This allows the input data and all weight data in the first dimension to be calculated separately, achieving multiple reuse of the input data. Simultaneously, the weight data and all input data in the second dimension are calculated separately, achieving multiple reuse of the weight data. Furthermore, since the matrix multiplication array is a three-dimensional array, each data point in each row or column vector of the input array and each data point in each row or column vector of the weight matrix can be reused multiple times. This three-dimensional in-memory computing architecture significantly reduces the number of computations and improves data computation efficiency. Additionally, the storage unit enables the storage of computation results.
[0045] As an alternative approach, the storage unit consists of multiple IGZO dynamic accumulators arranged in a two-dimensional planar array. Each IGZO dynamic accumulator is connected to one output of a matrix multiplication array. Figure 3 As shown, the IGZO dynamic accumulator stores the output of the matrix multiplication array through dynamic accumulation. The storage principle is shown in formula (2):
[0046] y t =Y j +y t-1 (2)
[0047] Among them, y t This refers to the data stored in the IGZO dynamic accumulator at the current moment, and the data stored in the IGZO dynamic accumulator at the previous moment.
[0048] See Figure 4The IGZO dynamic accumulator includes a first IGZO transistor G1, a second IGZO transistor G2, a third IGZO transistor G3, a fourth IGZO transistor G4, a first NMOS transistor N1, and a second NMOS transistor N2. The gate of the first IGZO transistor G1 is connected to the clock signal, and the drain of the first IGZO transistor G1 is connected to the output terminal of the matrix multiplication array. The source of the first IGZO transistor G1 is connected to the gate of the first NMOS transistor N1 and the gate of the second IGZO transistor G2. The drain of the first NMOS transistor N1 is connected to the source of the second IGZO transistor G2 and the source of the third IGZO transistor G3. The drain of the second IGZO transistor G2 is grounded. The gate of the third IGZO transistor G3 is connected to the inverted signal of the clock signal, and the drain of the third IGZO transistor G3 is connected to the gate of the second NMOS transistor and the gate of the fourth IGZO transistor G4. The drain of the second NMOS transistor N2 is connected to the source of the fourth IGZO transistor G4. The drain of the fourth IGZO transistor G4 is grounded.
[0049] The operation of the IGZO dynamic accumulator is as follows: when the clock signal CLK is high, the first IGZO transistor G1 is turned on, and the current received at the D terminal charges the gate of the first NMOS transistor. When the clock signal flips, the first NMOS transistor is turned off, the charge of the second IGZO transistor is maintained at the gate, and the third IGZO transistor is turned on to charge the gate of the second NMOS transistor.
[0050] IGZO dynamic accumulators use fewer transistors than static registers, offering an area advantage. During operation, the IGZO dynamic accumulator operates in two phases: charging and computation, with no feedback loop. Furthermore, IGZOs are characterized by low leakage current, which is not compensated for, thus eliminating additional power consumption. This provides a power efficiency advantage. Additionally, the high computation frequency of matrix multiplication arrays eliminates the need for prolonged storage of intermediate data results, avoiding the overhead of refreshing the IGZO dynamic accumulator. Existing IGZOs can already operate at low voltages, facilitating integration with CMOS circuits. Due to back-end line compatibility, advanced processes can achieve 3D stacking with CMOS circuits at low voltages, connecting to matrix multiplication arrays via 3D stacking. Because of the low leakage current of IGZOs, using IGZO dynamic accumulators to form memory cells allows for 3D integration within thicker processes, further reducing circuit area.
[0051] As an alternative approach, the matrix multiplication array 3 can consist of multiple multiply-accumulate computation units arranged in a three-dimensional array, with equidistant distances between adjacent units and their outputs connected. For example... Figure 2A cuboid marked with an "×+" symbol represents a multiply-accumulate calculation unit. Through broadcasting, each input data Xi of input matrix 1 can be transmitted to the first input terminal of all multiply-accumulate calculation units in the first dimension corresponding to that input data, serving as the first input of each multiply-accumulate calculation unit. Similarly, each weight data Wi of weight matrix 2 can be transmitted to the second input terminal of all multiply-accumulate calculation units in the second dimension corresponding to that weight data. Each multiply-accumulate calculation unit then performs calculations on the received data.
[0052] Specifically, the multiply-accumulate unit is used to perform multiply-accumulate calculations on the corresponding input data and the corresponding weight data; the multiply-accumulate unit includes a multiplier and an adder, the output of the multiplier is connected to the input of the adder; the first input of the multiplier is connected to the input matrix, the second input of the multiplier is connected to the weight matrix, and the output of the adder is connected to the input of the corresponding IGZO dynamic accumulator.
[0053] As an alternative, a CMOS transistor can be used instead of the multiply-accumulate unit. The CMOS transistor can be an NMOS transistor, a PMOS transistor, or other transistors. For details, see [link to documentation]. Figure 5 and Figure 6 The matrix multiplication array comprises multiple CMOS transistors arranged uniformly in a three-dimensional array. The gates of the CMOS transistors are connected to the corresponding input data Vinput, and the sources are connected to the corresponding weight data Vweight. The drains of adjacent CMOS transistors are connected and also connected to the input terminal of an IGZO dynamic accumulator. The input matrix converts the input data into an input voltage signal, and the weight matrix converts the weight data into a weight voltage signal. This allows the input data and weight data to be input into the matrix multiplication array composed of CMOS transistors in voltage form. The source current of the CMOS transistors is proportional to the product of the input voltage signal and the weight voltage signal. The output current of the matrix multiplication array charges the gate of the first-stage IGZO flip-flop. When the charge of the first-stage IGZO accumulates to a certain threshold, the flip-flop flips, outputting 1.
[0054] like Figure 7 As shown, the present invention also provides a computation method for a three-dimensional in-memory computing architecture, applied to the aforementioned three-dimensional in-memory computing architecture. The three-dimensional in-memory computing architecture includes a matrix multiplication array, an input matrix, a weight matrix, and a storage unit; the matrix multiplication array is a three-dimensional array; the input matrix is connected to the first input terminal of the matrix multiplication array, and the weight matrix is connected to the second input terminal of the matrix multiplication array; the storage unit is connected to the output terminal of the matrix multiplication array; the method includes the following steps:
[0055] Step 101: Map the input data to the input matrix, read the weight data from the weight storage array, and map the weight data to the weight matrix.
[0056] Step 102: Perform a mixed inner and outer product operation on the input matrix and the weight matrix to obtain the output result; broadcast the input matrix along the first dimension of the matrix multiplication array, and broadcast the weight matrix along the second dimension of the matrix multiplication array;
[0057] Step 103: Store the output results.
[0058] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).
[0059] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.
[0060] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.
Claims
1. A three-dimensional in-memory computing architecture, characterized in that, include: Matrix multiplication array, input matrix, weight matrix, and storage unit; The matrix multiplication array is a three-dimensional array; the input matrix is connected to the first input terminal of the matrix multiplication array, and the weight matrix is connected to the second input terminal of the matrix multiplication array; the storage unit is connected to the output terminal of the matrix multiplication array. The matrix multiplication array is used to perform a mixed inner and outer product operation on the input matrix and the weight matrix; the input matrix is broadcast along the first dimension of the matrix multiplication array, and the weight matrix is broadcast along the second dimension of the matrix multiplication array; The storage unit is used to store the output results of the matrix multiplication array.
2. The three-dimensional in-memory computing architecture according to claim 1, characterized in that, The storage unit consists of multiple IGZO dynamic accumulators, which are arranged in a two-dimensional planar array.
3. The three-dimensional in-memory computing architecture according to claim 1, characterized in that, The matrix multiplication array performs an outer product calculation on the first plane by taking the outer product of each column vector of the input matrix with each row vector of the weight matrix, and performs an inner product calculation on the third dimension by taking the inner product of each row vector of the input matrix with each column vector of the weight matrix; the first plane is the plane formed by the first dimension and the second dimension.
4. The three-dimensional in-memory computing architecture according to claim 2, characterized in that, The IGZO dynamic accumulator includes a first IGZO transistor, a second IGZO transistor, a third IGZO transistor, a fourth IGZO transistor, a first NMOS transistor, and a second NMOS transistor. The gate of the first IGZO transistor is connected to a clock signal, and the drain of the first IGZO transistor is connected to the output terminal of the matrix multiplication array. The source of the first IGZO transistor is connected to the gate of the first NMOS transistor and the gate of the second IGZO transistor. The drain of the first NMOS transistor is connected to the source of the second IGZO transistor and the source of the third IGZO transistor. The drain of the second IGZO transistor is grounded. The gate of the third IGZO transistor is connected to the inverted signal of the clock signal, and the drain of the third IGZO transistor is connected to the gate of the second NMOS transistor and the gate of the fourth IGZO transistor. The drain of the second NMOS transistor is connected to the source of the fourth IGZO transistor, and the drain of the fourth IGZO transistor is grounded.
5. The three-dimensional in-memory computing architecture according to claim 1, characterized in that, The matrix multiplication array includes multiple multiply-accumulate calculation units arranged in a three-dimensional array. Each multiply-accumulate calculation unit is used to perform multiplication and accumulation calculations on corresponding input data and corresponding weight data. Each multiply-accumulate calculation unit includes a multiplier and an adder. The output of the multiplier is connected to the input of the adder. The first input of the multiplier is connected to the input matrix, the second input of the multiplier is connected to the weight matrix, the output of the adder is connected to the input of the corresponding IGZO dynamic accumulator, and the outputs of two adjacent multiply-accumulate calculation units are connected.
6. The three-dimensional in-memory computing architecture according to claim 1, characterized in that, The matrix multiplication array includes multiple CMOS transistors arranged in a three-dimensional array. The gate of each CMOS transistor is connected to the corresponding input data, the source of each CMOS transistor is connected to the corresponding weight data, the drain of each CMOS transistor is connected to the input of an IGZO dynamic accumulator, and the drains of two adjacent CMOS transistors are connected together.
7. The three-dimensional in-memory computing architecture according to claim 1, characterized in that, The three-dimensional in-memory computing architecture also includes a weight storage array, which is connected to the input of an amplifier circuit, and the output of the amplifier circuit is connected to the weight matrix.
8. The three-dimensional in-memory computing architecture according to claim 1, characterized in that, The input matrix is used to convert input data into an input voltage signal, and the weight matrix is used to convert weight data into a weight voltage signal. The source current of the CMOS transistor is proportional to the product of the input voltage signal and the weight voltage signal.
9. A computational method for a three-dimensional in-memory computing architecture, applied to the three-dimensional in-memory computing architecture described in any one of claims 1-8, characterized in that, The three-dimensional in-memory computing architecture includes a matrix multiplication array, an input matrix, a weight matrix, and a storage unit; the matrix multiplication array is a three-dimensional array; the input matrix is connected to the first input terminal of the matrix multiplication array, and the weight matrix is connected to the second input terminal of the matrix multiplication array; the storage unit is connected to the output terminal of the matrix multiplication array. The input matrix and the weight matrix are subjected to a mixed inner and outer product operation to obtain the output result; the input matrix is broadcast along the first dimension of the matrix multiplication array, and the weight matrix is broadcast along the second dimension of the matrix multiplication array. The output results are stored.
10. The computation method of a three-dimensional in-memory computing architecture according to claim 9, characterized in that, Before performing the mixed inner and outer product operation on the input matrix and the weight matrix, the following is also included: The input data is mapped into the input matrix, the weight data is read from the weight storage array, and the weight data is mapped into the weight matrix.