Current sensor package based on gallium arsenide hall chip and method of manufacture

Abstract

The application relates to the technical field of semiconductor packaging bodies, in particular to a current sensor packaging body based on a gallium arsenide Hall chip and a preparation method thereof, which comprises the following steps: a first part is provided with a flow guide structure, the flow guide structure forms a flow path for a to-be-detected current; an isolation piece is arranged on the surface of the first part, a first Hall chip and a second Hall chip are arranged at different positions of the flow guide structure through the isolation piece, a signal processing chip is arranged on a second part, and the first Hall chip and the second Hall chip are connected with the signal processing chip respectively. The application guides the to-be-detected current to pass through the corresponding positions of the first Hall chip and the second Hall chip through the flow guide structure, improves the utilization rate of the magnetic field, realizes the electrical isolation of the Hall chip and the conductive frame through the isolation piece, takes into account the magnetic field detection strength and the voltage resistance performance, simultaneously separates and arranges the signal processing chip and the current-carrying area, reduces the magnetic field interference generated by the large current, and thus improves the sensitivity, the signal-to-noise ratio and the stability of the current detection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically to a current sensor package based on a gallium arsenide Hall chip and its fabrication method. Background Technology

[0002] In existing packaging structures, the Hall chip is mounted on the surface of a copper frame. The distance between the magnetically sensitive surface at the top of the Hall chip and the conductive frame (which serves as the current-carrying region) is formed by the chip thickness and an insulating layer, thus limiting the relative position between the magnetically sensitive surface and the current-carrying region due to the packaging structure. Because the magnetic field distribution varies at different locations within the conductive frame, especially at locations far from the effective current-carrying region or along the thickness of the current conductor, the magnetic flux density attenuates significantly. This can lead to a decrease in the magnetic field strength at the magnetically sensitive surface of the Hall chip, resulting in attenuation of the Hall output signal, affecting the resolution of current detection, and making it difficult to fully utilize the high sensitivity characteristics of the GaAs Hall chip.

[0003] On the other hand, in some existing packaging structures, the conductive frame extends to the conductive frame pin area on the opposite side through a bending structure, forming a certain overlap between the two bending areas. The Hall chip is then placed on the surface of the pin area. The distance between the Hall chip and the conductive frame needs to be adjusted to balance magnetic field strength and electrical insulation performance. A large distance reduces the magnetic field strength at the Hall chip's location, leading to decreased detection sensitivity; a small distance can result in insufficient creepage distance between the current-carrying copper conductor and the Hall chip's pin area, posing a risk of insulation breakdown under high-voltage operating conditions. Therefore, existing structures struggle to simultaneously achieve both strong magnetic field detection and high-voltage insulation performance for the Hall chip. In existing packaging structures, the Hall chip is connected to the corresponding pins via bonding wires. Some bonding wires need to cross the current-carrying area of ​​the current-carrying copper conductor, which can easily generate induced noise. Summary of the Invention

[0004] (a) Purpose of the invention The purpose of this invention is to provide a current sensor package and its fabrication method based on a gallium arsenide Hall chip. The current to be detected is guided through the corresponding positions of the first and second Hall chips by a current-conducting structure, thereby improving the magnetic field utilization rate. The electrical isolation between the Hall chip and the conductive frame is achieved by an isolator, which takes into account both the magnetic field detection strength and withstand voltage performance. At the same time, the signal processing chip is separated from the current-carrying area to reduce magnetic field interference generated by large currents, thereby improving the sensitivity, signal-to-noise ratio and stability of current detection.

[0005] (II) Technical Solution To address the above problems, this invention provides a current sensor package based on a gallium arsenide Hall effect chip, comprising: Conductive frame, signal processing chip, first Hall chip, second Hall chip, and isolator; The conductive frame includes a first part and a second part, which are spaced apart. The first part is provided with a current guiding structure, which forms a flow path for the current to be detected; The isolator is disposed on the surface of the first part, and the first Hall chip and the second Hall chip are disposed at different positions of the current guiding structure through the isolator. The current guiding structure is used to guide the current to be detected through the first Hall chip and the second Hall chip. The signal processing chip is disposed in the second part, and the first Hall chip and the second Hall chip are respectively connected to the signal processing chip.

[0006] In another aspect of the present invention, preferably, the first part is provided with a current terminal and a wiring terminal, wherein the current terminal is the end of the first part away from the second part, and the wiring terminal is the end of the first part closer to the second part; The current terminal includes a current inlet and a current outlet. The current to be detected enters from the current inlet, flows along the current guiding structure, and exits from the current outlet.

[0007] In another aspect of the present invention, preferably, the current guiding structure includes a first groove and a second groove, the first groove extending inward from the terminal and the second groove extending inward from the current terminal; The second groove includes a first groove and a second groove, which are connected. The first groove is a T-shaped groove, which is located in the middle of the first part and is symmetrically arranged along the longitudinal axis of the first part.

[0008] In another aspect of the present invention, preferably, the T-slot includes a horizontal groove portion and a vertical groove portion, wherein the vertical groove portion communicates with the horizontal groove portion; The second groove extends into the first part from one end of the transverse groove portion; The vertical groove portion of the T-slot is connected to the current end, and the two sides of the vertical groove portion are the current inlet and the current outlet. The first groove and the second groove are staggered; The first Hall chip is disposed at the bottom of the first groove, and the second Hall chip is disposed at the bottom of the second groove.

[0009] In another aspect of the present invention, preferably, the coverage area of ​​the isolation member is greater than or equal to the area where the first groove and the second groove are located; The first Hall chip is disposed at the bottom of the first groove through the isolation member, and the first Hall chip is connected to the signal processing chip through bonding wire; The second Hall chip is disposed at the bottom of the second groove through the isolator, and the second Hall chip is connected to the isolator through a bonding wire. The isolator is connected to the signal processing chip.

[0010] In another aspect of the present invention, preferably, the isolation component includes a first circuit interface, a second circuit interface, a shielding layer, and a circuit layer; the shielding layer is disposed between the first portion and the circuit layer, and the circuit layer connects the first circuit interface and the second circuit interface; The projection position of the first circuit interface corresponds to the second groove, and the projection position of the second circuit interface corresponds to the gap between the first part and the second part. The first circuit interface is connected to the second Hall chip via a bonding wire, and the second circuit interface is connected to the signal processing chip via a bonding wire.

[0011] In another aspect of the present invention, preferably, the second part includes a pin group and a support portion, the support portion being connected to a portion of the pins in the pin group, and the support portion being disposed at one end of the second part near the first part; The signal processing chip is disposed on the surface of the support portion, and the signal processing chip is connected to the corresponding pins in the pin group.

[0012] In another aspect of the present invention, preferably, the outer contour of the first portion is configured as a beveled edge structure symmetrical along the longitudinal axis of the first portion; The first part also includes a plurality of through holes, which are symmetrically arranged along the longitudinal axis of the first part.

[0013] In another aspect, preferably, the invention further includes a packaging housing that encapsulates the signal processing chip, the first Hall chip, the second Hall chip, the isolator, a portion of the first portion, and a portion of the second portion.

[0014] In another aspect, preferably, a method for fabricating a current sensor package based on a gallium arsenide Hall chip is provided. The method is applicable to fabricating the aforementioned current sensor package based on a gallium arsenide Hall chip, and includes: The conductive framework is fabricated based on its planar structure. Based on the structure of the isolation component, the isolation component is prepared; The insulating element is attached to the bottom of the conductive frame to obtain the first component; The signal processing chip is attached to the second part of the first component, and the first Hall chip and the second Hall chip are placed at corresponding positions in the first part of the first component to obtain the second component. The first Hall chip is connected to the signal processing chip, the second Hall chip is connected to the isolator, the isolator is connected to the signal processing chip, and the signal processing chip is connected to the second part to obtain the third component; The corresponding positions of the first Hall chip and the second Hall chip are filled with insulating adhesive to obtain a current sensor package based on gallium arsenide Hall chip.

[0015] (III) Beneficial Effects The above-described technical solution of the present invention has the following beneficial technical effects: This invention establishes a current-guiding structure in the first part of the conductive frame to form a current-guiding path for the current to be detected. This allows the current to pass through the detection positions corresponding to the first and second Hall chips, which helps to improve the utilization rate of the magnetic field generated in the current-carrying region and enhance the induced magnetic field strength of the Hall chips. This fully utilizes the high sensitivity of the gallium arsenide Hall chips and improves the resolution of high-current detection. By placing the signal processing chip in the second part, which is spaced apart from the first part, and using an isolation component as an intermediate connection circuit, the signal processing region can be separated from the high-current-carrying region. This reduces the interference of the alternating magnetic field generated by the current-carrying current on the signal processing and connection structure, balances magnetic field detection performance and high voltage withstand performance, reduces detection noise, and improves the signal-to-noise ratio, detection accuracy, and operational reliability of the current sensor. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the conductive frame, signal processing chip, first Hall chip, second Hall chip and isolation component structure according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a conductive frame structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the conductive frame and isolation component structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the isolation component structure according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the internal structure of an embodiment of the present invention; Figure 6 This is a schematic diagram of the overall structure of one embodiment of the present invention; Figure 7 This is a current flow path diagram according to an embodiment of the present invention; Figure label: 1: Conductive frame; 110: First part; 111: Current inlet; 112: Current outlet; 113: First groove; 114: Second groove; 114a: First slot; 114b: Second slot; 115: Through hole; 120: Second part; 121: Pin group; 122: Support part. 2: Signal processing chip, 3: First Hall chip, 4: Second Hall chip, 5: Isolator; 510: First circuit interface; 520: Second circuit interface. 6: Encapsulation housing. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0018] The accompanying drawings illustrate a layer structure according to an embodiment of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0019] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0022] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0023] Example 1 A current sensor package based on a gallium arsenide Hall chip. Figure 1 This is a schematic diagram of the conductive frame, signal processing chip, first Hall chip, second Hall chip, and isolation component structure according to an embodiment of the present invention; as shown. Figure 1 As shown, it includes: The components include a conductive frame 1, a signal processing chip 2, a first Hall chip 3, a second Hall chip 4, and an isolator 5. Here, the first Hall chip 3 and the second Hall chip 4 are both gallium arsenide Hall chips, used to sense the magnetic field formed around the conductive frame 1 by the current to be detected, and to convert the sensed magnetic field into a corresponding Hall detection signal.

[0024] Figure 2 A schematic diagram of a conductive frame structure according to an embodiment of the present invention is shown. Figure 3 A schematic diagram of the conductive frame and insulating structure according to an embodiment of the present invention is shown, as follows. Figure 2 and Figure 3As shown, the conductive frame 1 forms the current-carrying path for the current to be detected and also serves as a mounting and connection carrier for some functional components within the current sensor package. The conductive frame 1 includes a first part 110 and a second part 120, which are spaced apart. The first part 110 forms the current-carrying area, and the second part 120 is used to mount and connect the signal processing chip 2. By spaced the first part 110 and the second part 120, the high-current-carrying area and the signal processing area are spatially separated, reducing the impact of the magnetic field and heat generated during high-current flow on the operation of the signal processing chip 2. The specific material of the conductive frame 1 is not limited here, as long as it meets the requirements for current transmission and mechanical support of the package structure. For example, the conductive frame 1 can be made of copper, copper alloy, aluminum, aluminum alloy, or other conductive metal materials. The conductive frame 1 can be formed by stamping, bending, a combination of stamping and bending, etching, machining, or other suitable metal forming processes. The specific external structure of the first part 110 and the second part 120 is not limited here, as long as the first part 110 can form a flow area for the current to be detected, the second part 120 can be used to set and connect the signal processing chip 2, and a preset spatial interval is maintained between the first part 110 and the second part 120. Optionally, the first part 110 can be a plate-like structure, a strip-like structure, a bent plate-like structure, or a plate-like structure with local concave and convex structures, and the second part 120 can be a plate-like pin structure, a sheet-like pin structure, a support platform structure, etc. In this embodiment, the outer contour of the first part 110 is set as a symmetrical beveled edge structure along the longitudinal axis of the first part 110. The first part 110 has a longitudinal axis extending along its longitudinal direction, which refers to a reference center line extending along the length direction of the first part 110. The outer contours on both sides of the first part 110 are symmetrically arranged with respect to the longitudinal axis and respectively form dimensionally contracted beveled edges towards the ends. By setting a symmetrical beveled edge structure, the first part 110 can form a relatively regular outer contour in its width direction, and the structural dimensions and spatial distribution on both sides of the first part 110 can be kept relatively consistent. Furthermore, the beveled edge structure can be disposed at at least one end of the first portion 110 along the longitudinal axis, or it can be disposed at both ends of the first portion 110, so that the first portion 110 forms an end profile that gradually changes along the longitudinal axis. The inclination angle, length, and specific position of the beveled edge structure on the first portion 110 can be set according to the arrangement position of the current guiding structure, the installation position of the first Hall chip 3 and the second Hall chip 4, and the overall size of the conductive frame 1. This embodiment does not impose specific limitations on these aspects.

[0025] In this embodiment, the second part 120 includes a pin group 121 and a support part 122. The pin group 121 includes multiple pins, which are used to realize electrical connection between the current sensor package and external circuits, and can be used for power input, signal input, signal output, grounding, or other electrical signal transmission. The support part 122 is connected to some pins in the pin group 121. The support part 122 is used to support the signal processing chip 2. The support part 122 forms a support structure by connecting to some pins in the pin group 121, and also defines the position of the support part 122 and the pin group 121. The support part 122 is disposed at the end of the second part 120 near the first part 110, which can form a shorter signal transmission path between the signal processing chip 2 and the first part 110. The specific structure of the signal processing chip 2 is not limited here. Optionally, it can be a rectangular structure, and the area of ​​the support part 122 is larger than the area of ​​the signal processing chip 2.

[0026] The signal processing chip 2 is disposed on the surface of the support portion 122. The signal processing chip 2 can be attached to the surface of the support portion 122 by adhesive bonding. The signal processing chip 2 is connected to some pins of the pin group 121. The signal processing chip 2 can be connected to corresponding pins in the pin group 121 via bonding wires to realize signal transmission between the signal processing chip 2 and external circuits. Different pins in the pin group 121 can be connected to different functional terminals of the signal processing chip 2, thereby providing the signal processing chip 2 with functions such as operating power, reference potential, grounding, and detection signal output. Here, each corresponding pin includes at most one pin connected to the support portion 122 to prevent the possibility of signal crosstalk.

[0027] The first part 110 is provided with a current terminal and a wiring terminal. The current terminal is the end of the first part 110 away from the second part 120 and is used to connect to an external current circuit to be detected, so that the current to be detected enters the first part 110 and is transmitted along a preset flow path. The wiring terminal is the end of the first part 110 closer to the second part 120. The current terminal includes a current inlet 111 and a current outlet 112. The current inlet 111 and the current outlet 112 are used to realize the input and output of the current to be detected, respectively. The current to be detected enters from the current inlet 111, flows along the current guiding structure, and flows out from the current outlet 112. After the current to be detected enters the first part 110 from the current inlet 111, it flows along the flow path formed by the current guiding structure and finally flows out from the current outlet 112, thereby forming a continuous current-carrying path in the first part 110. The current inlet 111 and the current outlet 112 are respectively disposed at the current end of the first part 110, and the current inlet 111 and the current outlet 112 are spaced apart to form the input area and output area of ​​the current to be detected, respectively. Within a limited area, a reliable flow path is formed. Furthermore, in this embodiment, the current inlet 111 and the current outlet 112 are configured as a planar structure. A planar structure means that the side of the current inlet 111 and the current outlet 112 used for connection with external circuits has a relatively flat and continuous contact surface, allowing the current inlet 111 and the current outlet 112 to contact the corresponding pads on the external PCB with a larger contact area and form an electrical connection. Compared with connection structures with partial protrusions, linear contacts, or point contacts, the planar structure can increase the effective contact area between the current inlet 111, the current outlet 112 and the PCB pads, which is beneficial to improving the reliability of electrical connections during high current transmission. Simultaneously, the increased contact area with the external PCB pads enhances the heat conduction channel of the conductive frame 1 during overcurrent, allowing heat to be conducted to the PCB pads for dissipation more quickly. The first part 110 is provided with a current-guiding structure, which forms a flow path for the current to be detected. The specific content of the current-guiding structure is not limited here, as long as it can form a continuous conductive path and guide the current to be detected to flow in a preset direction. Optionally, the current-guiding structure may include one or more of the following: a straight current-guiding section, a bent current-guiding section, a curved current-guiding section, a reversing current-guiding section, a staggered current-guiding section, and current-guiding sections with different widths or different extension directions, or it may be formed by a combination of the above-mentioned current-guiding sections. In this embodiment, the current-guiding structure includes a first groove 113 and a second groove 114. The first groove 113 extends inward from the terminal, and the second groove 114 extends inward from the current terminal.The first groove 113 and the second groove 114 are both formed in local areas of the first portion 110, used to change the conductive cross-section and current distribution in different areas of the first portion 110, so that the current to be detected can flow along a preset path, and corresponding current-carrying areas are formed at the corresponding positions of the first Hall chip 3 and the second Hall chip 4. The first groove 113 and the second groove 114 can be formed by stamping, etching, milling, punching or other suitable processing methods on the first portion 110, and this embodiment does not specifically limit this. The depth of the first groove 113 and the second groove 114 can be set according to the magnitude of the current to be detected and the current flow path to be formed. Current cannot pass through the positions of the first groove 113 and the second groove 114, so the current will flow along the corresponding path, and the conductive frame 1 generates a magnetic field.

[0028] The second groove 114 includes a first groove body 114a and a second groove body 114b, which are connected to form a continuous groove structure. The first groove body 114a is a T-shaped groove, which is disposed in the middle of the first part 110 and symmetrically arranged along the longitudinal axis of the first part 110. The T-shaped groove includes a horizontal groove portion and a vertical groove portion, which are connected to the horizontal groove portion. The horizontal groove portion extends along the width direction of the first part 110, and the vertical groove portion extends along the longitudinal direction of the first part 110. The vertical groove portion of the T-shaped groove is connected to the current end, that is, it extends inward from the current end. The two sides of the vertical groove portion are a current inlet 111 and a current outlet 112. The current inlet 111 and the current outlet 112 form two current-carrying regions spaced apart at the current end, and a current flow path defined by a current guiding structure is formed between them. The specific length, width, and depth of the horizontal and vertical slots can be set according to the overall size of the first part 110, the magnitude of the current to be detected, and the installation positions of the first Hall chip 3 and the second Hall chip 4. This embodiment does not impose specific limitations on these parameters.

[0029] The second groove 114b extends into the first portion 110 along one end of the transverse groove and communicates with the first groove 114a. That is, the second groove 114b and the T-groove are not independent of each other, but together form a continuous second groove 114 structure. The second groove 114b can extend along the length direction, width direction, or at a certain angle relative to the length direction of the first portion 110. Its specific extension direction can be determined based on the arrangement of the first Hall chip 3 and the second Hall chip 4, as well as the desired current flow path.

[0030] The first groove 113 and the second groove 114b are staggered; here the staggered arrangement is such that the first groove 113 and the second groove 114b are located on both sides of the longitudinal axis of the first part 110, and their extension directions are opposite.

[0031] The bottoms of the first groove 113 and the second groove 114b are both U-shaped grooves. The first Hall chip 3 and the second Hall chip 4 are positioned as close as possible to the corresponding groove bottoms. The height of the top magnetically sensitive surfaces of the first Hall chip 3 and the second Hall chip 4 does not exceed the plane of the upper surface of the conductive frame 1. The bottoms of the first Hall chip 3 and the second Hall chip 4 are supported by the insulating member 5. Furthermore, the first part 110 also includes a plurality of through holes 115, which are symmetrically arranged along the longitudinal axis of the first part 110. The through holes 115 can enhance the bonding strength between the insulating adhesive and the conductive frame 1.

[0032] In this embodiment, the impedance of the copper conductor is reduced through pattern optimization design, which helps to reduce heat loss when a large current passes through. In addition, the current inlet 111 and the current outlet 112 are designed to be completely planar, allowing them to be completely flush with the pads on the PCB. Compared with the wing-shaped leads of conventional surface mount packages, the planar leads increase the contact area with the pads on the PCB, which can conduct heat to the PCB for heat dissipation more quickly, reducing the temperature rise of the entire conductive frame 1.

[0033] The isolator 5 is disposed on the surface of the first part 110, which can be located at the bottom of the first part 110. The isolator 5 can be disposed on the bottom surface of the first part 110 by bonding, pressing, or other fixing methods to keep the isolator 5 relatively fixed to the first part 110. The first Hall chip 3 and the second Hall chip 4 are disposed at different positions in the current guiding structure through the isolator 5. The isolator 5 is used to support the first Hall chip 3 and the second Hall chip 4. The current guiding structure is used to guide the current to be detected through the first Hall chip 3 and the second Hall chip 4. The coverage area of ​​the isolator 5 is greater than or equal to the area where the first groove 113 and the second groove 114 are located. The isolator 5 extends along the bottom surface of the first portion 110, and its coverage area at least covers the areas where the first groove 113 and the second groove 114b are located, so that the Hall chips disposed in the first groove 113 and the second groove 114b can be supported by the isolator 5. The coverage area of ​​the isolator 5 is greater than or equal to the area where the first groove 113 and the second groove 114b are located, so that the first Hall chip 3 and the second Hall chip 4 can be respectively disposed at the corresponding positions of the isolator 5, and the Hall chips are prevented from directly contacting the conductive frame 1.

[0034] The first Hall chip 3 is disposed at the bottom of the first groove 113 via the isolator 5, and is connected to the signal processing chip 2 via a bonding wire. The first Hall chip 3 is disposed on the side of the isolator 5 facing the first groove 113, and is located at the bottom of the first groove 113, with the first Hall chip 3 and the bottom of the first groove 113 spaced apart by the isolator 5. The first Hall chip 3 is used to detect the magnetic field generated by the current to be detected flowing through the corresponding current path of the first groove 113, and converts the detected magnetic field information into a corresponding electrical signal. The first Hall chip 3 is electrically connected to the signal processing chip 2 via a bonding wire to transmit the detection signal output by the first Hall chip 3 to the signal processing chip 2.

[0035] The second Hall chip 4 is disposed at the bottom of the second groove 114b via the isolator 5. The second Hall chip 4 is connected to the isolator 5 via a bonding wire, and the isolator 5 is connected to the signal processing chip 2. The second Hall chip 4 is not directly connected to the signal processing chip 2; the two are connected via the isolator 5, thereby forming a signal transmission path between the second Hall chip 4 and the signal processing chip 2.

[0036] Figure 4 A schematic diagram of the isolation component structure according to an embodiment of the present invention is shown, as follows: Figure 4 As shown, the isolation component 5 includes a first circuit interface 510, a second circuit interface 520, a shielding layer, and a circuit layer; the shielding layer is disposed between the first part 110 and the circuit layer, and the circuit layer connects the first circuit interface 510 and the second circuit interface 520; the circuit layer is disposed on the side of the shielding layer away from the first part 110, and the first circuit interface 510 and the second circuit interface 520 are respectively disposed at the corresponding connection positions of the circuit layer, and are electrically connected through the circuit layer.

[0037] The projection position of the first circuit interface 510 corresponds to the second groove 114, and the projection position of the second circuit interface 520 corresponds to the gap between the first part 110 and the second part 120. The first circuit interface 510 is connected to the second Hall chip 4 via a bonding wire. The bonding wire connecting the first circuit interface 510 and the second Hall chip 4 is confined within the second groove 114b. The second circuit interface 520 is connected to the signal processing chip 2 via a bonding wire.

[0038] The isolator 5, through its layered structure design and precise control of the assembly dimensions of its current-carrying structure with the conductive frame 1, avoids the bonding wires crossing the current-carrying area of ​​the conductive frame 1 within its internal circuit layer. The shielding layer is placed between the bottom of the conductive frame 1 and the circuit layer, which can weaken the induced noise generated by the alternating magnetic field of the large current, reduce the measurement error of the current sensor, and improve the signal-to-noise ratio.

[0039] Furthermore, in this embodiment, the insulating member 5 is made of a structure consisting of three metal layers and three insulating layers. The specific material of the insulating layers is not limited here; it can be an FPC flexible board, alumina ceramic, or aluminum nitride ceramic as the insulating layer material, in conjunction with the corresponding metal layers. Table 1 shows the structure of the insulating member 5 in this embodiment, as shown in Table 1, consisting of three metal layers and three insulating layers.

[0040] Table 1 Structure of Isolator 5 further, Figure 5 A schematic diagram of the internal structure of an embodiment of the present invention is shown, as follows: Figure 5 As shown, after the first Hall chip 3 and the signal processing chip 2 are connected by bonding wires, the position groove is filled with insulating adhesive. After the bonding wire connecting the first circuit interface 510 and the second Hall chip 4 is confined within the second groove 114b, the groove is filled with insulating adhesive. Furthermore, insulating adhesive wraps the perpendicular intersection area of ​​the conductive frame 1 and the insulating pad, further strengthening the insulation effect and improving the isolation withstand voltage characteristics of the current sensor. This reduces the risk of high voltage discharge breakdown of the conductive frame 1 to the Hall chip and the signal processing chip 2.

[0041] Figure 6 A schematic diagram of the overall structure of an embodiment of the present invention is shown, as follows. Figure 6 As shown, the device also includes a housing 6, which encapsulates the signal processing chip 2, the first Hall chip 3, the second Hall chip 4, the isolator 5, a portion of the first part 110, and a portion of the second part 120. The housing 6 can be formed using an insulating encapsulation material, such as epoxy resin, molding compound, or other encapsulation materials with insulating properties and mechanical strength. The housing 6 can be formed by injection molding, compression molding, potting, or other encapsulation processes, creating a stable bond between the housing 6, the conductive frame 1, and the isolator 5. After formation, the housing 6 encapsulates the signal processing chip 2, the first Hall chip 3, the second Hall chip 4, and the isolator 5, thereby mechanically securing the devices and reducing the impact of the external environment on the internal components.

[0042] Furthermore, in this embodiment, the physical distance between the first part 110 and the second part 120 is 0.97mm to prevent breakdown and ensure detection performance. The width of the connecting end is approximately 4.5mm, extending linearly along both sides at an angle of approximately 53° to a full width of 9.5mm, with a bevel transition height of approximately 1.6mm. Circular through holes 115 are distributed on both sides, perfectly mirror-symmetrical along the longitudinal axis, used to strengthen the bonding force between the insulating adhesive and the conductive frame 1. The through holes 115 penetrate the thickness direction of the board, with a diameter primarily of 0.5mm. The conductive frame 1 has a T-shaped groove arranged along the longitudinal axis at its center, consisting of a vertical groove (0.5mm wide, approximately 2.1mm deep along the Z direction) and a top horizontal groove, symmetrical about the longitudinal axis. The through holes 115 maintain left-right mirror symmetry. Figure 7 A current flow path diagram according to an embodiment of the present invention is shown, as follows: Figure 7 As shown, the structures of the first groove 113 and the second groove 114b do not possess left-right mirror symmetry—the first groove 113 on the left is the upper groove, extending downwards by approximately 1.3mm from the connecting end of the conductive frame 1, cutting off the path for the bottom current to flow from the left side to the edge; the second groove 114b on the right extends upwards from the middle horizontal groove portion to the upper part of the conductive frame 1 by approximately 1.3mm, reducing the effective cross-section on the right side of the middle. The first groove 113 and the second groove 114b on both sides act on different height ranges of the conductive frame 1, forming a staggered blocking layout of low and high. It is this asymmetrical layout that causes the remaining portion of the solid conductive frame 1 to form a continuous S-shaped bent conductive path, with the S-shaped conductive path bending twice along the current direction. The height of the Hall chip within the groove is controlled at 0.45mm≤H≤0.50mm, further enhancing the Hall chip's efficiency in picking up the magnetic field of the copper wire. The distance from the right edge of the signal processing chip 2 to the edge of the support portion 122 is 0.13mm, and the lower edge of the signal processing chip 2 is flush with the edge of the support portion 122.

[0043] In this embodiment, a current-guiding structure is set in the first part 110 of the conductive frame 1 to form a current-guiding path for the current to be detected, so that the current to be detected can pass through the detection positions corresponding to the first Hall chip 3 and the second Hall chip 4. This is beneficial to improve the utilization rate of the magnetic field generated in the current-carrying area and enhance the induced magnetic field strength of the Hall chip, thereby giving full play to the high sensitivity of the gallium arsenide Hall chip and improving the resolution of high current detection. The signal processing chip 2 is set in the second part 120, which is spaced apart from the first part 110, and the isolation component 5 is set as an intermediate connection circuit. This can separate the signal processing area from the high current-carrying area, reduce the interference of the alternating magnetic field generated by the current-carrying current on the signal processing and connection structure, take into account both magnetic field detection performance and high voltage withstand performance, reduce detection noise, and improve the signal-to-noise ratio, detection accuracy and working reliability of the current sensor.

[0044] Example 2 A method for fabricating a current sensor package based on a gallium arsenide Hall chip, the method being applicable to fabricating the aforementioned current sensor package based on a gallium arsenide Hall chip, the method comprising: Based on the planar structure of the conductive frame 1, the conductive frame 1 is fabricated. The material can be non-magnetic copper. The first part 110 and the second part 120, meeting the planar structure requirements, are fabricated by stamping. A plate-shaped conductive material can be fabricated according to the unfolded dimensions of the conductive frame 1, and the first part 110 and the second part 120 are formed sequentially or in one step by a stamping process, with the first part 110 and the second part 120 positioned at a preset interval. During the stamping process, a flow-guiding structure is formed on the first part 110, and the first groove 113, the second groove 114, and a connecting structure corresponding to the second part 120 are formed. By controlling the dimensions of the stamping die and the stamping position, the dimensions of the first part 110, the second part 120, and the flow-guiding structure meet the preset requirements. After stamping, the conductive frame 1 can be deburred, cleaned, and surface-treated to remove burrs, oil stains, and other attachments generated during the stamping process, improving the reliability of subsequent bonding of the isolator 5 and chip installation.

[0045] Based on the structure of the isolator 5, the isolator 5 is fabricated; the isolator 5 is fabricated according to its layer structure and planar dimensions, so that the isolator 5 has an external dimension and mounting area that matches the conductive frame 1. The isolator 5 includes a first circuit interface 510, a second circuit interface 520, a shielding layer, and a circuit layer. The shielding layer is disposed between the first portion 110 and the circuit layer, and the circuit layer is used to connect the first circuit interface 510 and the second circuit interface 520.

[0046] The isolator 5 is attached to the bottom of the conductive frame 1 to obtain the first component; the conductive frame 1 is first rotated 180 degrees with the silver-plated side of the pins facing down, and the side of the isolator 5 with the circuit interface is attached to the corresponding area of ​​the conductive frame 1 using insulating adhesive.

[0047] The signal processing chip 2 is attached to the second part 120 of the first component, and the first Hall chip 3 and the second Hall chip 4 are set at corresponding positions in the first part 110 of the first component to obtain the second component; after flipping, the signal processing chip 2, the first Hall chip 3 and the second Hall chip 4 are set at corresponding positions.

[0048] The first Hall chip 3 is connected to the signal processing chip 2, the second Hall chip 4 is connected to the isolator 5, the isolator 5 is connected to the signal processing chip 2, and the signal processing chip 2 is connected to the second part 120 to obtain the third component; specifically, the first Hall chip 3 and the signal processing chip 2 are directly connected through a bonding wire, the second Hall chip 4 is first connected to the first circuit interface 510 through a bonding wire, and the second circuit interface 520 is connected to the signal processing chip 2.

[0049] The corresponding positions of the first Hall chip 3 and the second Hall chip 4 are filled with insulating adhesive to obtain a current sensor package based on gallium arsenide Hall chips. Using standard semiconductor packaging processes, the cavity where the signal processing chip 2, the first Hall chip 3, and the second Hall chip 4 are connected is filled with insulating adhesive. The insulating adhesive wraps around the first Hall chip 3 and the second Hall chip 4, and the vertical intersection area where the conductive frame 1 and the insulating member 5 are attached also needs to be fixed with insulating adhesive. The purpose of all this is to enhance insulation performance.

[0050] Using standard semiconductor packaging processes, a molding process is performed to completely encapsulate the product, forming a molded device.

[0051] This embodiment features simple assembly, clear process path, high positioning accuracy, high insulation reliability, and suitability for mass production packaging. It can also fully utilize the detection performance of gallium arsenide Hall chips in high current detection scenarios.

[0052] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various methods existing in the prior art can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above.

[0054] The present invention has been described above with reference to embodiments thereof. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

[0055] Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the invention.

[0056] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A current sensor package based on a gallium arsenide Hall chip, characterized in that, include: Conductive frame, signal processing chip, first Hall chip, second Hall chip, and isolator; The conductive frame includes a first part and a second part, which are spaced apart. The first part is provided with a current guiding structure, which forms a flow path for the current to be detected; The isolator is disposed on the surface of the first part, and the first Hall chip and the second Hall chip are disposed at different positions of the current guiding structure through the isolator. The current guiding structure is used to guide the current to be detected through the first Hall chip and the second Hall chip. The signal processing chip is disposed in the second part, and the first Hall chip and the second Hall chip are respectively connected to the signal processing chip.

2. The current sensor package based on a gallium arsenide Hall chip according to claim 1, characterized in that, The first part is provided with a current terminal and a wiring terminal, wherein the current terminal is the end of the first part away from the second part, and the wiring terminal is the end of the first part closer to the second part; The current terminal includes a current inlet and a current outlet. The current to be detected enters from the current inlet, flows along the current guiding structure, and exits from the current outlet.

3. The current sensor package based on a gallium arsenide Hall chip according to claim 2, characterized in that, The current guiding structure includes a first groove and a second groove, wherein the first groove extends inward from the terminal and the second groove extends inward from the current terminal; The second groove includes a first groove and a second groove, which are connected. The first groove is a T-shaped groove, which is located in the middle of the first part and is symmetrically arranged along the longitudinal axis of the first part.

4. The current sensor package based on a gallium arsenide Hall chip according to claim 3, characterized in that, The T-slot includes a horizontal groove portion and a vertical groove portion, wherein the vertical groove portion is connected to the horizontal groove portion; The second groove extends into the first part from one end of the transverse groove portion; The vertical groove portion of the T-slot is connected to the current end, and the two sides of the vertical groove portion are the current inlet and the current outlet. The first groove and the second groove are staggered; The first Hall chip is disposed at the bottom of the first groove, and the second Hall chip is disposed at the bottom of the second groove.

5. The current sensor package based on a gallium arsenide Hall chip according to claim 4, characterized in that, The coverage area of ​​the isolation element is greater than or equal to the area where the first groove and the second groove are located; The first Hall chip is disposed at the bottom of the first groove through the isolation member, and the first Hall chip is connected to the signal processing chip through bonding wire; The second Hall chip is disposed at the bottom of the second groove through the isolator, and the second Hall chip is connected to the isolator through a bonding wire. The isolator is connected to the signal processing chip.

6. The current sensor package based on a gallium arsenide Hall chip according to claim 5, characterized in that, The isolation component includes a first circuit interface, a second circuit interface, a shielding layer, and a circuit layer; the shielding layer is disposed between the first part and the circuit layer, and the circuit layer connects the first circuit interface and the second circuit interface. The projection position of the first circuit interface corresponds to the second groove, and the projection position of the second circuit interface corresponds to the gap between the first part and the second part. The first circuit interface is connected to the second Hall chip via a bonding wire, and the second circuit interface is connected to the signal processing chip via a bonding wire.

7. The current sensor package based on a gallium arsenide Hall chip according to claim 6, characterized in that, The second part includes a pin group and a support portion, wherein the support portion is connected to a portion of the pins in the pin group, and the support portion is disposed at one end of the second part near the first part; The signal processing chip is disposed on the surface of the support portion, and the signal processing chip is connected to the corresponding pins in the pin group.

8. The current sensor package based on a gallium arsenide Hall chip according to claim 7, characterized in that, The outer contour of the first part is set as a beveled edge structure symmetrical along the longitudinal axis of the first part; The first part also includes a plurality of through holes, which are symmetrically arranged along the longitudinal axis of the first part.

9. The current sensor package based on a gallium arsenide Hall chip according to claim 1, characterized in that, It also includes a packaging housing that encapsulates the signal processing chip, the first Hall chip, the second Hall chip, the isolator, a portion of the first portion, and a portion of the second portion.

10. A method for fabricating a current sensor package based on a gallium arsenide Hall chip, characterized in that, The preparation method is applicable to preparing a current sensor package based on a gallium arsenide Hall chip as described in any one of claims 1-9, wherein the preparation method includes: The conductive framework is fabricated based on its planar structure. Based on the structure of the isolation component, the isolation component is prepared; The insulating element is attached to the bottom of the conductive frame to obtain the first component; The signal processing chip is attached to the second part of the first component, and the first Hall chip and the second Hall chip are placed at corresponding positions in the first part of the first component to obtain the second component. The first Hall chip is connected to the signal processing chip, the second Hall chip is connected to the isolator, the isolator is connected to the signal processing chip, and the signal processing chip is connected to the second part to obtain the third component; The corresponding positions of the first Hall chip and the second Hall chip are filled with insulating adhesive to obtain a current sensor package based on gallium arsenide Hall chip.

Images