Battery on-line monitoring and remote capacity checking system

Abstract

The application discloses a kind of battery on-line monitoring and remote nuclear capacity system, it is related to battery monitoring field.The system includes microprocessor, front-stage drive circuit, H bridge polarity switching drive circuit, constant current regulating circuit, analog-digital conversion chip, direct memory access controller, remote communication module and controllable discharge nuclear capacity load circuit.Microprocessor controls drive circuit to inject bidirectional constant current excitation pulse to battery, and the ohmic voltage step value of polarity reversal moment is extracted to solve internal resistance by high-frequency acquisition terminal voltage response of analog-digital conversion chip and direct memory access controller;Remote nuclear capacity instruction received by remote communication module is responded to simultaneously, and controllable discharge nuclear capacity load circuit is controlled to carry out nuclear capacity discharge and assess battery health degree.The application realizes high-precision internal resistance on-line measurement and safe remote nuclear capacity.

Description

Technical Field

[0001] This invention relates to the field of battery monitoring technology, specifically to an online battery monitoring and remote capacity assessment system. Background Technology

[0002] In power and industrial DC power supply systems, the internal resistance of a single battery cell is a key indicator for assessing battery health and remaining capacity. Online detection of cell internal resistance typically employs methods such as injecting AC signals or DC pulse excitation. However, industrial DC power grids are often filled with strong non-Gaussian heavy-tailed electromagnetic noise generated by devices such as frequency converters and switching power supplies.

[0003] Existing internal resistance measurement methods often rely on heavy hardware low-pass filter circuits under strong DC grid interference. This causes the steep step edge of the terminal voltage response of the battery cell under test to be smoothed and distorted at the moment of polarity reversal, making it impossible to accurately extract the true ohmic voltage step value. This seriously affects the accuracy and reliability of online measurement of the ohmic internal resistance of the battery cell. Summary of the Invention

[0004] This invention provides an online monitoring and remote capacity assessment system for batteries, aiming to solve the technical problems in the prior art, such as voltage step edge distortion caused by hardware filtering and smoothing, and low measurement accuracy of the internal resistance of the battery cell under test under non-Gaussian background noise interference.

[0005] To achieve the above objectives, the present invention provides an online monitoring and remote capacity assessment system for batteries, comprising: a microprocessor, a front-end drive circuit, an H-bridge polarity switching drive circuit, a constant current regulation circuit, an analog-to-digital converter chip, a direct memory access controller, a remote communication module, and a controllable discharge capacity assessment load circuit. The microprocessor includes an on-chip timer peripheral and a memory. The control output terminal of the on-chip timer peripheral is connected to the input terminal of the pre-stage driver circuit. The output terminal of the pre-stage driver circuit is connected to the control input terminal of the H-bridge polarity switching driver circuit. The H-bridge polarity switching drive circuit and the constant current regulation circuit are connected in series to form a bidirectional pulse excitation circuit. The power output terminal of the bidirectional pulse excitation circuit is used to connect to the battery cell under test. The analog sampling input terminal of the analog-to-digital converter chip is directly connected to the battery cell under test, the data output terminal of the analog-to-digital converter chip is connected to the direct memory access controller, and the bus output terminal of the direct memory access controller is connected to the memory. The remote communication module is connected to the microprocessor; the control terminal of the controllable discharge capacity load circuit is connected to the microprocessor, and the power terminal of the controllable discharge capacity load circuit is connected across the two ends of the battery pack composed of the battery cells under test. The microprocessor is configured to: The on-chip timer peripheral outputs a PWM control signal to the front-end drive circuit to drive the H-bridge polarity switching drive circuit and the constant current regulation circuit to inject a bidirectional constant current excitation pulse with an amplitude of the first target excitation current and a pulse width of the second target pulse width into the battery cell under test. During the application of the bidirectional constant current excitation pulse, the terminal voltage response sequence of the battery cell under test is acquired at high frequency by the analog-to-digital converter chip and the direct memory access controller and directly stored in the memory; The terminal voltage response sequence is read from the memory, and the ohmic voltage step value is extracted from the terminal voltage response sequence according to the polarity reversal time. The ohmic internal resistance value of the battery cell under test is calculated based on the ohmic voltage step value and the first target excitation current. In response to the remote capacity control command received through the remote communication module, the controllable discharge capacity control load circuit is controlled to connect to the battery pack for discharge, and the capacity control status of the battery pack is dynamically evaluated based on the calculated internal resistance of each battery cell under test during the discharge process.

[0006] Preferably, the bidirectional constant current excitation pulse includes a forward constant current charging pulse and a reverse constant current discharging pulse applied sequentially, with a dead time between the forward constant current charging pulse and the reverse constant current discharging pulse, and the algebraic sum of the charges of the forward constant current charging pulse and the reverse constant current discharging pulse in a single measurement cycle is zero.

[0007] Preferably, the microprocessor is further configured to: acquire a background noise sequence of a DC power grid before controlling the output of the bidirectional constant current excitation pulse; calculate the fractional heavy-tailed probability moment characteristics and initial fluctuation amplitude of the background noise sequence; and adaptively offset the first target excitation current and the second target pulse width based on the probability moment characteristics and the initial fluctuation amplitude.

[0008] Preferably, there is no hardware low-pass filter circuit connected between the analog sampling input terminal of the analog-to-digital converter chip and the battery cell under test, so as to preserve the steep step edge of the terminal voltage response sequence at the moment of polarity reversal.

[0009] Preferably, the microprocessor is further configured to: after reading the terminal voltage response sequence, introduce first-order polarization ordinary differential equation constraints of the battery cell under test, construct a block kernel autocovariance matrix, and reconstruct a continuous voltage curve for the discrete terminal voltage response sequence.

[0010] Preferably, the microprocessor is further configured to: perform forward state estimation recursion along the positive time axis and backward likelihood probability recursion along the reverse time axis, with the polarity reversal moment of the bidirectional constant current excitation pulse as the center; and eliminate non-Gaussian heavy-tailed noise in the terminal voltage response sequence by normalizing the forward state estimation probability distribution and the backward likelihood probability distribution.

[0011] Preferably, after the microprocessor calculates the ohmic internal resistance of the battery cell under test based on the ohmic voltage step value and the first target excitation current, it is further configured to: calculate the average normalized estimation error squared value of the calculation result; determine whether the estimation error squared value falls within a preset tolerance range; if so, output and store the calculated ohmic internal resistance value; if not, determine that the measurement is invalid.

[0012] Preferably, after determining that the calculated ohmic internal resistance value is valid, the microprocessor compares the ohmic internal resistance value with the pre-stored reference internal resistance value of the battery cell to be tested; if the increase exceeds a preset threshold, an alarm signal is generated and a digital signature is attached and stored in the memory.

[0013] Preferably, after the analog-to-digital converter chip completes a single sampling, the direct memory access controller directly writes the converted digital voltage and hardware timestamp into a designated buffer of the memory without CPU core intervention.

[0014] Preferably, the pre-stage driving circuit includes an isolation optocoupler and a totem pole driving circuit, and the H-bridge polarity switching driving circuit includes four symmetrically arranged wide-bandgap semiconductor power switches. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a topology block diagram of a battery online monitoring and remote capacity assessment system according to an embodiment of the present invention; Figure 2 This is a timing diagram of the excitation current and acquisition terminal voltage waveforms involved in the embodiment of the present invention; Figure 3 This is a flowchart illustrating the overall process of online system monitoring and remote capacity approval in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0019] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0020] The present invention provides an online monitoring and remote capacity assessment system for batteries, the overall hardware topology of which is as follows: Figure 1 As shown, this system constructs a closed-loop architecture based on the microprocessor 101, consisting of "adaptive excitation - high-frequency direct sampling - software soft filtering and calculation". Through deep collaboration between hardware circuit design and on-chip software algorithms, the system abandons the traditional, heavy hardware low-pass filter that causes physical distortion to key signals, fundamentally solving the problem of inaccurate internal resistance measurement caused by voltage step edge distortion under strong noise background. This enables high-precision, non-destructive online monitoring of the 200-ohm internal resistance of the battery cell under test.

[0021] Below, we will elaborate on the specific technical means and implementation methods of this invention step by step, from hardware topology to software algorithms, in conjunction with the system's workflow.

[0022] First, the system's operation begins with the microprocessor 101 sensing the external environment and precisely controlling the power circuit. For example... Figure 1As shown, the microprocessor 101 uses its on-chip timer peripheral to generate a specific PWM control signal and outputs the signal to the front-end drive circuit 102. Considering the complex electrical environment of industrial applications, the front-end drive circuit 102 uses an isolation optocoupler. This not only achieves electrical isolation between the low-voltage control side of the microprocessor and the power side of the subsequent stage, ensuring system safety, but also effectively amplifies the PWM signal through the totem-pole drive circuit cascaded after the optocoupler, thereby enhancing its driving capability for the subsequent switching transistors.

[0023] The enhanced drive signal then controls the H-bridge polarity switching drive circuit 103. In the power loop, the H-bridge polarity switching drive circuit 103 and the constant current regulation circuit 104 are connected in series to form a bidirectional pulse excitation loop for connecting the battery cell under test 200. In particular, to ensure that the edge of the excitation pulse injected into the battery is sufficiently steep and that the constant current accuracy meets the stringent requirements of high-frequency sampling, the four power switches in the H-bridge circuit are symmetrically arranged wide-bandgap semiconductor devices (such as SiC or GaN MOSFETs). It is thanks to the excellent switching characteristics of these devices that the system can inject a special pulse excitation signal that meets the strict timing requirements into the battery cell under test 200.

[0024] In terms of signal acquisition and data transmission, this system adopts a "direct acquisition + direct memory access controller (DMA) high-speed temporary storage" topology, completely changing the traditional signal processing method. For example... Figure 1 As shown on the right, the analog sampling input of the battery cell 200 under test is directly connected to the analog input of the analog-to-digital converter chip 105 (ADC). No hardware low-pass filter circuit is placed between them. The underlying physical mechanism of this design is that while hardware filters remove noise, they inevitably smooth out the most critical physical information of the terminal voltage response at the moment of excitation pulse polarity reversal: the steep ohmic voltage step edge (such as...). Figure 2 The ohmic voltage step (205) shown in waveform B results in an underestimation of the extracted step amplitude, ultimately distorting the internal resistance calculation. This "naked connection" direct sampling method preserves the battery's inherent physical step response.

[0025] Of course, without hardware filtering, the acquired data stream will contain a large amount of high-frequency background noise. To address this challenge, the system fully utilizes DMA (Direct Memory Access) technology. After the analog-to-digital converter chip 105 completes a single high-frequency sampling under the control of the microprocessor, the hardware-cascaded direct memory access controller 106 immediately intervenes, directly writing the converted digital voltage and its precise hardware timestamp into a pre-defined buffer in the microprocessor's memory / RAM via the system bus for temporary storage without CPU core intervention. This method not only ensures extremely high sampling rates and data integrity when the excitation pulse is as narrow as microseconds, but also greatly frees up the CPU core's computing resources, allowing it to focus on subsequent complex denoising and processing algorithms.

[0026] like Figure 1 As shown, the system also includes a remote communication module 107 (such as a 4G / 5G / NB-IoT or Ethernet module) connected to the microprocessor 101, and a controllable discharge capacity load circuit 108. The control terminal of the controllable discharge capacity load circuit 108 is connected to the microprocessor 101, and its power terminal is connected across the battery pack composed of the battery cells 200 under test. The remote control terminal interacts bidirectionally with the microprocessor 101 through the remote communication module 107, issuing remote capacity control commands and receiving internal resistance calculation data and capacity evaluation reports in real time.

[0027] After the hardware system completes stimulus injection and data temporary storage, the microprocessor 101 calls the algorithm module from memory / RAM, officially entering the software computation stage. The entire software computation and quality control process is as follows: Figure 3 As shown, each step proceeds sequentially according to strict logic: Step S301: Start the online measurement program for the internal resistance of a single battery cell.

[0028] When a measurement command is received from the external bus or the preset automatic monitoring cycle of the on-chip timer is reached, the microprocessor 101 triggers the start of the measurement program. During this stage, the microprocessor 101 first clears the designated buffer and initializes the pointer in the on-chip memory / RAM, establishing a data receiving queue. Then, it wakes up the analog-to-digital converter chip 105 and the direct memory access controller 106, configuring them with a high-frequency sampling rate and data bus transmission width to ensure the hardware channels are in a low-latency ready state, thus building a complete software operating environment for subsequent environmental noise sensing and data acquisition.

[0029] Step S302: Collect the background noise sequence of the DC power grid.

[0030] In a completely silent state without any applied drive pulses, the microprocessor 101 keeps the pre-stage drive circuit 102 and the H-bridge polarity switching drive circuit 103 in the off state, and does not output charge to the power circuit. At this time, the microprocessor 101 activates the analog-to-digital converter chip 105 and the direct memory access controller 106 to directly perform high-frequency continuous sampling of the original background noise of the DC grid acting on both ends of the battery cell 200 under test. The sampled analog voltage digital quantity, along with the on-chip hardware timestamp, is directly written to the designated silent buffer of the memory through the DMA channel without occupying CPU resources, forming the original noise time-domain sequence containing grid switching noise, ripple, and sudden interference.

[0031] Step S303: Calculate the fractional heavy-tailed probability moment characteristics and initial fluctuation amplitude of the background noise sequence.

[0032] The microprocessor 101 reads the background noise sequence from memory and calls the on-chip noise statistical analysis algorithm module. Considering the non-Gaussian, heavy-tailed, and sudden-impact physical properties of noise generated by frequent switching of high-power electronic devices (such as inverters and converters) in the DC power grid, the algorithm uses fractional lower-order moments to estimate the probability density of the noise sequence and calculates the fractional probability moment characteristics representing the degree of noise heavy-tailing. Simultaneously, it statistically analyzes the peak-to-peak value and variance of the noise sequence within a quiet window to obtain the initial fluctuation amplitude. Through these two indicators, the system mathematically completes a precise quantitative assessment of the current power grid interference environment.

[0033] Step S304: Adaptive hedging solution for the excitation current of the first target and the pulse width of the second target.

[0034] Based on the probability moment characteristics and initial fluctuation amplitude calculated in S303, the microprocessor 101 executes the on-chip adaptive offset solution algorithm. In order to ensure that the subsequently injected excitation signal can penetrate the strong heavy-tailed background noise (to ensure the signal-to-noise ratio) without causing excessive temperature rise or polarization shock to the battery (to ensure non-destructive measurement), the algorithm establishes a dual constraint equation based on the lower limit of the signal-to-noise ratio and the thermal limit of the battery, and adaptively inversely solves the optimal parameter combination required for this measurement: that is, the amplitude is "first target excitation current" (I_target) and the pulse width is "second target pulse width" (T_pulse).

[0035] Step S305: Output bidirectional pulses and collect the high-frequency terminal voltage response sequence and store it in the memory.

[0036] The microprocessor 101 configures the solved I_target and T_pulse to the on-chip timer peripheral, controlling it to output a PWM signal with the corresponding timing. This signal drives the H-bridge polarity switching drive circuit 103 and the constant current regulation circuit 104 via the pre-stage drive circuit 102, injecting current into the battery cell 200 under test. Figure 2 The bidirectional constant current excitation pulse shown in waveform A (sequentially includes a forward constant current charging pulse 201, a dead time 203, and a reverse constant current discharging pulse 202). Throughout the excitation injection process, the analog-to-digital converter chip 105 continuously acquires the battery terminal voltage at a high-frequency sampling rate in the megahertz (MHz) range, and the direct memory access controller 106 stores the converted terminal voltage response sequence into the response buffer of the memory in real time.

[0037] Step S306: Introduce the first-order polarization ordinary differential equation constraint of the battery cell under test, and construct the block kernel self-covariance matrix to reconstruct the continuous voltage curve.

[0038] After the excitation is applied, the CPU core of microprocessor 101 reads the discrete, raw terminal voltage response sequence containing high-frequency noise from memory. Due to the hardware elimination of the low-pass filter, high-frequency fluctuations exist in the data points. To reconstruct the continuous physical curve without smoothing steep step edges, the algorithm actively introduces the inherent electrochemical physical constraints of the battery cell 200 under test. First-order polarization ordinary differential equation: (U(t) = I · R_ohm + U_p(t), where U_p(t) is the polarization voltage). The algorithm uses this ordinary differential equation as the prior kernel function, constructs a block kernel autocovariance matrix using Cholesky decomposition, and performs global optimization and reconstruction on discrete data points to obtain a terminal voltage response curve that combines physical realism and continuity.

[0039] Step S307: Using the moment of polarity reversal as the center, perform bidirectional recursive denoising along the forward and reverse time axes.

[0040] Based on the reconstructed continuous voltage curve, the microprocessor 101... Figure 2The polarity reversal time 204 of the excitation pulse shown in waveform B (i.e., the intersection point t_rev after the dead time 203 and the entry of the reverse pulse) is used as the time center anchor point, initiating the bidirectional recursive smoothing and denoising algorithm. The algorithm performs forward Kalman state estimation recursion along the positive time axis, calculating the forward state probability distribution; simultaneously, it performs backward likelihood probability recursion along the reverse time axis, calculating the backward likelihood probability distribution. Since the statistical correlation of non-Gaussian heavy-tail noise in the two opposite directions of the time axis is extremely low, the algorithm performs a normalized product operation on the forward probability distribution and the backward likelihood probability distribution, mathematically canceling each other out and eliminating the non-Gaussian heavy-tail noise caused by the operation of the high-power switching transistor, thus faithfully reproducing the pure voltage response curve.

[0041] Step S308: Extract the pure ohmic voltage step value and calculate the ohmic internal resistance value.

[0042] On the purified voltage response curve after noise reduction, the microprocessor 101 precisely pinpoints the polarity reversal point at 204. Because the current undergoes an instantaneous switch between positive and negative directions at this moment, the electrochemical polarization and concentration polarization within the battery have not yet changed; the instantaneous voltage jump is entirely caused by the ohmic internal resistance. The microprocessor 101 directly extracts the amplitude of this instantaneous, undistorted voltage jump. Figure 2 The ohmic voltage step shown in waveform B is 205 ( Subsequently, based on the "first target excitation current" (I_target) determined in S304, and according to Ohm's law formula:

[0043] The true internal resistance of the 200 ohms of the battery cell under test can be accurately calculated.

[0044] Step S309: Calculate the average normalized estimation error squared value of the solution result.

[0045] After the calculation is completed, the microprocessor 101 performs posterior residual analysis using the reconstructed clean curve and the original acquired sequence. The algorithm calculates the normalized mean squared residual error (MSE) of the residuals within the entire measurement window. This value reflects the good fit between the prior electrochemical polarization physical model and the actual acquired response data, serving as a quantitative indicator for evaluating the reliability of the measurement results.

[0046] Step S310: Determine whether the estimated squared error value falls within the preset tolerance range; if so, output and store the calculated ohmic internal resistance value, and execute the intelligent operation and maintenance logic.

[0047] The microprocessor 101 compares the calculated estimated squared error value with a preset tolerance threshold range in the on-chip memory. If the estimated squared error value falls within the tolerance range, it indicates that the measurement was not damaged by sudden strong interference and the data is true and valid. The microprocessor 101 outputs the calculated ohmic internal resistance value to the memory. Subsequently, the system executes intelligent operation and maintenance logic: it calculates the increase of the internal resistance value with the pre-stored reference internal resistance value in the memory (such as the initial internal resistance of the battery at the factory or the historical health baseline); if the increase exceeds the preset health threshold (such as an increase of more than 20%), the system determines that the battery has the risk of aging or loose connection, immediately generates an alarm signal, and uses the microprocessor's on-chip private key to attach a digital signature to the internal resistance data and alarm information, encrypts and writes it into non-volatile memory, completing the secure storage and traceability closed loop of the data.

[0048] Step S311: If the estimated squared error value does not fall within the preset tolerance range, the measurement is deemed invalid.

[0049] If the estimated squared error exceeds the preset tolerance range (indicating that the DC grid experienced an extremely strong burst pulse interference exceeding its counterbalancing capacity during the measurement period, leading to fitting distortion), the microprocessor 101 directly triggers the anomaly protection mechanism, determining that the measurement is invalid. The system will discard the internal resistance value generated by this calculation, without updating the historical database, and simultaneously mark this sampling as invalid, waiting for the next cycle to restart the measurement, thereby completely eliminating the misleading influence of abnormal contamination data on the battery management system (BMS) operation and maintenance decisions.

[0050] Step S312: Respond to the remote capacity approval command and coordinate the execution of dynamic internal resistance tracking and remote secure capacity approval.

[0051] When the microprocessor 101 receives a remote capacity assessment command from the remote control terminal via the remote communication module 107, the microprocessor 101 closes the controllable discharge capacity assessment load circuit 108 and controls the battery pack to discharge at a preset constant current rate. During the discharge process, the microprocessor 101 cyclically triggers the software calculation process of steps S301 to S310 at preset time intervals, calculates the ohmic internal resistance value of each battery cell 200 under different depths of discharge (DOD) in real time, and plots a dynamic evolution curve. When the ohmic internal resistance of any battery cell 200 under test increases sharply to the preset capacity assessment safety threshold, or the battery pack terminal voltage reaches the discharge cutoff voltage, the microprocessor 101 immediately controls the controllable discharge capacity assessment load circuit 108 to disconnect to terminate the discharge, and generates a capacity assessment report containing the actual capacity of the battery pack and the location of the degraded cells. This report is then encrypted and uploaded to the remote control terminal via the remote communication module 107, completing the remote online capacity assessment closed loop.

[0052] In summary, the battery online monitoring and remote capacity assessment system provided by this invention constructs a rigorous technical closed loop through the deep collaborative integration of the aforementioned hardware topology and software algorithms. On the one hand, it utilizes a soft filtering mechanism of "hardware direct sampling + kernel reconstruction + bidirectional recursive denoising" to successfully cancel the non-Gaussian heavy-tail noise generated by the switching of high-power devices in the power grid, overcoming the challenge of high-precision measurement under strong interference. On the other hand, by injecting charge algebra and strictly zero bidirectional pulse signals, the system completely eliminates the cumulative impact of the measurement process on the battery's state of charge (SOC) and overheating damage, truly achieving non-destructive testing. Furthermore, the system combines a controllable discharge capacity assessment load with a remote communication module to achieve real-time tracking and safety protection of the dynamic evolution curve of the cell's internal resistance during capacity assessment discharge, completely eliminating the high cost and safety hazards of manual offline capacity assessment, and providing highly reliable technical support for accurate diagnosis of battery health and remote unmanned operation and maintenance.

[0053] The above are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A battery online monitoring and remote capacity assessment system, characterized in that, include: Microprocessor, pre-stage driver circuit, H-bridge polarity switching driver circuit, constant current regulation circuit, analog-to-digital converter chip, direct memory access controller, remote communication module, and controllable discharge capacitive load circuit. The microprocessor includes an on-chip timer peripheral and a memory, and the control output terminal of the on-chip timer peripheral is connected to the input terminal of the front-end drive circuit. The output terminal of the pre-stage drive circuit is connected to the control input terminal of the H-bridge polarity switching drive circuit. The H-bridge polarity switching drive circuit and the constant current regulation circuit are connected in series to form a bidirectional pulse excitation circuit. The power output terminal of the bidirectional pulse excitation circuit is used to connect to the battery cell under test. The analog sampling input terminal of the analog-to-digital converter chip is directly connected to the battery cell under test, the data output terminal of the analog-to-digital converter chip is connected to the direct memory access controller, and the bus output terminal of the direct memory access controller is connected to the memory. The remote communication module is connected to the microprocessor; the control terminal of the controllable discharge capacity load circuit is connected to the microprocessor, and the power terminal of the controllable discharge capacity load circuit is connected across the two ends of the battery pack composed of the battery cells under test. The microprocessor is configured to: The on-chip timer peripheral outputs a PWM control signal to the front-end drive circuit to drive the H-bridge polarity switching drive circuit and the constant current regulation circuit to inject a bidirectional constant current excitation pulse with an amplitude of the first target excitation current and a pulse width of the second target pulse width into the battery cell under test. During the application of the bidirectional constant current excitation pulse, the terminal voltage response sequence of the battery cell under test is acquired at high frequency by the analog-to-digital converter chip and the direct memory access controller and directly stored in the memory; The terminal voltage response sequence is read from the memory, and the ohmic voltage step value is extracted from the terminal voltage response sequence according to the polarity reversal time. The ohmic internal resistance value of the battery cell under test is calculated based on the ohmic voltage step value and the first target excitation current. In response to the remote capacity control command received through the remote communication module, the controllable discharge capacity control load circuit is controlled to connect to the battery pack for discharge, and the capacity control status of the battery pack is dynamically evaluated based on the calculated internal resistance of each battery cell under test during the discharge process.

2. The battery online monitoring and remote capacity assessment system according to claim 1, characterized in that, The bidirectional constant current excitation pulse includes a forward constant current charging pulse and a reverse constant current discharging pulse applied sequentially. There is a dead time between the forward constant current charging pulse and the reverse constant current discharging pulse, and the algebraic sum of the charges of the forward constant current charging pulse and the reverse constant current discharging pulse in a single measurement cycle is zero.

3. The battery online monitoring and remote capacity assessment system according to claim 1, characterized in that, The microprocessor is also configured to: Before controlling the output of the bidirectional constant current excitation pulse, the background noise sequence of the DC power grid is acquired; Calculate the fractional heavy-tailed probability moment characteristics and initial fluctuation amplitude of the background noise sequence; Based on the probability moment characteristics and the initial fluctuation amplitude, the first target excitation current and the second target pulse width are adaptively hedging and solved.

4. The battery online monitoring and remote capacity assessment system according to claim 1, characterized in that, There is no hardware low-pass filter circuit connected between the analog sampling input terminal of the analog-to-digital converter chip and the battery cell under test, so as to preserve the steep step edge of the terminal voltage response sequence at the moment of polarity reversal.

5. The battery online monitoring and remote capacity assessment system according to claim 1, characterized in that, The microprocessor is also configured to: after reading the terminal voltage response sequence, introduce first-order polarization ordinary differential equation constraints of the battery cell under test, construct a block kernel autocovariance matrix, and reconstruct a continuous voltage curve for the discrete terminal voltage response sequence.

6. The battery online monitoring and remote capacity assessment system according to claim 5, characterized in that, The microprocessor is also configured to: Centered on the moment when the polarity of the bidirectional constant current excitation pulse reverses, forward state estimation is recursively performed along the positive time axis, and backward likelihood probability is recursively performed along the reverse time axis. Non-Gaussian heavy-tailed noise in the terminal voltage response sequence is eliminated by normalizing the product of the forward state estimation probability distribution and the backward likelihood probability distribution.

7. The battery online monitoring and remote capacity assessment system according to claim 1, characterized in that, After the microprocessor calculates the ohmic internal resistance of the battery cell under test based on the ohmic voltage step value and the first target excitation current, it is further configured to: calculate the average normalized estimation error squared value of the calculation result; determine whether the estimation error squared value falls within a preset tolerance range; if so, output and store the calculated ohmic internal resistance value; if not, determine that this measurement is invalid.

8. The battery online monitoring and remote capacity assessment system according to claim 7, characterized in that, After determining that the calculated ohmic resistance value is valid, the microprocessor compares the ohmic resistance value with the pre-stored reference internal resistance value of the battery cell under test; if the increase exceeds a preset threshold, an alarm signal is generated and a digital signature is attached and stored in the memory.

9. The battery online monitoring and remote capacity assessment system according to claim 1, characterized in that, After the analog-to-digital converter chip completes a single sampling, the direct memory access controller directly writes the converted digital voltage and hardware timestamp into a designated buffer of the memory without CPU core intervention.

10. The battery online monitoring and remote capacity assessment system according to any one of claims 1 to 9, characterized in that, The pre-stage driving circuit includes an isolation optocoupler and a totem pole driving circuit, and the H-bridge polarity switching driving circuit includes four symmetrically arranged wide bandgap semiconductor power switches.

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