Signal processing device, microcontroller and electronic device

Abstract

The application discloses a signal processing device, a microcontroller and electronic equipment, which is used in cooperation with an analog-to-digital conversion unit for sampling an input analog signal and outputting original sampling data, and comprises a hardware calculation unit connected with the analog-to-digital conversion unit, used for receiving the original sampling data, pre-processing the original sampling data to obtain pre-processed data of a floating point type, and sending the pre-processed data to a target storage address so that a processor reads the pre-processed data from the target storage address. Based on the above technical scheme, the resource occupancy rate of a CPU can be reduced and the real-time performance of data processing can be improved during the pre-processing of the original sampling data.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a signal processing device, microcontroller, and electronic device. Background Technology

[0002] With the rapid development of industrial control and IoT technologies, microcontroller units (MCUs) are increasingly widely used in data acquisition, sensor signal processing, and other scenarios. Analog-to-digital converters (ADCs), as core peripherals within MCUs, play a crucial role in converting analog signals into digital signals.

[0003] In related technologies, the ADC sampling control logic of MCUs generally adopts a fully software post-processing architecture. Under this architecture, the MCU core first triggers ADC sampling. After sampling is complete, the Central Processing Unit (CPU) needs to read the raw sampled data shaped internally by the ADC via software, and then perform preprocessing operations such as calibration, filtering, and mean calculation. Finally, based on the processed data, the application layer control logic is executed. This preprocessing operation consumes CPU resources, and as the number of sampling channels and the sampling frequency increase, the CPU needs to consume a large amount of computing resources to complete the preprocessing of the raw sampled data. Therefore, existing technologies suffer from high CPU resource occupancy during signal preprocessing. Summary of the Invention

[0004] This application provides a signal processing device, microcontroller, and electronic device that can reduce CPU resource usage and improve the real-time performance of data processing during the preprocessing of raw sampled data.

[0005] In a first aspect, embodiments of this application provide a signal processing apparatus for working in conjunction with an analog-to-digital conversion unit, wherein the analog-to-digital conversion unit samples an input analog signal and outputs raw sampled data, and the signal processing apparatus includes: A hardware computing unit, connected to the analog-to-digital conversion unit, is used to receive the raw sampled data, preprocess the raw sampled data to obtain preprocessed floating-point data, and send the preprocessed data to a target storage address so that the processor can read the preprocessed data from the target storage address.

[0006] In some embodiments, the hardware computing unit includes the following components connected in sequence: A sampling latch circuit is used to latch the original sampling data; A floating-point conversion circuit is used to convert the original sampled data into floating-point data; The multiply-accumulate calibration circuit is used to perform multiply-accumulate calibration on the converted floating-point data to obtain calibration data; A sliding window buffer circuit is used to buffer the calibration data corresponding to multiple consecutive samples; A mean calculation circuit is used to calculate the mean of the calibration data in the sliding window buffer circuit to obtain the preprocessed data; The result latch and trigger circuit is used to latch the preprocessed data and trigger a signal after the preprocessed data is latched to send the preprocessed data to the target storage address.

[0007] In some embodiments, the hardware computing unit further includes: An extreme value filtering circuit is connected in series between the sliding window buffer circuit and the mean calculation circuit. It is used to remove the maximum and minimum values ​​from the calibration data in the sliding window buffer circuit, and then input the remaining data after removing the maximum and minimum values ​​to the mean calculation circuit.

[0008] In some embodiments, the hardware computing unit further includes: A calibration parameter register, which is connected to the multiply-accumulate calibration circuit, is used to store a preset first calibration coefficient; The multiply-accumulate calibration circuit is used to read the first calibration coefficient from the calibration parameter register and use the first calibration coefficient to perform multiply-accumulate calibration on the converted floating-point data to obtain the calibration data.

[0009] In some embodiments, the hardware computing unit further includes: The parameter shielding circuit is connected to the calibration parameter register; The parameter shielding circuit is used to detect whether the second calibration coefficient to be written to the calibration parameter register exceeds a preset threshold range. If the second calibration coefficient exceeds the preset threshold range, writing the second calibration coefficient is prohibited, and the calibration coefficient in the calibration parameter register is kept unchanged at the first calibration coefficient.

[0010] In some embodiments, the device further includes: A clock control circuit is used to provide a clock signal to the hardware computing unit.

[0011] In some embodiments, the device further includes: A crossbar switch matrix, the input of which is connected to the hardware computing unit, and the output of which is connected to a DMA controller or processor, is used to send the preprocessed data to the target storage address.

[0012] In some embodiments, the cross switch matrix is ​​also connected to the analog-to-digital converter unit via a bypass switch. The signal processing device has a first operating mode and a second operating mode. When the signal processing device is in the first operating mode, the bypass switch is in the open state and the hardware computing unit is in the operating state. When the signal processing device is in the second operating mode, the bypass switch is in the closed state and the hardware computing unit is in the closed state. The raw sampling data output by the analog-to-digital converter unit is transmitted to the cross switch matrix via the bypass switch.

[0013] In some embodiments, when the signal processing device is in the second operating mode, the clock control circuit is controlled to shut down the clock signal supplied to the hardware computing unit.

[0014] In some embodiments, the result latching and triggering circuit is further configured to generate a direct memory access request signal after the preprocessed data is latched, and to transfer the preprocessed data to the target memory address through the direct memory access controller according to the direct memory access request signal; or, to generate an interrupt request signal after the preprocessed data is latched, and to transfer the preprocessed data to the target memory address according to the interrupt request signal.

[0015] In some embodiments, the analog-to-digital conversion unit includes multiple sampling channels; The hardware computing unit adopts a time-division multiplexing architecture to preprocess the raw sampling data corresponding to the multiple sampling channels sequentially in multiple time slices; The sliding window buffer circuit includes multiple buffer areas, each of which corresponds to one of the multiple sampling channels. Each buffer area is used to store the calibration data corresponding to multiple consecutive samplings of the corresponding sampling channel. The hardware computing unit is also configured with multiple mean length configuration registers and multiple calibration coefficient registers that correspond one-to-one with the multiple sampling channels. When switching the sampling channel, the hardware computing unit automatically loads the buffer area, the mean length configuration register, and the calibration coefficient register corresponding to the current sampling channel.

[0016] In some embodiments, the device further includes: An anomaly detection circuit is connected to the hardware computing unit; The anomaly detection circuit is used to control the hardware computing unit to pause the preprocessing operation when an anomaly event is detected, and to control the hardware computing unit to output the previous preprocessed data and report the anomaly status; after the anomaly event is resolved, it controls the hardware computing unit to refresh the current cached data and reset the operation state to resume the preprocessing operation.

[0017] Secondly, embodiments of this application also provide a microcontroller, including an analog-to-digital conversion unit and a signal processing device as provided in the first aspect.

[0018] Thirdly, embodiments of this application also provide an electronic device, including a processor and a microcontroller provided in the second aspect.

[0019] The signal processing device provided in this application embodiment, by setting up an independent hardware computing unit, automatically completes preprocessing operations such as floating-point conversion, calibration, filtering, and mean calculation after the analog-to-digital conversion unit outputs the raw sampled data, and sends the final preprocessed data to the target storage address. In this way, the processor does not need to participate in the complex calculations at the underlying level, but only needs to read the final result from the target storage address, thereby making the CPU resource occupancy rate zero in the entire preprocessing process, which can effectively reduce the CPU resource occupancy rate. Furthermore, by preprocessing the raw sampled data through the hardware computing unit, the real-time performance of data processing can be ensured. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0022] Figure 1 A schematic diagram illustrating the connection between the hardware computing unit and the analog-to-digital conversion unit provided in an exemplary embodiment of this disclosure; Figure 2 A schematic diagram of a hardware computing unit provided in an exemplary embodiment of this disclosure; Figure 3 Another schematic diagram of the hardware computing unit provided as an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of the connection between the calibration parameter register and the parameter shielding circuit provided in an exemplary embodiment of this disclosure; Figure 5 A schematic diagram of the structure of a hardware computing unit including an anomaly detection circuit, provided as an exemplary embodiment of this disclosure; Figure 6 A schematic diagram of a structure connecting multiple hardware computing units and an analog-to-digital conversion unit, provided as an exemplary embodiment of this disclosure; Figure 7 Another schematic diagram showing the connection between multiple hardware computing units and an analog-to-digital conversion unit provided in an exemplary embodiment of this disclosure; Figure 8 Data flow diagram of a hardware computing unit provided in an exemplary embodiment of this disclosure; Figure 9 This is a schematic diagram of the structure of a microcontroller provided as an exemplary embodiment of the present disclosure.

[0023] Explanation of reference numerals in the attached figures: 10. Analog-to-digital converter; 101. ADC; 20. Hardware computing unit; 201. Sampling latch circuit; 202. Floating-point conversion circuit; 203. Multiply-accumulate calibration circuit; 204. Sliding window buffer circuit; 205. Mean calculation circuit; 206. Result latching and triggering circuit; 207. Extreme value filtering circuit; 208. Calibration parameter register; 209. Parameter masking circuit; 210. Anomaly detection circuit; 211. Register group; 30. Multiple analog sources; 40. DMA controller; 50. Bypass; 51. Bypass switch. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0025] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0026] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0027] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0028] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0029] This application provides a signal processing device integrated into an MCU as a hardware module within the MCU. Figure 1 As shown, the signal processing device works in conjunction with the analog-to-digital converter 10. The analog-to-digital converter 10 is used to sample the input analog signal and output the raw sampled data. The signal processing device includes a hardware computing unit 20, which is connected to the analog-to-digital converter 10. The hardware computing unit 20 is used to receive the raw sampled data, preprocess the raw sampled data to obtain floating-point type preprocessed data, and send the preprocessed data to a target memory address (e.g., memory, register file, or specific memory space) so that the processor can read the preprocessed data from the target memory address and execute the application layer control logic.

[0030] In some embodiments, the analog-to-digital conversion unit 10 can be any of a successive approximation analog-to-digital converter (SAR ADC), a pipelined analog-to-digital converter, etc., and its resolution can be 8 bits, 10 bits, 12 bits, or higher, which can be selected according to the actual application scenario. The sampling frequency of the analog-to-digital conversion unit 10 is controlled by a sampling trigger signal inside the MCU, which can be generated by a timer, a PWM module, or an external interrupt event.

[0031] In some embodiments, the analog signal may be an analog voltage or analog current signal output from an external sensor (e.g., a temperature sensor, a pressure sensor, a current sensor, a voltage sensor, etc.). After sampling and quantizing the analog signal, the analog-to-digital conversion unit 10 outputs raw sampled data in integer format, such as a 12-bit unsigned integer value or a 16-bit signed integer value.

[0032] In some embodiments, the hardware computing unit 20 is a hardware pipeline preprocessing unit integrated into the MCU, located after the analog-to-digital converter unit 10. This hardware computing unit 20 is driven by a single ADC sampling trigger signal to drive the entire pipeline processing, and the entire preprocessing process requires no processor intervention. Thus, the hardware computing unit 20 can complete data preprocessing independently of the processor, thereby freeing up processor computing resources and resulting in zero CPU resource utilization throughout the preprocessing process. This effectively reduces CPU resource utilization, and by preprocessing the raw sampled data through the hardware computing unit, real-time data processing can be ensured.

[0033] Specifically, such as Figure 2 As shown, the hardware computing unit 20 includes a sampling latch circuit 201, a floating-point conversion circuit 202, a multiply-accumulate calibration circuit 203, a sliding window buffer circuit 204, a mean calculation circuit 205, and a result latch and trigger circuit 206 connected in sequence.

[0034] In some embodiments, the sampling latch circuit 201 is used to latch the original sampled data after the ADC sampling is completed. Specifically, the input terminal of the sampling latch circuit 201 is connected to the output terminal of the analog-to-digital converter unit 10. After the analog-to-digital converter unit 10 completes one analog-to-digital conversion, the conversion completion signal triggers the sampling latch circuit 201 to latch the original sampled data output by the analog-to-digital converter unit 10, so that the original sampled data remains stable in the next clock cycle for subsequent circuit processing. The sampling latch circuit 201 can be composed of a D flip-flop array or a register group.

[0035] In some embodiments, the input of the floating-point conversion circuit 202 is connected to the output of the sampling latch circuit 201, and is used to convert the original sampled data into floating-point data. In some embodiments, the floating-point conversion circuit 202 uses the IEEE 754 single-precision floating-point format for conversion, and completes the conversion within a single clock cycle after the original sampled data is latched. Specifically, the floating-point conversion circuit 202 converts the original sampled data in integer format into 32-bit single-precision floating-point data conforming to the IEEE 754 standard. The conversion method includes re-encoding the sign bit, exponent bit, and mantissa bit of the integer according to the IEEE 754 standard. Furthermore, during the conversion process, the floating-point conversion circuit 202 supports multiple rounding modes, including truncation, rounding to the nearest even number, etc., and the specific rounding mode can be selected by the user through a configuration register. For example, for a 12-bit integer sampled value 2048 (corresponding to binary 100000000000), the floating-point conversion circuit 202 converts it into the corresponding IEEE 754 single-precision floating-point representation. In some embodiments, the floating-point conversion circuit 202 can also adopt a half-precision floating-point format or a custom fixed-point floating-point format to adapt to the accuracy and power consumption requirements of different application scenarios. In this way, the conversion from integer to floating-point is completed in a single clock cycle through the hardware floating-point conversion circuit, avoiding the instruction cycle overhead caused by software floating-point conversion, which is particularly suitable for MCUs without a hardware floating-point unit (FPU).

[0036] In some embodiments, the input of the multiply-accumulate calibration circuit 203 is connected to the output of the floating-point conversion circuit 202, and is used to perform multiply-accumulate calibration on the converted floating-point data to obtain calibration data. Specifically, the multiply-accumulate calibration circuit 203 performs multiply-accumulate operations according to the industry-standard linear calibration formula: calibration data = floating-point data × Gain + Offset, where Gain is the multiplier coefficient and Offset is the offset. The multiply-accumulate calibration circuit 203 internally includes a multiplier and an adder. The multiplier is used to perform multiplication of the floating-point data and Gain, and the adder is used to add the multiplication result and Offset. In some embodiments, the operation precision of the multiply-accumulate calibration circuit 203 can be single-precision floating-point, in which case the operation result is also in single-precision floating-point format.

[0037] In some embodiments, the hardware computing unit 20 further includes a calibration parameter register connected to the multiply-accumulate calibration circuit 203, used to store a preset first calibration coefficient (i.e., the aforementioned Gain and Offset). The multiply-accumulate calibration circuit 203 is used to read the first calibration coefficient from the calibration parameter register and perform multiply-accumulate calibration on the converted floating-point data using the first calibration coefficient to obtain the calibration data. The calibration parameter register can be a register group with a width of 32 bits or 64 bits, where a portion of the storage bits is used to store the multiplier coefficient Gain, and another portion is used to store the offset Offset. In some embodiments, the calibration parameter register can be read and written via the MCU's register configuration interface (such as the APB bus or AHB bus) to adapt to different types of sensors or different physical quantity conversion requirements. For example, for a temperature sensor, Gain = 0.01, Offset = -0.5 can be configured; for a current sensor, Gain = 0.02, Offset = 0.0, etc., can be configured.

[0038] Specifically, during the multiply-accumulate calibration process, the multiply-accumulate calibration circuit 203 receives floating-point data from the floating-point conversion circuit 202, and simultaneously reads Gain and Offset from the calibration parameter register. After performing multiply-accumulate operations, it outputs the calibration data. The calibration data is a floating-point value with actual physical meaning (e.g., a floating-point number representing physical quantities such as temperature, pressure, current, and voltage). Thus, by using a hardware multiply-accumulate calibration circuit to perform linear calibration operations instead of software, CPU resources are further freed up while ensuring consistency between calibration accuracy and computation speed.

[0039] In some embodiments, the input of the sliding window buffer circuit 204 is connected to the output of the multiply-accumulate calibration circuit 203 to buffer calibration data corresponding to multiple consecutive samples. Specifically, the sliding window buffer circuit 204 includes multiple cascaded storage units, such as registers or static random-access memory (SRAM), each storage unit storing calibration data corresponding to one sample. When new calibration data arrives, the sliding window buffer circuit 204 stores the new data in the first storage unit, and then passes the data in each storage unit sequentially to the next, finally removing the oldest data from the window. In this way, the sliding window buffer circuit 204 always maintains the calibration data of the most recent N samples, where N is the depth of the sliding window and is an integer greater than 1.

[0040] Specifically, the cache depth of the sliding window cache circuit 204 is a fixed value, such as 8, 16, or 64. The cache depth can be determined during the chip design phase and configured according to different MCU models. In this way, the deterministic timing of data processing is ensured through a hardware sliding window with a fixed cache depth.

[0041] In some embodiments, the input of the mean calculation circuit 205 is connected to the output of the sliding window buffer circuit 204, and is used to calculate the mean of the calibration data in the sliding window buffer circuit 204 to obtain preprocessed data. Specifically, the mean calculation circuit 205 includes an adder array and a divider. The adder array is used to sum the calibration data of all storage units in the sliding window buffer circuit 204, and the divider is used to divide the sum by the window length (i.e., the number of currently valid sampling points) to obtain the arithmetic mean. In some embodiments, the mean calculation circuit 205 allows users to configure the sliding window length (i.e., the number of valid sampling points for mean calculation) through a register. The configuration range of the sliding window length is 1 to the maximum buffer depth, and dynamic modification of the window length configuration is prohibited during sampling. In this way, users can adjust the filtering intensity according to actual application needs, while avoiding data processing logic abnormalities caused by changes in the window length during operation.

[0042] In some embodiments, the mean calculation circuit 205 performs an arithmetic mean, which is the sum of all valid sample values ​​within the current window divided by the number of valid sample points. In other embodiments, the mean calculation circuit 205 may also perform other forms of mean calculation, such as weighted average or exponential moving average.

[0043] In some embodiments, the input of the result latching and triggering circuit 206 is connected to the output of the mean calculation circuit 205, for latching preprocessed data and triggering a signal after the preprocessed data is latched, sending the preprocessed data to the target storage address. Specifically, the result latching and triggering circuit 206 includes a result register and a trigger signal generator. The result register is used to obtain and latch the preprocessed data from the output of the mean calculation circuit 205 after the mean calculation circuit 205 completes the mean calculation, so that the output data remains stable for subsequent reading. The trigger signal generator is used to generate a trigger signal after the result register completes latching. This trigger signal can be configured as an interrupt request signal or a direct memory access request signal.

[0044] In some embodiments, when the trigger signal is an interrupt request signal, the preprocessed data is transferred to the target storage address according to the interrupt status signal.

[0045] Specifically, when the trigger signal is an interrupt request signal, the interrupt request signal is sent to the interrupt controller of the MCU. The interrupt controller extracts the interrupt request from the interrupt request signal and sends the interrupt request to the processor connected to the MCU. In response to the interrupt request, the processor reads the preprocessed data from the result latch and trigger circuit 206 and writes it to the target memory address.

[0046] Specifically, the interrupts triggered by the result latching and triggering circuit 206 can include various interrupt types, such as full window completion interrupt (indicating that the current sliding window is full and the mean calculation is complete), parameter exception interrupt (indicating that an illegal configuration was detected), and overflow exception interrupt (indicating that the calculated data overflowed). Different interrupt types correspond to different interrupt vector numbers, and users can differentiate the handling of different interrupt events through interrupt service routines.

[0047] In some embodiments, the result latching and triggering circuit 206 is further configured to generate a Direct Memory Access (DMA) request signal after the preprocessed data is latched. Based on this DMA request signal, the preprocessed data is transferred to the target memory address via the DMA controller. Specifically, the DMA request signal generated by the trigger signal generator is sent to the DMA controller. Upon receiving the DMA request, the DMA controller, acting as the bus master, gains bus control and automatically moves the preprocessed data latched in the result register to a pre-configured target memory address (e.g., a designated buffer in the system SRAM). After the DMA transfer is complete, the DMA controller releases bus control and can issue a DMA completion interrupt to the processor. At this point, the processor can directly read the preprocessed data from the target memory address. Thus, by automatically triggering DMA transfer through hardware, fully automated data acquisition, preprocessing, and storage are achieved. Data processing and transfer can be completed without the CPU executing any instructions, truly achieving zero CPU overhead.

[0048] In some embodiments, the trigger signal output by the result latching and triggering circuit 206 can also be connected to both the interrupt controller and the DMA controller, allowing the user to choose between interrupt mode and DMA mode based on the actual application scenario. For example, in low-speed sampling scenarios, interrupt mode can be selected; in high-speed sampling scenarios, DMA mode is preferred to reduce CPU overhead.

[0049] In some embodiments, such as Figure 3 As shown, the hardware computing unit 20 also includes an extreme value filtering circuit 207, which is connected in series between the sliding window buffer circuit 204 and the mean calculation circuit 205. It is used to remove the maximum and minimum values ​​from the calibration data in the sliding window buffer circuit 204 and then input the remaining data after removing the maximum and minimum values ​​to the mean calculation circuit 205.

[0050] Specifically, the extreme value filtering circuit 207 is connected to the output of each storage unit of the sliding window buffer circuit 204. It reads all calibration data within the current sliding window before mean calculation and determines the maximum and minimum values ​​through a comparator network. The extreme value filtering circuit 207 includes a maximum value comparator and a minimum value comparator. The maximum value comparator selects the maximum value from all data within the window, and the minimum value comparator selects the minimum value. After determining the maximum and minimum values, the extreme value filtering circuit 207 transmits the remaining calibration data (excluding the maximum and minimum values) within the window to the mean calculation circuit 205. At this point, the mean calculation circuit 205 only performs mean calculation on the remaining data, effectively suppressing the interference of sudden impulse noise on the mean result. In some embodiments, the function of the extreme value filtering circuit 207 can be enabled or disabled by the user through a register. If the extreme value filtering function is disabled, all calibration data in the sliding window buffer circuit 204 is directly input into the mean calculation circuit 205 for mean calculation. In this way, users can flexibly configure whether to enable extreme value filtering according to the ambient noise conditions, which can balance anti-interference ability and computational efficiency.

[0051] In some embodiments, such as Figure 4As shown, the hardware computing unit 20 also includes a calibration parameter register 208, which is connected to the multiply-accumulate calibration circuit 203 and is used to store a preset first calibration coefficient. The signal processing device also includes a parameter shielding circuit 209 connected to the calibration parameter register 208. The parameter shielding circuit 209 detects whether a second calibration coefficient to be written to the calibration parameter register 208 exceeds a preset threshold range. If the second calibration coefficient exceeds the preset threshold range, writing the second calibration coefficient is prohibited, and the calibration coefficient in the calibration parameter register 208 is kept unchanged at the first calibration coefficient. The preset threshold range includes the upper and lower limits of the multiplier coefficient Gain and the upper and lower limits of the offset. The preset threshold range is predetermined based on the full-scale range of the analog-to-digital conversion unit 10, the output range of the sensor, and the physical quantity conversion relationship, and is stored in the threshold register inside the parameter shielding circuit 209. For example, for a 12-bit ADC sensor with an input range of 0-3.3V, the Gain value range can be preset to 0.001 to 10.0, and the Offset value range can be preset to -10.0 to 10.0. When a user attempts to write a coefficient with Gain = 100.0 that exceeds the range, the parameter masking circuit 209 detects that the coefficient exceeds the preset threshold range, rejects the write operation, and keeps the previously valid coefficient in the calibration parameter register unchanged. In this way, the hardware parameter masking mechanism effectively prevents calibration parameter abnormalities caused by software errors, electromagnetic interference, or illegal operations, enhancing the system's security and reliability.

[0052] In some embodiments, the signal processing apparatus provided in this application further includes a clock control circuit for providing a clock signal to the hardware computing unit 20. The clock control circuit is connected to the clock input terminal of the hardware computing unit 20 and is used to provide or disconnect a working clock to the hardware computing unit 20 according to the current operating mode of the signal processing apparatus. The clock control circuit may employ clock gating technology, including an AND gate or a clock enable trigger. When the enable signal is valid, the clock signal is output to the hardware computing unit 20 through the clock control circuit; when the enable signal is invalid, the clock control circuit disconnects the clock output, and the clock input of the hardware computing unit 20 is fixed at a low or high level, thereby reducing dynamic power consumption.

[0053] In some embodiments, the signal processing apparatus further includes a crossbar switch matrix. The input of the crossbar switch matrix is ​​connected to the hardware computing unit 20, and the output of the crossbar switch matrix is ​​connected to a DMA controller or processor, for sending preprocessed data to a target memory address. The crossbar switch matrix is ​​a programmable signal routing matrix used for high-speed, low-latency data routing between different peripheral modules within the MCU. In this embodiment, the input of the crossbar switch matrix is ​​connected to the output of the result latch and trigger circuit 206, and the output of the crossbar switch matrix is ​​connected to the DMA controller or processor via a bus (e.g., an AHB bus or an APB bus), for sending preprocessed data to the target memory address via the DMA controller or processor.

[0054] In some embodiments, the cross switch matrix is ​​also connected to the analog-to-digital converter 10 via a bypass switch. The signal processing device operates in two modes: a first operating mode and a second operating mode. In the first operating mode, the bypass switch is open, and the hardware computing unit 20 is operational. At this time, the signal processing device performs fully automatic hardware preprocessing. Specifically, in the first operating mode, the raw sampled data output by the analog-to-digital converter 10 sequentially passes through a sampling latch circuit 201, a floating-point conversion circuit 202, a multiply-accumulate calibration circuit 203, a sliding window buffer circuit 204, an extreme value filtering circuit 207 (if enabled), a mean calculation circuit 205, and a result latch and trigger circuit 206, completing fully automatic preprocessing before outputting floating-point type preprocessed data.

[0055] Furthermore, when the signal processing device is in the second operating mode, the bypass switch is closed and the hardware computing unit 20 is off, transmitting the raw sampled data output by the analog-to-digital converter 10 to the cross switch matrix via the bypass switch. Specifically, in the second operating mode, the hardware computing unit 20 is not operating, the bypass switch is closed, and the bypass connection between the output of the analog-to-digital converter 10 and the input of the cross switch matrix is ​​established. At this time, the raw sampled data (integer format) output by the analog-to-digital converter 10 does not undergo any floating-point conversion, multiply-accumulate calibration, or filtering processing, but is directly output to the target memory address or DMA controller via the cross switch matrix (as detailed below). Figure 7 (As shown).

[0056] Specifically, the crossbar switch matrix can route data from the source (analog-to-digital converter 10) to the target (DMA controller or target storage address) according to the preset routing configuration, without the need for CPU involvement.

[0057] In some embodiments, the second operating mode is fully compatible with traditional software post-processing architectures, enabling the signal processing device to achieve the advantages of hardware pre-processing while still supporting traditional software processing workflows that require raw data, thus ensuring seamless integration with the existing software ecosystem.

[0058] In some embodiments, the switching between the first and second operating modes is controlled by a mode register, and the user can select the operating mode by writing a value to the mode register via software. During mode switching, the hardware automatically clears the data in the sliding window buffer circuit 204 and resets the accumulation result of the mean calculation circuit 205 to ensure data integrity and timing consistency during the switching process.

[0059] In some embodiments, when the signal processing device is in the second operating mode, the clock control circuit is controlled to shut down the clock signal supplied to the hardware computing unit 20. Specifically, when the signal processing device switches to the second operating mode, the enable signal of the clock control circuit is disabled, and the clock control circuit stops outputting clock signals to the hardware computing unit 20, so that all circuits of the hardware computing unit 20 enter a static state, and the dynamic power consumption is reduced to near zero. At this time, only the analog-to-digital conversion unit 10 and the cross switch matrix remain in operation. Thus, in scenarios where hardware preprocessing is not required or in low-power system modes, significant power savings are achieved by shutting down the clock of the hardware computing unit 20.

[0060] In some embodiments, the analog-to-digital conversion unit 10 includes multiple sampling channels (e.g., channels CH1, CH2, ..., CHn, where n is an integer greater than 1), each sampling channel being used to connect to an analog signal source (e.g., a sensor output). The hardware computing unit 20 employs a time-division multiplexing architecture to preprocess the raw sampled data corresponding to multiple sampling channels sequentially within multiple time slices. Specifically, under the time-division multiplexing architecture, the hardware computing unit 20 may contain only one set of pipelined operation logic (i.e., a set of sampling latch circuit 201, floating-point conversion circuit 202, multiply-accumulate calibration circuit 203, mean calculation circuit 205, and result latching and triggering circuit 206, etc.), but is configured with an independent resource pool corresponding one-to-one with each of the multiple sampling channels.

[0061] Specifically, the sliding window buffer circuit includes multiple buffer regions, each corresponding one-to-one with a sampling channel. Each buffer region stores calibration data corresponding to multiple consecutive samples from the corresponding sampling channel. The hardware computing unit is also configured with multiple mean length configuration registers and multiple calibration coefficient registers, each corresponding one-to-one with the sampling channels. When switching sampling channels, the hardware computing unit automatically loads the buffer region, mean length configuration register, and calibration coefficient register corresponding to the current sampling channel. At this time, the independent resource pool includes the buffer region, mean length configuration register, and calibration coefficient register corresponding to each sampling channel.

[0062] For example, taking n sampling channels, where n is an integer greater than 2, the sliding window buffer circuit 204 can be divided into buffer area 2041 corresponding to channel CH1, buffer area 2042 corresponding to channel CH2, ..., buffer area 204n corresponding to channel CHn (2041-204n are not shown in the figure). Each channel corresponds to an average length configuration register and a calibration coefficient register (Gain and Offset). The buffer areas 2041-204n of each channel are independent storage spaces, each storing the calibration data of multiple consecutive samples of the corresponding channel, without interference between them.

[0063] Specifically, during channel switching, the hardware computing unit 20 automatically loads the independent resource pool corresponding to the current channel. Specifically, when the sampling channel of the analog-to-digital converter 10 switches from channel 1 to channel 2, the configuration selection logic in the hardware computing unit 20 automatically connects the buffer 2041, the mean length configuration register, and the calibration coefficient register corresponding to channel 2 to the pipeline operation logic, while simultaneously disconnecting the corresponding resources for channel 1. Channel switching is controlled by the channel selection signal of the analog-to-digital converter 10, which is also connected to the channel selection input of the hardware computing unit 20, ensuring the synchronization of channel switching. The pipeline operation logic of the hardware computing unit 20 remains unchanged; only the data path and configuration parameters switch with the channel switching, and the data processing of each channel does not affect each other. Thus, through a time-division multiplexing architecture, a single set of pipeline logic supports multi-channel preprocessing, achieving independent preprocessing functions for multi-channel acquisition with relatively low hardware overhead, ensuring the acquisition accuracy and timing consistency of each channel.

[0064] In some embodiments, the signal processing device further includes an anomaly detection circuit connected to the hardware computing unit 20. The anomaly detection circuit, upon detecting an anomaly, controls the hardware computing unit 20 to pause preprocessing operations, output the previously preprocessed data, and report the anomaly status. After the anomaly event is resolved, the circuit controls the hardware computing unit 20 to refresh the current cached data and reset the computation state to resume preprocessing operations.

[0065] Specifically, such as Figure 5As shown, the input terminals of the anomaly detection circuit 210 are respectively connected to the overflow flag output terminal of the mean calculation circuit 205, the empty / full status output terminal of the sliding window buffer circuit 204, and the operation anomaly output terminal of the multiply-accumulate calibration circuit 203 in the hardware computing unit 20. The anomaly detection circuit 210 internally includes an anomaly status register and an anomaly handling logic. When the anomaly detection circuit 210 detects an anomaly event, such as data overflow in the mean calculation circuit 205, the window length configuration of the sliding window buffer circuit 204 exceeding the buffer depth, or a floating-point operation anomaly in the multiply-accumulate calibration circuit 203, the anomaly handling logic of the anomaly detection circuit 210 immediately generates a pause control signal and sends it to the clock enable terminals of each circuit in the hardware computing unit 20, causing the hardware computing unit 20 to pause pipeline processing and maintain its current state. Simultaneously, the anomaly detection circuit 210 controls the result latching and triggering circuit 206 to output the previously latched valid preprocessed data (i.e., the result of the last successful calculation before the anomaly occurred), sets the corresponding flag bit in the anomaly status register, and sends an anomaly interrupt request to the interrupt controller for the upper-level system to handle the anomaly. After the anomaly event is resolved (e.g., the user clears the anomaly flag through the configuration register or reconfigures valid parameters), the anomaly detection circuit 210 generates a recovery control signal, controls the hardware computing unit 20 to refresh the current channel data in the sliding window buffer circuit 204 and the accumulation result of the mean calculation circuit 205, resets the intermediate state of the multiply-accumulate calibration circuit 203, and then releases the pause control signal, allowing the hardware computing unit 20 to resume normal pipeline operation. In this way, the hardware anomaly detection circuit 210 can achieve rapid anomaly detection and automatic recovery, forming a complete closed-loop fault tolerance mechanism, which can effectively improve the long-term stability and reliability of the system.

[0066] In some embodiments, the sampling clock of the analog-to-digital converter 10 and the operating clock of the hardware computing unit 20 may be the same or different, depending on the specific circumstances. In some embodiments, the operating frequency of the hardware computing unit 20 is higher than or equal to the sampling frequency of the analog-to-digital converter 10 to ensure that the pipeline can complete all preprocessing operations within each sampling cycle. For example, the operating clock frequency of the hardware computing unit 20 may be 100MHz, while the ADC sampling frequency may be 1MHz. In this case, within one sampling cycle (1μs), the hardware computing unit 20 has 100 clock cycles to complete pipeline processing, which can meet the timing requirements of single-cycle floating-point conversion, multiply-accumulate calibration, and mean calculation.

[0067] In some embodiments, the floating-point conversion circuit 202, the multiply-accumulate calibration circuit 203, and the mean calculation circuit 205 all adopt a pipelined architecture design, that is, each arithmetic unit can correspond to one or more registers to achieve single-cycle throughput at high clock frequencies. For example, the floating-point conversion circuit 202 can internally divide the integer-to-floating-point conversion process into multiple pipeline stages (such as sign bit extraction stage, exponent calculation stage, mantissa normalization stage, etc.). Although a single conversion requires a delay of multiple clock cycles, each clock cycle can accept new input data and output the previous processing result, realizing pipelined throughput under continuous sampling.

[0068] In some embodiments, the hardware computing unit 20 can also function as a peripheral module of the MCU, interacting with the CPU and memory via a system bus (such as the AHB / APB bus), connecting to the interrupt controller via an interrupt request line, and connecting to the DMA controller via a DMA request line. In some embodiments, the target memory address can be a specified buffer address in the SRAM memory within the MCU, or it can be a peripheral register address within the MCU, preset by the user via the DMA configuration register.

[0069] In some embodiments, the configuration registers of the hardware computing unit 20 (including the mean length configuration register, calibration parameter register, mode register, interrupt enable register, etc.) are mapped to the address space of the MCU, and the user can read and write the above registers through the CPU executing software instructions. At the same time, the status registers of the hardware computing unit 20 (including the full window flag, the exception flag, the operation completion flag, etc.) can also be read and queried by the CPU.

[0070] In some embodiments, taking a temperature acquisition scenario as an example, the analog-to-digital conversion unit 10 is configured with 12-bit resolution and a sampling frequency of 1kHz. The sliding window buffer circuit 204 of the hardware computing unit 20 is configured with a window length of 8 points, the extreme value filtering function is enabled, and the calibration parameters of the multiply-accumulate calibration circuit 203 are configured as Gain = 0.01 and Offset = -0.5, wherein, after the voltage signal output by the temperature sensor (e.g., thermocouple or thermistor) is sampled by the analog-to-digital converter 10, the sampling latch circuit 201 latches 12 bits of raw sampled data; the floating-point conversion circuit 202 converts the 12 bits of raw sampled data into IEEE754 single-precision floating-point values ​​within a single clock cycle; the multiply-accumulate calibration circuit 203 performs calibration operations to obtain the physical temperature value (e.g., 25.5℃); the sliding window buffer circuit 204 buffers the temperature values ​​sampled 8 times consecutively; the extreme value filtering circuit 207 removes the maximum and minimum values ​​from the 8 temperature values; the mean calculation circuit 205 calculates the arithmetic mean of the remaining 6 temperature values ​​to obtain preprocessed data; the result latch and trigger circuit 206 latches the average temperature value and triggers a DMA request; after the DMA controller responds to the DMA request, it moves the average temperature value to the target memory address. In this scenario, the processor does not participate in computation or data transfer throughout the entire process, reducing the CPU load by more than 90%, and controlling the total sampling and processing latency within a few dozen clock cycles, thus meeting the stringent real-time requirements of industrial closed-loop control.

[0071] In some embodiments, the signal processing device provided in this application can also be extended to other linear sensor acquisition scenarios such as pressure sensors, current sensors, voltage sensors, and photoelectric sensors. Different Gain and Offset parameters can be configured in the calibration parameter register of the multiply-accumulate calibration circuit 203, and the sliding window length can be adjusted to adapt to different sensor characteristics and filtering requirements.

[0072] In some embodiments, taking the hardware computing unit as a computing IP as an example, the signal processing device may include a crossbar switch matrix XBAR2, multiple computing IPs, and a crossbar switch matrix XBAR3 connected in sequence, such as... Figure 6As shown, multiple analog sources 30 (such as analog voltage or analog current signals output by temperature sensors, pressure sensors, current sensors, etc.) are connected to the input terminals of ADC101 through a crossbar switch matrix XBAR1 on the input side. XBAR1, as a programmable signal routing matrix, is used to route any analog signal from the multiple analog sources 30 to ADC101 for sampling, enabling flexible switching of multiple analog signal inputs. Furthermore, after sampling and quantizing the selected analog signal, ADC101 outputs the raw sampled data (integer format). The raw sampled data output by ADC101 is input to the cross switch matrix XBAR2. The cross switch matrix XBAR2 then selects one computing IP from multiple computing IPs to process the raw sampled data. The corresponding computing IP preprocesses the raw sampled data to obtain floating-point type preprocessed data. Then, the floating-point type preprocessed data is transmitted to the DMA controller 40 through the cross switch matrix XBAR3 on the output side. The DMA controller 40 automatically moves the preprocessed data to the target memory address (e.g., a designated buffer in the system SRAM) according to the preset configuration information. In the entire data flow path, from analog-to-digital conversion to hardware preprocessing and then to DMA transfer, all are automatically completed by hardware logic without the need for processor participation, realizing data acquisition and preprocessing with zero CPU overhead.

[0073] In some embodiments, Figure 6 The multiple analog sources 30 can be multiple independent sensor signal sources, such as multiple PV input current sensors in a photovoltaic inverter, three-phase current sensors in a motor driver, or multiple temperature sensors in industrial control. The number of multiple analog sources 30 can be expanded according to the actual application scenario.

[0074] In some embodiments, Figure 6 XBAR2 and XBAR3 can be integrated into different port groups of the same cross switch matrix, or they can be implemented as two independent cross switch matrices, depending on the internal layout of the chip and routing requirements.

[0075] In some embodiments, the ADC101 can also be connected to the cross switch matrix XBAR3 via a bypass switch, specifically as follows: Figure 7As shown, the ADC101 can be connected to the crossbar switch matrix XBAR3 via a bypass switch 51. The bypass switch 51 is located in the bypass 50 connecting the digital conversion unit 10 and the crossbar switch matrix XBAR3. When the signal processing device is in the first operating mode, the bypass switch 51 is open, and the computation IP is active. This allows the raw sampled data output by the ADC101 to sequentially pass through the sampling latch circuit 201, floating-point conversion circuit 202, multiply-accumulate calibration circuit 203, sliding window buffer circuit 204, extreme value filtering circuit 207 (if enabled), mean calculation circuit 205, and result latch and trigger circuit 206 in the computation IP, completing fully automatic preprocessing before outputting floating-point type preprocessed data. Furthermore, when the signal processing device is in the second operating mode, the computation IP is closed, and the bypass switch 51 is closed. At this time, the bypass 50 is active, allowing the raw sampled data output by the ADC101 to be output to the crossbar switch matrix XBAR3 via the bypass 50. Specifically, in the second operating mode, the calculation IP is not working, the bypass switch 51 is closed, and the bypass 50 is turned on, so that the raw sampled data (integer format) output by the ADC101 is directly output to the target storage address through the cross switch matrix XBAR3.

[0076] In some embodiments, the bypass switch 51 can be any of the following: a relay, an analog switch chip (such as a CMOS bidirectional analog switch), a transmission gate, an optocoupler, a metal-oxide-semiconductor field-effect transistor (MOSFET) switch, a transistor switching circuit, and a radio frequency switch.

[0077] like Figure 8 The diagram shows the data flow within the hardware computing unit 20. The raw sampled data obtained by the ADC 101 enters the hardware computing unit 20, is first latched, then converted to a floating-point value (via the floating-point conversion circuit 202) to obtain the converted floating-point data. Next, the converted floating-point data undergoes real-time value conversion (via the multiply-accumulate calibration circuit 203) to obtain the physical real-time value. This physical real-time value is then stored (via the sliding window buffer circuit 204). The stored physical real-time value is then filtered (via the mean calculation circuit 205), and finally, the filtered preprocessed data is output (via the result latch and trigger circuit 206). Thus, each hardware computing unit 20 processes the raw sampled data in a pipelined manner and then outputs the preprocessed data, ensuring that the preprocessing of the raw sampled data is automatically executed by the hardware logic according to a fixed timing sequence without processor intervention.

[0078] In some embodiments, such as Figure 8As shown, the hardware computing unit 20 includes a register group 211, which includes a calibration coefficient register for storing a first calibration coefficient. During floating-point conversion, the first calibration coefficient (gain and offset parameters) is read from the calibration coefficient register. The register group 211 may also include a length sliding window register for setting the size of the sliding window (i.e., the number of samples participating in the mean calculation) and controlling the cache depth of the sliding window cache circuit 204. Furthermore, the register group 211 may include a filter register for setting the filtering mode (e.g., selecting whether to perform mean or RMS calculation, whether to enable extreme value removal, etc.) and controlling the operating state of the mean calculation circuit 205. Thus, the hardware computing unit 20 provided in this embodiment, by hardware-implementing the complete process of floating-point conversion, multiplication-accumulation calibration, and filtering, achieves the completion of all calculations without CPU intervention under a single ADC trigger, directly outputting standard floating-point physical values. This significantly reduces CPU resource utilization and improves system response speed and acquisition consistency.

[0079] like Figure 9 As shown in the figure, this disclosure also provides a microcontroller, including an analog-to-digital converter 10 and the aforementioned signal processing device. The signal processing device includes a hardware computing unit 20, wherein the analog-to-digital converter 10 is used to sample the input analog signal and output raw sampled data; the hardware computing unit 20 is connected to the analog-to-digital converter 10, and the hardware computing unit 20 is used to receive the raw sampled data, preprocess the raw sampled data to obtain floating-point type preprocessed data, and send the preprocessed data to a target memory address so that the processor can read the preprocessed data from the target memory address.

[0080] In some embodiments, the hardware computing unit 20 can be referred to the above description of the hardware computing unit 20, and for the sake of brevity, it will not be repeated here.

[0081] In some embodiments, this disclosure also provides an electronic device including a processor and the microcontroller described above.

[0082] In some embodiments, the electronic device may be any one of the following: an industrial controller, a programmable logic controller, a data acquisition terminal, a remote terminal unit, a motor driver, a frequency converter, a servo driver, a photovoltaic inverter, an energy storage converter, a charging pile, a smart meter, an environmental monitoring device, a smart sensor node, a robot controller, a medical device, or an automotive electronic control unit. Those skilled in the art will understand that the above examples are merely illustrative, and any electronic device that requires analog signal sampling using an ADC and execution of control logic after data processing can adopt the technical solutions provided in the embodiments of this application.

[0083] As can be seen from the above technical solutions, the embodiments of this application, by integrating a hardware pipeline computing IP unit at the ADC backend, move all preprocessing operations originally performed by the CPU, such as integer-to-floating-point conversion, multiply-accumulate calibration, and mean filtering, to hardware for automatic completion. This effectively reduces CPU resource consumption and improves the real-time performance and consistency of data processing. Simultaneously, by setting dual working modes, multi-channel time-division multiplexing, and anomaly self-healing mechanisms, the signal processing device possesses good compatibility, scalability, and reliability, enabling its widespread application in various embedded control scenarios with high requirements for sampling accuracy, response speed, and system stability.

[0084] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0085] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A signal processing device, characterized in that, The signal processing device is used to work in conjunction with an analog-to-digital converter (ADC), which samples the input analog signal and outputs the raw sampled data. A hardware computing unit, connected to the analog-to-digital conversion unit, is used to receive the raw sampled data, preprocess the raw sampled data to obtain preprocessed floating-point data, and send the preprocessed data to a target storage address so that the processor can read the preprocessed data from the target storage address.

2. The apparatus according to claim 1, characterized in that, The hardware computing unit comprises, in sequence, the following: A sampling latch circuit is used to latch the original sampling data; A floating-point conversion circuit is used to convert the original sampled data into floating-point data; The multiply-accumulate calibration circuit is used to perform multiply-accumulate calibration on the converted floating-point data to obtain calibration data; A sliding window buffer circuit is used to buffer the calibration data corresponding to multiple consecutive samples; A mean calculation circuit is used to calculate the mean of the calibration data in the sliding window buffer circuit to obtain the preprocessed data; The result latch and trigger circuit is used to latch the preprocessed data and trigger a signal after the preprocessed data is latched to send the preprocessed data to the target storage address.

3. The apparatus according to claim 2, characterized in that, The hardware computing unit also includes: An extreme value filtering circuit is connected in series between the sliding window buffer circuit and the mean calculation circuit. It is used to remove the maximum and minimum values ​​from the calibration data in the sliding window buffer circuit, and then input the remaining data after removing the maximum and minimum values ​​to the mean calculation circuit.

4. The apparatus according to claim 2, characterized in that, The hardware computing unit also includes: A calibration parameter register, which is connected to the multiply-accumulate calibration circuit, is used to store a preset first calibration coefficient; The multiply-accumulate calibration circuit is used to read the first calibration coefficient from the calibration parameter register and use the first calibration coefficient to perform multiply-accumulate calibration on the converted floating-point data to obtain the calibration data.

5. The apparatus according to claim 4, characterized in that, The hardware computing unit also includes: The parameter shielding circuit is connected to the calibration parameter register; The parameter shielding circuit is used to detect whether the second calibration coefficient to be written to the calibration parameter register exceeds a preset threshold range. If the second calibration coefficient exceeds the preset threshold range, writing the second calibration coefficient is prohibited, and the calibration coefficient in the calibration parameter register is kept unchanged at the first calibration coefficient.

6. The apparatus according to claim 1, characterized in that, Also includes: A clock control circuit is used to provide a clock signal to the hardware computing unit.

7. The apparatus according to claim 6, characterized in that, Also includes: A crossbar switch matrix, the input of which is connected to the hardware computing unit, and the output of which is connected to a DMA controller or processor, is used to send the preprocessed data to the target storage address.

8. The apparatus according to claim 7, characterized in that, The cross switch matrix is ​​also connected to the analog-to-digital converter unit via a bypass switch. The signal processing device has two operating modes: a first operating mode and a second operating mode. When the signal processing device is in the first operating mode, the bypass switch is in the open state and the hardware computing unit is in the working state. When the signal processing device is in the second operating mode, the bypass switch is in the closed state and the hardware computing unit is in the closed state. The raw sampling data output by the analog-to-digital converter unit is transmitted to the cross switch matrix via the bypass switch.

9. The apparatus according to claim 8, characterized in that, When the signal processing device is in the second operating mode, the clock control circuit is controlled to shut down the clock signal sent to the hardware computing unit.

10. The apparatus according to claim 2, characterized in that, The result latching and triggering circuit is further configured to generate a direct memory access request signal after the preprocessed data is latched, and to transmit the preprocessed data to the target memory address through the direct memory access controller according to the direct memory access request signal; or, to generate an interrupt request signal after the preprocessed data is latched, and to transmit the preprocessed data to the target memory address according to the interrupt request signal.

11. The apparatus according to any one of claims 2-5, characterized in that, The analog-to-digital conversion unit includes multiple sampling channels; The hardware computing unit adopts a time-division multiplexing architecture to preprocess the raw sampling data corresponding to the multiple sampling channels sequentially in multiple time slices; The sliding window buffer circuit includes multiple buffer areas, each of which corresponds to one of the multiple sampling channels. Each buffer area is used to store the calibration data corresponding to multiple consecutive samplings of the corresponding sampling channel. The hardware computing unit is also configured with multiple mean length configuration registers and multiple calibration coefficient registers that correspond one-to-one with the multiple sampling channels. When switching the sampling channel, the hardware computing unit automatically loads the buffer area, the mean length configuration register, and the calibration coefficient register corresponding to the current sampling channel.

12. The apparatus according to any one of claims 1-10, characterized in that, Also includes: An anomaly detection circuit is connected to the hardware computing unit; The anomaly detection circuit is used to control the hardware computing unit to pause the preprocessing operation when an anomaly event is detected, and to control the hardware computing unit to output the previous preprocessed data and report the anomaly status; after the anomaly event is resolved, it controls the hardware computing unit to refresh the current cached data and reset the operation state to resume the preprocessing operation.

13. A microcontroller, characterized in that, It includes an analog-to-digital conversion unit and a signal processing apparatus as described in any one of claims 1-12.

14. An electronic device, characterized in that, Includes a processor and a microcontroller as described in claim 13.

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