Firmware code searching method and storage device

Abstract

The present application provides a firmware code searching method and a storage device. The method includes: in a firmware code searching operation, skipping at least a first bit in a basic address code, introducing a scanning code in the basic address code from a second bit in the basic address code to obtain at least a scanning address code; and searching a target firmware code from a memory module according to the scanning address code. Thus, the efficiency of searching the firmware code from the memory module with unknown specification can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a firmware code search method and storage device. Background Technology

[0002] With the advancement of technology, the number of brands and models of memory modules circulating in the market is increasing. Different brands of memory modules, or different models within the same brand, may use different specifications and / or have different physical locations for storing specific firmware code (such as boot codes). Furthermore, after a period of use, the physical location within the memory module pre-set to store specific firmware code may change due to factors such as wear and / or reduced reliability.

[0003] Therefore, how to quickly find specific firmware code (such as boot code) from memory modules with unknown specifications is one of the topics that those skilled in the art have been dedicated to researching. Summary of the Invention

[0004] This invention provides a firmware code search method and storage device, which can effectively improve the efficiency of searching for firmware code from memory modules with unknown specifications.

[0005] This invention provides a firmware code searching method for a storage device. The storage device includes a memory module, and the firmware code searching method includes: in a firmware code searching operation, skipping at least one first bit in a basic address code, introducing a scan code into the basic address code starting from a second bit to obtain at least one scan address code; and searching for target firmware code from the memory module based on the at least one scan address code.

[0006] This invention also provides a storage device, including a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a firmware code search method.

[0007] Based on the above, in the firmware code search operation, at least one first bit in the basic address code can be skipped, and starting from the second bit in the basic address code, a scan code is introduced into the basic address code to obtain the scan address code. This scan address code can then be used to search for the target firmware code in the memory module. This effectively improves the efficiency of searching for firmware code in memory modules with unknown specifications. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of the basic address code, the first bit, and the second bit according to an embodiment of the present invention;

[0012] Figure 5 and Figure 6 This is a schematic diagram of at least a partial scan loop of the firmware code search operation according to an embodiment of the present invention;

[0013] Figure 7 This is a schematic diagram illustrating the physical locations of scan address codes in memory modules of different specifications according to embodiments of the present invention; and

[0014] Figure 8 This is a flowchart illustrating a firmware code search method according to an embodiment of the present invention. Detailed Implementation

[0015] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0016] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0017] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0018] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0019] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0027] In one embodiment, the memory controller 123 may further include a non-volatile memory circuit 26. The non-volatile memory circuit 26 can be used to store data non-volatilely. For example, the non-volatile memory circuit 26 may include a read-only memory (ROM), an electronic fuse memory circuit, and / or a similar non-volatile memory.

[0028] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage cells for non-volatile storage of data.

[0029] In one embodiment, a physical unit may include at least one physical programming unit. For example, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell. In one embodiment, a physical programming unit is also referred to as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the invention is not limited thereto.

[0030] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0031] In one embodiment, a physical erase unit may include multiple physical programming units. For example, the multiple physical programming units in a physical erase unit may be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the multiple physical programming units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0032] In one embodiment, an entity unit may include at least one entity erase unit. In another embodiment, if an entity unit includes multiple entity erase units, this entity unit is also referred to as a virtual block. Multiple entity erase units contained in the same virtual block can operate synchronously.

[0033] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0034] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0035] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0036] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0037] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0038] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0039] In one embodiment, the memory control circuit 23 may automatically perform a search operation (also known as a firmware code search operation) under certain conditions (e.g., in response to a specific situation). This firmware code search operation can be used to attempt to quickly find a specific firmware code (also known as a target firmware code) from the memory module 122. In one embodiment, the memory control circuit 23 may automatically perform this firmware code search operation in response to this specific situation.

[0040] In one embodiment, the aforementioned specific situation may include the storage device 12 being powered on (or turned on). For example, in response to the storage device 12 being powered on (or switched from a power-off state to a power-on state) while in a power-off state, the memory control circuit 23 may automatically perform this firmware code search operation. In one embodiment, the aforementioned specific situation may also include any situation where it is necessary to search for target firmware code from a memory module 122 whose specifications are unknown (for the memory control circuit 23), which will not be described in detail here.

[0041] In one embodiment, the target firmware code may include a boot code for the storage device 12. This boot code can be used to manage, control, and / or operate the memory module 122. In one embodiment, the target firmware code may carry information for managing, controlling, and / or operating the memory module 122 (also referred to as management information).

[0042] In one embodiment, this management information may reflect that the page address of a physical page in memory module 122 is represented by a certain number of bits (also called page bits). In one embodiment, this management information may reflect the total number of physical blocks in memory module 122 and / or the total number of physical pages contained in a physical block. In addition, this management information may also include any information that can be used to manage, control, and / or operate memory module 122 (e.g., bad block distribution information, etc.), which will not be elaborated here.

[0043] In one embodiment, after performing a firmware code search operation, if the storage location of the target firmware code in the memory module 122 is successfully found through this firmware code search operation, the memory control circuit 23 can read the target firmware code from this storage location (starting from). Then, the memory control circuit 23 can run this target firmware code and manage, control, and / or operate the memory module 122 based on this target firmware code.

[0044] In one embodiment, if the storage location of the target firmware code in the memory module 122 cannot be found through this firmware code search operation, the memory control circuit 23 may execute an error handling procedure. For example, this error handling procedure may include reporting an error message to the host system 11 and / or putting the storage device 12 into maintenance mode, etc.

[0045] In one embodiment, during a firmware code search operation, the memory control circuit 23 may obtain an address code (also referred to as a base address code). In one embodiment, the memory control circuit 23 may read this base address code from the non-volatile memory 26.

[0046] In one embodiment, this basic address code may contain multiple bits (also referred to as basic bits). In one embodiment, a basic address code may contain 24 bits (i.e., basic bits). In one embodiment, the total number of basic bits in a basic address code may also be adjusted according to practical needs, and the present invention does not impose any limitations.

[0047] In one embodiment, each basic bit is 0. In another embodiment, each basic bit may also be 1. However, it should be noted that if each basic bit is 1, then the bits 0 and 1 described in the following embodiments need to be swapped.

[0048] In one embodiment, the memory control circuit 23 can read information (also called basic information) used to generate this basic address code from the non-volatile memory 26. Then, the memory control circuit 23 can dynamically generate this basic address code based on this basic information.

[0049] In one embodiment, this basic information may include basic bit information and length information. The basic bit information may reflect the value of each basic bit (e.g., 0). The length information may reflect the total number of basic bits in a basic address code. In one embodiment, this basic information may include other information that can be used to dynamically generate this basic address code, and this invention is not limited thereto.

[0050] In one embodiment, after obtaining the basic address code, during the firmware code search operation, the memory control circuit 23 can skip at least one bit (also called the first bit) of this basic address code and start from a certain bit (also called the second bit) of this basic address code, introducing a scan code into this basic address code to obtain at least one scan address code. For example, in the basic address code, this scan code is represented by binary code to indicate the value corresponding to this scan code. Then, the memory control circuit 23 can search for the target firmware code from the memory module 122 according to this scan address code.

[0051] In one embodiment, each first bit is 0. In another embodiment, the total number of first bits is a preset number. For example, in one embodiment, assuming the basic address code contains 24 basic bits and this preset number is 8, then the first bit may include the first 8 bits (i.e., bits 0-7 in the basic address code) counted sequentially from the least significant bit to the most significant bit among these 24 basic bits. In one embodiment, the total number of first bits (i.e., the preset number) may also be adjusted according to practical needs, and this invention does not impose any limitations.

[0052] In one embodiment, the second bit is the first bit adjacent to the first bit. For example, in one embodiment, assuming that the basic address code contains 24 basic bits and the first bit contains the first 8 bits (i.e., bits 0-7 in the basic address code) counted sequentially from the least significant bit to the most significant bit in these 24 basic bits, then the second bit can be the 9th bit (i.e., bit 8 in the basic address code) counted sequentially from the least significant bit to the most significant bit in these 24 basic bits.

[0053] Figure 4 This is a schematic diagram illustrating the basic address code, the first bit, and the second bit according to an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, in the basic address code 41, the first 8 bits counted sequentially from the least significant bit to the most significant bit (i.e., bits 0-7 in the basic address code 41) can be considered as bit B(1) (i.e., the first bit). Furthermore, in the basic address code 41, the 9th bit counted sequentially from the least significant bit to the most significant bit (i.e., bit 8 in the basic address code 41) can be considered as bit B(2) (i.e., the second bit). Bits 0-7 correspond to the minimum offset interval of 256 pages, therefore bit 8 can be considered as the start offset bit (START_SHIFT_BIT). It should be noted that the total number of bits B(1) (i.e., the first bit) can be more or less; this invention does not impose any limitations.

[0054] In one embodiment, the memory control circuit 23 can obtain at least one scan address code by introducing a scan code into the base address code (e.g., base address code 41) before the specifications of the memory module 122 are determined. The memory control circuit 23 can then use this scan address code to attempt to quickly search for the target firmware code in the memory module 122.

[0055] by Figure 4 For example, in one embodiment, the memory control circuit 23 may start from the least significant bit of the basic address code 41 and skip bits 0-7 (i.e., bit B(1)) in the basic address code 41. Then, the memory control circuit 23 may start from bit 8 (i.e., bit B(2)) in the basic address code 41 and introduce a scan code into the basic address code 41 to obtain at least one scan address code. After the scan code is introduced into the basic address code 41, some bits in the basic address code 41, except for the skipped bits 0-7 (i.e., bit B(1)), will be replaced by this scan code to form a scan address code.

[0056] In one embodiment, the firmware code search operation may include one or more scan loops. In one embodiment, the first scan loop initiated or executed in the firmware code search operation is also referred to as the initial scan loop. In one embodiment, in this initial scan loop, the value corresponding to the scan code introduced to the basic address code is 0.

[0057] Figure 5 and Figure 6 This is a schematic diagram of at least a partial scan loop of the firmware code search operation according to an embodiment of the present invention. Please refer to... Figure 5 In one embodiment, it is assumed that scan loop 1 is the first scan loop to be started or executed in the firmware code search operation (i.e., the initial scan loop).

[0058] In one embodiment, during scan cycle 1 (i.e., the initial scan cycle), the memory control circuit 23 can introduce scan code 501 to... Figure 4 In the basic address code 41, a portion of the bits originally located in the basic address code 41 are replaced. The value corresponding to the scan code 501 is 0. By introducing the scan code 501 into the basic address code 41, the memory control circuit 23 can obtain the scan address code 51.

[0059] In one embodiment, after obtaining the scan address code 51, the memory control circuit 23 can generate a read instruction based on the scan address code 51. This read instruction instructs the memory module 122 to read data from the physical location in the memory module 122 corresponding to the scan address code 51. Then, the memory control circuit 23 can transmit this read instruction to the memory module 122 to attempt to search for the target firmware code in the memory module 122.

[0060] In one embodiment, if the target firmware code can be found in the memory module 122 based on the scan address code 51, the memory control circuit 23 can stop the firmware code search operation after executing scan loop 1. However, in another embodiment, if the target firmware code cannot be found in the memory module 122 based on the scan address code 51, the memory control circuit 23 can enter the next scan loop (i.e., scan loop 2) of the firmware code search operation after executing scan loop 1.

[0061] In one embodiment, during multiple scan cycles of the firmware code search operation, the value corresponding to the scan code introduced to the base address code can be switched among multiple values ​​(also called candidate values) in a preset order. In one embodiment, these candidate values ​​may include integers from 0 to 8. For example, in scan cycle 1, the memory control circuit 23 has set the value corresponding to scan code 501 to 0 among these candidate values.

[0062] Therefore, upon entering the next scan cycle (e.g., scan cycle 2), the memory control circuit 23 can, according to a preset order, set the value corresponding to the scan code introduced to the basic address code 41 to the next value (e.g., 1) that has not yet been used among these candidate values. It should be noted that these candidate values ​​and the order in which they are used can also be adjusted according to practical needs, and the present invention does not impose any restrictions on them.

[0063] In one embodiment, when the value corresponding to the scan code is odd (e.g., 1, 3, 5, 7), the scan code can be shifted in the basic address code starting from the second bit in the current scan cycle based on at least one shift value (also called the first shift value) to generate at least one scan address code (also called the first scan address code). That is, by introducing the scan code with the corresponding odd value into the basic address code, the first scan address code can be dynamically generated.

[0064] by Figure 5 For example, in scan loop 2, memory control circuit 23 can introduce scan code 502, which corresponds to the value 1 and whose binary representation is "00000001", into basic address code 41 to replace some bits originally located in basic address code 41. By introducing scan code 502 into basic address code 41, memory control circuit 23 can obtain at least one of scan address codes 52(1)-52(7).

[0065] Specifically, in scan loop 2, when the first shift value is 0, the memory control circuit 23 can use scan code 502 to replace the 9th bit (i.e., bit B(2)) in the basic address code 41 to obtain scan address code 52(1). When the first shift value is 1, the memory control circuit 23 can use scan code 502 to replace the 10th bit (i.e., shift 1 bit from bit B(2) to a higher bit) in the basic address code 41. And so on. Assuming the maximum value of the first shift value is 6, when the first shift value is one of 2-6, the memory control circuit 23 can use scan code 502 to replace one of the 11th to 15th bits in the basic address code 41 (i.e., shift 2 to 6 bits from bit B(2) to a higher bit) to obtain one of scan address codes 52(3)-52(7).

[0066] In one embodiment, the memory control circuit 23 may generate a corresponding read instruction based on the scan address code 52(i). This read instruction instructs the memory module 122 to read data from the physical location in the memory module 122 corresponding to the scan address code 52(i). The memory control circuit 23 may then transmit this read instruction to the memory module 122 to attempt to search for the target firmware code in the memory module 122.

[0067] In one embodiment, if the target firmware code can be found in the memory module 122 based on the scan address code 52(i), the memory control circuit 23 can stop the firmware code search operation after executing scan loop 2. However, in another embodiment, if the target firmware code cannot be found in the memory module 122 based on the scan address code 52(i), the memory control circuit 23 can enter the next scan loop (i.e., scan loop 3) of the firmware code search operation after executing scan loop 2.

[0068] In one embodiment, when the value corresponding to the scan code is even (e.g., 0, 2, 4, 6, 8), the scan code can be shifted in the basic address code starting from the second bit based on at least one shift value (also called the second shift value) during the current scan cycle to generate at least one scan address code (also called the second scan address code). That is, by introducing the scan code with an even value into the basic address code, the second scan address code can be dynamically generated.

[0069] In one embodiment, the maximum number of first shift values ​​is greater than the maximum number of second shift values. In one embodiment, the second shift value may include the maximum value of the first shift value (e.g., 6). In one embodiment, the maximum number of second shift values ​​is 1 (e.g., the second shift value can only be 6), while the maximum number of first shift values ​​can be 7 (e.g., the first shift value can be 0-6). In one embodiment, the first shift value, the second shift value, the maximum number of the first shift value, and the maximum number of the second shift value can all be adjusted according to practical needs, and the present invention does not impose any limitations on them.

[0070] Please refer to Figure 6 In one embodiment, after entering scan loop 3, the memory control circuit 23 can set the value corresponding to scan code 503 to the next unused value (e.g., 2) among these candidate values ​​according to a preset order. In scan loop 3, the memory control circuit 23 can introduce scan code 503 corresponding to the value 2 and whose binary representation is "10" into the basic address code 41 to replace some bits originally located in the basic address code 41. Figure 5 and Figure 6 For example, the second shift value is 6. Therefore, the memory control circuit 23 can use scan code 503 to replace bits 15-16 in the basic address code 41 to obtain scan address code 53.

[0071] In one embodiment, the memory control circuit 23 may generate a corresponding read instruction based on the scan address code 53. This read instruction instructs the memory module 122 to read data from the physical location in the memory module 122 corresponding to the scan address code 53. Then, the memory control circuit 23 may transmit this read instruction to the memory module 122 to attempt to search for the target firmware code in the memory module 122.

[0072] In one embodiment, if the target firmware code can be found in the memory module 122 based on the scan address code 53, the memory control circuit 23 can stop the firmware code search operation after executing scan loop 3. However, in another embodiment, if the target firmware code cannot be found in the memory module 122 based on the scan address code 53, the memory control circuit 23 can enter the next scan loop (i.e., scan loop 4) of the firmware code search operation after executing scan loop 3.

[0073] by Figure 6 For example, in scan cycle 4, memory control circuit 23 can introduce scan code 504, which corresponds to the value 3 and whose binary representation is "11", into base address code 41 to replace some bits originally located in base address code 41. By introducing scan code 504 into base address code 41, memory control circuit 23 can obtain at least one of scan address codes 54(1)-54(7).

[0074] Specifically, in scan loop 4, when the first shift value is 0, the memory control circuit 23 can use scan code 504 to replace the 9th-10th bits in the basic address code 41 to obtain scan address code 54(1). When the first shift value is 1, the memory control circuit 23 can use scan code 504 to replace the 10th-11th bits in the basic address code 41. And so on. Assuming the maximum value of the first shift value is 6, the memory control circuit 23 can obtain one of the scan address codes 54(3)-54(7) by adjusting the first shift value. Then, the memory control circuit 23 can search for the target firmware code in the memory module 122 based on at least one of the scan address codes 54(3)-54(7). For details of the relevant operation, please refer to scan loop 2, which will not be repeated here.

[0075] In one embodiment, if the target firmware code cannot be found in the memory module 122 based on the scan address code 54(j), the memory control circuit 23 may enter the next scan cycle (i.e., scan cycle 5) of the firmware code search operation after executing scan cycle 4.

[0076] In one embodiment, during scan loop 5, the memory control circuit 23 may introduce a scan code 505 corresponding to the value 4 and whose binary representation is "100" into the base address code 41 to replace some bits originally located in the base address code 41. For example, the memory control circuit 23 may use scan code 505 to replace bits 15-17 in the base address code 41 to obtain scan address code 55. Then, the memory control circuit 23 may search for the target firmware code in the memory module 122 based on scan address code 55. For related operational details, please refer to scan loop 1 and / or scan loop 3, which will not be repeated here.

[0077] Figure 7 This is a schematic diagram illustrating the physical locations of the scan address codes used in multiple scan cycles in memory modules of different specifications, according to an embodiment of the present invention. Please refer to... Figure 7 In one embodiment, two types of memory modules are used as examples. One memory module (also known as a first type of memory module) uses 11 bits (i.e., page bits) to represent the page address of its internal physical pages, while the other memory module (also known as a second type of memory module) uses 12 bits (i.e., page bits) to represent the page address of its internal physical pages.

[0078] In one embodiment, where the specifications of the memory module 122 are unknown, Figure 5 and Figure 6 Taking the firmware code search operation shown as an example, one or more scan address codes dynamically generated in each scan cycle can correspond to different physical locations in these two types of memory modules.

[0079] For example, in scan loop 1, scan address code 51 can correspond to physical page (0) of physical block (0) of the first type of memory module (page bit count = 11). Simultaneously, scan address code 51 can also correspond to physical page (0) of physical block (0) of the second type of memory module (page bit count = 12). Similarly, in other scan loops, each scan address code can correspond to a specific physical page of a specific physical block of the first type of memory module; please refer to [reference needed] for details. Figure 7 The table.

[0080] In one embodiment, by introducing scan codes into basic address codes and changing and moving scan codes according to specific rules, under certain circumstances (e.g., when the storage device 12 is powered on), the entity location most likely to contain the target firmware code or information related to the target firmware code (e.g., identification information or preamble information of the target firmware code) can be quickly found from the memory module 122 based on only a few dynamically generated scan address codes.

[0081] For example, the most common storage location for the target firmware code is the first physical page (i.e., physical page (0)) of the first physical block (i.e., physical block (0)) of various types of memory modules. However, in some cases (e.g., when the first physical block is corrupted or its reliability is reduced), the target firmware code may be migrated to the first physical page (i.e., physical page (0)) of another physical block (e.g., physical block (1)) of the memory module. In this case, if a blind scan of all possible address codes is performed in the traditional way, it may take a very long time to find the target firmware code in the memory module.

[0082] However, as Figure 7As shown, assuming the target firmware code is stored in the first physical page (i.e., physical page (0)) of the physical block (1) of the memory module 122, the memory control circuit 23 can find the target firmware code in the memory module 122 by means of the dynamically generated scan address code 52 (4) when scanning loop 2 is executed, without knowing the specifications of the memory module 122 (e.g., the number of page bits). From the start of scanning to confirming the storage location of the target firmware code in the memory module 122, the memory control circuit 23 may only need to perform (at least) 5 read and verification operations on the memory module 122. Thus, the efficiency of searching for firmware code in the memory module 122 whose specifications have not yet been determined can be greatly improved, thereby improving the power-on efficiency (or boot efficiency) of the storage device 12. After obtaining the target firmware code, the memory control circuit 23 can completely manage, control and / or operate the memory module 122 based on this target firmware code.

[0083] In one embodiment, the memory control circuit 23 may dynamically generate a scan address code based on the following virtual code.

[0084] PHYSICAL_BLOCK_ADDRESS = (INDEX << SCAN_SHIFT_BIT) << START_SHIFT_BIT

[0085] In the virtual code described above, INDEX represents the candidate value of the scan code used in the current scan cycle, and its value range can be 0~8; SCAN_SHIFT_BIT represents the number of cyclic shifts, and the shift range for odd indices can be set to 0~6, while the shift range for even indices can be fixed at 6; START_SHIFT_BIT represents the starting shift number, and its value can be fixed at 8, corresponding to a minimum 256-page addressing granularity; while PHYSICAL_BLOCK_ADDRESS represents the physical block address (i.e., scan address code) generated based on the candidate value, the number of cyclic shifts, and the starting shift number.

[0086] In one embodiment, the information generated by performing at least one shift operation on the candidate value can be regarded as a scan code, and this scan code can be incorporated into the basic address code to generate the corresponding scan address code. It should be noted that the above virtual code is only an example and can be adjusted according to practical needs.

[0087] In one embodiment, after a certain scan address code is dynamically generated, the memory control circuit 23 can read data (also called target data) from a certain entity unit (also called target entity unit) in the memory module 122 according to the scan address code.

[0088] Taking scan address code 51 as an example, after dynamically generating scan address code 51, the memory control circuit 23 can send a read command to the memory module 122 according to scan address code 51. This read command can be used to instruct data to be read from the physical location in the memory module 122 corresponding to scan address code 51. The physical location corresponding to scan address code 51 is the physical location of the target physical unit, and the data stored in this physical location is the target data. After receiving this read command, the memory module 122 can send back the target data in response to the read command.

[0089] In one embodiment, after obtaining the target data, the memory control circuit 23 can confirm whether the target data meets specific conditions (also known as preset conditions). If (or in response to) the target data meets the preset conditions, the memory control circuit 23 can determine that the storage location of the target firmware code in the memory module 122 has been found, and stop the firmware code search operation. Alternatively, if (or in response to) the target data does not meet the preset conditions, the memory control circuit 23 can determine whether to continue the firmware code search operation based on whether the number of times the firmware code search operation has been executed has reached a threshold value.

[0090] In one embodiment, this threshold value can be 50. In another embodiment, this threshold value can also be adjusted according to practical needs. In one embodiment, this threshold value can correspond to the maximum scan cycle. In one embodiment, when the number of times the firmware code search operation is executed reaches this threshold value, it indicates that enough reads of the target data have been performed but the target firmware code still cannot be found. At this time, the memory control circuit 23 can stop this firmware code search operation.

[0091] In one embodiment, during the firmware code search operation, the memory control circuit 23 can update the number of times the firmware code search operation is executed, each time target data is read from the memory module 122 based on a scan address code.

[0092] For example, the memory control circuit 23 can increment this execution count by 1. If (or in response to) the target data not meeting the preset conditions, the memory control circuit 23 can determine whether this execution count has reached a threshold value. If this execution count has not reached (e.g., is less than) this threshold value, the memory control circuit 23 can continue to execute the unfinished firmware code search operation (e.g., execute the remaining operations in the current or next scan cycle).

[0093] However, if the number of executions has reached (e.g., greater than or equal to) this threshold value, the memory control circuit 23 may stop the firmware code search operation and determine that the firmware code search operation has failed (i.e., the storage location of the target firmware code in the memory module 122 cannot be found through this firmware code search operation). In response to the firmware code search operation failure, the memory control circuit 23 may execute the relevant error handling program (e.g., reporting error messages and / or entering maintenance mode, etc.).

[0094] In one embodiment, the above-mentioned preset conditions include the following conditions:

[0095] A. The target data does not contain any uncorrectable bits;

[0096] B. The logical cluster address field of the target data contains preset information (also known as the first preset information); and

[0097] C. The signature field of the target data contains preset information (also known as the second preset information).

[0098] In one embodiment, after reading target data from memory module 122 based on a certain scan address code, memory control circuit 23 may instruct decoding circuit 25 to decode the target data. Memory control circuit 23 may determine whether there are any uncorrectable bits in the target data based on the decoding result of decoding circuit 25. If there are no uncorrectable bits in the target data (i.e., all (erroneous) bits in the target data can be corrected), then memory control circuit 23 may determine that condition A has been met. However, if there are uncorrectable bits in the target data (i.e., at least one (erroneous) bit in the target data cannot be corrected), then memory control circuit 23 may determine that condition A has not been met.

[0099] In one embodiment, after reading target data from memory module 122 based on a certain scan address code, memory control circuit 23 can confirm whether a specific field of the target data contains first preset information. In one embodiment, this specific field may include a logical cluster address field.

[0100] Generally, this logical cluster address field is used to record the logical cluster address information corresponding to the entity page containing the target data. However, for entity pages containing target firmware code or information related to the target firmware code (such as target firmware code identification information or preamble information), this logical cluster address field is used to record a signature.

[0101] In one embodiment, the memory control circuit 23 can compare the information recorded in the logical cluster address field of the target data with the verification information (also known as the magic number) pre-stored in the non-volatile memory 26. If they are the same, the memory control circuit 23 can determine that the logical cluster address field of the target data does indeed record the first preset information, and determine that condition B has been met. However, if they are different, the memory control circuit 23 can determine that the logical cluster address field of the target data does not record the first preset information, and determine that condition B has not been met.

[0102] In one embodiment, after reading target data from memory module 122 based on a certain scan address code, memory control circuit 23 can confirm whether another specific field of the target data contains second preset information. In one embodiment, this specific field may include a signature field. This signature field is used to record identification information. For example, this identification information may include encoded information corresponding to a specific string (e.g., binary encoded information). In one embodiment, this signature field is located in the first two bytes of the target data.

[0103] In one embodiment, the memory control circuit 23 can compare the information recorded in the signature field of the target data with the verification information (e.g., the encoding information corresponding to a specific string) pre-stored in the non-volatile memory 26. If they are the same, the memory control circuit 23 can determine that the signature field of the target data does indeed record the second preset information, and determine that condition C has been met. However, if they are different, the memory control circuit 23 can determine that the signature field of the target data does not record the second preset information, and determine that condition C has not been met.

[0104] In one embodiment, after reading target data from memory module 122 based on a certain scan address code, memory control circuit 23 can verify whether conditions A, B, and C are satisfied one by one. If (or in response to) conditions A, B, and C are all satisfied, memory control circuit 23 can determine that the target data meets the preset conditions. However, if (or in response to) at least one of conditions A, B, and C is not satisfied, memory control circuit 23 can determine that the target data does not meet the preset conditions. It should be noted that, in one embodiment, memory control circuit 23 can dynamically change the verification order of conditions A, B, and C, and this invention does not limit this. In one embodiment, the preset conditions can also be adjusted according to practical needs, and this invention does not limit this.

[0105] In one embodiment, the memory control circuit 23 can support a two-stage (or multi-stage) firmware code search operation. This two-stage (or multi-stage) firmware code search operation includes a first-stage scan and a second-stage scan. The first-stage scan is performed before the second-stage scan to attempt to search for the target firmware code in the memory module 122. In one embodiment, the operation of dynamically generating a scan address code by incorporating the scan code into the basic address code and then searching for the target firmware code in the memory module 122 based on this dynamically generated scan address code belongs to the second-stage scan.

[0106] In one embodiment, after initiating the firmware code search operation, the memory control circuit 23 may first perform a first-stage scan. In the first-stage scan, the memory control circuit 23 may read at least one scan address code (also called a preset scan address code) from a preset storage space. For example, this preset storage space is located in non-volatile memory 26. Unlike the scan address codes dynamically generated by introducing scan codes in the second-stage scan, each preset scan address code used in the first-stage scan is not dynamically generated by introducing scan codes. These preset scan address codes can serve as address information with a relatively high hit rate and are pre-stored in this preset storage space.

[0107] In one embodiment, during the first-stage scan, after obtaining the preset scan address code, the memory control circuit 23 can directly search for the target firmware code in the memory module 122 based on this preset scan address code. For example, during the first-stage scan, the memory control circuit 23 can directly generate a read instruction based on this preset scan address code, and based on this read instruction, attempt to read the target firmware code or information related to the target firmware code (such as the identification information or preamble information of the target firmware code) from one or more physical locations in the memory module 122 with a relatively high hit rate.

[0108] In one embodiment, during the first-stage scan, the memory control circuit 23 can determine whether the target firmware code can be found in the memory module 122 based on a preset scan address code. If the target firmware code can be found in the memory module 122 based on the preset scan address code, the memory control circuit 23 can stop this firmware code search operation before entering the second-stage scan. However, if the target firmware code cannot be found in the memory module 122 based on the preset scan address code, the memory control circuit 23 can continue to enable the second-stage scan after the first-stage scan ends (e.g., the preset scan address code is exhausted). During the second-stage scan, the memory control circuit 23 can perform the operation of dynamically generating a scan address code by introducing the scan code into the basic address code and searching for the target firmware code in the memory module 122 based on the dynamically generated scan address code. The relevant details have been described above and will not be repeated here.

[0109] In one embodiment, by introducing a two-stage (or multi-stage) firmware code search operation, in the initial stage of the firmware code search operation (e.g., the first stage scan), the memory control circuit 23 has the opportunity to quickly find the target firmware code from the memory module 122 based on pre-stored preset scan address codes, thereby significantly improving the search efficiency for the target firmware code. However, if the first stage scan fails to find the target firmware code, the above-mentioned dynamic generation of scan address codes is activated instead, and one or more scan address codes with a relatively high search hit rate are automatically generated in the second stage scan to search for the target firmware code. Compared with the traditional method of blindly scanning all possible address codes, whether the phased or non-phased firmware code search operation proposed in this embodiment is used, the efficiency of searching for firmware code from memory modules with unknown specifications can be effectively improved.

[0110] Figure 8 This is a flowchart illustrating a firmware code search method according to an embodiment of the present invention.

[0111] Please refer to Figure 8 In step S801, during the firmware code search operation, at least one first bit in the basic address code is skipped, and starting from the second bit in the basic address code, a scan code is introduced into the basic address code to obtain at least one scan address code.

[0112] In step S802, the target firmware code is searched for in the memory module according to the scan address code.

[0113] However, Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 8 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0114] In summary, the firmware code searching method and storage device proposed in this invention can skip at least one first bit in the basic address code and introduce scan codes into the basic address code starting from the second bit, even when the specifications of the memory module are not yet determined, to dynamically generate multiple scan address codes. By changing the candidate values ​​corresponding to the scan codes and the positions of the scan codes in the basic address code according to preset rules, a smaller number of scan address codes can be used to prioritize searching for the physical locations that are more likely to store the target firmware code or information related to the target firmware code, without having to blindly scan all possible address codes one by one. Therefore, the number of read and verification operations required for firmware code searching can be effectively reduced, the efficiency of searching for target firmware code from memory modules with unknown specifications can be improved, and the power-on or boot-up efficiency of the storage device can be further improved.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of searching for a firmware code, characterized by, A method for searching firmware code, wherein the storage device comprises a memory module, and the firmware code searching method comprises: In a firmware code searching operation, skipping at least a first bit in a base address code, introducing a scan code in the base address code starting from a second bit in the base address code to obtain at least a scan address code; and Searching for a target firmware code from the memory module according to the scan address code.

2. The method of claim 1, wherein, The first bits are all 0, and the second bit is the first bit adjacent to the first bits.

3. The method of claim 1, wherein the firmware code search method is characterized by, The total number of the first bits is a preset number.

4. The method of claim 1, wherein the firmware code search method is characterized by, In an initial scan cycle of the firmware code searching operation, a value corresponding to the scan code is 0.

5. The method of claim 1, wherein the firmware code search method is characterized by, In a plurality of scan cycles of the firmware code searching operation, the value corresponding to the scan code is switched among a plurality of candidate values in a preset order.

6. The method of claim 5, wherein the firmware code search method is characterized by, When the value corresponding to the scan code is odd, the scan code is moved in the base address code starting from the second bit based on at least a first shift value in a current scan cycle to generate at least a first scan address code.

7. The method of claim 6, wherein the firmware code search method is characterized by, When the value corresponding to the scan code is even, the scan code is moved in the base address code starting from the second bit based on at last a second shift value in the current scan cycle to generate at least a second scan address code, wherein an upper limit of the number of the first shift values is greater than an upper limit of the number of the second shift values.

8. The method of claim 7, wherein the firmware code search method is characterized by, The second shift values include a maximum value of the first shift values, and an upper limit of the number of the second shift values is 1.

9. The method of claim 1, wherein, Searching for the target firmware code from the memory module according to the scan address code comprises: Reading target data from a target entity unit in the memory module according to the scan address code; Determining whether the target data meets a preset condition; In response to the target data meeting the preset condition, determining that a storage location of the target firmware code in the memory module has been found, and stopping the firmware code searching operation; and In response to the target data not meeting the preset condition, determining whether to continue performing the firmware code searching operation according to whether a number of executions of the firmware code searching operation reaches a threshold value.

10. The method of claim 9, wherein the firmware code search method is characterized by, The preset condition comprises a plurality of conditions including: No uncorrectable bit exists in the target data; A first preset information is recorded in a logical cluster address field of the target data; and A second preset information is recorded in a signature field of the target data.

11. The method of claim 1, wherein the firmware code search method is characterized by: The firmware code searching method further comprises: Before searching for the target firmware code from the memory module according to the scan address code, reading at least a preset scan address code from a preset storage space, and searching for the target firmware code from the memory module according to the preset scan address code.

12. A memory device, comprising: Comprises: a connection interface connected to a host system; a memory module; and a memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to perform the firmware code searching method of any one of claims 1-11.

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