A thread load usage calculation method suitable for microcontrollers

Abstract

The application discloses a thread load usage rate calculation method suitable for a microcontroller, and realizes low-load thread load usage rate calculation in a real-time operating system based on a DMA module, and comprises the following steps: configuring a carrying source address of the DMA module and task occupation time Ti of each thread in the operating system; initializing a buffer address and length for storing received data, and system time Tsys; calling last scheduling system time Tsch and last remaining length Lsch; when scheduling is needed, according to the obtained current system time Tsys and current remaining length Lsys, in combination with the last scheduling system time Tsch, the last remaining length Lsch and the data buffer length L, the number of DMA carrying times passed in each thread is calculated and saved to the task occupation time Ti of each thread, Tsch is updated to Tsys, and Lsch is updated to Lsys; and according to the task occupation time Ti of each thread and the current system time Tsys, the load usage rate of each thread is calculated.

Description

Technical Field

[0001] This invention belongs to the field of MCUs, and more specifically, relates to a data sampling mechanism using a DMA (Direct Memory Access) module to implement a low-load method for calculating the CPU load utilization of each thread in a real-time operating system. Background Technology

[0002] Currently, most real-time operating systems in the embedded field provide interfaces for calculating thread CPU load. This is typically done using software timers. Once enabled, the system periodically triggers an interrupt to refresh the timer counter. When software scheduling is activated, the timer's occupancy time is updated. Calling the query interface then calculates the software load percentage of each thread based on the system's current counter and the thread's occupancy time.

[0003] 1. In the field of MCU, the memory and computing power available to the terminal node are extremely limited. Enabling software load computing will significantly reduce system performance. In practical applications, it is often only used for debugging.

[0004] 2. The mechanism for calculating the load itself also requires CPU load, and timer interrupts will frequently interrupt each thread, causing the calculation results of the actual load required by the thread to be inaccurate. Summary of the Invention

[0005] To address at least one of the aforementioned technical problems, this invention provides a method for calculating thread load utilization in microcontrollers. This method utilizes the DMA (Distributed Memory Access) hardware peripheral commonly available on the MCU to reduce interrupt response frequency, and uses a peripheral with timing functionality to control the DMA transfer frequency, thereby achieving high-precision, low-load software load calculation.

[0006] According to one aspect of the present invention, a method for calculating thread load utilization suitable for microcontrollers is provided, which implements low-load thread load utilization calculation in a real-time operating system based on a DMA module, comprising: Configure the DMA module's transfer source address and the task time Ti of each thread in the operating system; Initialize the address and length of the buffer used to store received data, as well as the system time Tsys; Retrieve the previous scheduling system time Tsch and the previous remaining length Lsch; Based on the current system time Tsys and the current remaining length Lsys, combined with the previous scheduling system time Tsch, the previous remaining length Lsch, and the data buffer length L, calculate the number of DMA moves in each thread and save them to the task occupancy time Ti of each thread, and update Tsch = Tsys and Lsch = Lsys. The load utilization of each thread is calculated based on the task time Ti of each thread and the current system time Tsys.

[0007] As a further technical solution, the method also includes: During operating system initialization, locate the handle of the current thread recorded in the operating system, record the member variable name of any object of the thread, and use its address as the DMA transfer source address D1 during programming.

[0008] As a further technical solution, the method also includes: Locate the state variables of each thread in the operating system and create the task time Ti for each thread.

[0009] As a further technical solution, the method also includes: When the scheduler is enabled, the previous scheduling system time Tsch and the previous remaining length Lsch are initialized.

[0010] As a further technical solution, the method also includes: Before enabling the operating system, configure the interrupt function for DMA transfer completion, and update Tsys when the transfer is complete.

[0011] As a further technical solution to enable load computing, it also includes: Configure the baud rate of the peripheral module according to the timing accuracy and enable the DMA transmit / receive function.

[0012] As a further technical solution, after enabling the DMA transmit / receive function, the method further includes: Depending on whether data needs to be transmitted externally, external loopback can be achieved by connecting the transmit and receive pins after enabling the pin, or the internal loopback function of the peripheral device can be used.

[0013] As a further technical solution, when obtaining thread load utilization, the method further includes: Starting from the beginning address of the task list that records task information, retrieve the task time Ti of each thread, divide the task time Ti of each thread by the current system time Tsys, and obtain the load utilization ratio of each thread.

[0014] As a further technical solution, the interrupt frequency of the operating system is determined by the data buffer length L and the DMA request frequency of the peripheral module.

[0015] According to one aspect of the present invention, an apparatus for calculating thread load utilization of a microcontroller is provided. The apparatus comprises a DMA module, a timing module, and a processing module. The DMA module is used for DMA transfer, the peripheral module is used to control the transfer frequency of the DMA module, and the processing module is used to execute the thread load utilization calculation method for a microcontroller after enabling load calculation.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The hardware peripherals commonly available in the MCU terminal are used to sample the data occupied by the thread load. The sampling process is completely handed over to DMA and peripherals with timing functions, replacing the timer interrupt method. The interrupt response frequency is determined by the length of the data buffer.

[0017] 2. By utilizing the thread information within the data buffer, the load utilization rate over a recent period can be statistically analyzed.

[0018] 3. If a communication peripheral is chosen for timing, enabling the relevant pins allows for simultaneous transmission of sampled data, thereby establishing a communication network that shares the current MCU load status. This can be further extended to more advanced training models, simultaneously sending data to the domain control center, allowing the domain control center to run more advanced models to statistically analyze the load status of each node, such as machine learning models. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a method for calculating thread load utilization in a microcontroller, as provided in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram illustrating the specific data flow of DMA transport provided in an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram illustrating the data flow of historical usage rates after system enablement, provided as an embodiment of the present invention. Detailed Implementation

[0023] In the real-time operating system of MCU, traditional software load calculation methods rely on software timers to trigger timer interrupts. The interrupt response frequency of this method is one-to-one with the timing accuracy. On the one hand, it will greatly increase the additional system load, and on the other hand, the frequent interruptions will affect the normal operation of the thread to a certain extent.

[0024] To address this, this invention designs a low-load thread load utilization calculation method suitable for MCUs. It utilizes the DMA (Direct Memory Access) hardware peripheral commonly available on the MCU to reduce interrupt response frequency, and uses a peripheral with timing capabilities to control the DMA transfer frequency, achieving high-precision, low-load software load calculation. It should be noted that "peripherals with timing capabilities" can be considered as peripherals that can provide trigger signals at a stable rate. Taking UART as an example, its ability to provide trigger signals at a stable rate can be considered as having timing capabilities.

[0025] Furthermore, the technical solution adopted by this invention to solve its technical problem is as follows: The number of DMA data transfers is used instead of the time counter value. Before each thread is scheduled, the number of DMA transfers during the execution of each thread is recorded. The ratio of this number of transfers to the total number of transfers is used to represent the CPU load utilization of the thread. Before enabling the system, a fixed cyclic transfer process for DMA is configured, so that DMA continuously performs transfer actions at fixed intervals during normal system operation. By cooperating with other peripherals to provide a transfer enable signal, the transfer speed of DMA can be controlled, thus achieving a timing function.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined to form new technical solutions. Such combinations are not bound by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0027] Please see Figure 1 , Figure 2 and Figure 3 Taking a DMA+UART peripheral as an example, the specific process of the method described in this invention is explained as follows: Step 1: During system initialization, the variable name used by the operating system to store current thread information can be obtained. During the pre-compilation stage, the address of this variable needs to be declared externally and used as the source address for DMA data transfer. This embodiment of the invention uses the thread's task ID as an example, but it can actually be replaced with any sampling object.

[0028] Specifically, find the handle of the current thread in the operating system, record the member variable name of its task ID, and take its address as the source address D1 for DMA transfer during programming.

[0029] Step 2: During task creation, the operating system simultaneously creates handles and status variables for recording threads. A member variable `Ti` needs to be added to the status variables to record thread occupancy information. Specifically, locate the status variables for each thread in the operating system, record or add the time counter `Ti`, and complete the creation of the task occupancy time.

[0030] It's important to note that the handle in step 1 records the address of the current handle, while step 2 refers to the handle bound to the task itself. In the operating system, tasks are dynamically created, and the relationship between the two is that, with task scheduling, the handle in step 1 will point to the handle of the task currently being processed by the CPU. Furthermore, creating task handles is a standard OS procedure; the emphasis here is on adding a time-counting state variable to it.

[0031] Step 3, in the load balancing phase, mainly involves initializing the DMA loop transfer list configuration and enabling relevant peripherals. Peripherals need to be configured with baud rates according to timing precision and have DMA transmit / receive functions enabled. Depending on whether data needs to be transmitted externally, external loopback can be achieved by connecting the transmit and receive pins after enabling the pin, or the internal loopback function typically provided by the peripheral can be used. For specific list configuration details, please refer to [reference needed]. Figure 2 The data flow diagram shows that the direction of data transfer is from the thread task ID to the peripheral sending FIFO, and from the peripheral receiving FIFO to the data buffer. The transfer length is the buffer length L.

[0032] Specifically, global variables are initialized, including the Buffer storing the received data and the system time Tsys (which can also be considered as a recorded DMA cycle count). Initializing the Buffer storing the received data further includes initializing the Buffer's length L and address D2. After the data transfer begins, the current remaining length of the Buffer is represented by Lsys. The number of data items transferred can be obtained by subtracting the current remaining length from the total Buffer length; if the hardware supports this, it can also be obtained by querying the DMA registers. Tsys will be updated via a DMA completion interrupt after each Buffer transfer task is completed.

[0033] Taking a DMA+UART peripheral as an example, before enabling the system, configure D1 to the UART transmit FIFO, and the UART receive FIFO to D2 for cyclic transfer. Initialize the UART and enable transmission and reception. The baud rate configuration is calculated according to the timing accuracy requirements. For example, if the timing accuracy requirement is 20µs, since the UART frame has 8 data bits and 1 stop bit, totaling 10 bits, the UART baud rate can be configured to 500000.

[0034] This step also includes: configuring the interrupt function for DMA transfer completion, updating Tsys when the transfer is complete, and automatically maintaining the updating and acquisition of Lsys by the hardware.

[0035] Step 4: Before enabling system scheduling, the system time needs to be initialized, recorded by the total number of transfers (Tsys) and the remaining length of the current transfer (Lsys). During system operation, DMA transfers are CPU-independent, so Lsys is automatically updated by hardware, while Tsys is updated in the DMA completion interrupt function after the current transfer is completed.

[0036] Initializing the system time also includes initializing the DMA count value from the last scheduling, namely the last scheduling system time Tsch and the last remaining length Lsch.

[0037] After enabling the operating system, each time a system scheduling occurs, obtain the current Tsys and Lsys, calculate the number of DMA transfers traversed by the thread and save it to Ti, and update Tsch = Tsys and Lsch = Lsys.

[0038] Step 5: Before each thread switch is triggered by the scheduler, it will determine the appropriate parameters based on the specified parameters. Figure 1 The calculation formula uses the total number of DMA moves in the previous thread as the counting unit.

[0039] Specifically, the total number of DMA moves in the previous thread is counted, including: Step A), obtain Tsys and the current remaining length Lsys; Step B), calculate Ti = L × (Tsys - Tsch) + (Lsch - Lsys); Step C), update Tsch = Tsys, Lsch = Lsys.

[0040] When obtaining the thread load percentage, start searching from the beginning address of the task list that records task information, obtain the time count Ti for each thread, and divide it by the system count Tsys to get the load utilization percentage of each thread.

[0041] In summary, the workload duration of each task and the total system runtime can be obtained, which can be used to calculate the CPU utilization of each task. The interrupt frequency of the entire process is determined by the length of the data buffer and the DMA request frequency of the peripherals. Taking the DMA+UART scheme as an example, a 100-byte buffer and a baud rate of 500,000 can achieve a timing accuracy of 20µs. Compared with a timing scheme with the same 20µs accuracy, the interrupt response frequency can be reduced to 1% of the original.

[0042] If we only focus on the historical usage rate after the system is enabled, the configuration of the data buffer can be further simplified, such as... Figure 3 As shown, only the transfer of sampled data to the transmit FIFO is configured. In this case, there is no need to consider the space usage of the buffer, so the number of transfers can be configured to be large enough, and the space utilization and interrupt frequency can be further optimized.

[0043] Based on the same inventive concept as the aforementioned method embodiments, this embodiment of the invention also provides an apparatus for calculating thread load utilization rate suitable for microcontrollers. The apparatus consists of a DMA module, a timing module, and a processing module. The DMA module is used for DMA transfer, the timing module is used to control the transfer frequency of the DMA module, and the processing module is provided by the microcontroller and is used to execute the thread load utilization rate calculation method suitable for microcontrollers after enabling load calculation.

[0044] In summary, the key points of this invention are: 1. By using the DMA of a microcontroller and peripherals with timing functions, a framework for hardware-timed sampling data is built to realize a scheme for calculating the CPU utilization of each thread in a real-time operating system with low interrupt load.

[0045] 2. A software solution that uses DMA transfer counts as the timing unit and records the DMA transfer counts during the scheduling process for load calculation.

[0046] 3. By using a loopback receiving method, the system can simultaneously sample and record recent thread scheduling information during timing, which can be used for local recording and statistics of load utilization over a recent period.

[0047] Any points not elaborated above are common knowledge in this field.

[0048] The terms “comprising” and “having”, and any variations thereof, in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or apparatus that includes a series of steps or units, not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention.

Claims

1. A method for calculating thread load utilization in a microcontroller, characterized in that, Implementing low-load thread load utilization calculation in a real-time operating system based on the DMA module, including: Configure the DMA module's transfer source address and the task time Ti of each thread in the operating system; Initialize the address and length of the buffer used to store received data, as well as the system time Tsys; Retrieve the previous scheduling system time Tsch and the previous remaining length Lsch; When scheduling is required, based on the current system time Tsys and the current remaining length Lsys, combined with the previous scheduling system time Tsch, the previous remaining length Lsch and the data buffer length L, calculate the number of DMA moves in each thread and save them to the task occupancy time Ti of each thread, and update Tsch = Tsys and Lsch = Lsys. The load utilization of each thread is calculated based on the task time Ti of each thread and the current system time Tsys.

2. The method for calculating thread load utilization of a microcontroller according to claim 1, characterized in that, The method further includes: During operating system initialization, locate the handle of the current thread recorded in the operating system, record the member variable name of any object of the thread, and use its address as the DMA transfer source address D1 during programming.

3. The method for calculating thread load utilization of a microcontroller according to claim 2, characterized in that, The method further includes: Locate the state variables of each thread in the operating system and create the task time Ti for each thread.

4. The method for calculating thread load utilization of a microcontroller according to claim 1, characterized in that, The method further includes: When the scheduler is enabled, the previous scheduling system time Tsch and the previous remaining length Lsch are initialized.

5. The method for calculating thread load utilization of a microcontroller according to claim 1, characterized in that, The method further includes: Before enabling the operating system, configure the interrupt function for DMA transfer completion, and update Tsys when the transfer is complete.

6. The method for calculating thread load utilization for microcontrollers according to claim 1, characterized in that, Enabling load computing also includes: Configure the baud rate of the peripheral module according to the timing accuracy and enable the DMA transmit / receive function.

7. The method for calculating thread load utilization of a microcontroller according to claim 6, characterized in that, After enabling the DMA transmit / receive function, the method further includes: Depending on whether data needs to be transmitted externally, external loopback can be achieved by connecting the transmit and receive pins after enabling the pin, or the internal loopback function of the peripheral device can be used.

8. The method for calculating thread load utilization of a microcontroller according to claim 1, characterized in that, When obtaining thread load utilization, the method further includes: Starting from the beginning address of the task list that records task information, retrieve the task time Ti of each thread, divide the task time Ti of each thread by the current system time Tsys, and obtain the load utilization ratio of each thread.

9. The method for calculating thread load utilization of a microcontroller according to claim 1, characterized in that, The operating system's interrupt frequency is determined by the data buffer length L and the DMA request frequency of the peripheral modules.

10. A device for calculating thread load utilization in a microcontroller, characterized in that, The device comprises a DMA module, a timing module, and a processing module. The DMA module is used for DMA transfer, the peripheral module is used to control the transfer frequency of the DMA module, and the processing module is used to execute the thread load utilization calculation method for microcontrollers as described in any one of claims 1-9 after enabling load calculation.

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