A hardware loss-aware heterogeneous computing operating system and a computing power assetization method and storage medium thereof

Abstract

This invention relates to a heterogeneous computing power operating system architecture based on hardware loss awareness, along with its computing power assetization method and storage medium, belonging to the field of heterogeneous computing power scheduling and trusted transactions. Addressing the shortcomings of existing solutions that rely solely on nominal computing power measurement, cannot quantify hardware loss, and have fixed cross-domain transaction matching mechanisms, this invention adopts a kernel HAL and upper-layer transaction layered isolation architecture. The system collects hardware operating indicators to calculate the hardware health profit and loss factor Ψ, and normalizes the nominal computing power to obtain standardized effective computing power units (CUs). Local scheduling and cross-domain computing power lending are completed through software Zone partitioning and the PECP2.0 four-dimensional profit and loss model, suppressing additional cross-domain losses. The matching unit incorporates local compliance verification and custom matching weights, outputting Top-K computing power candidates. After matching, the smart contract freezes the CU quota, dynamically verifies Ψ throughout the fulfillment process, automatically distributes revenue according to the actual effective CUs, and records all transaction hashes on the blockchain for evidence storage. This invention constructs a complete closed loop for heterogeneous computing power from hardware access, loss-aware scheduling, intelligent matching to on-chain settlement, adapting to multi-cloud hybrid heterogeneous computing power trusted asset circulation scenarios.

Description

Technical Field

[0001] This invention relates to the fields of heterogeneous computing power operating system kernel-level hardware abstraction and adaptation, AI acceleration hardware wear quantification and measurement, and distributed cluster federated scheduling technology. In particular, it relates to a heterogeneous computing power operating system based on hardware wear awareness, a method for realizing computing power assetization, and a computer-readable storage medium. It is applicable to standardized asset measurement and trusted transaction scenarios for heterogeneous GPU / NPU computing power clusters across multiple regions and operating entities. With the explosive growth of artificial intelligence and large-scale models, computing power has become a core productive force in the digital economy. Unlike traditional operating systems such as Linux and Windows, which only manage CPU, memory, and disk resources for single devices, this invention's computing power operating system can abstract massive numbers of servers, heterogeneous accelerator cards, and cross-regional data centers into a unified supercomputing power resource pool for scheduling and management, realizing standardized supply and assetized circulation of computing power. Background Technology

[0002] With the rapid iteration and deployment of large-scale models and AI inference technologies, multiple architectures and protocols of AI inference engines coexist within computing clusters, including TensorRT, ONNXRuntime, Triton, and the LLaMA series. These inference engines exhibit significant heterogeneity in communication protocols, request parameters, tensor data structures, operational and maintenance detection mechanisms, and performance indicator systems. Existing computing power scheduling platforms mostly use hard-coded binding of a single inference engine or rely on general HTTP gateways for basic message forwarding, resulting in inherent technical shortcomings. Simultaneously, mainstream cluster scheduling frameworks, hardware virtualization solutions, and cross-domain scheduling architectures suffer from multi-layered systemic defects in their underlying design, detailed below.

[0003] Existing shortcomings in native heterogeneous adaptation of various AI inference engines

[0004] General gateways only complete message pass-through and cannot parse core data such as AI-specific tensors, memory usage, and inference latency, and cannot adapt to the differentiated underlying data requirements of heterogeneous inference engines. The hard-coded coupling is extremely high. Adding or replacing the inference engine requires modifying the scheduling kernel source code and restarting the cluster service, which can easily cause business interruption and result in poor cluster stability. There is no unified standard for collecting performance indicators and operating status of various engines, and the scheduling platform cannot generate a globally standardized operation and maintenance view, resulting in high operation and maintenance costs for ultra-large-scale clusters.

[0005] Existing mainstream computing power scheduling systems have multiple inherent defects. Currently, Kubernetes, Slurm, LSF, and various chip vendors' proprietary scheduling platforms all have inherent shortcomings in their underlying architecture: Hardware partitioning solutions are vendor-dependent: fine-grained logical partitioning is highly dependent on the original manufacturer's fixed virtualization capabilities (NVIDIA MIG), and there is no unified standardized partitioning method for domestic NPUs, FPGAs, and general-purpose ASICs. Static resource allocation leads to computing power fragmentation: the smallest scheduling unit is limited to the entire machine or a complete physical accelerator card; lightweight inference tasks occupy the entire card, resulting in idle computing power; and large model training tasks are constrained by resource fragmentation and cannot be flexibly expanded. Static partitioning presents a paradox of nonlinear loss: the industry generally mistakenly believes that the finer the partition granularity, the higher the computing power utilization. In reality, as the number of logical partitions N increases, the implicit losses caused by context switching, memory fragmentation, and bus bandwidth contention grow superlinearly (α>1). Existing technologies have not built a quantitative mapping model between the number of partitions and system overhead, and cannot predict the performance degradation caused by excessive partitioning. Parallel acceleration models are detached from real hardware wear and tear: Traditional scheduling only uses the ideal Amdahl acceleration formula and does not introduce multi-zone communication attenuation factors, resulting in a huge deviation between theoretical computing power and actual effective output; at the same time, it cannot distinguish between hardware baseline health margin and real-time degradation indicators, lacks a quantitative perception mechanism for the degree of physical aging of hardware, cannot make scheduling decisions based on real effective computing power (rather than nominal computing power), and cannot quantify the aging wear and tear caused by temperature, continuous high load, and hardware errors. The scheduling logic only achieves basic load balancing and lacks a value optimization model: Traditional scheduling takes instantaneous load balancing as the minimum goal, and only passively limits flow and avoids faults. It does not build a four-dimensional profit and loss evaluation model that integrates the benefits of parallel task operation, hardware life extension, and the dual losses of partitioning, and cannot solve for the globally optimal number of partitions.

[0006] Cross-domain distributed cluster centralized scheduling privacy and operational shortcomings With the large-scale implementation of the East-West Data Sharing Project, distributed computing clusters operating across regions and multiple entities have become the mainstream deployment model. Traditional centralized hierarchical scheduling architectures face two core problems when applied to cross-domain scenarios: First, in order to meet the needs of global scheduling and decision-making, the original business data and model operation data are forced to be uploaded to the central node, resulting in an irreconcilable contradiction between data privacy protection and global scheduling efficiency, and posing serious compliance and regulatory risks. Second, the underlying computing nodes lack local autonomous scheduling and decision-making capabilities, resulting in long fault response links and high layered operation and maintenance costs.

[0007] In summary, existing technologies face three irreconcilable contradictions in the field of heterogeneous computing power scheduling: 1. The disconnect between the adaptation layer and the application layer: The heterogeneity of the inference engine leads to hard-coded adaptation code, which cannot achieve seamless access and hot-swappability, and lacks the ability to deeply analyze AI tensor data; 2. The separation between the scheduling layer and the hardware layer: The scheduling strategy relies on nominal computing power and static partitioning, lacks quantitative perception of real-time physical losses of hardware (Ψ factor), and has not established a quantitative mapping model between partition granularity and system nonlinear losses, resulting in a tradeoff between computing power utilization and hardware lifespan. 3. The disconnect between centralized control and data privacy: Cross-domain scheduling relies on the centralized uploading of raw data, which raises data compliance risks. Furthermore, the lack of autonomy among lower-level nodes leads to delayed fault response and high maintenance costs.

[0008] Therefore, there is an urgent need for an integrated heterogeneous computing power operating system architecture that can be integrated down to the operating system kernel level, combining hardware wear and tear awareness, computing power asset measurement, and federated autonomous scheduling, in order to solve the above-mentioned technical bottlenecks. Summary of the Invention

[0009] Purpose of the invention To address the shortcomings of existing technologies, such as difficulties in adapting to heterogeneous multi-engine architectures, hardware partition vendor lock-in, inability to quantify computing power loss, scheduling limited to load balancing, and lack of compliance for cross-domain transactions, this invention provides a heterogeneous computing power operating system architecture based on hardware loss awareness, along with a method for assetizing computing power and storage media. This invention constructs a full-stack heterogeneous computing power operating system foundation covering kernel driver abstraction, unified computing power measurement, intelligent partition scheduling, tenant credit management, and compliant cross-domain asset transactions. It shields the underlying differences of various heterogeneous hardware through the kernel HAL hardware abstraction layer and uses the hardware health and loss factor Ψ to standardize the conversion of nominal computing power to effective computing power. It employs a pure software Zone logical partitioning and a three-level federated hierarchical scheduling architecture to improve resource utilization efficiency. Combined with DID digital identity, credit rating, and blockchain notarization, it achieves standardized, liquidable, and tradable asset-based operation of heterogeneous computing power.

[0010] Definition of key technical symbols To clearly define the technical parameters, the core measurement and evaluation symbols in this application are uniformly interpreted as follows: Ψ: Hardware health loss factor, with a value range of 0 < Ψ ≤ 1. It is calculated based on real-time hardware temperature, continuous load, hardware error frequency, and memory wear, and quantifies the computing power attenuation coefficient caused by hardware aging and overload. P ref : Baseline health value, a hardware health gain / loss factor under no-load conditions in the new hardware standard, and a unified benchmark for the conversion of computing power across the entire domain; CU raw Original measured computing power of hardware, the original computing power output value of hardware as specified by the manufacturer or collected in real time; CU: Standard computing power unit, a unified unit of measurement for computing power assets after Ψ normalization, serving as the sole measurement benchmark for kernel scheduling and asset transactions; (Equation 1) CU = CU raw × W / W ref N opt Optimal number of partitions: The optimal number of logical partitions per hardware unit, obtained by solving the PECP2.0 four-dimensional profit and loss model. PECP2.0 Four-Dimensional Transaction Profit and Loss Model: A quantitative evaluation model that integrates four dimensions: computing power delivery efficiency, hardware loss cost, cross-domain transmission overhead, and task fulfillment risk. Score (Zone) : Multidimensional matching degree scoring function for computing power partitioning; (Equation 2) Scores ( Zone ) = Σw i × F i (Zone) In the formula w i Preset weight coefficients for each matching dimension. F i (Zone) This is the evaluation function for the corresponding dimension's computing power partitioning; DID: A unique distributed digital identity identifier for tenants, distinguishing between the identities of computing power providers and demanders.

[0011] Technical solution First aspect: A heterogeneous computing power operating system based on hardware loss awareness.

[0012] The system is deployed on server hardware and is divided into a kernel-mode underlying runtime domain and a user-mode system service layer. The kernel-mode and system service layers complete isolated high-speed data interaction through a kernel ring buffer. The system contains five core units that work together in a layered manner to complete the entire business chain, including hardware access, loss perception, computing power metering, scheduling and allocation, tenant management, and cross-domain asset transactions. Hardware Abstraction and Driver Adaptation Unit. This unit includes a driver adaptation sublayer, a unified register mapping sublayer, and an instruction forwarding sublayer, constructing a kernel-level HAL layered adaptation framework. It interfaces with native drivers for various heterogeneous computing hardware such as GPUs, NPUs, and FPGAs, maintaining a global register mapping table that stores physical addresses, virtual addresses, and hardware access latency parameters. Based on this global register mapping table, it normalizes the register addresses and hardware access timings of various chip types, outputting a unified standardized register access interface. Through the HAL layer, it collects real-time full-scale hardware operating metrics, with core metrics including a hardware health and performance factor Ψ that characterizes hardware wear and tear. The driver adaptation sublayer encapsulates independent, dedicated driver adaptation plugins for different manufacturers' acceleration hardware. Each plugin supports dynamic loading, unloading, and replacement; adding or deleting plugins does not require restarting the main operating system kernel. The instruction forwarding sublayer translates standardized kernel operation instructions into corresponding hardware architecture-specific low-level instructions for hardware execution, simultaneously transmitting all raw low-level operating metrics collected from the hardware back to the computing power operating system kernel management layer. The system incorporates hardware circuit breaker management logic: pre-configuring a minimum hardware health threshold. P min When real-time monitoring Ψ<Ψ min At this point, the Hardware Abstraction and Driver Adaptation Unit stops issuing operation instructions to the hardware, and the kernel management layer simultaneously marks the hardware resource as unavailable; after hardware isolation, the Ψ value is continuously polled and collected until... Ψ ≥Ψ min Automatically release hardware isolation; after hardware triggers circuit breaker, the sub-scheduling module automatically migrates the tasks running on the hardware to other healthy computing nodes within the Zone, ensuring uninterrupted business operation.

[0013] Computing power normalization and metering unit. Interacts and connects with the hardware abstraction and driver adaptation unit, using the baseline health value corresponding to the standard reference hardware. P ref As a unified conversion benchmark across the entire domain, combined with the real-time hardware health and profit / loss factor Ψ, the original measured computing power of the hardware is calculated based on Equation 1. CU raw Cross-architecture conversion is performed to output a unified, standardized computing power unit (CU). The CU serves as the sole resource measurement benchmark for the kernel scheduling layer, tenant accounts, and asset transactions, achieving standardized asset quantification of heterogeneous computing power. The computing power normalization and metering unit incorporates built-in computing power recovery statistical logic: hardware failure or a persistently low Ψ value... P min When the threshold is reached, all allocated CU quotas for the hardware are reclaimed, and the total number of effective CUs in the cluster is recalculated and updated based on the real-time Ψ value of the remaining normal hardware in the cluster.

[0014] Resource partitioning and scheduling unit. A three-tiered federated scheduling architecture (nodes, clusters, and regions) is built based on a self-developed pure software Zone logical partitioning framework. Zone partitioning does not rely on the hardware virtualization capabilities of the original chip manufacturer and adapts to fine-grained resource allocation across all heterogeneous acceleration hardware. A PECP2.0 four-dimensional transaction profit and loss model is introduced to perform local computing power scheduling and cross-domain computing power sharing. Cross-network bandwidth, data transmission, and task migration losses are quantified and deducted from the nominal CU to calculate the deliverable effective computing power. The scheduling process prioritizes matching partitions with the optimal number of partitions. N opt The computing power is partitioned in the running state to avoid non-linear performance loss caused by excessive partitioning. When the local computing power inventory is insufficient, computing power borrowing requests are initiated at the cluster level and region level. The PECP2.0 four-dimensional transaction profit and loss model includes four quantitative evaluation dimensions: computing power delivery efficiency, hardware loss cost, cross-domain transmission overhead, and task fulfillment risk. The weighted sum of the four dimensions is used to calculate the fair transaction unit price of a single zone CU.

[0015] Multi-tenant Rights and Credit Management Unit. A unique DID digital identity is assigned to each tenant, and logical isolation of multi-tenant computing power, memory, and network resources is achieved through software Zones. A dedicated rights account is established to record nominal CUs, deliverable valid CUs, and tenant reputation scores. Deliverable valid CUs are dynamically updated in real-time according to Formula 1 based on the hardware Ψ value. Zone access verification and hardware circuit breaker isolation operations are dynamically executed based on the hardware health and loss factor Ψ, and tiered access control is implemented for tenants based on reputation scores. The system divides tenants into multiple credit levels based on their reputation scores, restricting high-specification computing power transactions and large-scale computing power scheduling permissions for low-credit-level tenants; during task execution, if the hardware Ψ falls below a certain threshold... P min Threshold-based dynamic circuit breaking is triggered, and the corresponding supplier tenant's credit score is simultaneously reduced, forcing the supplier to ensure the health of the hardware.

[0016] Cross-domain intelligent matching and compliance evidence storage unit. It receives computing power listing parameters published by suppliers and computing power order parameters submitted by demanders. Listing parameters must include at least the supplier's expected minimum price and local sales constraints. It executes a two-level verification process: the first level is a hard interception based on local compliance, directly removing computing power partitions that do not meet the demander's local control and data security legal and regulatory requirements from the matching queue; the second level is a weighted ranking based on matching degree, adjusting the weights of computing power partitions that pass compliance verification based on the supplier's configured local priority / cross-domain open mode, using Equation 2 multidimensional matching degree function. Score (Zone)The system completes the sorting of computing power zones across the entire domain, extracts the top K items to generate a Top-K candidate recommendation list for tenants to select from. The system presets four matching weight strategies: speed, cost, compliance, and green. When the difference in matching scores between any two or more zones is less than a preset judgment threshold, a secondary sorting is initiated, and the order of the candidate list is fine-tuned by combining comprehensive operating costs, estimated task latency, tenant reputation scores, and hardware carbon efficiency indicators. Computing power zones with bids lower than the supplier's expected bottom price are directly removed from the candidate matching set. The transaction matching execution logic is as follows: When K=1, the system automatically selects the top-scoring computing power resource and directly jumps to the smart contract process; when K is set to multiple preset values, multiple sets of computing power resource comparison lists are generated for the demand side to select; after the resource selection is completed, the smart contract is triggered to freeze the tenant's corresponding nominal CU quota; after the task is fully fulfilled, automatic revenue sharing and settlement are completed based on the hardware Ψ re-inspection record of the entire task cycle; a unique hash identifier is added to the entire process operation log, including CU measurement records, weight configuration parameters, candidate matching lists, resource selection instructions, and contract settlement records, and written to the consortium blockchain for permanent storage, ensuring that the transaction certificate is tamper-proof and fully traceable.

[0017] This system is based on a self-developed pure software Zone logical partitioning framework, a hardware health and loss quantification system, and a three-level federated hierarchical scheduling architecture, with kernel-level reconstruction and upgrades. Among them, the software Zone does not rely on the chip manufacturer's hardware virtualization capabilities and supports fine-grained resource allocation for any heterogeneous accelerator card. The hardware health and loss factor Ψ is used to quantify the non-linear computing power loss caused by temperature, load, and hardware errors. The three-level federated scheduling architecture is divided into a node local scheduling layer, a cluster collaborative scheduling layer, and a cross-regional borrowing scheduling layer to achieve hierarchical autonomous computing power allocation. The five major units form a hierarchical and progressive architecture between the underlying hardware scheduling base and the upper-level computing power asset trading module, with clear boundaries between the two layers of protected objects and no functional overlap.

[0018] This system is compatible with three computing power delivery scenarios: bare metal servers, KVM / QEMU virtualization, and Kubernetes containers. The standardized computing unit (CU) serves as a unified metering basis for resource quota allocation, scheduling, and management of virtual machine instances, Pod containers, and physical computing hardware. The hardware abstraction and driver adaptation unit, computing power normalization and metering unit, resource partitioning and scheduling unit, multi-tenant rights and credit management unit, and cross-domain intelligent matching and compliance evidence storage unit are initialized sequentially according to the architectural hierarchy during system startup. During system operation, cross-unit data interaction is achieved through shared memory and a kernel-mode circular buffer. Each unit only exposes standardized call interfaces for access and invocation by upper-layer modules and units at the same layer.

[0019] The system adds a visual operation and maintenance and audit interface unit, which interacts and connects with the five core units; it is used for the visual display of the total distribution of global computing power (CU), hardware loss distribution, zone partition operation status, and full log of computing power matching transactions. At the same time, it opens a standardized audit interface to regulatory agencies, supporting the export of complete and traceable computing power transaction certificates.

[0020] The second aspect: A method for realizing computing power assetization based on hardware loss awareness.

[0021] The application of any of the above-mentioned hardware loss-aware heterogeneous computing operating systems includes the following steps: Step 1: Hardware-level adaptation and hardware wear and tear indicator collection. A kernel-level HAL layered adaptation framework is built through the hardware abstraction and driver adaptation unit, connecting to the native driver interfaces of various heterogeneous computing hardware. A global register mapping table is used to complete the normalized mapping of multi-chip register addresses and access timing. The driver adaptation sublayer encapsulates dedicated driver adaptation plugins for GPUs and NPUs from different manufacturers and supports dynamic loading and unloading. The instruction forwarding sublayer converts standard kernel operation instructions into hardware-specific low-level instructions for execution, while simultaneously collecting the hardware health and wear factor Ψ, which characterizes the hardware wear and tear status, and transmitting all hardware indicators back to the kernel management layer.

[0022] Step 2: Hardware computing power normalization and conversion, standardizing computing power asset quantification. This is achieved by normalizing computing power and using measurement units to establish a baseline health value. P ref To unify the conversion benchmark, the real-time Ψ value and the original measured computing power of the hardware were combined. CU raw Based on Equation 1, cross-architecture computing power conversion is completed, generating standardized computing power units (CUs). The CU is used as the sole measurement standard for global computing power scheduling and asset quantification. When the hardware health profit and loss factor Ψ is lower than the preset value... P min When the threshold is reached, hardware circuit breaker isolation is triggered and the hardware resource is marked as unavailable. Isolation is lifted when the Ψ value recovers to above the threshold. If there is a hardware failure or Ψ remains below the threshold for an extended period, the isolation will be lifted. P min If the hardware is reclaimed, all allocated CU quotas will be recovered, and the total number of effective CUs in the cluster will be recalculated.

[0023] Step 3: Software Zone Partitioning and Three-Tier Federated Computing Power Scheduling. A three-tiered federated scheduling architecture (nodes, clusters, and regions) is built based on pure software Zone logical partitioning using resource partitioning and scheduling units. Local computing power scheduling and cross-domain computing power sharing are performed using the PECP2.0 four-dimensional transaction profit and loss model. Deducting cross-network, transmission, and task migration losses, the available effective computing power is calculated, and the optimal number of partitions is prioritized during the scheduling process. Nopt The computing power partitioning of the state.

[0024] Step 4: Multi-tenant Isolation and Credit-Based Hierarchical Management. Independent DID digital identities are assigned to tenants through a multi-tenant rights and credit management unit. Logical isolation of multi-tenant computing power, memory, and network resources is achieved through Zones. Tenant rights accounts, including nominal CUs, effective CUs, and reputation scores, are maintained. Zone access verification and hardware circuit breaker isolation are dynamically executed based on real-time hardware Ψ values. Hierarchical access control is implemented based on tenant reputation scores; multiple hardware circuit breakers will lower the supplier tenant's reputation score.

[0025] Step 5: Cross-Domain Intelligent Matching and Blockchain Compliance Evidence Storage. The cross-domain intelligent matching and compliance evidence storage unit receives supplier computing power listing parameters and demander computing power order parameters. First, it performs a local compliance pre-screening to eliminate computing power partitions that do not meet regional regulations or whose bids are lower than the supply floor price. For compliant computing power partitions, it performs Top-K intelligent matching and sorting based on a multi-dimensional matching degree function. After selecting computing power resources, it freezes the tenant's CU quota. Upon completion of the task, it automatically distributes revenue based on the full-cycle Ψ review record. It calculates a unique hash value for the entire process log of CU measurement, matching sorting, and contract settlement, and writes it to the consortium blockchain for permanent evidence storage.

[0026] Each step strictly follows the hierarchical order of the heterogeneous computing power operating system kernel state and system service layer architecture, realizing a closed-loop business process from hardware wear and tear perception to cross-domain computing power asset settlement. This method is adaptable to multiple computing power delivery scenarios: in KVM / QEMU virtualization scenarios, CU serves as virtual machine instance resource quota; in Kubernetes container scenarios, CU serves as Pod container resource quota; and in bare metal server scenarios, CU serves as the basis for physical hardware resource allocation and scheduling.

[0027] Third aspect: A computer-readable storage medium

[0028] The storage medium stores a computer program, which, when executed by a processor, implements the above-described method for realizing computing power assets based on hardware wear and tear awareness.

[0029] Beneficial effects Compared with existing technologies, this invention has six core technological advantages: Deep hardware abstraction in kernel mode completely shields heterogeneous hardware differences. A three-layer isolation mechanism is constructed, consisting of kernel HAL layered adaptation, unified register mapping, and standardized instruction translation. This completely hides the underlying hardware differences of GPUs, domestic NPUs, FPGAs, etc., at the kernel level. Upper-layer scheduling and transaction modules do not need to distinguish hardware models, achieving completely hardware-independent scheduling and solving the hardware binding defects of traditional scheduling vendors.

[0030] Computing power is standardized and measured based on actual hardware wear and tear, ensuring accurate and reliable measurement. A hardware health and loss factor Ψ is introduced into the computing power conversion, eliminating the problems of inflated computing power and measurement distortion caused by traditional scheduling relying on nominal hardware computing power. Computing power values ​​are corrected based on real-time hardware aging and load wear, and all scheduling and asset transaction activities are conducted based on real and effective computing power, significantly improving the overall utilization rate of cluster resources.

[0031] Pure software zone partitioning combined with the PECP2.0 four-dimensional profit and loss model achieves optimal global value. It enables fine-grained resource allocation without relying on the original hardware virtualization capabilities; and it uses the PECP2.0 model to solve for the optimal number of partitions N per hardware unit. opt The goal is to find a balance between improving resource utilization and avoiding nonlinear losses in partitions, thereby maximizing the overall effective net output of the cluster's computing power.

[0032] Standardized Computing Unit (CU) assets combined with blockchain notarization establish a trusted foundation for computing power circulation. Heterogeneous hardware computing power is uniformly quantified into standardized CU assets. This is combined with DID tenant identity, credit score grading, two-way supply and demand pricing, Top-K intelligent matching, and consortium blockchain notarization to construct a complete computing power bank trading system. Computing power can be accurately measured, freely matched across regions, and the entire transaction process is notarized and traceable, meeting the compliant cross-domain computing power trading needs of East Data West Computing.

[0033] Full-scenario adaptability and hardware circuit breaker self-healing support the long-term stable operation of large-scale clusters. The system is compatible with three mainstream computing power delivery forms: bare metal, virtualization, and containers; it is equipped with a hardware real-time circuit breaker, computing power quota recovery, and fault task migration self-healing mechanism based on the Ψ factor, which can identify the sub-health state of hardware in advance, reduce the probability of cluster failure and downtime, and adapt to the long-term stable operation of large-scale computing power clusters with tens of thousands of cards.

[0034] This invention forms a progressive and complete IP matrix with prior patents, clearly defining the levels of technological innovation. Building upon the applicant's existing patents on mid-level scheduling logic such as Zone partitioning, federated autonomous scheduling, and heterogeneous adaptation to multiple inference engines, this invention completes a heavy restructuring in the kernel state. It adds a kernel HAL hardware abstraction layer, real-time perception of underlying hardware losses, and a full-chain innovation for standardized computing power asset transactions across the entire CU domain. This forms a layered and progressive protection matrix encompassing the underlying kernel, mid-level scheduling, and upper-level asset transactions, highlighting distinct technical features and avoiding functional overlap or duplicate protection issues. Attached Figure Description

[0035] Figure 1 is a schematic diagram of the overall layered architecture of a heterogeneous computing power operating system architecture system based on hardware loss awareness according to the present invention. Figure 2 is a flowchart of the hardware health gain / loss factor Ψ collection and CU standardized computing power conversion in an embodiment of the present invention; Figure 3 is a schematic diagram of the resource partitioning, local scheduling and cross-domain computing power sharing logic based on the PECP2.0 four-dimensional profit and loss model in an embodiment of the present invention; Figure 4. Flowchart of cross-domain computing power matching and settlement based on PECP2.0 in an embodiment of the present invention; Figure 5 is a schematic diagram of the hierarchical management system architecture of multi-tenant DID identity, rights account, and credit score in an embodiment of the present invention. Detailed Implementation

[0036] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0037] Example 1: System Overall Layered Architecture and Initialization Process As shown in Figure 1, this invention is deployed on a hybrid computing cluster equipped with various heterogeneous hardware such as x86 CPUs, NVIDIA GPUs, and Ascend NPUs. After the system powers on, the kernel-mode hardware abstraction and driver adaptation unit is initialized first: the driver adaptation sublayer dynamically loads dedicated driver plugins adapted to NVIDIA and Ascend hardware, and the plugin loading process does not require restarting the operating system kernel; the register unified mapping sublayer constructs a globally unified register mapping table, converting the differentiated physical register addresses of different architecture hardware into a unified virtual address space of the system; the instruction forwarding sublayer completes the initialization of the kernel standard instruction and hardware low-level instruction mutual translation engine. After the kernel domain unit initialization is completed, the user-mode system service layer computing power normalization and metering unit, resource partitioning and scheduling unit, multi-tenant rights and credit management unit, cross-domain intelligent matching and compliance evidence storage unit, and visual operation and maintenance audit unit are started in sequence; each unit completes isolated data interaction through the kernel ring buffer and shared memory, and the units only interact through standardized interface calls. After the system completes full unit initialization, it initiates a periodic hardware indicator collection task, calculates the hardware health profit and loss factor Ψ corresponding to each hardware in real time, and enters the routine scheduling and computing power asset trading business process.

[0038] Example 2: Computing power normalization calculation and hardware circuit breaker recovery process As shown in Figure 2, the system collects real-time data on the underlying temperature, load, and hardware error of a single Ascend NPU, and comprehensively calculates the current hardware health gain / loss factor. Ψ=0.85 A unified benchmark health value across the entire region P ref =1.0 Real-time raw computing power of hardware CU raw =1000 The computing power is normalized and the measurement unit is substituted into Equation 1 to complete the conversion: CU = 1000 × 0.85 / 1.0 = 850 The effective computing power of this hardware standardization is 850 CU The cluster's global computing resource view is synchronously entered as a basis for scheduling and asset transaction measurement. A minimum threshold for hardware health is preset. P min =0.6 If the NPU operates under high load for an extended period, and Ψ continuously drops to 0.58, the hardware circuit breaker logic is triggered: the hardware abstraction unit stops issuing hardware operation commands, the kernel marks the hardware as unavailable, and all inference and training tasks on that hardware are automatically migrated to healthy computing nodes in the same zone; the system continuously polls and monitors the hardware Ψ value, and Ψ recovers to 0.82 (≥ 0.58) after the hardware is cooled down and maintained. Min The hardware isolation will be automatically lifted, and the device will be reintegrated into the cluster's computing resource pool. If a permanent hardware failure occurs and Ψ remains below a certain value for an extended period... Pmin Unable to recover, the system reclaims all 850 CU allocations for the affected hardware, iterates through the real-time Ψ and CU values ​​of the remaining normal hardware in the cluster, updates the total effective CU of the cluster globally, and synchronously updates the computing power distribution data on the operation and maintenance visualization interface. Simulation tests verify that when using traditional hardware partitioning and nominal computing power scheduling schemes, the overall effective computing power utilization rate of a heterogeneous cluster of the same size is 62%; while using the CU normalization metering based on Ψ factor awareness proposed in this application... N opt After implementing the optimal partitioning scheduling strategy, the overall effective computing power utilization rate of the cluster increased to 89.7%, and the early identification rate of hardware sub-health faults reached 92%.

[0039] Example 3: Software Zone Partitioning, PECP2.0 Scheduling, and Cross-Domain Computing Power Sharing As shown in Figure 3, when the cluster receives a large-scale model training request with high computing power, and the remaining effective CUs cannot meet the task's computing power requirements, the resource partitioning and scheduling unit initiates a computing power borrowing request to the next-level cluster scheduling layer. The system first determines the overall benefit of cross-domain borrowing: if the cross-domain transmission loss and data migration overhead are too high (determined to be low overall benefit), the system prioritizes entering the local waiting and repair process, continuously monitoring the hardware Ψ factor until local computing power is released; if the overall cross-domain benefit is positive, then it enters the PECP2.0 four-dimensional transaction benefit model.

[0040] The model comprehensively calculates the computing power delivery efficiency, hardware Ψ loss cost, cross-regional network transmission overhead, and task fulfillment risk for the target cross-domain computing power partition, and weights the calculation of the fair transaction cost per CU. During scheduling and execution, the system traverses all Zone partitions in the cluster, prioritizing the selection of partitions with a number equal to the target. N opt The system allocates tasks based on computing power partitions, avoiding the superlinear losses caused by excessive partitioning, such as memory fragmentation, bus contention, and context switching, thus maximizing global computing power output. Finally, the system completes scheduling based on the converted effective CUs and simultaneously updates the global computing power asset view.

[0041] Example 4: Flowchart of Cross-Domain Computing Power Matching and Settlement Based on PECP2.0 like Figure 4 As shown, the computing power matching and settlement process begins with the supplier posting listing information, setting the computing power partition identifier, nominal CU quota, expected reserve price, and local sales constraints (such as local preference). The demand side submits computing power orders, specifying task characteristics, a custom multi-dimensional weight vector (such as speed, cost, compliance, and green strategies), and the number of candidates K. After receiving the parameters, the system first executes a veto based on local compliance, directly eliminating computing power partitions that do not comply with regulations. Subsequently, the system constructs a multi-dimensional matching function: Scores ( Zone ) = Σw i × F i (Zone), The system iterates through all compliant computing power partitions and scores them. The system extracts the top K items to generate a Top-K candidate recommendation list: when K=1, the system automatically selects the computing power partition with the highest score and jumps to the smart contract process; when K>1, the system pushes the candidate list to the user interaction terminal, allowing tenants to "compare" before selecting the target resource.

[0042] Once resources are selected, the smart contract automatically freezes the nominal CU quota in the requester's account. Throughout the entire task execution lifecycle, the system continuously collects hardware health profit and loss factors Ψ. After task fulfillment, the system calculates the actual effective CU consumed based on the average Ψ over the entire cycle, driving the smart contract to complete automatic revenue sharing and settlement. Simultaneously, the system generates unique hash identifiers for order parameters, weight configurations, candidate lists, selected instructions, and settlement flow, writes them to the consortium blockchain for permanent storage, and provides standardized audit interfaces to meet the stringent regulatory requirements of financial and government computing power transactions.

[0043] Example 5: Multi-tenant DID Identity, Credit Rating and Dynamic Management As shown in Figure 5, the system assigns a unique DID digital identity to all supply and demand tenants, and establishes an independent rights account for each tenant. The account updates three core data types in real time: nominal CU, dynamic valid CU, and tenant credit score; the system has a built-in credit decay coefficient. α(t) The system calculates the tenant's current credit score in real time based on performance records and hardware failure records. S curr Complete credit rating and management.

[0044] Tenant A, as a computing power provider, had its GPUs repeatedly trigger hardware circuit breakers due to prolonged overload operation. As a result, the system automatically downgraded Tenant A's reputation score and real-time credit value. S curr When tenant A subsequently posted its computing power listing, due to its low credit rating, the system restricted its authority to post high-premium computing power orders and forcibly raised the minimum listing price.

[0045] Tenant B has consistently provided healthy computing resources, with its hardware Ψ remaining stable above 0.9, no circuit breaker failures, and the highest credit score. During system scheduling, high-priority large model training and inference tasks are prioritized for allocation to the computing power partitions under Tenant B's name. Tenant B's current credit score... S currIt will be included as a positive weighting dimension in the matching score function in Figure 4, and the credit rating will incentivize suppliers to continuously maintain the health of the hardware and improve the overall stability of the cluster computing power delivery.

[0046] Relationship with prior application This application, together with the applicant's five previously filed patent applications, constitutes the same computing power OS technology matrix. Each of the prior patents only covers a single module such as mid-level scheduling and middleware adaptation. The core innovation of this application lies in sinking the hardware loss perception capability down to the underlying HAL kernel of the operating system, adding a complete transaction link for the standardization of computing power assets across the entire CU domain, with clear layered protection boundaries and no duplicate technical solutions. The details are as follows: Application No. 2026109829535, "A Heterogeneous Computing Power Scheduling Method and System Based on Dynamic Logical Partitioning and Disposal Balance Algorithm," focuses only on the pure software Zone partitioning in the user-mode middle layer and the PECP2.0 four-dimensional disposal loss and gain optimization scheduling logic. On this basis, this application adds a kernel-mode HAL hardware abstraction adaptation layer, sinking the Ψ hardware loss perception down to the driver acquisition layer, and expanding the complete CU computing power asset metering and cross-domain matching transaction link.

[0047] Application No. 202610847053X, "A Heterogeneous Computing Power Dynamic Scheduling System for Multi-Model Inference," focuses on load balancing and fault-level self-healing mechanisms in multi-inference engine scenarios. This application integrates the scheduling logic into resource partitioning and scheduling units, while also expanding to bare metal, virtualization, and container full computing power delivery scenarios, and adding cross-domain computing power asset trading and blockchain evidence storage capabilities.

[0048] Application No. 2026108547067, "A Multi-AI Model Cooperative Scheduling System and Method Based on Federated Autonomy of Computing Power Clusters": Only a three-level federated hierarchical scheduling framework is built, and the borrowing and scheduling is performed based on the nominal computing power of the hardware; this application introduces Ψ loss conversion, and all federated borrowing and scheduling are carried out based on standardized effective CUs, and the measurement results truly reflect the actual output of the hardware.

[0049] Application No. 2026108119007, "A Heterogeneous Adaptation Access System and Method for Multiple Types of Artificial Intelligence Inference Engines", belongs to the application layer middleware inference engine adaptation scheme. This application kernelizes the heterogeneous adaptation logic and uniformly takes over the adaptation process of various hardware and inference engines through the underlying HAL, shielding the upper layer business perception.

[0050] Application No. 2026108101319, "An Artificial Intelligence Task Closed-Loop Scheduling System and Method Based on Multi-Level Linkage," only covers regional access and basic compliance closed-loop logic. This application reconstructs a local compliance veto hard interception mechanism in the cross-domain matching unit, and superimposes a complete transaction system of two-way supply and demand quotations, Top-K intelligent matching, and blockchain asset clearing.

[0051] Application No. 2026110465953, entitled "A Cross-Domain Heterogeneous Computing Power Trading System and Method Based on Trusted Management, Fair Measurement, and Intelligent Matching," focuses on upper-layer computing power asset trading scenarios, constructing a complete trading mechanism encompassing supplier listing, demand-side order matching, smart contract settlement, and blockchain auditing. However, this solution primarily relies on upper-layer business logic, failing to delve into the operating system kernel to build a hardware abstraction layer, and also neglecting computing power measurement based on real-time hardware wear perception. This application, building upon this trading system, further constructs a full-stack heterogeneous computing power operating system foundation covering kernel-level HAL, computing power normalization and measurement, and resource partitioning scheduling. It integrates cross-domain intelligent matching and compliant evidence storage as upper-layer capabilities of the operating system. Simultaneously, this application collects hardware health and loss factors Ψ in the kernel level and outputs standardized effective CUs, ensuring that transaction matching and contract settlement are based on effective computing power after real hardware wear perception, rather than nominal computing power. The two patents protect the market-side processes of computing power transactions in a hierarchical manner: the prior patent protects the overall architecture and operating system from the underlying hardware access to the upper-level asset transactions. The boundaries between the two are clear and there is no overlap in their technical solutions.

[0052] In summary, this application, together with the aforementioned six prior applications, constitutes a full-stack heterogeneous computing power operating system technology matrix covering the kernel driver layer, mid-level partition scheduling, and upper-level computing power asset transactions. Unlike the prior patents that focus on single-dimensional scheduling algorithms or adaptation middleware, the core contribution of this application lies in providing a full-stack solution at the operating system foundation level. Each patent has a clearly defined level of protected subject matter and a clear technological evolution path, collectively forming a multi-dimensional intellectual property protection system for computing power OS.

[0053] The specific embodiments of the present invention have been described in detail above with reference to the accompanying drawings. Those skilled in the art will understand that, without departing from the essential spirit of the present invention, equivalent substitutions or conventional optimizations can be made to the collection method of the hardware health gain / loss factor Ψ, the scheduling strategy of Zone partitioning, and the weighting dimension of the matching degree function. All modifications and variations made based on the core concept of the present invention fall within the protection scope of the claims of the present invention.

Claims

1. A heterogeneous computing power operating system based on hardware loss awareness, characterized in that, Deployed on server hardware, the system separates the kernel-mode underlying runtime domain from the user-mode system service layer. The kernel and system service layers rely on a kernel ring buffer for isolated data interaction. The system comprises five core, interconnected units: The Hardware Abstraction and Driver Adaptation Unit (HAL) comprises a driver adaptation sublayer, a register unified mapping sublayer, and an instruction forwarding sublayer. It is used to construct a kernel-mode HAL layered adaptation framework, interface with native driver interfaces of various heterogeneous computing hardware, maintain a global register mapping table storing physical addresses, virtual addresses, and hardware access latency parameters, and perform a normalized mapping of register addresses and hardware access timings for multiple chip types based on this global register mapping table to generate a unified and standardized register access interface. Furthermore, it collects low-level hardware operating metrics in real time through the HAL layer, and these operating metrics include at least a hardware health and loss factor Ψ used to characterize the hardware's wear and tear status. The computing power normalization and metering unit interacts and connects with the hardware abstraction and driver adaptation unit to use the benchmark health value corresponding to the standard reference hardware. Ψ ref As a unified conversion benchmark across the entire domain, combined with the real-time collected hardware health and loss factor Ψ, the original measured computing power of the hardware is evaluated. CU raw Perform cross-architecture conversion to output a unified and standardized computing unit (CU). The conversion calculation formula is as follows: CU = CU raw × Ψ / Ψ ref Furthermore, the CU is used as the sole resource measurement benchmark for the kernel scheduling layer, thereby achieving standardized asset quantification of heterogeneous computing power. The resource partitioning and scheduling unit is based on a three-level federated hierarchical scheduling architecture of nodes, clusters, and regions, built on pure software Zone logical partitioning. It introduces the PECP2.0 four-dimensional transaction profit and loss model to perform local computing power scheduling and cross-domain computing power sharing. It quantifies and deducts three types of losses—cross-network bandwidth, data transmission, and task migration—from the nominal CU to calculate the deliverable effective computing power. The scheduling process prioritizes matching the partitions with the optimal number of partitions. N opt Computing power partitioning in operation status; The multi-tenant rights and credit management unit assigns a unique DID digital identity to supply and demand tenants, and relies on the software Zone to complete the logical isolation of multi-tenant computing power, video memory and network resources; it establishes a dedicated rights account that records the nominal CU, effective CU and tenant credit score, and dynamically executes Zone access verification and hardware circuit breaker isolation operations based on the hardware health profit and loss factor Ψ, and implements hierarchical permission management for tenants based on credit score; The cross-domain intelligent matching and compliance evidence storage unit receives computing power listing parameters published by suppliers and computing power order parameters submitted by demanders. The listing parameters at least include the supplier's expected floor price and local sales constraints. It uses a multi-dimensional matching function: Scors (Zone) = Σw i × F i (Zone) The system performs matching and sorting of the compliant computing power partitions across the entire domain, extracts the top K items to generate a Top-K candidate recommendation list for tenants to select from; at the same time, it performs blockchain notarization on the entire process operation log, including CU metering records, weight configuration parameters, candidate matching lists, resource selection instructions, and contract settlement records. Each core unit shares a unified CU measurement benchmark and hardware loss characterization factor Ψ throughout the entire process, forming a complete closed-loop computing power operating system foundation from hardware bottom-level access, hardware loss perception computing power conversion, partitioned resource scheduling, tenant credit management, and cross-domain computing power asset transaction settlement.

2. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The driver adaptation sublayer encapsulates independent and dedicated driver adaptation plugins for GPUs and NPUs from different manufacturers. Each driver adaptation plugin supports dynamic loading and unloading, and plugin addition, replacement, and removal operations do not require restarting the main operating system kernel. The instruction forwarding sublayer translates standardized kernel operation instructions into corresponding hardware architecture-specific low-level instructions and sends them to the hardware for execution. At the same time, it sends all raw low-level operating indicators collected by the hardware back to the computing power operating system kernel management layer.

3. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The system has built-in hardware circuit breaker control logic: pre-configures minimum hardware health thresholds. Ψ min When the monitored hardware health gain / loss factor Ψ is less than Ψ min When this occurs, the hardware abstraction and driver adaptation unit stops issuing operation instructions to the corresponding hardware and simultaneously notifies the kernel management layer to mark the hardware as a resource unavailable state. After the hardware is marked as isolated, the value of Ψ is continuously polled and monitored until Ψ recovers to a value greater than or equal to 1. Ψ min The hardware isolation state is lifted at that time.

4. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The computing power normalization and metering unit is also configured with computing power recovery statistical logic: when hardware failure occurs or Ψ remains below 1 for an extended period... Ψ min When the threshold is reached, all allocated CU quotas for the hardware are reclaimed, and the total number of effective CUs in the cluster is recalculated and updated based on the real-time Ψ value of the remaining normal hardware in the cluster.

5. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, In the resource partitioning and scheduling unit, when there is a shortage of local computing power inventory, requests for computing power borrowing are initiated at the cluster level and the region level level. The PECP2.0 four-dimensional transaction profit and loss model includes four quantitative evaluation dimensions: computing power delivery efficiency, hardware loss cost, cross-domain transmission overhead, and task performance risk. The fair transaction price of a single Zone unit CU is calculated by weighted summation of the four dimensions.

6. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, In the multi-tenant rights and credit management unit, the deliverable valid CU follows a conversion formula. Effective CU = Nominal CU × (Ψ / Ψ ref ) Dynamically updated in real time; the system classifies tenants into multiple credit levels based on their credit scores, restricting high-specification computing power transactions and large-scale computing power scheduling permissions for tenants with low credit levels; hardware Ψ drops below a certain threshold during task execution. Ψ min When the threshold is reached, a dynamic circuit breaker is triggered, and the corresponding supplier tenant's credit score is simultaneously reduced.

7. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The cross-domain intelligent matching and compliance evidence storage unit has a built-in local compliance veto hard interception mechanism, which directly removes computing power partitions that do not meet the requirements of the demander's regional control and data security laws and regulations from the matching and sorting queue; the local sales constraint includes a local priority mode and a cross-domain open mode. When the supplier configures the local priority mode, the matching order of computing power partitions in the same region is prioritized during the sorting stage; the system presets four matching weight strategies: speed, cost, compliance, and green; when the difference between the matching scores of any two or more zones is less than the preset judgment threshold, a secondary sorting is initiated, and the order of the candidate list is fine-tuned by combining comprehensive operating costs, estimated task latency, tenant credit score, and hardware carbon efficiency indicators.

8. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, In the cross-domain intelligent matching and compliance evidence storage unit, when K=1, the system automatically selects the top-scoring computing power resource and directly jumps to the smart contract process; when K is set to multiple preset values, multiple sets of computing power resource comparison lists are generated for the demand party to select independently. Once the resources are selected, a smart contract is triggered to freeze the tenant's corresponding nominal CU quota; after the task is fully completed, automatic revenue sharing and settlement are completed based on the hardware Ψ re-inspection records throughout the task's lifecycle; the entire process operation log is written to the consortium blockchain with a unique hash identifier for permanent storage.

9. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The system reuses the Zone partitioning mechanism, Ω / Ψ hardware loss quantification system, and three-level federated scheduling architecture disclosed in the applicant's prior patent. The hardware abstraction and driver adaptation unit corresponds to the underlying hardware scheduling unit, the resource partitioning and scheduling unit corresponds to the three-level federated collaborative scheduling layer, and the computing power normalization and measurement unit and the cross-domain intelligent matching and compliant evidence storage unit correspond to the fair measurement and computing power asset trading layer, forming a hierarchical and progressive architecture of the underlying hardware scheduling base and the upper-level computing power asset trading module. Each unit operates in conjunction with the prior patent scheduling mechanism.

10. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The heterogeneous computing power operating system is adapted to three types of computing power delivery scenarios: bare metal servers, KVM / QEMU virtualization, and Kubernetes containers; the standardized computing power unit (CU) serves as a unified metering basis for resource quota allocation, scheduling and management of virtual machine instances, Pod containers, and physical computing power hardware.

11. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The hardware abstraction and driver adaptation unit, computing power normalization and metering unit, resource partitioning and scheduling unit, multi-tenant rights and credit management unit, and cross-domain intelligent matching and compliance evidence storage unit are initialized sequentially according to the architectural hierarchy during the system startup phase. During the system operation phase, cross-unit data interaction is achieved through shared memory and kernel-mode ring buffer. Each unit only exposes standardized call interfaces to the outside world for access and call by upper-layer modules and units at the same layer.

12. The heterogeneous computing power operating system based on hardware loss awareness according to claim 1, characterized in that, The system also adds a visual operation and maintenance and audit interface unit, which interacts and connects with the five core units; it is used for the visual display of the total global computing power (CU) distribution, hardware Ψ loss distribution, Zone partition operation status, and full log of computing power matching transactions. At the same time, it opens a standardized audit interface to regulatory agencies and supports the export of complete and traceable computing power transaction certificates.

13. A method for realizing computing power assetization based on hardware loss awareness, characterized in that, The system applied to the hardware loss-aware heterogeneous computing power operating system architecture system according to any one of claims 1 to 12 includes the following steps: Step 1: Build a kernel-mode HAL layered adaptation framework through the hardware abstraction and driver adaptation unit, connect to the native driver interface of various heterogeneous computing hardware, complete the normalization mapping of multi-chip register addresses and access timing based on the global register mapping table, and synchronously collect the hardware health loss factor Ψ, which represents the hardware wear and tear status, in real time. Step 2: Using computing power normalization and measurement units to establish a baseline health value Ψ ref To standardize the conversion benchmark, the original measured computing power of the hardware was analyzed in conjunction with real-time Ψ values. CU raw Perform cross-architecture conversion to generate standardized computing power units (CUs), and use CUs as the sole measurement standard for global computing power scheduling and asset quantification. Step 3: Based on pure software Zone logical partitioning, a three-level federated hierarchical scheduling architecture is built through resource partitioning and scheduling units. Local computing power scheduling and cross-domain computing power sharing are performed based on the PECP2.0 four-dimensional transaction profit and loss model. The available effective computing power is calculated after deducting various transmission and migration losses. Step 4: Assign independent DID digital identities to tenants through the multi-tenant rights and credit management unit, realize logical isolation of multi-tenant resources based on Zone, maintain tenant rights accounts including nominal CU, effective CU, and credit score, and dynamically execute Zone access verification, hardware circuit breaker isolation, and tenant credit rating management based on hardware Ψ value. Step 5: Receive the supplier's computing power listing parameters and the demand side's computing power order parameters through the cross-domain intelligent matching and compliance evidence storage unit, complete the Top-K intelligent matching and sorting of the entire computing power partition based on the multi-dimensional matching degree function, and perform blockchain evidence storage on the entire process log of CU measurement, matching and sorting, and contract settlement. Each step is executed in strict accordance with the hierarchical order of the heterogeneous computing power operating system kernel state and system service layer architecture, realizing a closed-loop end-to-end system from hardware loss perception to computing power asset transactions.

14. The method for realizing computing power assetization based on hardware loss awareness according to claim 13, characterized in that, The specific process of collecting hardware health gain / loss factors Ψ and hardware register normalization mapping in step 1 includes: the driver adaptation sublayer encapsulates dedicated driver adaptation plugins for GPUs and NPUs from different manufacturers and supports dynamic loading and unloading; the instruction forwarding sublayer converts standard kernel operation instructions into hardware-specific low-level instructions for execution, while simultaneously sending all original hardware operating indicators back to the operating system kernel management layer.

15. The method for realizing computing power assetization based on hardware loss awareness according to claim 13, characterized in that, The second step of the computing power normalization process also includes: when the hardware health loss factor Ψ is lower than the preset value. Ψ min When the threshold is reached, hardware circuit breaker isolation is triggered and the hardware resource is marked as unavailable. Isolation is lifted when the Ψ value recovers to above the threshold. If there is a hardware failure or Ψ remains below the threshold for an extended period, hardware circuit breaker isolation will be triggered. Ψ min If so, all allocated CU quotas for the hardware will be reclaimed, and the total number of effective CUs in the cluster will be recalculated.

16. The method for realizing computing power assetization based on hardware loss awareness according to claim 13, characterized in that, In step 5, during the Top-K intelligent matching and sorting process, it is verified whether the demand side's quotation is lower than the expected minimum price filled in by the supplier. The computing power partition with a quotation lower than the minimum price is directly removed from the candidate matching set. At the same time, the computing power partition that does not meet the regional requirements is filtered in combination with the local sales constraints configured by the supplier.

17. The method for realizing computing power assetization based on hardware loss awareness according to claim 13, characterized in that, The method is adaptable to various computing power delivery scenarios: in KVM / QEMU virtualization scenarios, CU serves as virtual machine instance resource quotas; in Kubernetes container scenarios, CU serves as Pod container resource quotas; and in bare metal server scenarios, CU serves as the basis for physical hardware resource allocation and scheduling.

18. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the computing power assetization method based on hardware loss awareness as described in any one of claims 13 to 17.

19. A computer program product, characterized in that, The computer program product stores a computer program, which, when executed by a processor, implements the computing power assetization method based on hardware loss awareness as described in any one of claims 13 to 17.

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