Risc-v chip tcm compatibility detection method and device, and electronic equipment

Abstract

The application provides a compatibility detection method for a TCM of a RISC-V chip, and belongs to the technical field of RISC-V chip verification. The method comprises the following steps: configuring a physical address range of a tightly coupled memory (TCM) of a RISC-V chip as a target memory attribute to be verified; enabling the TCM; writing a test function into an address space of the TCM; jumping a program counter of a processor in the RISC-V chip to the address space of the TCM, and executing the test function in the address space by the processor; if the processor successfully executes all instructions of the test function and returns a success flag, it is confirmed that the target memory attribute is compatible with the TCM; if the processor triggers an exception event, an exception register corresponding to the RISC-V chip is read; if the exception register indicates that the exception event is a fetch instruction type exception, and a fault address recorded by the exception register belongs to an address region corresponding to the TCM, it is determined that the target memory attribute is incompatible with the TCM. The implementation difference between hardware and specification documents can be quickly identified.

Description

Technical Field

[0001] This application relates to the field of RISC-V chip verification technology, and more particularly to a compatibility testing method for a RISC-V chip TCM. Background Technology

[0002] The RISC-V architecture offers memory attributes such as cacheable, non-cacheable, and device. Tightly Coupled Memory (TCM) is a high-speed on-chip storage commonly used for running real-time critical code. Some chip documentation states that TCM can be configured as device or non-cacheable, but in actual hardware, discrepancies arise between the documentation and the implementation: when TCM is configured as device and attempts to fetch instructions, a fetch exception occurs. This exception is recorded in the machine cause register (mcause) and the machine trap value register (mtval), potentially leading to program crashes and impacting system reliability.

[0003] Existing memory attribute verification methods mostly employ data read / write tests, which only verify data access and cannot detect hidden defects in instruction fetching and execution. A few exception capture verification solutions are designed for general-purpose memory, are not adapted to TCM, and do not utilize RISC-V-specific mcause and mtval to locate faults; manual JTAG debugging relies on external tools and has a low degree of automation.

[0004] The existing location-independent code loading technology is used for dynamic library business module updates. It is a software business solution, does not perform hardware compatibility testing, does not configure multiple memory attributes for TCM, and does not use pointer fetch exceptions as a criterion for judgment, thus failing to solve the aforementioned problems.

[0005] Therefore, there is currently a lack of automated testing schemes for RISC-V chip TCM to verify instruction execution capabilities under different memory attributes, making it difficult to quickly identify implementation differences between hardware and specification documents. Summary of the Invention

[0006] This application provides a method, apparatus, and electronic device for compatibility testing of RISC-V chip TCM, which can automatically detect instruction execution capabilities under different memory attributes and quickly identify implementation differences between hardware and specification documents.

[0007] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a compatibility testing method for a RISC-V chip TCM, the method comprising: Configure the physical address range of the tightly coupled memory (TCM) of the RISC-V chip as the target memory attribute to be verified; Enable the TCM so that the address region corresponding to the TCM can be read and written normally. Write the test function into the address space of the TCM; The program counter of the processor in the RISC-V chip jumps to the address space of the TCM, and the processor executes the test function in the address space; If the processor successfully executes all instructions of the test function and returns a success flag, then the target memory attribute is confirmed to be compatible with the TCM. If the processor triggers an abnormal event, the abnormal register corresponding to the RISC-V chip is read. If the exception register indicates that the exception event is a fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then it is determined that the target memory attribute is incompatible with the TCM.

[0008] In some embodiments, the target memory attribute includes at least one of the following: device attributes and non-cached attributes.

[0009] In some embodiments, the method further includes: confirming whether a fetch exception has occurred by checking the value of the mcause register; The fault address is obtained by reading the mtval register; it is then determined whether the fault address belongs to the address region corresponding to the TCM.

[0010] In some embodiments, the return success flag includes: determining whether the first register is set to a first value; If the first register is set to the first value, then a success flag is returned.

[0011] In some embodiments, the processor executing the test function within the address space includes: The processor executes the test function by calling registers and the internal resources of the TCM.

[0012] In some embodiments, the test function is generated using a position-independent compilation method; the test function is deployed to any starting address of the TCM and runs normally.

[0013] Secondly, embodiments of this application provide a compatibility testing device for a RISC-V chip TCM, the device comprising: The configuration module is used to configure the physical address range of the TCM of the RISC-V chip to the target memory attribute to be verified. The enable module is used to enable the TCM so that the address area corresponding to the TCM can be read and written normally. The write module is used to write the test function into the address space of the TCM; The processing module is used to jump the program counter of the processor in the RISC-V chip to the address space of the TCM, and the processor executes the test function in the address space; The confirmation module is used to confirm that the target memory attribute is compatible with the TCM if the processor successfully executes all the instructions of the test function and returns a success flag; If the processor triggers an abnormal event, the abnormal register corresponding to the RISC-V chip is read. If the exception register indicates that the exception event is a fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then it is determined that the target memory attribute is incompatible with the TCM.

[0014] In some embodiments, the target memory attribute includes at least one of the following: device attributes and non-cached attributes.

[0015] In some embodiments, the processing module is further configured to confirm whether an instruction fetch exception has occurred by checking the value of the mcause register; The fault address is obtained by reading the mtval register; it is then determined whether the fault address belongs to the address region corresponding to the TCM.

[0016] In some embodiments, the confirmation module is specifically used to determine whether the first register is set to a first value; If the first register is set to the first value, then a success flag is returned.

[0017] In some embodiments, the processing module is specifically configured to execute the test function by calling registers and the internal resources of the TCM.

[0018] In some embodiments, the test function is generated using a position-independent compilation method; the test function is deployed to any starting address of the TCM and runs normally.

[0019] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising: a processor and a memory communicatively connected to the processor; wherein... The processor memory stores instructions that can be executed by the processor, which are then executed by the processor to enable the processor to perform the aforementioned RISC-V chip TCM compatibility detection method.

[0020] Fourthly, embodiments of this application provide a computer-readable storage medium storing executable instructions for implementing the above-described RISC-V chip TCM compatibility detection method when executed by a processor.

[0021] Fifthly, embodiments of this application provide a computer program product, which includes a computer program / instruction. When the computer program / instruction is processed and executed, it implements the above-described compatibility detection method for the RISC-V chip TCM.

[0022] The compatibility detection method for a RISC-V chip TCM provided in this application includes: configuring the physical address range of the tightly coupled memory (TCM) of the RISC-V chip as the target memory attribute to be verified; enabling the TCM so that the address region corresponding to the TCM can be read and written normally; writing a test function into the address space of the TCM; jumping the program counter of the processor in the RISC-V chip to the address space of the TCM, and executing the test function in the address space; if the processor successfully executes all instructions of the test function and returns a success flag, then the target memory attribute is confirmed to be compatible with the TCM; if the processor triggers an exception event, then reading the exception register corresponding to the RISC-V chip; if the exception register indicates that the exception event is an instruction fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then the target memory attribute is determined to be incompatible with the TCM. This application embodiment writes the test function into the TCM with the target memory attributes configured and actually jumps to execute it, and combines the RISC-V exception register to identify the instruction fetch exception generated by the TCM address. Unlike traditional tests that only perform data read and write, it can truly verify the instruction execution capability of the TCM under the corresponding memory attributes, and effectively identify hidden defects where the hardware implementation is inconsistent with the chip documentation. The detection process is automatically completed on the chip without the need for external debugging tools. At the same time, through dual verification of exception type and fault address, false judgments are reduced, and the detection results are objective and reliable. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the processing flow of the RISC-V chip TCM compatibility detection method provided in the embodiments of this application; Figure 2 This is a schematic diagram of the composition structure of the RISC-V chip TCM compatibility detection device provided in the embodiments of this application; Figure 3 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0028] The scientific terms used in the embodiments of this application are explained below.

[0029] 1) RISC-V: An open-source reduced instruction set architecture widely used in embedded processor chips, allowing for flexible configuration of memory and storage subsystem hardware.

[0030] 2) Memory Attributes: In the RISC-V architecture, these are access characteristic identifiers defined for physical memory regions. They specify the caching and memory access order rules when the CPU accesses this address segment, and mainly include the following three categories: Cacheable: Allows the CPU to cache data in this memory area using a high-speed cache, improving access speed. It is generally used for ordinary programs and data memory. Non-cacheable: The CPU is prohibited from using the cache, and each access directly accesses the underlying physical storage; Device type: Memory attribute designed for peripheral registers. Memory access is strictly executed in program order and caching is not allowed. It is generally used for peripherals. Some chip documents claim that it can be configured for use by TCM.

[0031] 3) Tightly Coupled Memory (TCM): The chip has built-in high-speed on-chip SRAM memory, which is divided into instruction tightly coupled memory (ITCM) and data tightly coupled memory (DTCM). It does not go through a cache, has a fixed access latency, and is used to store interrupt and real-time critical code.

[0032] 4) Machine cause (mcause): RISC-V architecture privileged status control status register (CSR); when an exception occurs in the processor, this register records the specific type code of the exception, such as instruction fetch access failure, illegal instruction, etc.

[0033] 5) Machine Trap Value (mtval): RISC-V architecture privileged status control status register; when a memory access exception occurs, it saves the faulty memory address that triggered the exception, which is used to locate the erroneous access address.

[0034] 6) Instruction Fetch Anomaly: An anomaly in which a hardware error occurs when the CPU is reading instructions from a certain memory address; in this invention, it specifically refers to the CPU's inability to read instructions normally from the TCM address, causing the program to be unable to continue running.

[0035] 7) JTAG debugging: A chip hardware debugging interface that connects to the chip via an external debugger, allowing you to read and write registers and observe the CPU's operating status; however, it requires external hardware tools and cannot achieve automated testing on the board.

[0036] Position-independent code: A type of program code generated during compilation that does not use absolute memory address addressing, but only relies on relative offset addressing; the code image can be copied to any starting address in memory and run directly without relocation processing.

[0037] It should be understood that in the various embodiments of this application, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0038] A schematic diagram of the processing flow of the RISC-V chip TCM compatibility detection method provided in this application embodiment is shown below. Figure 1 As shown, it includes at least: Step S101: Configure the physical address range of the TCM of the RISC-V chip to the target memory attribute to be verified.

[0039] In some embodiments, the target memory attribute can be a device attribute or a non-cached attribute. Configuring the physical address range of the RISC-V chip's TCM as the target memory attribute to be verified can also be referred to as test environment initialization.

[0040] Step S102: Enable the TCM so that the address region corresponding to the TCM can be read and written normally.

[0041] Step S103: Write the test function into the address space of the TCM.

[0042] In some embodiments, the test function code is small, with its binary image size less than or equal to the TCM's address space, ensuring it can be fully contained. The test function is self-verifying; its body contains a clear sequence of operations (e.g., performing write and read-back verification on a specific register, or performing a simple arithmetic operation and storing the result), and concludes with a unique return instruction sequence (such as a specific immediate return) or jump instruction to indicate successful execution. The test function is generated using a position-independent compilation method, without using any absolute addressing, ensuring correct execution regardless of the starting address of the TCM. The test function exhibits strong isolation; it does not depend on external memory or complex peripherals, only calling registers and the TCM's internal resources to avoid introducing additional interference variables.

[0043] In some embodiments, the processor copies the binary code of the test function to the starting address of the TCM's address space via a memory write operation.

[0044] Step S104: The program counter of the processor in the RISC-V chip is switched to the address space of the TCM, and the processor executes the test function in the address space.

[0045] In some embodiments, the program counter is jumped to the starting address of the TCM's address space based on a processor jump instruction, so that the processor executes the test function in the address space.

[0046] In some embodiments, the main program running on the processor is stored in memory, such as SRAM or DDR.

[0047] Step S105: If the processor successfully executes all instructions of the test function and returns a success flag, then the target memory attribute is confirmed to be compatible with the TCM.

[0048] In some embodiments, returning a success flag includes: determining whether a first register is set to a first value; if the first register is set to the first value, then confirming the return of a success flag. Here, the first register is a pre-defined register, which can be an existing register or a newly added register. The first value is a preset value, such as 0 or 1, used to indicate successful execution.

[0049] In other embodiments, the success flag may also be the processor returning to the main control program. That is, the processor returning to the main control program indicates successful execution.

[0050] In some embodiments, the compatibility of the target memory attribute with the TCM means that the current target memory attribute supports TCM execution instructions.

[0051] Step S106: If the processor triggers an abnormal event, the abnormal register corresponding to the RISC-V chip is read.

[0052] In some embodiments, if the processor in the RISC-V chip jumps to the address space of the TCM and then triggers an exception event, the exception register corresponding to the RISC-V chip is read. The exception event can be one or more of the following: instruction fetch failure, illegal instruction, and access error exception.

[0053] In some embodiments, the exception register may be one or more of mcause and mtval in the RISC-V chip.

[0054] Step S107: If the exception register indicates that the exception event is a fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then it is determined that the target memory attribute is incompatible with the TCM.

[0055] In some embodiments, if the fault address recorded in the exception register belongs to the address region corresponding to the TCM, then it is confirmed that the cause of the exception event is related to the attempt to fetch an instruction from the TCM address, and it is determined that the target memory attribute is incompatible with the TCM.

[0056] The incompatibility between the target memory attribute and the TCM means that the current target memory attribute does not support the TCM execution instructions.

[0057] In some embodiments, steps S101-S107 can be executed cyclically to configure multiple different target memory attributes in sequence, and TCM instruction execution compatibility results corresponding to each memory attribute can be obtained. For different memory attributes, corresponding TCM instruction execution compatibility test reports are generated, which can provide empirical evidence for the chip's software development manual or directly expose inconsistencies between hardware design and attribute configuration specifications.

[0058] It should be noted that the foregoing embodiments of this invention use TCM as the storage region under test, but this invention is not limited to TCM. Those skilled in the art should understand that the core detection process of this method can be applied to other memories or address windows that support memory attribute configuration under the RISC-V architecture, such as on-chip shared SRAM, DDR specified address segments, and peripheral mapped storage windows. Simply replace the object under test with the corresponding target storage address range, execute "configure target memory attributes, write test functions, jump to the target address to execute the test function, and determine whether an instruction fetch exception corresponding to the target address occurs based on the exception register," and the instruction execution compatibility test under different memory attributes of the storage region can be completed. Therefore, this invention has good versatility and is not limited to the single hardware module TCM.

[0059] Application Scenario Example 1 The chip shares on-chip SRAM and kernel local high-speed RAM, which also support PMA (Physical Memory Attribute) configuration. The chip manual may claim that it supports code execution under the device / non-cacheable attribute, but the actual hardware has defects.

[0060] In this scenario, the test object in the RISC-V chip TCM compatibility testing method provided in this application embodiment can be replaced from TCM to on-chip SRAM; the remaining steps—configuring memory attributes, writing test functions, jumping to execution, and reading mcause / mtval to determine instruction fetch anomalies—remain completely unchanged and are used to verify whether instructions can be executed under different memory attributes of on-chip ordinary high-speed SRAM.

[0061] Application Scenario Example 2 Some RISC-V SoCs map the address windows of certain peripherals into the CPU address space, and some hardware designs want to execute code within this window. The address window is configured with the `device` or `non-cacheable` attribute; the datasheet states that instructions can be executed, but hardware instruction fetching will result in an error.

[0062] In this scenario, the tested object in the RISC-V chip TCM compatibility testing method provided in this application embodiment can be replaced with the peripheral mapping address window; the rest of the testing logic remains unchanged.

[0063] The RISC-V chip TCM compatibility testing method provided in this application has the following technical effects: First, this application provides real-world hardware verification of TCM memory attribute-instruction execution compatibility. It goes beyond traditional data read / write verification, allowing the processor to actually fetch instructions from the TCM address space configured with the memory attributes to be verified and execute test functions. This directly exposes hidden defects where "chip specifications claim TCM supports a certain type of memory attribute, but the hardware cannot actually execute instructions under that attribute." It identifies inconsistencies between documentation descriptions and hardware implementations, providing real-world hardware behavior evidence for chip firmware development and chip manual revisions, thus preventing system crashes from being exposed only during subsequent software development phases.

[0064] Second, by using the processor's own hardware behavior and exception registers as objective criteria, the detection results are accurate and reliable. When an exception occurs, the RISC-V architecture exception registers are used to distinguish the exception type and locate the fault address. Only when it is confirmed that the exception is a fetch-type exception triggered by the TCM address is the memory attribute incompatibility determined. This can filter out irrelevant interference exceptions such as data access exceptions and peripheral failures, avoid misjudgments, and improve the reliability of compatibility judgment results.

[0065] Third, it enables automated on-board testing, eliminating reliance on external debugging tools. The entire testing process is completed within the RISC-V chip, without the need for manual intervention using a JTAG debugger to observe the CPU's operating status. Verification can be completed without an external emulator, making it suitable for both the FPGA prototyping stage before chip fabrication and for chip evaluation and firmware integration testing after fabrication, improving verification efficiency and reducing limitations imposed by testing environment conditions.

[0066] Fourth, the detection logic is simple and can adapt to iterative testing of multiple sets of memory attributes. This solution fully covers the entire process of attribute configuration, code deployment, jump execution, and abnormal or normal branch judgment. It can directly output a binary judgment result of "compatible or incompatible", which facilitates subsequent looping through multiple memory attributes to be verified, batch completion of compatibility screening of various memory attributes of TCM, and rapid acquisition of complete compatibility assessment conclusions.

[0067] A schematic diagram of the RISC-V chip TCM compatibility testing device provided in this application embodiment is shown below. Figure 2 As shown, the compatibility testing device for the RISC-V chip TCM includes: Configuration module 201 is used to configure the physical address range of the TCM of the RISC-V chip as the target memory attribute to be verified. Enable module 202 is used to enable the TCM so that the address area corresponding to the TCM can be read and written normally; The writing module 203 is used to write the test function into the address space of the TCM; Processing module 204 is used to jump the program counter of the processor in the RISC-V chip to the address space of the TCM, and the processor executes the test function in the address space; The confirmation module 205 is used to confirm that the target memory attribute is compatible with the TCM if the processor successfully executes all the instructions of the test function and returns a success flag; If the processor triggers an abnormal event, the abnormal register corresponding to the RISC-V chip is read. If the exception register indicates that the exception event is a fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then it is determined that the target memory attribute is incompatible with the TCM.

[0068] In some embodiments, the target memory attribute includes at least one of the following: device attributes and non-cached attributes.

[0069] In some embodiments, the processing module 204 is further configured to confirm whether an instruction fetch exception has occurred by checking the value of the mcause register; The fault address is obtained by reading the mtval register; it is then determined whether the fault address belongs to the address region corresponding to the TCM.

[0070] In some embodiments, the confirmation module 205 is specifically used to determine whether the first register is set to a first value; If the first register is set to the first value, then a success flag is returned.

[0071] In some embodiments, the processing module 204 is specifically used to execute the test function by calling registers and the internal resources of the TCM.

[0072] In some embodiments, the test function is generated using a position-independent compilation method; the test function is deployed to any starting address of the TCM and runs normally.

[0073] This application provides an electronic device, and a schematic diagram of the structure of the electronic device is shown below. Figure 3 As shown, the device includes a processor 410 and a memory 450 communicatively connected to the processor 410. The electronic device also includes a bus 440; various modules of the electronic device are coupled together via the bus 440. Multiple processors may be included. It is understood that the bus 440 is used to implement communication between these modules. In addition to a data bus, the bus 440 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 3 The general labeled all buses as Bus 440.

[0074] The processor 410 has signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware models, etc., wherein the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0075] The memory 450 stores executable instructions for implementing the error handling method of the NAND FLASH controller provided in the embodiments of this application; the memory 450 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. The memory 450 may optionally include one or more storage devices physically located away from the processor core 410.

[0076] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof.

[0077] In some embodiments, the electronic device may further include: Operating system 451 includes system programs for handling various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., for implementing various basic business functions and handling hardware-based tasks; The network communication module 452 is used to reach other computing devices via one or more (wired or wireless) network interfaces 420, exemplary network interfaces 420 including Bluetooth, WiFi, and Universal Serial Bus (USB).

[0078] This application provides a computer-readable storage medium storing executable instructions. When these executable instructions are executed by a processor, they trigger the processor to execute the RISC-V chip TCM compatibility detection method provided in this application. For example... Figure 1 The compatibility test of the RISC-V chip TCM is shown.

[0079] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disc, or CD-ROM, etc.; or it may be a device that includes one or any combination of the above-mentioned memories.

[0080] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, model, subroutine, or other unit suitable for use in a computing environment.

[0081] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0082] This application provides a computer program product, which includes a computer program / instruction. When the computer program / instruction is executed by a processor, it implements the compatibility detection method for the RISC-V chip TCM described in this application.

[0083] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A compatibility testing method for a RISC-V chip TCM, characterized in that, The method includes: Configure the physical address range of the tightly coupled memory (TCM) of the RISC-V chip as the target memory attribute to be verified; Enable the TCM so that the address region corresponding to the TCM can be read and written normally. Write the test function into the address space of the TCM; The program counter of the processor in the RISC-V chip jumps to the address space of the TCM, and the processor executes the test function in the address space; If the processor successfully executes all instructions of the test function and returns a success flag, then the target memory attribute is confirmed to be compatible with the TCM. If the processor triggers an abnormal event, the abnormal register corresponding to the RISC-V chip is read. If the exception register indicates that the exception event is a fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then it is determined that the target memory attribute is incompatible with the TCM.

2. The compatibility testing method for the RISC-V chip TCM according to claim 1, characterized in that, The target memory attribute includes at least one of the following: Device properties and non-cached properties.

3. The compatibility testing method for the RISC-V chip TCM according to claim 1, characterized in that, The method further includes: Check the value of the mcause register to determine if a fetch exception has occurred; The fault address is obtained by reading the mtval register; it is then determined whether the fault address belongs to the address region corresponding to the TCM.

4. The compatibility testing method for the RISC-V chip TCM according to claim 1, characterized in that, The success flag includes: Determine if the first register is set to the first value; If the first register is set to the first value, then a success flag is returned.

5. The compatibility testing method for the RISC-V chip TCM according to claim 1, characterized in that, The processor executes the test function within the address space including: The processor executes the test function by calling registers and the internal resources of the TCM.

6. The method according to any one of claims 1 to 5, characterized in that, The test function is generated using a position-independent compilation method; the test function is deployed to any starting address of the TCM and runs normally.

7. A compatibility testing device for a RISC-V chip TCM, characterized in that, The device includes: The configuration module is used to configure the physical address range of the tightly coupled memory (TCM) of the RISC-V chip to the target memory attribute to be verified. The enable module is used to enable the TCM so that the address area corresponding to the TCM can be read and written normally. The write module is used to write the test function into the address space of the TCM; The processing module is used to jump the program counter of the processor in the RISC-V chip to the address space of the TCM, and the processor executes the test function in the address space; The confirmation module is used to confirm that the target memory attribute is compatible with the TCM if the processor successfully executes all the instructions of the test function and returns a success flag; If the processor triggers an abnormal event, the abnormal register corresponding to the RISC-V chip is read. If the exception register indicates that the exception event is a fetch exception and the fault address recorded by the exception register belongs to the address region corresponding to the TCM, then it is determined that the target memory attribute is incompatible with the TCM.

8. The apparatus according to claim 7, characterized in that, The target memory attribute includes at least one of the following: Device properties and non-cached properties.

9. The apparatus according to claim 7, characterized in that, The processing module is also used to confirm whether an instruction fetch exception has occurred by checking the value of the mcause register; The fault address is obtained by reading the mtval register; it is then determined whether the fault address belongs to the address region corresponding to the TCM.

10. The apparatus according to claim 7, characterized in that, The confirmation module is specifically used to determine whether the first register is set to the first value; If the first register is set to the first value, then a success flag is returned.

11. The apparatus according to claim 7, characterized in that, The processing module is specifically used to execute the test function by calling registers and the internal resources of the TCM.

12. The apparatus according to claim 7, characterized in that, The test function is generated using a position-independent compilation method; the test function is deployed to any starting address of the TCM and runs normally.

13. An electronic device, characterized in that, The electronic device includes: A processor and a memory communicatively connected to the processor; wherein, The processor memory stores instructions that can be executed by the processor, which are executed by the processor to enable the processor to perform the compatibility testing method for the RISC-V chip TCM according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that, It stores executable instructions for use by a processor to implement the RISC-V chip TCM compatibility detection method according to any one of claims 1 to 6.

15. A computer program product, characterized in that, The computer program product includes a computer program / instruction that, when executed by a processor, implements the compatibility detection method for the RISC-V chip TCM as described in any one of claims 1 to 6.

Images