Memory command line reference voltage determination method, apparatus, device, medium, and program product
Patent Information
- Application Number
- CN202611074225.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-20
- Publication Date
- 2026-11-03
AI Technical Summary
In existing DDR systems, there are technical issues with the reference voltage of multiple command lines. Existing technologies cannot effectively solve the problem that the two-dimensional eye diagram is easily skewed by some command lines when multiple command lines share a single reference voltage, which leads to system instability.
By obtaining the delay margins corresponding to each training code pattern under the reference voltage of each command line, the fluctuation of the delay margins is determined, and the reference voltage corresponding to the minimum variance is selected as the target reference voltage. This avoids the eye diagram being affected by certain special command lines and selects a reference voltage that is more suitable for all command lines.
This ensures the stability of the DDR subsystem command lines, avoids system instability caused by multiple command lines sharing a single reference voltage, and improves system stability.
Smart Images
Figure CN123030530A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a method, apparatus, device, medium, and program product for determining a memory command line reference voltage. Background Technology
[0002] The evolution of the DDR (Double Data Rate Synchronous Dynamic Random Access Memory, a core memory peripheral of the processor) protocol, from 800MT / s in DDR2 to 6400MT / s in DDR5, has seen a continuous increase in DDR clock frequency. The DDR subsystem has also added training modules for the chip select (CS) / command control lines (CA) and control registers for DRAMVREFCA (Command Control Line Register) and VREFCS (Chip Select) to the DDR5 protocol. Each rank of the CS signal line corresponds to one signal line, with a maximum of two lines per DRAM. Each DRAM has 14 CA lines. The clock frequency used for the CS / CA signal lines is also very high. High accuracy is required in the one-dimensional and two-dimensional (delay and reference voltage) training process, which necessitates that the training algorithm selects an accurate delay while simultaneously finding an accurate reference voltage.
[0003] In traditional technology, the RCD acts as an intermediary for the CA (Carrier Array) on the DIMM, independently driving the 14 CA signals to the DRAM. The delay control register for the CA signal lines can be configured in the RCD (RW1B / RW1C). Multiple DRAM ranks share this delay configuration register, and multiple CA signal lines share this set of delay control registers. For the CA line configuration on the DRAM side, including VREFCA and ODT, there is a one-to-many situation (14 CA signal lines share one VREFCA configuration). Therefore, the difficulties in CA training include delay and the sharing problem of VREFCA, and the accuracy requirements of the training algorithm are high.
[0004] However, the current training latency of CA and the determination of VREFCA using the intersection method of multiple command line eye diagrams cannot solve the problem of multiple command lines sharing a single reference voltage. This makes the two-dimensional eye diagram easily skewed by certain command lines, which in turn leads to the selection of points being skewed by these command lines, resulting in system instability. Summary of the Invention
[0005] Therefore, it is necessary to provide a method, apparatus, device, medium, and program product for determining the reference voltage of the memory command line that can guarantee system stability, in order to address the above-mentioned technical problems.
[0006] In a first aspect, this application provides a method for determining a memory command line reference voltage, the method comprising:
[0007] Obtain the delay margins corresponding to each training code pattern under the reference voltage of each command line;
[0008] For each reference voltage, the fluctuation of the delay margin is determined based on the delay margin corresponding to each training code pattern under the reference voltage;
[0009] The target reference voltage is selected based on the fluctuation of the time delay margin corresponding to each reference voltage.
[0010] In one embodiment, determining the fluctuation of the delay margin for each reference voltage, based on the delay margin corresponding to each training code pattern under the reference voltage, includes:
[0011] For each reference voltage, the average value is obtained based on the delay margin corresponding to each training code pattern under the reference voltage;
[0012] Based on the delay margins corresponding to each training code pattern under the reference voltage and the average value, the variance of each delay margin is determined, and the variance is used as the fluctuation of the delay margin.
[0013] In one embodiment, selecting a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage includes:
[0014] The reference voltage corresponding to the smallest variance is selected as the target reference voltage.
[0015] In one embodiment, the training patterns include first training patterns where each command line is pulled high in turn and second training patterns where each command line is pulled low in turn. Each first training pattern is characterized by the reference voltage of each command line being pulled high, and each second training pattern is characterized by the reference voltage of only one command line being pulled low. The step of obtaining the delay margin corresponding to each training pattern under each command line reference voltage includes:
[0016] The current reference voltage is determined based on the reference voltage range.
[0017] Under the current reference voltage, determine the delay margins under the first training code pattern corresponding to each command line, and the delay margins under the second training code pattern corresponding to each command line.
[0018] Based on the reference voltage range, the next reference voltage is determined as the new current reference voltage. Then, the steps of determining the delay margins under the first training code pattern corresponding to each command line and the delay margins under the second training code pattern corresponding to each command line are continued under the current reference voltage until the reference voltage range is traversed and the delay margins corresponding to each training code pattern under the reference voltage of each command line are obtained.
[0019] In one embodiment, after selecting a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage, the method further includes:
[0020] Each third training code pattern is generated based on the target reference voltage;
[0021] Based on the third training code pattern, determine the sampling data of each command line corresponding to each delay;
[0022] The target delay is determined based on the sampled data from each command line.
[0023] In one embodiment, determining the sampled data of each command line corresponding to each delay based on the third training code pattern includes:
[0024] Obtain the latency range and determine the current latency based on the latency range;
[0025] Under the third training code pattern, determine the sampled data corresponding to each command line under the current delay;
[0026] Based on the delay range, the next delay is determined as the new current delay, and the process continues to execute the step of determining the sampled data corresponding to each command line under the current delay under the third training code pattern, until the delay range is traversed to obtain the sampled data of each command line corresponding to each delay.
[0027] Secondly, this application also provides a memory command line reference voltage determination device, the device comprising:
[0028] The training information acquisition module is used to acquire the delay margins corresponding to each training code pattern under each command line reference voltage.
[0029] The fluctuation determination module is used to determine the fluctuation of the delay margin for each reference voltage based on the delay margin corresponding to each training code pattern under the reference voltage.
[0030] The reference voltage determination module is used to select a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage.
[0031] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.
[0032] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the methods in any of the above embodiments.
[0033] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.
[0034] The aforementioned method, apparatus, device, medium, and program product for determining the memory command line reference voltage obtains the delay margins corresponding to each training code pattern under each command line reference voltage; for each reference voltage, based on the delay margins corresponding to each training code pattern under the reference voltage, the fluctuation of the delay margins is determined; based on the fluctuation of the delay margins corresponding to each reference voltage, a target reference voltage is selected. This introduces the fluctuation of the delay margins, and by selecting the target reference voltage based on this fluctuation, it avoids the eye diagram being affected by certain special command lines, selects a reference voltage more suitable for all command lines, and ensures stability. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a schematic diagram of DDR5 memory connections on a DIMM in one embodiment;
[0037] Figure 2 This is a flowchart illustrating a method for determining the memory command line reference voltage in one embodiment;
[0038] Figure 3 In one embodiment, two training code types correspond to two command lines;
[0039] Figure 4 This is a flowchart illustrating a method for determining the memory command line reference voltage in another embodiment;
[0040] Figure 5 This is a block diagram of a memory command line reference voltage determination device in one embodiment;
[0041] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0043] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.
[0044] Combination Figure 1 , Figure 1 This is a schematic diagram of DDR5 memory connection on a DIMM in one embodiment. DIMM stands for Dual In-line Memory Module, and DDR stands for Double Data Rate Synchronous Dynamic Random Access Memory, which is the core storage peripheral of the processor.
[0045] Both the RCD (Registering CLOCK DRIVER, which helps improve the stability of RDIMM) and DDR5 chips support QCATM (QCA Training Mode, chip-side command line signal training mode, mainly used for one-dimensional training of command signal delay). The training process of CA (Command Control Line) is completed by the cooperation of the controller, RCD, and chip. The controller is responsible for sending the specified training pattern to the RCD; the RCD is responsible for entering training mode and directly passing the pattern sent by the controller to the DRAM (Dynamic Random-Access Memory) chip without processing; after the DRAM chip enters QCATM, after receiving the pattern sent by the controller, the chip samples and feeds back according to the specification, and then the DQ (Data Signal) line in the chip is pulled high and low to feed back to the controller. The RCD completes one-dimensional delay training by continuously adjusting the delay position.
[0046] Two-dimensional training adds VREFCA (Reference voltage for CA, the reference voltage for the particle command line, each particle has an independent reference voltage configuration register) to the delay. It adjusts the delay of RCD and VREFCA at the particle end, and selects the optimal delay and VREFCA for CA[13:0]. In two-dimensional training, the selection of points in the two-dimensional eye diagram needs to take into account both the delay and the margin of VREF (reference voltage). Moreover, due to the special characteristic of CA having 14 lines, the selected delay and VREF need to be relatively friendly to all CA lines to ensure the stability of the DDR subsystem command line.
[0047] However, the method of finding the intersection of multiple command line eye diagrams cannot solve the problem that multiple command lines sharing a single reference voltage can cause the two-dimensional eye diagram to be easily skewed by certain command lines, which in turn can lead to the selection of points being skewed by these command lines, resulting in system instability.
[0048] Therefore, in one embodiment, such as Figure 2 As shown, a method for determining the reference voltage of a memory command line is provided. This embodiment illustrates the application of this method to a controller. In this embodiment, the method includes the following steps:
[0049] S202: Obtain the delay margin corresponding to each training code pattern under the reference voltage of each command line.
[0050] The training pattern is pre-set and generated by the controller. It is a binary bit stream with a specific structure and sequence. The training pattern is sent to each memory chip through the CA (command / address) bus for testing and calibrating the reference voltage of the CA bus.
[0051] In some optional embodiments, the training patterns include first training patterns in which each command line is pulled high in turn and second training patterns in which each command line is pulled low in turn. Each first training pattern has a reference voltage of each command line pulled high, and each second training pattern has a reference voltage of only one command line pulled low. Combined with... Figure 3 As shown, Figure 3 In one embodiment, two training code patterns correspond to two command lines. For each command line, two training code patterns are used: one high and one low. Since there are 14 command lines, this results in 14 training code patterns. (Combined with...) Figure 3 The command lines CA0 and CA1 implement two training patterns during training. When the command line CA is pulled low or high, the other command lines CA remain high. A total of 28 training patterns are generated during the training of the 14 CA lines, which is closer to the real use scenario.
[0052] In this application, for each of the 28 training code patterns under each reference voltage, a time delay margin is obtained. The time delay margin is the time distance from the current operating point (sampling time) to the nearest failure boundary.
[0053] S204: For each reference voltage, determine the fluctuation of the delay margin based on the delay margin corresponding to each training code pattern under the reference voltage.
[0054] The fluctuation refers to the fluctuation of the delay margin corresponding to the 28 training code patterns under each reference voltage. That is, each reference voltage corresponds to 28 training code patterns, and a delay margin can be calculated under each training code pattern. Then, the fluctuation of the delay margin under each reference voltage is determined based on these 28 delay margins.
[0055] In some alternative embodiments, the fluctuation can be represented by variance. In other embodiments, the fluctuation can also be represented by other statistics, such as standard deviation, mean absolute deviation, coefficient of variation, etc., without specific limitations.
[0056] In some optional embodiments, the fluctuation of the delay margin is determined based on the delay margin corresponding to each training code pattern under the reference voltage, including: for each reference voltage, obtaining the average value based on the delay margin corresponding to each training code pattern under the reference voltage; determining the variance of each delay margin based on the delay margin corresponding to each training code pattern under the reference voltage and the average value, and using the variance as the fluctuation of the delay margin.
[0057] In this application, each reference voltage corresponds to 28 time delay margins. In order to determine the fluctuation situation, the average value of the 28 time delay margins under each reference voltage is first calculated, and then the variance is obtained based on the 28 time delay margins and the average value under each reference voltage.
[0058] The specific variance formula is S 2 =1 / n[(x1-M) 2 +(x2-M) 2 +…+(xn-M) 2 ], where M is the average value of x1, x2...xn, x is the time delay margin corresponding to different training code patterns, and n is 28 (28 training code patterns). This allows us to obtain the fluctuation of the time delay margin under each reference voltage.
[0059] S206: Select the target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage.
[0060] In this application, to avoid the eye diagram being affected by certain special command lines, the fluctuation of the time delay margin corresponding to each reference voltage is considered. In this way, if some command lines have eye diagram irregularities or deviate significantly from most eye diagrams, the corresponding reference voltage will not be selected, thereby ensuring the correctness of the reference voltage selection and improving the stability of the system.
[0061] In some optional embodiments, a target reference voltage is selected based on the fluctuation of the time delay margin corresponding to each reference voltage, including selecting the reference voltage corresponding to the smallest variance as the target reference voltage.
[0062] In this application, the reference voltage corresponding to the smallest variance is selected as the target reference voltage. For example, the fluctuation of each reference voltage is calculated above, and then the reference voltage with the smallest fluctuation is selected as the target voltage. That is to say, under the target voltage, the fluctuation of the data of each command line is the smallest, avoiding the influence of some special command lines on the eye diagram, selecting a reference voltage that is more suitable for all command lines, and solving the problem of multiple command lines using a common reference voltage.
[0063] The aforementioned method for determining the reference voltage of the memory command line obtains the delay margins corresponding to each training code pattern under each command line reference voltage; for each reference voltage, based on the delay margins corresponding to each training code pattern under the reference voltage, the fluctuation of the delay margin is determined; based on the fluctuation of the delay margin corresponding to each reference voltage, a target reference voltage is selected. This introduces the fluctuation of the delay margin, and the target reference voltage is selected based on this fluctuation, thereby avoiding the influence of certain special command lines on the eye diagram, selecting a reference voltage more suitable for all command lines, and ensuring stability.
[0064] In some optional embodiments, the training patterns include first training patterns in which each command line is pulled high in turn and second training patterns in which each command line is pulled low in turn. Each first training pattern is where only one command line reference voltage is pulled high, and each second training pattern is where only one command line reference voltage is pulled low. Obtaining the delay margins corresponding to each training pattern under each command line reference voltage includes: determining the current reference voltage based on the reference voltage range; determining the delay margins under the first training pattern corresponding to each command line and the delay margins under the second training pattern corresponding to each command line under the current reference voltage; determining the next reference voltage as the new current reference voltage based on the reference voltage range, and continuing to execute the steps of determining the delay margins under the first training pattern corresponding to each command line and the delay margins under the second training pattern corresponding to each command line under the current reference voltage, until the reference voltage range is traversed completely, and obtaining the delay margins corresponding to each training pattern under each command line reference voltage.
[0065] The training patterns in this application only include pull-up and pull-down, that is, each command line has a training pattern of 0 to 1 (pull-up) and 1 to 0 (pull-down), which is more in line with the actual situation.
[0066] The reference voltage range is predetermined, for example, 0x10 to 0x50 for information 0. In this application, the reference voltage range can be traversed to determine the current reference voltage. Under the current reference voltage, the delay margins under the first training code pattern corresponding to each command line and the delay margins under the second training code pattern corresponding to each command line are determined. That is, training is performed for 28 code patterns to obtain 28 delay margins. After the determination is completed, the next current reference voltage is obtained according to the reference voltage range, and then the above process is repeated to obtain the 28 delay margins corresponding to each reference voltage.
[0067] The subsequent calculation of the time delay margin fluctuation for each reference voltage is then performed, and the target reference voltage is determined based on the fluctuation.
[0068] Specifically, in combination Figure 4 As shown, Figure 4 This is a flowchart of a memory command line reference voltage determination method in another embodiment. In this embodiment, the memory command line reference voltage determination method takes the command signal line (CA) training of a DDR5 chip as an example, and specifically includes:
[0069] 1) Complete the basic memory initialization process. Determine the current reference voltage by traversing the preset reference voltage range VREFCA (0x10-0x50).
[0070] 2) Scan the second training pattern Pattern[0] (pulled low) for the 14 CA[13:0] command lines.
[0071] 3) Save the Margin (delay margin) results obtained from scanning the second training pattern Pattern[0], a total of 14 data.
[0072] 4) Scan the first training pattern Pattern[1] (pull up) for the 14 CA[13:0] command lines.
[0073] 5) Save the Margin (delay margin) results obtained from scanning the first training pattern[1], a total of 14 data.
[0074] 6) Traverse the preset reference voltage range VREFCA to obtain 28 margin (delay margin) data corresponding to each reference voltage VREFCA, and save them.
[0075] 7) Calculate the average value M of the 28 margin data corresponding to each reference voltage VREFCA.
[0076] 8) Calculate the variance of the time delay margin corresponding to each reference voltage VREFCA.
[0077] 9) Iterate through the variance of the time delay margin corresponding to the reference voltage VREFCA, and find the reference voltage VREFCA corresponding to the minimum variance.
[0078] 10) Confirm the final target reference voltage of the chip and configure the PDA (Pattern-Dependent Adjustment, a technology that dynamically adjusts timing parameters according to the data transmission mode) into the memory chip.
[0079] To facilitate understanding, the training process of the QCA reference voltage of DDR5 device[0] is used as an example, and the following data example is given:
[0080] The following data is the one-dimensional margin scan data of pattern[0] and pattern[1] of particle 0 vref 0x33~0x37 (Parity lane13 was not trained in this example):
[0081] device[ 0] lane[ 0] vref[0x37] pattern[0]margin
[118] pattern[1]margin
[124]
[0082] device[ 0] lane[ 1] vref[0x37] pattern[0]margin
[120] pattern[1]margin
[122]
[0083] device[ 0] lane[ 2] vref[0x37] pattern[0]margin
[120] pattern[1]margin
[120]
[0084] device[ 0] lane[ 3] vref[0x37] pattern[0]margin
[116] pattern[1]margin
[126]
[0085] device[ 0] lane[ 4] vref[0x37] pattern[0]margin
[116] pattern[1]margin
[126]
[0086] device[ 0] lane[ 5] vref[0x37] pattern[0]margin
[116] pattern[1]margin
[128]
[0087] device[ 0] lane[ 6] vref[0x37] pattern[0]margin
[120] pattern[1]margin
[120]
[0088] device[ 0] lane[ 7] vref[0x37] pattern[0]margin
[114] pattern[1]margin
[128]
[0089] device[ 0] lane[ 8] vref[0x37] pattern[0]margin
[122] pattern[1]margin
[118]
[0090] device[ 0] lane[ 9] vref[0x37] pattern[0]margin
[118] pattern[1]margin
[124]
[0091] device[ 0] lane
[10] vref[0x37] pattern[0]margin
[120] pattern[1]margin
[122]
[0092] device[ 0] lane
[11] vref[0x37] pattern[0]margin
[114] pattern[1]margin
[126]
[0093] device[ 0] lane
[12] vref[0x37] pattern[0]margin
[120] pattern[1]margin
[122]
[0094] device[ 0] lane[ 0] vref[0x36] pattern[0]margin
[120] pattern[1]margin
[122]
[0095] device[ 0] lane[ 1] vref[0x36] pattern[0]margin
[122] pattern[1]margin
[122]
[0096] device[ 0] lane[ 2] vref[0x36] pattern[0]margin
[122] pattern[1]margin
[120]
[0097] device[ 0] lane[ 3] vref[0x36] pattern[0]margin
[116] pattern[1]margin
[124]
[0098] device[ 0] lane[ 4] vref[0x36] pattern[0]margin
[118] pattern[1]margin
[124]
[0099] device[ 0] lane[ 5] vref[0x36] pattern[0]margin
[116] pattern[1]margin
[126]
[0100] device[ 0] lane[ 6] vref[0x36] pattern[0]margin
[124] pattern[1]margin
[118]
[0101] device[ 0] lane[ 7] vref[0x36] pattern[0]margin
[116] pattern[1]margin
[126]
[0102] device[ 0] lane[ 8] vref[0x36] pattern[0]margin
[124] pattern[1]margin
[118]
[0103] device[ 0] lane[ 9] vref[0x36] pattern[0]margin
[118] pattern[1]margin
[120]
[0104] device[ 0] lane
[10] vref[0x36] pattern[0]margin
[120] pattern[1]margin
[122]
[0105] device[ 0] lane
[11] vref[0x36] pattern[0]margin
[116] pattern[1]margin
[126]
[0106] device[ 0] lane
[12] vref[0x36] pattern[0]margin
[120] pattern[1]margin
[120]
[0107] device[ 0] lane[ 0] vref[0x35] pattern[0]margin
[122] pattern[1]margin
[120]
[0108] device[ 0] lane[ 1] vref[0x35] pattern[0]margin
[122] pattern[1]margin
[120]
[0109] device[ 0] lane[ 2] vref[0x35] pattern[0]margin
[122] pattern[1]margin
[120]
[0110] device[ 0] lane[ 3] vref[0x35] pattern[0]margin
[118] pattern[1]margin
[122]
[0111] device[ 0] lane[ 4] vref[0x35] pattern[0]margin
[120] pattern[1]margin
[122]
[0112] device[ 0] lane[ 5] vref[0x35] pattern[0]margin
[116] pattern[1]margin
[126]
[0113] device[ 0] lane[ 6] vref[0x35] pattern[0]margin
[124] pattern[1]margin
[118]
[0114] device[ 0] lane[ 7] vref[0x35] pattern[0]margin
[118] pattern[1]margin
[124]
[0115] device[ 0] lane[ 8] vref[0x35] pattern[0]margin
[124] pattern[1]margin
[118]
[0116] device[ 0] lane[ 9] vref[0x35] pattern[0]margin
[122] pattern[1]margin
[120]
[0117] device[ 0] lane
[10] vref[0x35] pattern[0]margin
[122] pattern[1]margin
[118]
[0118] device[ 0] lane
[11] vref[0x35] pattern[0]margin
[118] pattern[1]margin
[124]
[0119] device[ 0] lane
[12] vref[0x35] pattern[0]margin
[122] pattern[1]margin
[118]
[0120] device[ 0] lane[ 0] vref[0x34] pattern[0]margin
[122] pattern[1]margin
[118]
[0121] device[ 0] lane[ 1] vref[0x34] pattern[0]margin
[124] pattern[1]margin
[118]
[0122] device[ 0] lane[ 2] vref[0x34] pattern[0]margin
[124] pattern[1]margin
[116]
[0123] device[ 0] lane[ 3] vref[0x34] pattern[0]margin
[120] pattern[1]margin
[122]
[0124] device[ 0] lane[ 4] vref[0x34] pattern[0]margin
[120] pattern[1]margin
[122]
[0125] device[ 0] lane[ 5] vref[0x34] pattern[0]margin
[118] pattern[1]margin
[122]
[0126] device[ 0] lane[ 6] vref[0x34] pattern[0]margin
[124] pattern[1]margin
[116]
[0127] device[ 0] lane[ 7] vref[0x34] pattern[0]margin
[118] pattern[1]margin
[124]
[0128] device[ 0] lane[ 8] vref[0x34] pattern[0]margin
[126] pattern[1]margin
[116]
[0129] device[ 0] lane[ 9] vref[0x34] pattern[0]margin
[122] pattern[1]margin
[120]
[0130] device[ 0] lane
[10] vref[0x34] pattern[0]margin
[124] pattern[1]margin
[118]
[0131] device[ 0] lane
[11] vref[0x34] pattern[0]margin
[118] pattern[1]margin
[122]
[0132] device[ 0] lane
[12] vref[0x34] pattern[0]margin
[124] pattern[1]margin
[118]
[0133] device[ 0] lane[ 0] vref[0x33] pattern[0]margin
[124] pattern[1]margin
[118]
[0134] device[ 0] lane[ 1] vref[0x33] pattern[0]margin
[126] pattern[1]margin
[118]
[0135] device[ 0] lane[ 2] vref[0x33] pattern[0]margin
[126] pattern[1]margin
[116]
[0136] device[ 0] lane[ 3] vref[0x33] pattern[0]margin
[120] pattern[1]margin
[122]
[0137] device[ 0] lane[ 4] vref[0x33] pattern[0]margin
[122] pattern[1]margin
[120]
[0138] device[ 0] lane[ 5] vref[0x33] pattern[0]margin
[120] pattern[1]margin
[122]
[0139] device[ 0] lane[ 6] vref[0x33] pattern[0]margin
[128] pattern[1]margin
[114]
[0140] device[ 0] lane[ 7] vref[0x33] pattern[0]margin
[118] pattern[1]margin
[120]
[0141] device[ 0] lane[ 8] vref[0x33] pattern[0]margin
[128] pattern[1]margin
[114]
[0142] device[ 0] lane[ 9] vref[0x33] pattern[0]margin
[126] pattern[1]margin
[116]
[0143] device[ 0] lane
[10] vref[0x33] pattern[0]margin
[124] pattern[1]margin
[118]
[0144] device[ 0] lane
[11] vref[0x33] pattern[0]margin
[120] pattern[1]margin
[122]
[0145] device[ 0] lane
[12] vref[0x33] pattern[0]margin
[124] pattern[1]margin
[116]
[0146] Calculate the variance (margin_dif) for each reference voltage Vref:
[0147] device[ 0] vref[0x37] avg
[120] pattern[0]margin_dif[0x84] pattern[1]margin_dif[0x1a0]
[0148] device[ 0] vref[0x36] avg
[120] pattern[0]margin_dif[0x70] pattern[1]margin_dif[0x110]
[0149] device[ 0] vref[0x35] avg
[120] pattern[0]margin_dif[0x54] pattern[1]margin_dif[0xb0]
[0150] device[ 0] vref[0x34] avg
[120] pattern[0]margin_dif[0x88] pattern[1]margin_dif[0xe8]
[0151] device[ 0] vref[0x33] avg
[120] pattern[0]margin_dif[0x124] pattern[1]margin_dif[0x1b4]
[0152] Choose 0x35, which has the smallest variance among vref ranges of 0x33 to 0x37, as the target reference voltage.
[0153] In the above embodiments, based on the improved training pattern, a variance algorithm is introduced to select the optimal reference voltage. The improved training pattern is closer to real-world usage scenarios, and the introduction of the variance algorithm avoids the influence of certain special command lines on the eye diagram, selecting a reference voltage more suitable for all command lines and solving the problem of multiple command lines using a common reference voltage. Simultaneously, each command line has a training pattern of 0 to 1 (pull-high) and 1 to 0 (pull-low). The variance algorithm can select a reference voltage with similar margins (delay margins) for both pull-low and pull-high training patterns, thus finding a reference voltage for all command lines that balances both training patterns, resulting in a more stable system.
[0154] In some optional embodiments, after selecting a target reference voltage based on the fluctuation of the delay margin corresponding to each reference voltage, the method further includes: generating each third training code pattern based on the target reference voltage; determining each sampled data of each command line corresponding to each delay based on the third training code pattern; and determining the target delay based on each sampled data of each command line.
[0155] In this application, after obtaining the target voltage through training, the command line is also trained in one dimension to update the delay configuration in the delay register RCD. Specifically, each third training code pattern is first generated based on the target reference voltage. Then, the controller sends the third training code pattern to each memory chip through the delay register RCD and obtains the feedback data of each command line corresponding to each memory chip, i.e., the sampled data. Finally, the target delay is determined based on the sampled data.
[0156] In some optional embodiments, determining the sampled data of each command line corresponding to each delay based on the third training code pattern includes: obtaining the delay range and determining the current delay based on the delay range; determining the sampled data of each command line corresponding to the current delay under the third training code pattern; determining the next delay as the new current delay based on the delay range, and continuing to execute the step of determining the sampled data of each command line corresponding to the current delay under the third training code pattern until the delay range is traversed to obtain the sampled data of each command line corresponding to each delay.
[0157] In this application, the current delay can be determined first based on the delay range, and then the RCD can be controlled to forward the third training code pattern to each memory particle under the current delay, and obtain the sampling data corresponding to each memory particle.
[0158] The delay range is then used to determine the next current delay, and this process continues until the delay range is traversed to obtain the sampled data for each command line corresponding to each delay.
[0159] In this application, the data feedback results of each sampled dataset memory particle are used. Therefore, the median value of the delay range can be used as the initial delay, and the training code pattern is forwarded to each memory particle based on the initial delay to obtain the data feedback results of each memory particle under the initial delay. The delay step size and each adjustment direction are determined, and the initial delay is adjusted based on the delay step size and each adjustment direction to obtain other delays. The training code pattern is forwarded to each memory particle based on the other delays to obtain the data feedback results of each memory particle under each other delay. Specifically, this includes: for each adjustment direction, adjusting the initial delay based on the adjustment direction and the delay step size to obtain the current other delay; obtaining the data feedback results of each memory particle under the current other delay; if the data feedback results do not change, adjusting the current other delay based on the adjustment direction and the delay step size to obtain a new current other delay, and continuing to execute the step of obtaining the data feedback results of each memory particle under the current other delay until the data feedback results change.
[0160] The target latency can be determined based on the data feedback results of each memory chip at each latency, and the data feedback results that jump. The latency corresponding to the data feedback results that jump is used to determine the target latency. Specifically, the reference latency corresponding to each adjustment direction is determined. The reference latency is the latency corresponding to the data feedback results that jump in the adjustment direction. The mathematical statistics of the reference latency corresponding to each adjustment direction are calculated as the target latency.
[0161] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.
[0162] Based on the same inventive concept, this application also provides a memory command line reference voltage determination device for implementing the memory command line reference voltage determination method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more memory command line reference voltage determination device embodiments provided below can be found in the limitations of the memory command line reference voltage determination method described above, and will not be repeated here.
[0163] In one exemplary embodiment, such as Figure 5 As shown, a memory command line reference voltage determination device is provided, including: a training information acquisition module 501, a fluctuation determination module 502, and a reference voltage determination module 503, wherein:
[0164] The training information acquisition module 501 is used to acquire the delay margins corresponding to each training code pattern under each command line reference voltage.
[0165] The fluctuation determination module 502 is used to determine the fluctuation of the delay margin for each reference voltage based on the delay margin corresponding to each training code pattern under the reference voltage.
[0166] The reference voltage determination module 503 is used to select a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage.
[0167] In some optional embodiments, the fluctuation determination module 502 is specifically used to obtain the average value of each training code pattern corresponding to each reference voltage based on each delay margin under the reference voltage; and to determine the variance of each delay margin based on each delay margin corresponding to each training code pattern under the reference voltage and the average value, and to use the variance as the fluctuation of the delay margin.
[0168] In some alternative embodiments, the reference voltage determination module 503 is specifically used to select the reference voltage corresponding to the smallest variance as the target reference voltage.
[0169] In some optional embodiments, the training patterns include first training patterns in which each command line is pulled high in turn and second training patterns in which each command line is pulled low in turn. Each first training pattern is where the reference voltage of each command line is pulled high, and each second training pattern is where the reference voltage of only one command line is pulled low. The training information acquisition module 501 is specifically used to determine the current reference voltage based on the reference voltage range, and under the current reference voltage, determine the delay margins under the first training pattern corresponding to each command line and the delay margins under the second training pattern corresponding to each command line. Based on the reference voltage range, determine the next reference voltage as the new current reference voltage, and continue to execute the steps of determining the delay margins under the first training pattern corresponding to each command line and the delay margins under the second training pattern corresponding to each command line under the current reference voltage, until the reference voltage range is traversed and the delay margins corresponding to each training pattern under the reference voltage of each command line are obtained.
[0170] In some optional embodiments, the above apparatus further includes: a target delay determination module, configured to generate each third training code pattern based on a target reference voltage; determine each sampled data of each command line corresponding to each delay based on the third training code pattern; and determine the target delay based on each sampled data of each command line.
[0171] In some optional embodiments, the target delay determination module is specifically used to obtain the delay range and determine the current delay based on the delay range; under the third training code pattern, determine the sampled data corresponding to each command line under the current delay; determine the next delay as the new current delay based on the delay range, and continue to execute the step of determining the sampled data corresponding to each command line under the current delay under the third training code pattern until the delay range is traversed to obtain the sampled data of each command line corresponding to each delay.
[0172] Each module in the aforementioned memory command line reference voltage determination device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.
[0173] In one exemplary embodiment, a computer device is provided, which may be a controller, and its internal structure diagram may be as follows: Figure 6As shown, this computer device includes a processor, input / output (I / O) interfaces, and a communication interface. The processor and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory of this computer device includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The I / O interfaces are used for exchanging information between the processor and other storage devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for determining a memory command line reference voltage.
[0174] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0175] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.
[0176] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.
[0177] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0178] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0179] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0180] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0181] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A method for determining the reference voltage of a memory command line, characterized in that, The method includes: Obtain the delay margins corresponding to each training code pattern under the reference voltage of each command line; For each reference voltage, the fluctuation of the delay margin is determined based on the delay margin corresponding to each training code pattern under the reference voltage; The target reference voltage is selected based on the fluctuation of the time delay margin corresponding to each reference voltage.
2. The method according to claim 1, characterized in that, For each reference voltage, determining the fluctuation of the delay margin based on the delay margin corresponding to each training code pattern under the reference voltage includes: For each reference voltage, the average value is obtained based on the delay margin corresponding to each training code pattern under the reference voltage; Based on the delay margins corresponding to each training code pattern under the reference voltage and the average value, the variance of each delay margin is determined, and the variance is used as the fluctuation of the delay margin.
3. The method according to claim 2, characterized in that, The step of selecting a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage includes: The reference voltage corresponding to the smallest variance is selected as the target reference voltage.
4. The method according to any one of claims 1 to 3, characterized in that, The training patterns include first training patterns in which each command line is pulled high in turn and second training patterns in which each command line is pulled low in turn. Each first training pattern is in which the reference voltage of each command line is pulled high, and each second training pattern is in which the reference voltage of only one command line is pulled low. The step of obtaining the delay margins corresponding to each training code pattern under each command line reference voltage includes: The current reference voltage is determined based on the reference voltage range. Under the current reference voltage, determine the delay margins under the first training code pattern corresponding to each command line, and the delay margins under the second training code pattern corresponding to each command line. Based on the reference voltage range, the next reference voltage is determined as the new current reference voltage. Then, the steps of determining the delay margins under the first training code pattern corresponding to each command line and the delay margins under the second training code pattern corresponding to each command line are continued under the current reference voltage until the reference voltage range is traversed and the delay margins corresponding to each training code pattern under the reference voltage of each command line are obtained.
5. The method according to any one of claims 1 to 3, characterized in that, After selecting a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage, the method further includes: Each third training code pattern is generated based on the target reference voltage; Based on the third training code pattern, determine the sampling data of each command line corresponding to each delay; The target delay is determined based on the sampled data from each command line.
6. The method according to claim 5, characterized in that, The step of determining the sampled data for each command line corresponding to each delay based on the third training code pattern includes: Obtain the latency range and determine the current latency based on the latency range; Under the third training code pattern, determine the sampled data corresponding to each command line under the current delay; Based on the delay range, the next delay is determined as the new current delay, and the process continues to execute the step of determining the sampled data corresponding to each command line under the current delay under the third training code pattern, until the delay range is traversed to obtain the sampled data of each command line corresponding to each delay.
7. A memory command line reference voltage determination device, characterized in that, The device includes: The training information acquisition module is used to acquire the delay margins corresponding to each training code pattern under each command line reference voltage. The fluctuation determination module is used to determine the fluctuation of the delay margin for each reference voltage based on the delay margin corresponding to each training code pattern under the reference voltage. The reference voltage determination module is used to select a target reference voltage based on the fluctuation of the time delay margin corresponding to each reference voltage.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.