A method for calculating the parasitic capacitance of a plated through hole conductor plate and related device
Patent Information
- Application Number
- CN202610868369.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-16
- Publication Date
- 2026-11-03
AI Technical Summary
Existing technologies lack a fast and accurate method to calculate the parasitic capacitance of perforated conductor plates, resulting in low engineering design efficiency and an inability to meet the requirements of high-frequency electromagnetic compatibility and signal integrity.
By obtaining the structural parameters of the perforated parallel plate capacitor, a physical model of the perforated perturbation electric field is established. The perforation is equivalent to an electric dipole. The leakage electric field energy is calculated using the polarization coefficient, and then the parasitic capacitance value is determined by the energy method.
It achieves fast and accurate calculation of parasitic capacitance of perforated conductor plates, reduces reliance on time-consuming full-wave electromagnetic simulation, meets the needs of early-stage engineering design and optimization, and the error between the calculation results and simulation results is less than 10%.
Smart Images
Figure CN123031646A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electromagnetic compatibility technology, and in particular to a method and related apparatus for calculating the parasitic capacitance of an open conductor plate. Background Technology
[0002] In high-voltage, high-power power electronics and electrical systems, conductor plates (such as power buses and shielding enclosures) are commonly perforated with various types of holes (e.g., round holes, elliptical holes, rectangular holes, and square holes) to meet requirements for heat dissipation, weight reduction, and wiring. These openings disturb the electric field distribution near the conductor plate, thereby altering its parasitic capacitance. With increasing operating frequencies and equipment integration, the impact of parasitic capacitance on system electromagnetic compatibility (EMC) and signal integrity is becoming increasingly significant.
[0003] Currently, mature theoretical formulas exist for the parasitic capacitance of non-perforated parallel plates. However, when perforations are present, traditional formulas become inapplicable: complex edge electric fields are formed at the edges of the perforations, introducing unpredictable additional capacitance. There is currently a lack of analytical formulas for rapidly estimating the parasitic capacitance of perforated conductor plates in engineering applications. Typically, engineers must rely on time-consuming full-wave electromagnetic simulation software (such as ANSYS and HFSS) for modeling and analysis, which is inefficient and detrimental to early-stage multi-scheme design and optimization. Therefore, there is an urgent need for an analytical method that can quickly and accurately calculate the parasitic capacitance of perforated conductor plates to guide engineering design. Summary of the Invention
[0004] The purpose of this application is to provide a method and related apparatus for calculating the parasitic capacitance of an open-hole conductor plate, which can realize the rapid and accurate estimation of the parasitic capacitance of an open-hole parallel plate capacitor and reduce the reliance on complex electromagnetic simulation.
[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a method for calculating the parasitic capacitance of an open-hole conductor plate, including: Obtain the structural parameters of the perforated parallel plate capacitor; the structural parameters include the area of the plates facing each other, the distance between the plates, the number of openings, and the shape and size of the openings. Based on the physical model of the electric field disturbance caused by the opening, each opening is equivalent to an electric dipole. Using the polarization coefficient corresponding to the shape of the opening, combined with the structural parameters, the leakage electric field energy caused by the opening is calculated. Based on the leakage electric field energy, the parasitic capacitance value after the hole is opened is determined by the energy method. The parasitic capacitance value is output as the calculation result of the parasitic capacitance of the perforated conductor plate.
[0006] In a second aspect, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for calculating the parasitic capacitance of an open-hole conductor plate as described above.
[0007] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for calculating the parasitic capacitance of an open conductor plate as described above.
[0008] Fourthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method for calculating the parasitic capacitance of an open-hole conductor plate as described above.
[0009] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a method and related apparatus for calculating the parasitic capacitance of an open-ended conductor plate. By obtaining the structural parameters of the open-ended parallel plate capacitor, a physical model of the perturbation electric field of the opening is established. The opening is equivalent to an electric dipole, and the leakage electric field energy is calculated by combining the polarization coefficient of the corresponding shape. Finally, the analytical result of the parasitic capacitance after the opening is obtained directly through the energy method. The calculation can be completed quickly without the need for time-consuming full-wave simulation, which can meet the efficiency requirements of early-stage engineering design and optimization. Moreover, clear analytical formulas are given for common opening forms such as circular holes and elliptical holes. The calculation accuracy meets the engineering estimation requirements and effectively solves the problem of lack of rapid estimation methods in the prior art. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 This is an application environment diagram of a method for calculating the parasitic capacitance of an open conductor plate according to an embodiment of this application.
[0012] Figure 2 This is a flowchart illustrating a method for calculating the parasitic capacitance of an open conductor plate according to an embodiment of this application.
[0013] Figure 3 This is a schematic diagram of a parallel plate capacitor structure with a single circular hole provided in an embodiment of this application.
[0014] Figure 4This is a schematic diagram illustrating the derivation method of a parallel plate capacitor with a circular hole provided in an embodiment of this application.
[0015] Figure 5 This is a schematic diagram comparing the calculated value of the aperture capacitance formula with the Maxwell 3D simulation value provided in an embodiment of this application.
[0016] Figure 6 This is a schematic diagram comparing the calculated value of the elliptical aperture capacitance formula with the Maxwell 3D simulation value provided in an embodiment of this application.
[0017] Figure 7 A comparison chart of simulation solutions and formula solutions for an opening ratio of 20% to 80% provided in an embodiment of this application.
[0018] Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0021] The method for calculating the parasitic capacitance of an open conductor plate provided in this application embodiment can be applied to, for example, Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be set up independently, integrated into server 104, or placed in the cloud or on another server.
[0022] The terminal 102 can be, but is not limited to, various desktop computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, and smart in-vehicle devices. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted devices. The server 104 can be implemented using a standalone server or a server cluster composed of multiple servers, or it can be a cloud server.
[0023] In one exemplary embodiment, such as Figure 2As shown, a method for calculating parasitic capacitance of a perforated conductor plate is provided. This method is executed by a computer device, specifically can be executed independently by a computer device such as a terminal or a server, or can be executed jointly by a terminal and a server. In the embodiments of the present application, the method is applied to Figure 1 the server 104 in the above as an example for description, which includes the following steps 201 to 204. Wherein: Step 201: Acquire structural parameters of a perforated parallel-plate capacitor; the structural parameters include the facing area of the plates, the spacing between the plates, the number of perforations, as well as the shape and dimension parameters of the perforations; Step 202: Based on the physical model of electric field perturbation caused by the perforations, equivalent each perforation to an electric dipole, and use the electric polarization coefficient corresponding to the shape of the perforation in combination with the structural parameters to calculate the leakage electric field energy caused by the perforations; Step 203: Determine the parasitic capacitance value after perforation through the energy method according to the leakage electric field energy; Step 204: Output the parasitic capacitance value as the calculation result of the parasitic capacitance of the perforated conductor plate.
[0024] Wherein, in an exemplary embodiment, when executing steps 201 to 204, the specific implementation may be as follows: First, analyze the change of leakage electric field energy caused by the perforations. Consider an infinite conductor plate, where a uniform electric field exists in the upper half space . As shown Figure 3 , when a circular hole with a radius a is opened on the plate, the presence of the perforation will perturb the electric field, causing part of the electric field lines to leak into the lower half space, and this leaked electric field stores additional electric energy.
[0025] The leakage electric field energy can be calculated by integration. In the region on the surface of the conductor plate (z=0) and inside the circular hole (ρ<a), the potential distribution in the perforated region is .
[0026] Through the electric field energy density formula integrated over the whole space, and using Gauss's theorem to convert the volume integral into a surface integral over the hole surface, it can be deduced that the leakage electric field energy caused by a single circular hole is: ; Wherein, the electric polarization intensity P and the equivalent dipole moment p of the perforation are introduced, as shown Figure 4 , , because the direction of the equivalent dipole moment on both sides of the hole is opposite to the direction of the electric field before the hole is opened, that is and are in opposite directions, hence there is a -1 term.
[0027] For a perforated conductor plate, its polarization characteristics can be characterized by the electric polarization coefficient To describe it. According to dielectric polarization theory, the relative permittivity With polarizability The relationship is: ; Electrosusceptibility The relationship with the polarization intensity P is as follows: ; ; For a circular hole of radius a, its polarization coefficient for: ; Substituting the above formula, we get: ; because ,so ; Formula C K1 It can be changed to: ; When N holes are opened on both the upper and lower plates, the formula for calculating the parasitic capacitance is: ; in, The vacuum permittivity, a Where is the radius of the hole. S The area of the plates facing each other. d The distance between the plates. N This represents the number of openings.
[0028] When the opening is an elliptical opening, the calculation of the parasitic capacitance of the plate is as follows: Similar to the case of a circular hole, the influence of an elliptical hole on the electric field distribution on an infinitely large conductor plate can be compared with the case of elliptical holes on the upper and lower plates of a parallel-plate capacitor.
[0029] Let the major semi-axis of the elliptical hole be c, and the minor semi-axis be b. Without the hole, a uniform electric field E0 exists above the conductor plane (direction perpendicular to the conductor plane). After the hole is opened, the normal component of the electric field intensity on the opened surface is E0 / 2, consistent with the conclusion for a circular hole. The potential distribution on the opened surface can be obtained using the Green's function in elliptical coordinates, and its expression is: ; in, , E ( k ) is a complete elliptic integral of the second kind.
[0030] ; In the formula, k is the independent variable of the elliptic function. It is the integral variable.
[0031] For the major axis of the ellipse is l The minor axis of the ellipse is w An ellipse, whose polarization coefficient for: ; The derivation method is the same as for the parallel plate capacitor with a circular hole, except that the polarization coefficient of an ellipse is used instead. Substituting the polarization coefficient of the ellipse into the capacitance formula of the parallel plate, we get: .
[0032] If the number of openings in each board is N, then the formula for calculating the parasitic capacitance is: ; in, The vacuum permittivity, S The area of the plates facing each other. d The distance between the plates. N Number of holes l The major axis of the ellipse w The minor axis of the ellipse E(e) It is a complete elliptic integral of the second kind.
[0033] In a specific embodiment, the calculation and verification of the capacitance of the parallel plate with the circular hole are as follows: This embodiment illustrates the application and verification of the circular hole capacitor formula. Consider a pair of parallel conductor plates, with length, width, and height of 1000mm × 1000mm × 2mm respectively, and a plate spacing of 200mm. A circular hole with a radius of 200mm is made in the center of each of the upper and lower plates.
[0034] The theoretical capacitance calculated using the circular aperture capacitance formula is 42.028 pF; according to Maxwell 3D simulation results, the capacitance between the two plates is 41.732 pF (e.g., ...). Figure 5 The relative error between the simulated value and the calculated value is only 0.70%, which verifies that the capacitor formula for the perforated parallel plate derived in this application has good accuracy in actual calculations.
[0035] In a specific embodiment, the calculation and verification of the capacitance of the parallel plate with an elliptical hole are as follows: This embodiment illustrates the application and verification of the elliptical hole capacitance formula. Consider a pair of parallel plates with dimensions of 1000mm × 1000mm × 1mm and a plate spacing of 100mm. Each of the upper and lower plates has 25 elliptical holes arranged in a 5×5 array. The major axis of each elliptical hole is 120mm and the minor axis is 60mm.
[0036] Based on the formula for capacitance at an elliptical aperture, numerical calculations using MATLAB yielded a theoretical capacitance value of 87.508 pF. Simulation results from Maxwell 3D show a value of 87.536 pF (e.g., ...). Figure 6 The relative error between the theoretical and simulated values is 0.03%, which verifies the high accuracy and reliability of the derived formula in the elliptical hole structure.
[0037] In a specific embodiment, the influence of the opening ratio and the applicability of the formula are as follows: Considering that in the extreme case of extremely large aperture sizes, the conductor plate will approach a grid structure composed of conductive lines, it is questionable whether the above-derived formula is still applicable to calculating capacitance in such cases. Its accuracy may not reach the level of calculation and verification for the capacitance of parallel plates with circular apertures. To clarify the applicability of this formula, particularly within the range of aperture size proportions that it remains applicable, this embodiment conducts the following research: Two parallel conductor plates, each 1000mm × 1000mm in size, were selected, with a fixed spacing of 100mm between them. During the study, a 5×5 uniform aperture array was created on the plates, dividing each plate into 25 identical 200mm × 200mm units, with a circular aperture at the center of each unit. The ratio of the aperture diameter to the unit side length (i.e., aperture diameter / 200mm) was used as the aperture ratio parameter to systematically investigate its impact on the accuracy of capacitance calculation.
[0038] This embodiment performs a series of simulations using Maxwell 3D for different aperture ratios ranging from 20% to 80%, obtaining the capacitance values for the corresponding structures. After the simulations are completed, the simulated capacitance values obtained for each ratio are compared with the theoretical values calculated using the circular aperture capacitance formula. The results are as follows. Figure 7 As shown, the calculation error of the formula gradually increases with the increase of the proportion of openings. In engineering applications, it is generally considered that when the proportion of openings is less than or equal to 70%, the relative error between the formula solution and the simulation solution is less than or equal to 6.77%, which is less than the usually acceptable error limit of 10%. Therefore, within this range, the formula still has good practicality and reliability.
[0039] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 8As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores the parasitic capacitance values of the perforated conductor plate. The I / O interfaces are used for information exchange between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a method for calculating the parasitic capacitance of the perforated conductor plate.
[0040] Figure 8 The structures shown are merely block diagrams of some structures related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.
[0041] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0042] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0043] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with relevant regulations and be authorized by the owner of the corresponding device.
[0044] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).
[0045] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchain. The processors involved in the embodiments provided in this application may be, but are not limited to, general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc.
[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0047] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for calculating the parasitic capacitance of an open-hole conductor plate, characterized in that, include: Obtain the structural parameters of the perforated parallel plate capacitor; the structural parameters include the area of the plates facing each other, the distance between the plates, the number of openings, and the shape and size of the openings. Based on the physical model of the electric field disturbance caused by the opening, each opening is equivalent to an electric dipole. Using the polarization coefficient corresponding to the shape of the opening, combined with the structural parameters, the leakage electric field energy caused by the opening is calculated. Based on the leakage electric field energy, the parasitic capacitance value after the hole is opened is determined by the energy method. The parasitic capacitance value is output as the calculation result of the parasitic capacitance of the perforated conductor plate.
2. The method for calculating the parasitic capacitance of an open-hole conductor plate according to claim 1, characterized in that, When the opening is a circular hole, the formula for calculating the parasitic capacitance value is: ； in, The vacuum permittivity, a Where is the radius of the hole. S The area of the plates facing each other. d The distance between the plates. N This represents the number of openings.
3. The method for calculating the parasitic capacitance of an open-hole conductor plate according to claim 2, characterized in that, When the opening is an elliptical opening, the formula for calculating the parasitic capacitance value is: ； In the formula, l The major axis of the ellipse w The minor axis of the ellipse E(e) It is a complete elliptic integral of the second kind.
4. The method for calculating the parasitic capacitance of an open-hole conductor plate according to claim 3, characterized in that, The formula for calculating the second kind of complete elliptic integral is: ； In the formula, k is the independent variable of the elliptic function. It is the integral variable.
5. The method for calculating the parasitic capacitance of an open-hole conductor plate according to claim 4, characterized in that, The polarization coefficient is determined based on the shape of the opening.
6. The method for calculating the parasitic capacitance of an open-hole conductor plate according to claim 5, characterized in that, When the opening is a round hole, according to the formula Determine the polarization coefficient; According to the formula Determine the polarization coefficient.
7. The method for calculating the parasitic capacitance of an open-hole conductor plate according to claim 6, characterized in that, The formula for calculating the leakage electric field energy is: ； In the formula, It is a uniform electric field.
8. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that the processor executes the computer program to implement a method for calculating the parasitic capacitance of an open conductor plate according to any one of claims 1-7.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements a method for calculating the parasitic capacitance of an open conductor plate according to any one of claims 1-7.
10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements a method for calculating the parasitic capacitance of an open conductor plate according to any one of claims 1-7.