High-speed differential signal driving circuit and implementation method thereof

Abstract

The invention belongs to the field of high-speed analog integrated circuit design, and provides a high-speed differential signal driving circuit and an implementation method thereof, and the high-speed differential signal driving circuit comprises an input part, an LVPECL part, a CML part and an output part. The input part comprises an adjustable current source, a first NMOS (N-channel Metal Oxide Semiconductor) tube and a second NMOS tube; the LVPECL part comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, the CML part comprises a ninth NMOS (N-channel Metal Oxide Semiconductor) tube, a tenth NMOS tube, a third PMOS (P-channel Metal Oxide Semiconductor) tube, a fourth PMOS tube, a third resistor and a fourth resistor; and the output part comprises a P output end and an N output end. By designing the simplified LVPECL part and the CML part, the circuit scale and the parasitic capacitance are reduced, and the power consumption and the chip area are reduced; the input part is shared by the LVPECL part and the CML part, so that a common pre-driver is omitted.

Description

Technical Field

[0001] The present invention relates to the field of high-speed analog integrated circuit design, and in particular to a high-speed differential signal driving circuit and an implementation method thereof. Background Art

[0002] In the field of high-speed data communication, regardless of clock or data, signals are generally transmitted in differential form, because differential signals have good advantages such as good resistance to common-mode interference and reduced electromagnetic interference. The most common driver-level high-speed differential signal output forms are current mode logic and low-voltage positive emitter coupled logic. Compared with the low-voltage differential signal form, these two output standards have larger bandwidth, larger swing, and lower noise, so they are more suitable for high-speed clock signal large swing drive output. High-performance clock chips usually integrate these two most mainstream output signal modes. The traditional approach of the driver level is to integrate these two output drivers in the chip separately, drive the same pair of output differential pins together, and select the output mode by switching the enable control signal. However, this will increase the chip area, and will reduce the output bandwidth and signal amplitude due to the increase in the parasitic capacitance of the output differential pins. In order to improve this problem, the prior art has proposed a variety of circuit structures and methods to realize a unified multi-level standard output circuit, or a differential signal driving circuit integrating multiple output standards.

[0003] Patent US8823414B2 discloses an output driver circuit that integrates multiple signal formats and has adjustable internal output resistance. Although it is suitable for integrating multiple output formats and has a high degree of integration, it has a complex structure and requires pre-drive and common-mode feedback loops; and the output differential pins introduce more parasitic capacitance. Patent CN 117879589A discloses a multi-level output circuit and method for a multi-voltage domain architecture. However, there are deficiencies such as non-standard output stage structure, difficulty in adapting to common load configurations such as current mode logic and low-voltage positive emitter coupled logic, and difficulty in accurately adjusting output common-mode voltage and output impedance. Patent CN 116208142A discloses a differential signal drive circuit and a method for selecting a differential signal drive circuit. The method proposed in this patent integrates multiple output formats, but there are many switches and multiple pre-drivers are required, so the structure is not compact enough, which will bring the disadvantages of large area and high power consumption. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a high-speed differential signal driving circuit and an implementation method thereof, which reduces the circuit scale and parasitic capacitance, and reduces power consumption and chip area by designing a streamlined LVPECL part and CML part; and eliminates the common pre-driver by sharing the input part of the LVPECL part and the CML part.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A high-speed differential signal driving circuit comprises: an input part, an LVPECL part, a CML part and an output part; the input part comprises: an adjustable current source, a first NMOS tube and a second NMOS tube; the LVPECL part comprises: third to eighth NMOS tubes, a first PMOS tube, a second PMOS tube, a first resistor and a second resistor; the CML part comprises: a ninth NMOS tube, a tenth NMOS tube, a third PMOS tube, a fourth PMOS tube, a third resistor and a fourth resistor; the output part comprises: a P output terminal and an N output terminal;

[0007] The gate of the first NMOS tube is connected to the external positive input terminal; the gate of the second NMOS tube is connected to the external negative input terminal; the source of the first NMOS tube and the second NMOS tube are respectively connected to the first end of the adjustable current source; the drain of the first NMOS tube and the second NMOS tube are respectively connected to the source of the third NMOS tube and the fourth NMOS tube; the drain of the first NMOS tube is connected to the source of the tenth NMOS tube through the third line; the drain of the second NMOS tube is connected to the source of the ninth NMOS tube through the fourth line; the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube through the sixth line; the drain of the third NMOS tube and the fourth NMOS tube are respectively connected to the first end of the first resistor and the second resistor; the drain of the third NMOS tube is respectively connected to the gate of the sixth NMOS tube and the drain of the eighth NMOS tube through the Out1_n line; the drain of the fourth NMOS tube is respectively connected to the gate of the fifth NMOS tube and the drain of the seventh NMOS tube through the second line; the second ends of the first resistor and the second resistor are respectively connected to the first The drain of the PMOS tube is connected to the drain of the second PMOS tube; the gate of the first PMOS tube is connected to the gate of the second PMOS tube through a fifth line; the gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube through a fifth line; the gate of the ninth NMOS tube is connected to the gate of the tenth NMOS tube through an eighth line; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube through a seventh line; the drains of the third PMOS tube and the fourth PMOS tube are respectively connected to the second ends of the third resistor and the fourth resistor; The P output end is respectively connected to the source of the fifth NMOS tube, the drain of the ninth NMOS tube and the first end of the third resistor; the N output end is respectively connected to the source of the sixth NMOS tube, the drain of the tenth NMOS tube and the first end of the fourth resistor; the drains of the first PMOS tube to the fourth PMOS tube, the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are respectively connected to the external high level end; the second end of the adjustable current source, the source of the seventh NMOS tube and the source of the eighth NMOS tube are respectively connected to the external low level end.

[0008] Preferably, the common mode voltage value of the P output terminal and the N output terminal is controlled by the adjustable current source, the first resistor, the second resistor, the third resistor and the fourth resistor.

[0009] Preferably, a method for implementing a high-speed differential signal driving circuit comprises:

[0010] Determine an operating mode; the operating mode includes: LVPECL mode and CML mode;

[0011] When the working mode is the LVPECL mode, the line voltages of the eighth line and the seventh line are respectively set to a low level and a high level, and the ninth NMOS tube, the tenth NMOS tube, the third PMOS tube and the fourth PMOS tube are controlled to remain in a closed state;

[0012] The line voltages of the En_LVPEC circuit and the fifth circuit are set to a high voltage and a low voltage respectively, the third NMOS tube, the fourth NMOS tube, the first PMOS tube and the second PMOS tube are controlled to remain in an on state, and the seventh NMOS tube and the eighth NMOS tube are controlled to remain in an off state;

[0013] When the working mode is the CML mode, the line voltages of the sixth line and the fifth line are set to a low level and a high level respectively, and the LVPECL part is controlled to remain in a closed state;

[0014] The line voltage of the En_CML line is set to a high level, and the ninth NMOS transistor and the tenth NMOS transistor are controlled to remain in an on state.

[0015] The present invention discloses the following technical effects:

[0016] The present invention provides a high-speed differential signal driving circuit and an implementation method thereof. By designing a streamlined LVPECL part and a CML part, the problems of large circuit scale and parasitic capacitance of the existing driving circuit are solved, and a driving circuit with lower power consumption and chip area is realized. By sharing an input part with the LVPECL part and the CML part, the problem that a pre-driver needs to be set in a conventional driving circuit is solved, and a driving circuit with higher device utilization is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 A high-speed differential signal driving circuit diagram provided by an embodiment of the present invention;

[0019] Figure 2 LVPECL mode circuit diagram provided by an embodiment of the present invention;

[0020] Figure 3 A CML mode circuit diagram provided by an embodiment of the present invention;

[0021] Description of reference numerals:

[0022] MN1-first NMOS tube, MN2-second NMOS tube, MN3-third NMOS tube, MN4-fourth NMOS tube, MN5-fifth NMOS tube, MN6-sixth NMOS tube, MN7-seventh NMOS tube, MN8-eighth NMOS tube, MN9-ninth NMOS tube, MN10-tenth NMOS tube, MP1-first PMOS tube, MP2-second PMOS tube, MP3-third PMOS tube, MP4-fourth PMOS tube, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, Ib1-adjustable current source, PAD_P-P output end, PAD_N-N output end, Out1_n-first line, Out1_p-second line, Out2_n-third line, Out2_p-fourth line, Enb_LVPECL-fifth line, En_LVPECL-sixth line, Enb_CML_R50-seventh line, En_CML-eighth line. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The purpose of the present invention is to provide a high-speed differential signal driving circuit and its implementation method, which reduces the circuit scale and parasitic capacitance, power consumption and chip area by designing a streamlined LVPECL part and CML part; and eliminates the common pre-driver by sharing the input part of the LVPECL part and the CML part.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Figure 1 A high-speed differential signal driving circuit diagram provided by an embodiment of the present invention, such as Figure 1As shown, the present invention provides a high-speed differential signal driving circuit, including: an input part, an LVPECL part, a CML part and an output part; the input part includes: an adjustable current source Ib1, a first NMOS tube MN1 and a second NMOS tube MN2; the LVPECL part includes: third to eighth NMOS tubes MN8, a first PMOS tube MP1, a second PMOS tube MP2, a first resistor R1 and a second resistor R2; the CML part includes: a ninth NMOS tube MN9, a tenth NMOS tube MN10, a third PMOS tube MP3, a fourth PMOS tube MP4, a third resistor R3 and a fourth resistor R4; the output part includes: a P output terminal PAD_P and an N output terminal PAD_N;

[0027] The gate of the first NMOS tube MN1 is connected to the external positive input terminal; the gate of the second NMOS tube MN2 is connected to the external negative input terminal; the source of the first NMOS tube MN1 and the second NMOS tube MN2 are respectively connected to the first end of the adjustable current source Ib1; the drain of the first NMOS tube MN1 and the second NMOS tube MN2 are respectively connected to the source of the third NMOS tube MN3 and the fourth NMOS tube MN4; the drain of the first NMOS tube MN1 is connected to the source of the tenth NMOS tube MN10 through the third line Out2_n; the drain of the second NMOS tube MN2 is connected to the source of the ninth NMOS tube MN9 through the fourth line Out2_p; the third NMOS tube MN1 is connected to the source of the tenth NMOS tube MN10 through the third line Out2_n; the drain of the second NMOS tube MN2 is connected to the source of the ninth NMOS tube MN9 through the fourth line Out2_p; the drain of ... The gate of the S transistor MN3 is connected to the gate of the fourth NMOS transistor MN4 through the sixth line En_LVPECL; the drains of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are respectively connected to the first ends of the first resistor R1 and the second resistor R2; the drain of the third NMOS transistor MN3 is respectively connected to the gate of the sixth NMOS transistor MN6 and the drain of the eighth NMOS transistor MN8 through the Out1_n line; the drain of the fourth NMOS transistor MN4 is respectively connected to the gate of the fifth NMOS transistor MN5 and the drain of the seventh NMOS transistor MN7 through the second line Out1_p; the second ends of the first resistor R1 and the second resistor R2 are respectively connected to the first PMOS transistor MP1 and the second PMOS transistor MP2. The drain of the MOS tube MP2 is connected; the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2 through the fifth line Enb_LVPECL; the gate of the seventh NMOS tube MN7 is connected to the gate of the eighth NMOS tube MN8 through the fifth line Enb_LVPECL; the gate of the ninth NMOS tube MN9 is connected to the gate of the tenth NMOS tube MN10 through the eighth line En_CML; the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4 through the seventh line Enb_CML_R50; the drains of the third PMOS tube MP3 and the fourth PMOS tube MP4 are connected to the third resistor R3 and the fourth resistor R4 respectively. 4; the P output terminal PAD_P is respectively connected to the source of the fifth NMOS tube MN5, the drain of the ninth NMOS tube MN9 and the first end of the third resistor R3; the N output terminal PAD_N is respectively connected to the source of the sixth NMOS tube MN6, the drain of the tenth NMOS tube MN10 and the first end of the fourth resistor R4; the drains of the first PMOS tube MP1 to the fourth PMOS tube MP4, the drain of the fifth NMOS tube MN5 and the drain of the sixth NMOS tube MN6 are respectively connected to the external high level end; the second end of the adjustable current source Ib1, the source of the seventh NMOS tube MN7 and the source of the eighth NMOS tube MN8 are respectively connected to the external low level end.

[0028] Preferably, the common mode voltage value of the P output terminal PAD_P and the N output terminal PAD_N is controlled by the adjustable current source Ib1 , the first resistor R1 , the second resistor R2 , the third resistor R3 and the fourth resistor R4 .

[0029] Furthermore, a method for implementing a high-speed differential signal driving circuit includes:

[0030] Determine the working mode; the working modes include: LVPECL mode and CML mode;

[0031] When the working mode is the LVPECL mode, the line voltages of the eighth line En_CML and the seventh line Enb_CML_R50 are respectively set to a low level and a high level, and the ninth NMOS tube MN9, the tenth NMOS tube MN10, the third PMOS tube MP3 and the fourth PMOS tube MP4 are controlled to remain in a closed state;

[0032] The line voltages of the En_LVPEC line and the fifth line Enb_LVPECL are set to high voltage and low voltage respectively, the third NMOS tube MN3, the fourth NMOS tube MN4, the first PMOS tube MP1 and the second PMOS tube MP2 are controlled to remain in the on state, and the seventh NMOS tube MN7 and the eighth NMOS tube MN8 are controlled to remain in the off state;

[0033] When the working mode is the CML mode, the line voltages of the sixth line En_LVPECL and the fifth line Enb_LVPECL are set to a low level and a high level respectively, and the LVPECL part is controlled to remain in a closed state;

[0034] The line voltage of the En_CML line is set to a high level, and the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are controlled to remain in an on state.

[0035] Specifically, the first NMOS tube MN1 and the second NMOS tube MN2 are input differential NMOS tubes, and the adjustable current source Ib1 is an adjustable current source. The input tube pair is multiplexed in two modes. The current value of the adjustable current source Ib1 can be configured differently according to different working modes of LVPECL or CML to ensure that the final driver differential output common mode level is a standard value. The input differential signal is connected to the gates of the first NMOS tube MN1 and the second NMOS tube MN2 respectively, and can be in the form of a sine wave or a square wave.

[0036] refer to Figure 2In the LVPECL mode, the eighth line En_CML line voltage = 0 (low level), the seventh line Enb_CML_R50 line voltage = VDD (high level), so the NMOS pair tubes of the CML part, the ninth NMOS tube MN9, the tenth NMOS tube MN10, and the third PMOS tube MP3 and the fourth PMOS tube MP4 are in the off state. The sixth line En_LVPECL line voltage = VDD, the fifth line Enb_LVPECL line voltage = 0, so the third NMOS tube MN3 and the fourth NMOS tube MN4 are turned on, as common source and common gate tubes; the first PMOS tube MP1 and the second PMOS tube MP2 are turned on, and the load resistors, the first resistor R1 and the second resistor R2, are connected to VDD to complete the first stage amplification function, and the output signal second line Out1_p and the first line Out1_n are connected to the second stage NMOS source follower fifth NMOS tube MN5 and the sixth NMOS tube MN6. The seventh NMOS tube MN7 and the eighth NMOS tube MN8 are respectively the gate enable control tubes of the fifth NMOS tube MN5 and the sixth NMOS tube MN6, and are in the off state at this time, that is, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 work in the source follower state. The outputs of the fifth NMOS tube MN5 and the sixth NMOS tube MN6 of the source follower are connected to the P output terminal PAD_P and the N output terminal PAD_N, which are differential output pads (PAD chip pins), and are connected to the off-chip load network through the differential output pins packaged in the chip. In this mode, the adjustable current source Ib1 and the first resistor R1 and the second resistor R2 define the common mode voltage of the second line Out1_p and the first line Out1_n of the first-stage output node, and the voltage follower output characteristics of the second-stage source follower are used to achieve flexible adaptation to the off-chip LVPECL format load network.

[0037] refer to Figure 3In CML mode, the sixth line En_LVPECL line voltage = 0, the fifth line Enb_LVPECL line voltage = VDD, so the third NMOS tube MN3 and the fourth NMOS tube MN4 of the LVPECL part of the NMOS pair are in the off state, and the first PMOS tube MP1 and the second PMOS tube MP2 of the PMOS switch tube are also in the off state; the gates of the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are pulled down to GND (low level) by the seventh NMOS tube MN7 and the eighth NMOS tube MN8, so the circuits in the LVPECL part are all in the off state. In CML mode, the eighth line En_CML line voltage = VDD, so the ninth NMOS tube MN9 and the tenth NMOS tube MN10 of the NMOS pair are turned on, as common source and common gate tubes, and the current of the first NMOS tube MN1 and the second NMOS tube MN2 of the input differential pair tubes is directed to the third resistor R3, the fourth resistor R4 load or the output chip pin. At this time, if the line voltage of the seventh line Enb_CML_R50 = 0, the third resistor R3 and the fourth resistor R4 are enabled as an on-chip load with a typical value of 50 ohms, and together with the adjustable current source Ib1, determine the common mode voltage value of the output stage, and drive the differential voltage signal to the chip pin. At this time, if the line voltage of the seventh line Enb_CML_R50 = VDD, the on-chip resistors of the third resistor R3 and the fourth resistor R4 are high impedance to the on-chip power supply VDD, and it is an open drain amplification mode at this time, for example, the P output terminal PAD_P and the N output terminal PAD_N are connected to the off-chip 50 ohm resistor to the off-chip VDD.

[0038] Optionally, the output structure of this embodiment also has flexible and expandable capabilities. For example, common medium and low speed differential signals LVDS, LVCMOS, etc. can also be connected in parallel to the differential output chip pins, but compatibility with more standards will inevitably introduce more parasitic capacitance and reduce the output stage bandwidth.

[0039] The beneficial effects of the present invention are as follows:

[0040] The present invention reduces the circuit scale and parasitic capacitance, reduces power consumption and chip area by designing a simplified LVPECL part and a CML part; and eliminates the common pre-driver by sharing the input part between the LVPECL part and the CML part.

[0041] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0042] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A high-speed differential signal driving circuit, characterized in that: include: Input part, LVPECL part, CML part and output part; The input part includes: an adjustable current source, a first NMOS transistor and a second NMOS transistor; the LVPECL part includes: third to eighth NMOS transistors, a first PMOS transistor, a second PMOS transistor, a first resistor and a second resistor; the CML part includes: a ninth NMOS transistor, a tenth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third resistor and a fourth resistor; the output part includes: a P output terminal and an N output terminal; The gate of the first NMOS tube is connected to the external positive input terminal; the gate of the second NMOS tube is connected to the external negative input terminal; the source of the first NMOS tube and the second NMOS tube are respectively connected to the first end of the adjustable current source; the drain of the first NMOS tube and the second NMOS tube are respectively connected to the source of the third NMOS tube and the fourth NMOS tube; the drain of the first NMOS tube is connected to the source of the tenth NMOS tube through the third line; the drain of the second NMOS tube is connected to the source of the ninth NMOS tube through the fourth line; the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube through the sixth line; the drain of the third NMOS tube and the fourth NMOS tube are respectively connected to the first end of the first resistor and the second resistor; the drain of the third NMOS tube is respectively connected to the gate of the sixth NMOS tube and the drain of the eighth NMOS tube through the Out1_n line; the drain of the fourth NMOS tube is respectively connected to the gate of the fifth NMOS tube and the drain of the seventh NMOS tube through the second line; the second ends of the first resistor and the second resistor are respectively connected to the first The drain of the PMOS tube is connected to the drain of the second PMOS tube; the gate of the first PMOS tube is connected to the gate of the second PMOS tube through a fifth line; the gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube through a fifth line; the gate of the ninth NMOS tube is connected to the gate of the tenth NMOS tube through an eighth line; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube through a seventh line; the drains of the third PMOS tube and the fourth PMOS tube are respectively connected to the second ends of the third resistor and the fourth resistor; The P output end is respectively connected to the source of the fifth NMOS tube, the drain of the ninth NMOS tube and the first end of the third resistor; the N output end is respectively connected to the source of the sixth NMOS tube, the drain of the tenth NMOS tube and the first end of the fourth resistor; the drains of the first PMOS tube to the fourth PMOS tube, the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are respectively connected to the external high level end; the second end of the adjustable current source, the source of the seventh NMOS tube and the source of the eighth NMOS tube are respectively connected to the external low level end.

2. The method for implementing a high-speed differential signal driving circuit according to claim 1, characterized in that: The common mode voltage value of the P output terminal and the N output terminal is controlled by the adjustable current source, the first resistor, the second resistor, the third resistor and the fourth resistor.

3. A method for implementing a high-speed differential signal driving circuit, characterized in that: A high-speed differential signal driving circuit according to claim 1, wherein the method comprises: Determine an operating mode; the operating mode includes: LVPECL mode and CML mode; When the working mode is the LVPECL mode, the line voltages of the eighth line and the seventh line are respectively set to a low level and a high level, and the ninth NMOS tube, the tenth NMOS tube, the third PMOS tube and the fourth PMOS tube are controlled to remain in a closed state; The line voltages of the En_LVPEC circuit and the fifth circuit are set to a high voltage and a low voltage respectively, the third NMOS tube, the fourth NMOS tube, the first PMOS tube and the second PMOS tube are controlled to remain in an on state, and the seventh NMOS tube and the eighth NMOS tube are controlled to remain in an off state; When the working mode is the CML mode, the line voltages of the sixth line and the fifth line are set to a low level and a high level respectively, and the LVPECL part is controlled to remain in a closed state; The line voltage of the En_CML line is set to a high level, and the ninth NMOS transistor and the tenth NMOS transistor are controlled to remain in an on state.

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