Parameter extraction method for equivalent circuit model of GaN HEMT device

Abstract

The invention discloses a method for extracting parameters of an equivalent circuit model of a GaN HEMT device. The method at least comprises the following steps of S1, modeling the GaN HEMT device into a small-signal equivalent circuit model; s2, extracting external parasitic parameters based on the model in the step S1; s3, internal intrinsic parameters are extracted; in the step S1, the equivalent circuit model comprises external parasitic parameters and internal intrinsic parameters, and the external parasitic parameters are not affected by applied bias voltage and comprise parasitic capacitances Cpg, Cpd and Cpg between metal electrodes, external parasitic inductances Lg, Ld and Ls and external parasitic resistances Rg, Rd and Rs; internal intrinsic parameters are influenced by a channel structure and a bias condition when the device works, and comprise a channel resistor Rgs, a gate-drain resistor Rgd and a drain-source output conductor Gds; capacitors Cgs, Cgd and Cds are arranged among the ports; the transconductance is gm, and the time delay parameter is tau.

Description

Technical Field

[0001] The present invention belongs to the technical field of GaN HEMT, and particularly relates to a method for extracting parameters of an equivalent circuit model of a GaN HEMT device. Technical Background

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) have characteristics such as high-frequency response, high breakdown voltage, and high reliability due to the unique properties of GaN-based materials, and are ideal devices for high-power applications. Any system-level design such as GaN amplifiers, oscillators, and mixers requires an accurate device model, and this accurate model should be able to simulate phenomena including breakdown characteristics, forward conduction, and dispersion effects. The accurate extraction of small-signal circuit models helps to understand the circuit behavior of devices. In addition, it also plays a key role in analyzing how microwave performance changes with the variation of device geometry. Therefore, the effectiveness of device modeling highly depends on the accuracy of small-signal models.

[0003] One of the main objectives of device modeling is to accurately describe the radio-frequency input and output characteristics of devices, ensuring that the electrical characteristics of devices can be described by mathematical expressions under any working conditions and external environments. Compact models (equivalent circuit models) are usually established based on limited measurement data obtained through specific measurement techniques to ensure that the models can cover all working states of devices.

[0004] In existing research, scholars have conducted detailed research on the equivalent circuit topologies of small-signal models. However, there is no precise and perfect optimization method for extracting the intrinsic parameters inside the models. Most scholars choose to take the average value of the intrinsic parameters within the entire frequency band as the model parameters, without considering the actual application scenarios of devices (such as high-frequency devices), nor the influence degree of the intrinsic parameters on the entire circuit model.

[0005] However, in practical applications, the reasonable value of the intrinsic parameters greatly affects the results of model simulation, restricting the accuracy and stability of the models.

[0006] Therefore, in view of the technical defects existing in the prior art, it is necessary to propose a solution to solve the technical problems existing in the prior art. Summary of the Invention

[0007] Based on the above objectives, the present invention proposes a method for extracting parameters of a small-signal equivalent circuit model of a GaN HEMT device, which can optimize the extracted values of the intrinsic parameters according to the application frequency band of the device. This method can quantify the error of the circuit model, further improving the accuracy and stability of the small-signal equivalent circuit model, thereby improving the R & D efficiency of GaN HEMT radio-frequency devices, shortening the R & D cycle, and providing strong support for the technological progress and product performance of related industries.

[0008] To solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:

[0009] A method for extracting parameters of an equivalent circuit model of a GaN HEMT device, at least including the following steps:

[0010] Step S1: Model the GaN HEMT device as a small-signal equivalent circuit model;

[0011] Step S2: Based on the model in Step S1, extract external parasitic parameters;

[0012] Step S3: Extract internal intrinsic parameters;

[0013] In Step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters. Among them, the external parasitic parameters are not affected by the applied bias voltage, including parasitic capacitances C pg , C pd and C pg , external parasitic inductances L g , L d and L s , and external parasitic resistances R g , R d and R s ; the internal intrinsic parameters are affected by the channel structure and bias conditions during device operation, including channel resistance R gs , gate-drain resistance R gd , drain-source output conductance G ds ; capacitances C gs , C gd , C ds between each port; transconductance g m , delay parameter τ;

[0014] The said Step S3 further includes the following steps:

[0015] After extracting the external parasitic parameters, measure the S parameters of the device at the bias operating point, and use the matrix network transformation formula to de-embed the external parasitic parameters to obtain the intrinsic Y parameters of the device; the expressions for extracting the intrinsic parameters are as follows:

[0016]

[0017] G ds = Re(Y 22 + Y 12 )

[0018] g m = mag(Y 21 - Y 12 )

[0019]

[0020] Obtain the maximum point of the device transconductance as the selected operating point of the device, and obtain the curves of the extracted values of each intrinsic parameter within 0 - 40 GHz under this bias through the above formula;

[0021] Calculate the average value of each intrinsic parameter over the entire frequency band; define the model error as:

[0022]

[0023] where S Sim，ij is the simulated S - parameter data, and S Mea，ij is the measured S - parameter data;

[0024] Let the difference between the upper and lower limits of the model error be γ, and let the extracted value of a certain intrinsic parameter at a certain frequency point be A. Let:

[0025]

[0026] where, is the average value of this intrinsic parameter over the entire frequency band, and α is the ratio of the extracted value at this frequency point to the average value over the entire frequency band;

[0027] Substitute the extracted value A of a certain intrinsic parameter into the circuit model for simulation, take the average values of other intrinsic parameters over the entire frequency band, calculate different α and their corresponding upper and lower limits γ of the model accuracy error, and take the lowest value of γ as the extracted value of this intrinsic parameter; extract all internal intrinsic parameters in this way.

[0028] As a further improvement scheme, the gate length of the GaN HEMT device is 100 nm, the total gate width is 75 μm, where the single - finger gate width is 37.5 μm, and the gate index is 2.

[0029] As a further improvement scheme, in step S2, when extracting the external parasitic capacitance, the following steps are included:

[0030] Under low - frequency conditions and in the channel - off state, simplify the small - signal equivalent circuit of the GaN HEMT device into a circuit model containing only capacitors;

[0031] Test the S - parameters of the device after de - embedding. The imaginary part of the Y - parameter of the device after de - embedding has the following linear relationship with the angular frequency:

[0032] Im(Y 11 ) = ω(C pg + C gs + C pgd + C gd )

[0033] Im(Y 22 ) = ω(C pd + Cds +C pgd +C gd )

[0034] Im(Y 12 ) = Im(Y 21 ) = -ω(C pgd +C gd )

[0035] The extraction of parasitic capacitance is optimized using the annealing algorithm;

[0036] First, initialize the capacitances C pg , C pd , C b to small values, calculate the error between the simulation results and the measured data, and gradually adjust their values until the optimal capacitance values are obtained;

[0037] Next, optimize C pgd , with an initial value of 0, and adjust it through simulation until the minimum error is obtained to get C pgd ; finally, optimize C gs and C gd using the annealing algorithm to obtain C gs , C gd ; ultimately, the optimized external parasitic capacitance values are obtained.

[0038] As a further improvement, in step S2, when extracting the external parasitic inductance, the following steps are included:

[0039] Under the cold field - cutoff condition, the equivalent circuit model at high frequencies ignores the capacitive reactance and considers the influence of the channel distributed resistance R c . By deriving the Z - parameters in the equivalent circuit, the expression of its imaginary part is obtained, and a graph is plotted with ω 2 as the abscissa and ω·Im(Z) of the imaginary part as the ordinate; thus, three parasitic inductance values are extracted from the slope of the curve, and the specific extraction formulas are as follows:

[0040]

[0041] where, R g , R s , R d are the parasitic resistance values, L g , L s , L d are the parasitic inductance values, C g , C s , C d are the parasitic capacitance values; multiplying both sides of the above three equations by the angular frequency ω can obtain the imaginary part of the Z - parameter as:

[0042]

[0043]

[0044] With ω 2 as the abscissa and the imaginary part of ωZ as the ordinate, draw a straight line, and the slope of the straight line is the extracted value of the three parasitic inductances.

[0045] Compared with the prior art, the present invention models the GaN HEMT device as a small-signal equivalent circuit model, and can optimize the extracted value of the intrinsic parameters according to the device application frequency band. This method can quantify the error of the circuit model, further improve the accuracy and stability of the small-signal equivalent circuit model, thereby improving the R & D efficiency of the GaN HEMT radio frequency device, shortening the R & D cycle, and providing strong support for the technological progress and product performance of related industries. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a three-dimensional view of the small-signal equivalent circuit model of the GaN HEMT device of the present invention;

[0047] Figure 2 is a plan view of the small-signal equivalent circuit model of the GaN HEMT device of the present invention;

[0048] Figure 3 is a schematic diagram of the principle of the small-signal equivalent circuit under the low-frequency cold-field - cut-off condition of the present invention;

[0049] Figure 4 is a schematic diagram of the principle of the small-signal equivalent circuit under the high-frequency cold-field - cut-off condition of the present invention;

[0050] Figure 5 is for Im(ωZ ij ) versus ω 2 variation curve schematic diagram under the high-frequency cold-field - cut-off condition of the present invention;

[0051] Figure 6 is for Re(Z ij ) versus 1 / (V gs -V th ) variation curve schematic diagram;

[0052] Figure 7 is a schematic diagram of the small-signal equivalent circuit diagram under the cold-field - cut-off condition of the present invention;

[0053] Figure 8 is a comparison schematic diagram of the measured value and the simulated value of the small-signal equivalent circuit under the cold-field - cut-off state within 0 - 40 GHz;

[0054] Figure 9 is a schematic diagram of the extracted value curve of each intrinsic parameter under this bias within 0 - 40 GHz;

[0055] Figure 10 Schematic diagram for comparing the small-signal equivalent circuit model with the test results of the actual device when using the full-band average value as the model parameter

[0056] Figure 11 Schematic diagram for the influence of adjusting a single intrinsic parameter value on the simulated S parameters

[0057] Figure 12 Schematic diagram for the influence of taking the intrinsic parameter values at different frequency points on the model error stability

[0058] Figure 13 Schematic diagram for comparing the circuit model errors after optimizing the extracted intrinsic parameters Detailed implementation manner

[0059] The present invention provides a method for extracting parameters of an equivalent circuit model of a GaN HEMT device, which at least includes the following steps:

[0060] Step S1: Model the GaN HEMT device as a small-signal equivalent circuit model;

[0061] Step S2: Based on the model in step S1, extract the external parasitic parameters;

[0062] Step S3: Extract the internal intrinsic parameters;

[0063] In step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters. Among them, the external parasitic parameters are affected by reasons such as the physical size of the device and are not affected by the applied bias voltage, including the parasitic capacitances C pg , C pd and C pg , the external parasitic inductances L g , L d and L s , and the external parasitic resistances R g , R d and R s ; the internal intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R gs , the gate-drain resistance R gd , the drain-source output conductance G ds ; the capacitances C gs , C gd , C ds between each port; the transconductance g m , the delay parameter τ, etc. See Figure 1 and Figure 2, shown are the cubic diagram and the planar diagram of the small-signal equivalent circuit model of the GaN HEMT device adopted by the present invention, which altogether include 17 elements. Among them, the intrinsic parameters of the model are within the dotted line frame and are related to the bias applied to the device. The GaN HEMT device used in the example of the present invention has a designed gate length of 100 nm, a total gate width of 75 μm, a single-finger gate width of 37.5 μm, a gate index of 2, and a radio frequency test data frequency band range of 0 to 40 GHz.

[0064] In step S2, the specific extraction process includes:

[0065] (1) External parasitic capacitance extraction

[0066] Under low-frequency conditions (usually less than 3 GHz) and in the channel-off state, ignoring the influence of the inductor, the small-signal equivalent circuit of the GaN HEMT device is simplified to a circuit model containing only capacitors. Refer to Figure 3 . The extraction of the parasitic capacitance is optimized using the annealing algorithm. First, initialize the capacitances C pg , C pd , C b to small values, and calculate the error between the simulation results and the measured data, and gradually adjust their values until the optimal capacitance values (C pg = 2.50 fF, C pd = 2.46 fF, C b = 23.48 fF) are obtained. Then, optimize C pgd , with the initial value set to 0, and adjust it through simulation until the minimum error is obtained, resulting in C pgd = 1.05 fF. Finally, considering the influence of the gate-drain spacing, further optimize C gs and C gd , and finally obtain C gs = 22.99 fF, C gd = 24.05 fF through the annealing algorithm. After these steps, the optimized external parasitic capacitance values are finally obtained.

[0067] The key to extracting the external parasitic parameters of the small-signal model is to simplify Figure 2 the equivalent circuit at a specific bias point. At low frequencies (usually below 3 GHz), the inductive reactance jωL is very small and can be ignored, and under the channel-off condition (i.e., the cold-field - cut-off condition), the transistor current is almost non-existent. At this time, it is equivalent to a passive device. Therefore, the small-signal circuit model can be equivalent to a circuit with only capacitive reactance, as shown in Figure 3 . Considering comprehensively, the present invention selects the test data at 1 GHz to extract the parasitic parameters.

[0068] Under the cold-field - cut-off condition (V gs < V th , V ds = 0 V), where, V thThe threshold voltage of the device for measurement is -2V. The S-parameters of the device after de-embedding are tested. From the circuit structure relationship of Figure 3 , it can be known that the imaginary part of the Y-parameter of the device after de-embedding has a linear relationship with the angular frequency as described by the following formula:

[0069] Im(Y 11 ) = ω(C pg + C gs + C pgd + C gd )

[0070] Im(Y 22 ) = ω(C pd + C ds + Ck pgd + C gd )

[0071] Im(Y 12 ) = Im(Y 21 ) = -ω(C pgd + C gd )

[0072] Where C pg , C pd , C pgd are external parasitic capacitances, and C gs , C ds , C gd are the channel capacitance values under the cut-off condition.

[0073] From the above analysis, the general idea of extracting the external parasitic capacitance is to solve six unknowns. Using the method of solving three unknowns with three equations, first determine the equivalent relationship of three unknowns using the physical dimensions of the device, and then solve the remaining three unknowns using the equations. Subsequently, since the equivalent relationship of the three unknowns obtained from the physical dimensions is not completely equivalent, but the values of the three unknowns have been obtained in the first step, scan the remaining parameters starting from 0 and solve the equations to obtain the most appropriate values. When extracting the external parasitic capacitance, it can be divided into three steps:

[0074] First, when the device is in the cut-off state, it can be considered that the depletion region widths of the gate-source and gate-drain are the same, that is, C gs = C gd = C b and C ds = 0. Since the parasitic capacitance C pgd is the parasitic capacitance between the gate-drain metal electrodes, its value is much smaller than C pg and C pd , so this value is ignored in the first step.

[0075] Adopt the annealing algorithm. By initializing the capacitance, from C pg , C pd, C b Starting from the small value of b , its value is gradually and randomly adjusted, and the adjusted capacitor combination is substituted into the circuit model for simulation to calculate the error between the simulation value and the measured value. The algorithm determines whether the new capacitor value is better by calculating the change in the error between the simulation value and the measured value, and gradually adjusts the parameter search range during the optimization process to ensure that the error gradually decreases, and finally obtains the capacitor value that best matches the measured data. When the error between the simulation value and the measured data is the smallest, the values of the three capacitors are C pg = 2.50 fF, C pd = 2.46 fF, C b = 23.48 fF.

[0076] Secondly, with the other parameters unchanged, the annealing algorithm is used to optimize C pgd . First, C pgd is initialized to 0, its value is gradually adjusted starting from a small range, and circuit simulation is performed after each adjustment to calculate the error between the simulation value and the measured data. When the error between the simulation value and the measured data is the smallest, the capacitor value C pgd = 1.05 fF is obtained.

[0077] Finally, since the distance between the gate and drain electrodes is very small, it can be considered that the extracted C pgd is a fixed value, and due to the electrode size, C gs will not be exactly equal to C gd . The annealing algorithm is used to scan C gs and C gd starting from 23.48 fF and perform circuit simulation. When the error between the simulation value and the measured data is the smallest, the capacitor values C gs = 22.99 fF, C gd = 24.05 fF are obtained.

[0078] In summary, finally, the values of C pg , C pd , C pgd obtained using the annealing algorithm are the external parasitic capacitance parameter values.

[0079] (2) Extraction of external parasitic inductance

[0080] Under the cold field - cut - off condition, when the frequency exceeds 25 GHz, the capacitive reactance of the parasitic capacitance can be ignored, and the equivalent circuit diagram of the device under this condition is shown in Figure 4 . The equivalent circuit model at high frequencies ignores the capacitive reactance and considers the influence of the channel distributed resistance R c . By deriving the Z - parameter in the equivalent circuit, the expression of its imaginary part is obtained, and with ω 2Plot with the real part ω·Re(Z) as the abscissa and the imaginary part ω·Im(Z) as the ordinate. From this, the values of three parasitic inductances can be extracted from the slope of the curve.

[0081] From Figure 4 the Z-parameter relationship of the equivalent circuit can be obtained:

[0082]

[0083] where R g , R s , R d are parasitic resistance values, L g , L s , L d are parasitic inductance values, C g , C s , C d are parasitic capacitance values. Multiplying both sides of the above three equations by the angular frequency ω simultaneously, the imaginary part of the Z-parameter can be obtained as:

[0084]

[0085] Taking ω 2 as the abscissa and the imaginary part of ωZ as the ordinate to draw a straight line. Therefore, in the Z-parameter becomes the intercept, and the slope of the straight line is the extracted value of the three parasitic inductances. See Figure 5 , which shows the schematic diagram of the curve of Im(ωZ ij ) varying with ω 2 under the high-frequency cold field - cut-off condition of the present invention, which is the extraction result.

[0086] (3) External parasitic resistance extraction

[0087] The extraction of parasitic resistance needs to be carried out under high-frequency conditions and the influence of the channel distributed resistance R c should be considered. In the small-signal state, ignoring the heating effect, the channel distributed resistance is proportional to 1 / (V gs - V th ). When 1 / (V gs - V th ) approaches zero, the value of R c can be ignored. The extraction of parasitic resistance is calculated through the intercept of the real part of the Z-parameter. By measuring the Z-parameter at different bias voltages (such as V gs = -0.5V, 0V, 0.5V, 1V, 1.5V) and fitting a straight line, finally calculating the intercept of the fitted straight line on the Y-axis to obtain the parasitic resistance value. The expression formula of the channel distributed resistance Rc and the formula of the real part of the Z-parameter are as follows:

[0088] Extracting the external parasitic resistance needs to be carried out at high frequencies. Since the device channel behaves as a transmission line with distributed effects when conducting at this time, the channel distributed resistance R c must be considered when extracting the parasitic resistance parameters. Because the heating effect of the device can be ignored in the small-signal state, the channel distributed resistance R c does not consider temperature correlation here, and its expression is as follows:

[0089]

[0090] where L channel , W channel are the channel length and width respectively, μ n，channel is the channel electron mobility, and C ox is the gate oxide capacitance. The above formula shows that R c is proportional to 1 / (V gs -V th ). When 1 / (V gs -V th ) approaches zero, the value of R c can be ignored. Taking the real part intercept of the Z-parameter relationship is the parasitic resistance value. Therefore, the real part of the Z-parameter can be rewritten as:

[0091]

[0092] According to the above formula, select to measure the Z-parameter values at the bias points V gs =-0.5V, 0V, 0.5V, 1V, 1.5V, V ds =0V, and fit a straight line to the parameter values under different biases. See Figure 6 . The figure shows the schematic diagram of the curve of Re(Z ij ) varying with 1 / (V gs -V th ). Calculating the intercept of the fitted straight line on the Y-axis can obtain the extracted value of the parasitic resistance.

[0093] (4) Verification of external parasitic parameters

[0094] To verify the accuracy of the extracted value of the parasitic parameter, it can be judged by comparing the measured value with the simulated value under the cold-field - cut-off condition. See Figure 7 . The figure shows the small-signal equivalent circuit diagram under the cold-field - cut-off condition in the present invention.

[0095] The result obtained by constructing the extracted value of the parasitic parameter into a circuit in ADS (Advanced Design System) software and simulating it within 0 - 40 GHz. See Figure 8 . The figure shows the comparison schematic diagram of the measured value and the simulated value of the small-signal equivalent circuit under the cold-field - cut-off state within 0 - 40 GHz.Figure 8 It shows that the measured values match well with the circuit simulation values, and the parasitic parameter values are accurately extracted. Due to external reasons such as test equipment, test RF data will oscillate at high frequencies, so the error of the simulation values at high frequencies is inevitable.

[0096] Step S3 further includes the following steps:

[0097] (1) Internal intrinsic parameter extraction

[0098] After extracting the parasitic parameters, by measuring the S parameters of the device at the bias operating point and using the matrix network transformation formula to de-embed the external parasitic parameters, the intrinsic Y parameters of the device can be obtained. The expressions for extracting the intrinsic parameters are as follows:

[0099]

[0100] G ds =Re(Y 22 +Y 12 )

[0101] g m =mag(Y 21 -Y 12 )

[0102]

[0103] Through DC testing, it can be known that the device has a maximum transconductance point when the bias gate voltage is V gs =-1V and V ds =10V. This point is the operating point selected for the device of the present invention example. The curves of the extracted values of each intrinsic parameter under this bias within 0 to 40 GHz are obtained through the above formula, as Figure 9 shown. Among them, Figure 9 (a) is C ds 、C gs 、C gd ; Figure 9 (b) is G ds 、g m ; Figure 9 (c) is R gs 、R gd , Figure 9 (d) is τ, and the extracted values of each intrinsic parameter under the bias V gs =-1V and V ds =10V within 0 to 40 GHz.

[0104] In the prior art, the above-mentioned extracted average value of the entire frequency band is used as a model parameter. However, inaccurate intrinsic parameter values will increase the error of the model. In order to further improve the accuracy and stability of the circuit model, the present invention proposes a quantization error analysis method, which can more accurately extract the numerical values of each internal intrinsic parameter.

[0105] From Figure 9 each intrinsic parameter is obtained, and the average value in the entire frequency band is calculated, as shown in Table 1 below.

[0106] Table 1 Average value of each intrinsic parameter in the entire frequency band

[0107] <![CDATA[C gs > 92.92 fF <![CDATA[C gd > 6.25 fF <![CDATA[C ds > 15.14 fF <![CDATA[R gs > 3.90 Ω <![CDATA[R gd > 169.14 Ω <![CDATA[G ds > 1.35 mS <![CDATA[g m > 50.84 mS τ 1.23 ps

[0108] The obtained external parasitic parameters and the extracted values of the internal intrinsic parameters are substituted into the circuit model for simulation. And in order to further evaluate the accuracy of the small-signal equivalent circuit model, the model error is defined as:

[0109]

[0110] Where S Sim，ij is the simulated S-parameter data, and S Mea，ij is the measured S-parameter data.

[0111] The obtained simulation data and the measured data results are as follows Figure 10 shown, where Figure 10 (a) is the comparison between the model-simulated S-parameters and the measured S-parameters of the actual device, Figure 10 (b) is the curve of the error between the model-simulated result and the actual measurement result changing with frequency.

[0112] From Figure 10 the results, it can be seen that the model accuracy gradually decreases as the frequency increases, which does not meet the requirements of the high-frequency device model. Let the difference between the upper and lower limits of the model error be γ, which reflects the stability of the model accuracy in the entire frequency band. In the above figure, γ is 7.465%, indicating that the performance of the model in the entire frequency band is not accurate.

[0113] (2) Optimize the extracted values of the internal intrinsic parameters

[0114] Therefore, the purpose of the present invention is to further reduce the model error by optimizing the numerical values of the intrinsic parameters. It is necessary to optimize and adjust the initial values of the extracted intrinsic parameters. In the adjustment, it is found by comparison that adjusting only the value of parameter R gs significantly affects only the S 11 parameter, and has almost no effect on the remaining S parameters. Similarly, parameters g m , C gd and C ds also show an impact on specific S parameters. See Figure 11, showing the influence of adjusting a single intrinsic parameter value on the simulated S-parameters, where Figure 11 (a) shows the relationship between R gs -S 11 ; Figure 11 (b) shows the relationship between C gd -S 12 ; Figure 11 (c) shows the relationship between g m -S 21 ; Figure 11 (d) shows the relationship between C ds -S 22 . Figure 11 It shows the specific influence on the S-parameters after adjusting each parameter.

[0115] From Figure 11 it can be seen that the simulation results of the small-signal model are greatly affected by the above four intrinsic parameter values. Therefore, the present invention proposes a quantitative error analysis method. It can be found from Figure 9 that the extracted values of these four intrinsic parameters show a pattern of increasing with the increase of frequency. Taking R gs as an example, the average value within the entire frequency band is 3.90 Ω. At low frequencies, R gs has a minimum value of 2.78 Ω, and at high frequencies, it has a maximum value of 4.63 Ω. Now, assume that the extracted value of any intrinsic parameter (such as R gs ) at a certain frequency point is A, and let:

[0116]

[0117] is the average value within the entire frequency band, and α is the ratio of the extracted value at this frequency point to the average value of the entire frequency band. For example, according to the calculation, the range of α is 0.71 - 1.19. Substitute the extracted value A into the circuit model for simulation, and take the average values of other parameters in the entire frequency band to make α correspond to the upper and lower limits γ of the model accuracy error. See Figure 12 , which shows a schematic diagram of the influence of taking the intrinsic parameter values at different frequency points on the model error stability. It can be found that when adjusting the values of these four intrinsic parameters (which have the greatest influence on the model accuracy), γ will have a lowest point when α > 1, indicating that the small-signal circuit model error is the most stable at this time. And due to its pattern of gradually increasing with the increase of frequency, that is, taking the values in the high-frequency band (α > 1), it also meets the working conditions of the device at high frequencies.

[0118] Set the values of these four intrinsic parameters as Figure 12 the value of the lowest point of γ in Figure 13 , and combine with other model parameters extracted before. Substitute the small-signal equivalent circuit model into the ADS software for simulation to obtain the model after optimization and the actual measurement results. See Figure 13 , which shows a schematic diagram of the circuit model error comparison after optimizing the extracted intrinsic parameters.

[0119] It is found from Figure 13 that the stability of the small-signal circuit model after optimizing the intrinsic parameters (i.e., γ = 3.46%) is significantly improved compared with that before optimization (γ = 7.465%), and the error accuracy of the model in the high-frequency part is as low as 2.01% at minimum, meeting the working conditions of the device at high frequencies. It is proved that the present invention has a remarkable effect on reducing the error rate of the small-signal circuit model and improving the stability of the model, and has certain practical value for further improving the accuracy of the small-signal model.

[0120] For the above technical solution of the present invention, the method for extracting and optimizing the intrinsic parameters of the small-signal circuit model is proposed. Compared with the method of extracting the intrinsic parameters in the prior art, which takes the average value of the full frequency band, the present invention adopts a quantitative error analysis method to extract the intrinsic parameter values at specific frequency points by quantitatively analyzing the error stability of the model. At the same time, the present invention proposes four component parameters that have the greatest influence on the simulation results of the model among the intrinsic parameters inside the model. The optimized circuit model not only has a significant improvement in accuracy, but also fully enhances the error stability in the full frequency band.

[0121] The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0122] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in the present invention can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in the present invention, but will conform to the widest scope consistent with the principles and novel features disclosed in the present invention.

Claims

1. A method for extracting parameters of an equivalent circuit model of a GaN HEMT device, characterized in that: At least the following steps are included: Step S1: Modeling the GaN HEMT device as a small signal equivalent circuit model; Step S2: extracting external parasitic parameters based on the model of step S1; Step S3: extracting internal intrinsic parameters; In step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters, wherein the external parasitic parameters are not affected by the applied bias voltage, including the parasitic capacitance C between the metal electrodes. pg , C pd and C pg , external parasitic inductance L g , L d and L s , and the external parasitic resistance R g , R d and R s ; The internal intrinsic parameters are affected by the channel structure and bias conditions when the device is working, including the channel resistance R gs , gate-drain resistance R gd , drain-source output conductance G ds ; Capacitance C between each port gs , C gd , C ds ; Transconductance g m , delay parameter τ; The step S3 also includes the following steps: After extracting the external parasitic parameters, the intrinsic Y parameters of the device are obtained by measuring the S parameters of the device at the bias operating point and using the matrix network transformation formula to remove the external parasitic parameters; the expression for extracting the intrinsic parameters is as follows: G ds =Re(Y 22 +Y 12 ) g m =mag(Y 21 -AND 12 ) The maximum transconductance point of the device is obtained as the selected working point of the device, and the extraction value curves of each intrinsic parameter under the bias within 0 to 40 GHz are obtained by the above formula; The average value of each intrinsic parameter in the whole frequency band is calculated; the model error is defined as: Where S Sim,ij is the simulated S parameter data, S Mea,ij It is the test S parameter data; Assume that the difference between the upper and lower limits of the model error is γ, and the extracted value of a certain intrinsic parameter at a certain frequency point is A, and let: in, is the average value of the intrinsic parameter in the whole frequency band, and α is the ratio of the extracted value at this frequency point to the average value of the whole frequency band; Substitute a certain intrinsic parameter extraction value A into the circuit model for simulation, take the average value of the whole frequency band for other intrinsic parameters, calculate the upper and lower limits γ of the model accuracy error corresponding to different α, and take the value of the lowest point of γ as the extraction value of the intrinsic parameter; in this way, all internal intrinsic parameters are extracted.

2. The parameter extraction method of the GaN HEMT device equivalent circuit model according to claim 1, characterized in that: The gate length of the GaN HEMT device is 100nm, the total gate width is 75um, of which the single-finger gate width is 37.5um and the gate index is 2.

3. The parameter extraction method of the GaN HEMT device equivalent circuit model according to claim 2, characterized in that: In step S2, when extracting the external parasitic capacitance, the following steps are included: Under low frequency conditions and in the channel off state, the small signal equivalent circuit of the GaN HEMT device is simplified to a circuit model containing only capacitors; The S parameters of the test device after de-embedding, the imaginary part of the Y parameter of the device after de-embedding and the angular frequency are linearly related as described in the following formula: In(Y 11 )=ω(C pg +C gs +C pgd +C gd ) In(Y 22 )=ω(C pd +C ds +C pgd +C gd ) In(Y 12 )=In(Y 21 )=-ω(C pgd +C gd ) The annealing algorithm is used to optimize the extraction of parasitic capacitance; First, initialize the capacitor C pg , C pd , C b The value is minimized, and the error between the simulation calculation and the measured data is gradually adjusted to obtain the optimal capacitance value. Next, optimize C pgd , the initial value is set to 0, and when it is adjusted to the minimum error through simulation, C pgd ; Finally, optimize C gs and C gd , C is obtained by annealing algorithm gs , C gd ; Finally, the optimized external parasitic capacitance value is obtained.

4. The method for extracting parameters of the GaN HEMT device equivalent circuit model according to claim 2, characterized in that: In step S2, when extracting the external parasitic inductance, the following steps are included: Under cold field-cutoff conditions, the equivalent circuit model at high frequencies ignores the capacitive reactance and considers the channel distributed resistance R c The influence of the Z parameter in the equivalent circuit is deduced to obtain the expression of its imaginary part, and the expression of 2 Plot the graph with ω·Im(Z) as the horizontal coordinate and the imaginary part ω·Im(Z) as the vertical coordinate; thus, the values ​​of the three parasitic inductances are extracted from the slope of the curve. The specific extraction formula is as follows: Among them, R g , R s , R d is the parasitic resistance value, L g , L s , L d is the parasitic inductance value, C g , C s , C d is the parasitic capacitance value; multiplying the angular frequency ω on both sides of the above three equations can obtain the imaginary part of the Z parameter: ω 2 Draw a straight line with ω as the horizontal coordinate and the imaginary part of ωZ as the vertical coordinate. The slope of the straight line is the extracted value of the three parasitic inductances.

Images