A control method of a single-phase common ground type five-level inverter of double negative one state

Abstract

The application discloses a control method of a single-phase common ground type five-level inverter of double negative one state. Firstly, a sine modulation signal is compared with four same-phase laminated triangular carriers to generate four preprocessed signals, and the voltage value of a switching capacitor C2 is compared with a preset reference voltage value to generate one preprocessed signal. Then, according to the switching state of the inverter under six working modes, the above-mentioned five preprocessed signals are used for logic operation to obtain the control signals of each switching tube. The control method of the application adopts a synergic control method combining the carrier same-phase laminated modulation technology with the switching capacitor voltage hysteresis control, can make the switching capacitor voltage in the inverter stable at U PV , the output voltage of the negative half cycle is not distorted, the output voltage waveform quality is high, meanwhile, the capacitor voltage fluctuation frequency is reduced, and the switching loss of part of the switching tubes is reduced, which is beneficial to improving the efficiency of the inverter and improving the anti-interference ability of the inverter.

Description

Technical Field

[0001] This invention belongs to the field of power electronics DC-AC conversion technology, specifically relating to a control method for a single-phase common-ground five-level inverter with dual negative one-state. Background Technology

[0002] To address challenges such as energy depletion and environmental pollution, vigorously developing and utilizing renewable energy has become a global consensus. Solar energy, with its wide distribution and flexible development advantages, has stood out among numerous new energy sources. By the end of 2025, the cumulative installed power generation capacity in China reached 3.89 billion kilowatts, of which solar power generation capacity reached 1.2 billion kilowatts, a year-on-year increase of 35.4%. It is projected that by 2030, the cumulative installed capacity of photovoltaic power will exceed 2 billion kilowatts, making photovoltaic power generation a core power source in my country's energy structure. By 2035, it is expected to surpass thermal power to become the largest power source, accounting for nearly one-third of total power generation.

[0003] As one of the core components of a photovoltaic (PV) power generation system, the photovoltaic (PV) inverter directly determines the overall operating efficiency and safety stability of the system. Based on electrical isolation methods, PV inverters can be divided into isolated and non-isolated types. Isolated inverters, due to the presence of a transformer, have lower efficiency, larger size, and higher cost. Non-isolated inverters, by eliminating the transformer, improve efficiency, size, and cost. However, due to the lack of electrical isolation provided by the transformer, the parasitic capacitance of the PV cells to ground generates common-mode voltage under high-frequency switching operations, leading to common-mode leakage current. The presence of common-mode leakage current causes electromagnetic interference and radiation to the power system, resulting in harmonic distortion of the grid-connected current and reducing conversion efficiency. In research on leakage current suppression in non-isolated PV inverters, topology optimization or modulation strategy optimization are typically used to suppress common-mode voltage variations.

[0004] Among these, the common-ground topology is the most effective improvement for suppressing leakage current. By connecting the DC-side negative terminal and the AC-side neutral point to a common ground, leakage current can be completely suppressed. However, this topology has an inherent drawback: the switched capacitor in its inverter main circuit continuously discharges during the negative half-cycle of the output, and the effective charging time is insufficient to replenish the capacitor charge, resulting in waveform distortion during the negative half-cycle of the output voltage. Existing mainstream modulation strategies, including carrier stacking modulation, carrier phase shift modulation, and space vector modulation, cannot effectively improve the waveform distortion during the negative half-cycle. To address this issue, existing research employs a single-threshold comparison control method for the switched capacitor voltage. By optimizing the capacitor charging time, effective charge replenishment is achieved, maintaining capacitor voltage stability and effectively suppressing output voltage waveform distortion. However, this method significantly increases the frequency of switched capacitor voltage fluctuations, increases the switching losses of the switching transistors, and reduces the inverter's anti-interference capability.

[0005] In view of this, it is indeed necessary to design a novel single-phase common-ground inverter and control method to solve the above problems. Contents of the Invention

[0006] The main objective of the present invention is to propose a cooperative control method combining carrier phase-disposition modulation technology and switched-capacitor voltage hysteresis control for a novel single-phase common-ground inverter main circuit, which effectively solves the problem of continuous discharge of the switched capacitor in the negative half-cycle of existing common-ground inverters, resulting in no distortion of the output voltage in the negative half-cycle and high quality of the output voltage waveform; meanwhile, the introduction of switched-capacitor voltage hysteresis control can reduce the capacitance voltage fluctuation frequency, thereby reducing the switching loss of part of the switching tubes, and improving the efficiency and anti-interference capability of the inverter.

[0007] To achieve the above inventive objective, the present invention provides a control method for a single-phase common-ground inverter. The single-phase common-ground inverter is a single-phase common-ground five-level inverter main circuit with two negative states and one zero state. First, a sinusoidal modulation signal is compared with four paths of phase-disposition triangular carriers, and the voltage value of the switched capacitor C2 is subjected to hysteresis comparison with a preset reference voltage value to generate five paths of preprocessed signals. Then, logical operation is performed on the five paths of preprocessed signals according to the conduction states of the switching tubes under six operating modes to obtain the driving signals of each switching tube. The method specifically includes the following steps: Step 1: The sinusoidal modulation wave uref is respectively intersected with the phase-disposition triangular carriers ucr1, ucr2, ucr3 and ucr4. When uref>ucr1, a high level is output, and when uref<ucr1, a low level is output, which is recorded as preprocessed signal A, and its inversion gives preprocessed signal a; when uref>ucr2, a high level is output, and when uref<ucr2, a low level is output, which is recorded as preprocessed signal B, and its inversion gives preprocessed signal b; when uref>ucr3, a high level is output, and when uref<ucr3, a low level is output, which is recorded as preprocessed signal C, and its inversion gives preprocessed signal c; when uref>ucr4, a high level is output, and when uref<ucr4, a low level is output, which is recorded as preprocessed signal D, and its inversion gives preprocessed signal d; Step 2: The voltage of the switched capacitor C2 is sampled and defined as uC2, and a reference voltage uCref slightly lower than the voltage of the photovoltaic cell PV is defined. The voltage uC2 of the switched capacitor C2 and the set reference voltage uCref are subjected to hysteresis control to obtain preprocessed signal E, and its inversion gives preprocessed signal e.

[0008] Step 3: Perform AND operations on the inverted signal a of preprocessed signal A with preprocessed signal B, and on the inverted signal c of preprocessed signal C with preprocessed signal D and preprocessed signal E respectively. Then perform an OR operation on the results of the two AND operations to obtain the drive signals ug1 and ug7 for switching transistors S1 and S7. Perform AND operations on the inverted signal b of preprocessed signal B with preprocessed signal C, and on the inverted signal c of preprocessed signal C with preprocessed signal D and on the inverted signal e of preprocessed signal E respectively. Then perform an OR operation on the results of the two AND operations with the inverted signal e of preprocessed signal D. The inverted signal d is ORed to obtain the drive signal ug2 for switch S2; the inverted signals a and c of preprocessed signal A, and the inverted signals c, D, and E of preprocessed signal C are ANDed, and the results of the two AND operations are ORed to obtain the drive signal ug3 for switch S3; the inverted signal b of preprocessed signal B and preprocessed signal C are ANDed, and the result of the AND operation is ORed with preprocessed signal A to obtain the drive signal ug for switch S4. 4. Perform a bitwise AND operation on the inverted signal c of preprocessed signal C, preprocessed signal D, and preprocessed signal E. Then, perform an OR operation on the result of the AND operation with the inverted signal d of preprocessed signal A and preprocessed signal D to obtain the drive signal ug5 for switch S5. Perform a bitwise AND operation on the inverted signal c of preprocessed signal C, preprocessed signal D, and preprocessed signal E to obtain the drive signal ug6 for switch S6. Perform a bitwise AND operation on the inverted signal a of preprocessed signal A and preprocessed signal B to obtain the drive signal ug for switch S8. 8; Perform AND operations on the inverted signal a of preprocessed signal A and preprocessed signal B, the inverted signal c of preprocessed signal C and preprocessed signal D and preprocessed signal E respectively, and then perform an OR operation on the result of the two AND operations with preprocessed signal A to obtain the drive signal ug9 of switch S9; Perform AND operations on the inverted signal c of preprocessed signal C, preprocessed signal D and preprocessed signal E, and then perform an OR operation on the result of the AND operation with the inverted signal d of preprocessed signal D to obtain the drive signal ug10 of switch S10.

[0009] The single-phase common-ground five-level inverter topology with dual negative-one-state configuration includes a photovoltaic cell PV, a five-level inverter circuit capable of negative-one-state selection, a single-phase output LC filter circuit, and a single-phase load. The five-level inverter includes a DC-side input filter capacitor Cdc, two switching capacitors C1 and C2, and ten switching transistors S1 to S10. Switches S2, S4, S5, and S9 are IGBTs with freewheeling diodes, while the remaining switches are IGBTs without freewheeling diodes. The single-phase output LC filter circuit and single-phase load include a filter inductor Lf, a filter capacitor Cf, and a single-phase load Ro. The positive terminal of the photovoltaic cell PV is connected to the positive terminal of the DC-side input filter capacitor Cdc, the collector of switching transistor S1, and the collector of switching transistor S3. The emitter of switching transistor S1 is connected to the positive terminal of switching capacitor C1, the collector of switching transistor S2, and the collector of switching transistor S4. The electrodes are connected; the negative terminal of the switching capacitor C1 is connected to the emitter of the switching transistor S5, the emitter of the switching transistor S6, and the collector of the switching transistor S7; the emitter of the switching transistor S3 is connected to the positive terminal of the switching capacitor C2, the collector of the switching transistor S5, and the collector of the switching transistor S8; the negative terminal of the switching capacitor C2 is connected to the emitter of the switching transistor S9 and the emitter of the switching transistor S10; the emitter of the switching transistor S4 is connected to the collector of the switching transistor S6, the emitter of the switching transistor S8, the collector of the switching transistor S10, and one end of the filter inductor Lf; the other end of the filter inductor Lf is connected to the positive terminal of the filter capacitor Cf and one end of the single-phase load Ro; the negative terminal of the photovoltaic cell PV is connected to the negative terminal of the DC-side output filter capacitor Cdc, the emitter of the switching transistor S2, the emitter of the switching transistor S7, the collector of the switching transistor S9, the negative terminal of the filter capacitor Cf, and the other end of the single-phase load Ro.

[0010] The beneficial effects of this invention are as follows: This invention adopts a collaborative control method that combines carrier in-phase cascade modulation technology with switched capacitor voltage hysteresis control. This method can effectively replenish the charge of the switched capacitor during the negative half-cycle of the inverter's operation, avoiding continuous voltage drops in a single switched capacitor. This results in distortion-free output voltage during the negative half-cycle of the inverter and high-quality output voltage waveform. At the same time, the introduction of switched capacitor voltage hysteresis control in this invention can effectively reduce the frequency of capacitor voltage fluctuations compared to the traditional single voltage direct comparison control scheme. This, in turn, reduces the switching losses of some switching transistors and improves the inverter's efficiency and anti-interference capability. Attached Figure Description

[0011] Figure 1 This is a main circuit diagram of a single-phase common-ground five-level inverter with two negative states and one ground state.

[0012] Figure 2 This is a schematic diagram of the control method of the present invention.

[0013] Figure 3 This is a timing diagram of the driving signals for the present invention.

[0014] Figure 4 This is a schematic diagram of mode one in this invention.

[0015] Figure 5 This is a schematic diagram of mode two in this invention.

[0016] Figure 6 This is a schematic diagram of mode three in this invention.

[0017] Figure 7 This is a schematic diagram of mode four in this invention.

[0018] Figure 8 This is a schematic diagram of mode five in this invention.

[0019] Figure 9 This is a schematic diagram of mode six in this invention.

[0020] Figure 10 The output SPWM voltage waveform diagram of this invention.

[0021] Figure 11 The voltage waveform of the switched capacitor C2 in this invention is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] It should be emphasized that, in describing this invention, various formulas and constraints are distinguished by consistent reference numerals, but it is not excluded that different reference numerals may be used to identify the same formulas and / or constraints. The purpose of this arrangement is to more clearly illustrate the features of this invention.

[0024] The single-phase common-ground inverter of this invention is a dual-negative-one-state single-phase common-ground five-level inverter main circuit, and its topology is as follows: Figure 1 As shown.

[0025] The control method of the single-phase common-ground inverter of the present invention is as follows: Figure 2 As shown, the main steps include: Step 1: Intersect the sinusoidal modulation wave uref with phase-shifted stacked triangular carriers ucr1, ucr2, ucr3, and ucr4 respectively. When uref>ucr1, a high level is output; when uref<ucr1, a low level is output, which is designated as preprocessing signal A, and its inverse is taken to obtain preprocessing signal a. When uref>ucr2, a high level is output; when uref<ucr2, a low level is output, which is designated as preprocessing signal B, and its inverse is taken to obtain preprocessing signal b. When uref>ucr3, a high level is output; when uref<ucr3, a low level is output, which is designated as preprocessing signal C, and its inverse is taken to obtain preprocessing signal c. When uref>ucr4, a high level is output; when uref<ucr4, a low level is output, which is designated as preprocessing signal D, and its inverse is taken to obtain preprocessing signal d. Step 2: Sample the voltage of the switched capacitor C2 and define it as uC2, and simultaneously define uCref as a voltage slightly lower than the voltage of the photovoltaic cell PV. Perform hysteresis control on the voltage uC2 of the switched capacitor C2 and the set reference voltage uCref to obtain preprocessing signal E, and take its inverse to obtain preprocessing signal e.

[0026] Step 3: Perform AND operations on the inverted signal a of preprocessed signal A with preprocessed signal B, and on the inverted signal c of preprocessed signal C with preprocessed signal D and preprocessed signal E respectively. Then perform an OR operation on the results of the two AND operations to obtain the drive signals ug1 and ug7 for switching transistors S1 and S7. Perform AND operations on the inverted signal b of preprocessed signal B with preprocessed signal C, and on the inverted signal c of preprocessed signal C with preprocessed signal D and on the inverted signal e of preprocessed signal E respectively. Then perform an OR operation on the results of the two AND operations with the inverted signal e of preprocessed signal D. The inverted signal d is ORed to obtain the drive signal ug2 for switch S2; the inverted signals a and c of preprocessed signal A, and the inverted signals c, D, and E of preprocessed signal C are ANDed, and the results of the two AND operations are ORed to obtain the drive signal ug3 for switch S3; the inverted signal b of preprocessed signal B and preprocessed signal C are ANDed, and the result of the AND operation is ORed with preprocessed signal A to obtain the drive signal ug for switch S4. 4. Perform a bitwise AND operation on the inverted signal c of preprocessed signal C, preprocessed signal D, and preprocessed signal E. Then, perform an OR operation on the result of the AND operation with the inverted signal d of preprocessed signal A and preprocessed signal D to obtain the drive signal ug5 for switch S5. Perform a bitwise AND operation on the inverted signal c of preprocessed signal C, preprocessed signal D, and preprocessed signal E to obtain the drive signal ug6 for switch S6. Perform a bitwise AND operation on the inverted signal a of preprocessed signal A and preprocessed signal B to obtain the drive signal ug for switch S8. 8; Perform AND operations on the inverted signal a of preprocessed signal A and preprocessed signal B, the inverted signal c of preprocessed signal C and preprocessed signal D and preprocessed signal E respectively, and then perform an OR operation on the result of the two AND operations with preprocessed signal A to obtain the drive signal ug9 of switch S9; Perform AND operations on the inverted signal c of preprocessed signal C, preprocessed signal D and preprocessed signal E, and then perform an OR operation on the result of the AND operation with the inverted signal d of preprocessed signal D to obtain the drive signal ug10 of switch S10.

[0027] Through the above control, the inverter drive signal timing diagram can be obtained as follows: Figure 3 As shown. Under this control method, the inverter can obtain six operating modes, as follows: Figures 4-9 As shown below. The working principle of each mode of the inverter is briefly analyzed below. 0 indicates that the switching transistor is off, and 1 indicates that the switching transistor is on.

[0028] Mode 1 (M1): such as Figure 4As shown, in this mode, the inverter's switching state is [0,0,0,1,1,0,0,0,1,0]. Switches S4, S5, and S9 are in the on state, while switches S1, S2, S3, S6, S7, S8, and S10 are in the off state. Switched capacitors C1 and C2 are connected in series through switch S5. Current flows from the positive terminal of switched capacitor C1, through S4-Lf-Ro-S9, and finally back to the negative terminal of switched capacitor C2. At this time, the inverter operates in a positive binary state, and both switched capacitors C1 and C2 are in the discharging state. The inverter output SPWM voltage is 2U. PV .

[0029] Mode 2 (M2): such as Figure 5 As shown, in this mode, the inverter's switching state is [1,0,1,0,0,0,1,1,1,0], with switches S1, S3, S7, S8, and S9 in the on state, and switches S2, S4, S5, S6, and S10 in the off state. Current flows from the positive terminal of the photovoltaic cell (PV), through S1-C1-S7, S3-C2-S9, and S3-S8-Lf-Ro, and finally returns to the negative terminal of the photovoltaic cell (PV). At this time, the inverter operates in positive state 1, with switched capacitors C1 and C2 both in the charging state. The DC-side photovoltaic cell (PV) directly supplies power to the single-phase load Ro, and the inverter outputs an SPWM voltage of U. PV .

[0030] Mode 3 (M3): such as Figure 6 As shown, in this mode, the inverter's switching state is [0,1,0,1,0,0,0,0,0,0], with switches S2 and S4 in the ON state and switches S1, S3, S5, S6, S7, S8, S9, and S10 in the OFF state. The current in the LC filter and the single-phase load Ro freewheels in the loop formed by S2 and S4. At this time, the inverter operates in the zero state, with both switched capacitors C1 and C2 floating, and the inverter output SPWM voltage is 0.

[0031] Mode 4 (M4): such as Figure 7 As shown, in this mode, the inverter's switching state is [1,0,0,0,1,0,1,0,0,1], with switches S1, S5, S7, and S10 in the on state and switches S2, S3, S4, S6, S8, and S9 in the off state. Current flows from the positive terminal of the photovoltaic cell (PV), through S1-C1-S7, and then back to the negative terminal of the PV cell. Simultaneously, current flows from the positive terminal of the switching capacitor C2, through S5-S7-Ro-Lf-S10, and back to the negative terminal of the switching capacitor C2. At this time, the inverter operates in a negative-one state. The DC-side photovoltaic cell (PV) charges the switching capacitor C1 through the loop, and the switching capacitor C2 discharges to the load. The inverter outputs an SPWM voltage of -U. PV .

[0032] Mode 5 (M5): such as Figure 8 As shown, in this mode, the inverter's switching states are [0,1,1,0,0,1,0,0,1,0], with switches S2, S3, S6, and S9 in the ON state, and switches S1, S4, S5, S7, S8, and S10 in the OFF state. Current flows from the positive terminal of the photovoltaic cell (PV), through S3-C2-S9, and then back to the negative terminal of the PV cell. Simultaneously, current flows from the positive terminal of the switching capacitor C1, through S2-Ro-Lf-S6, and back to the negative terminal of the switching capacitor C1. At this time, the inverter operates in a negative-one state. The DC-side photovoltaic cell (PV) charges the switching capacitor C2 through the loop, and the switching capacitor C1 discharges to the load. The inverter outputs an SPWM voltage of -U. PV .

[0033] Modal 6 (M6): such as Figure 9 As shown, in this mode, the inverter's switching state is [0,1,0,0,1,0,0,0,0,1]. Switches S2, S5, and S10 are in the on state, while switches S1, S3, S4, S6, S7, S8, and S9 are in the off state. Switched capacitors C1 and C2 are connected in series through switch S5. Current flows from the positive terminal of switched capacitor C1, through S2-Ro-Lf-S10, and finally back to the negative terminal of switched capacitor C2. At this time, the inverter operates in a negative two-state, with both switched capacitors C1 and C2 in a discharging state, and the inverter output SPWM voltage is -2U. PV .

[0034] Table 1 shows the switching state, switched capacitor state, and output SPWM voltage of the single-phase common-ground five-level inverter topology with dual negative one-state operation under different operating modes.

[0035] Table 1. Switch state, switched capacitor state, and output SPWM voltage under each operating mode of the inverter.

[0036] Based on the above implementation scheme, a MATLAB / Simulink simulation was performed on a single-phase common-ground five-level inverter with dual negative one-state operation. Under the same operating condition, the output SPWM voltage waveform and the voltage waveform of the switched capacitor C2 were obtained, as shown below. Figure 10 and Figure 11 As shown, (a) are waveforms controlled by single-threshold comparison of switched capacitor voltage, and (b) are waveforms controlled by hysteresis of switched capacitor voltage. Figure 10 It can be seen that under both types of switched capacitor voltage control schemes, the inverter output voltage in the negative half-cycle did not exhibit waveform distortion. This good waveform characteristic is due to the fact that the inverter can effectively replenish the charge of the switched capacitor during the negative half-cycle, effectively preventing the capacitor voltage from continuously dropping. Figure 11 The comparison of the voltage waveforms of the switched capacitor C2 is shown. During the same operating time, the single threshold comparison control scheme for the switched capacitor voltage has a higher voltage fluctuation frequency and a smaller voltage ripple amplitude, which makes the switching transistor work more frequently and thus increases the switching loss. The switched capacitor voltage hysteresis control scheme has a slightly larger voltage ripple amplitude, but it can effectively reduce the voltage fluctuation frequency, reduce the switching loss of the switching transistor, and thus improve the efficiency and anti-interference capability of the inverter.

[0037] In summary, this invention employs a collaborative control method combining carrier in-phase cascaded modulation technology and switched capacitor voltage hysteresis control. This enables the inverter to achieve alternating charging and discharging of the two switched capacitors during the negative half-cycle of operation, effectively replenishing the capacitor charge, stabilizing the capacitor voltage at its rated value, and ensuring distortion-free output SPWM voltage during the negative half-cycle, thus improving the output voltage waveform quality. Furthermore, the introduction of switched capacitor voltage hysteresis control effectively reduces the capacitor voltage fluctuation frequency, thereby reducing the switching losses of some switching transistors and improving the inverter's efficiency and anti-interference capability.

[0038] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A control method for a single-phase common-ground five-level inverter with dual negative one-state operation, applied to a single-phase common-ground five-level inverter topology with dual negative one-state operation, characterized in that: Comprise the following three steps: First step: sine modulation wave uref respectively with the same phase layering triangular carrier ucr1, ucr2, ucr3, ucr4 intersection, when uref > ucr1, output high, when uref < ucr1, output low, recorded as preprocessed signal A, get its inverse to get preprocessed signal a; when uref > ucr2, output high, when uref < ucr2, output low, recorded as preprocessed signal B, get its inverse to get preprocessed signal b; when uref > ucr3, output high, when uref < ucr3, output low, recorded as preprocessed signal C, get its inverse to get preprocessed signal c; when uref > ucr4, output high, when uref < ucr4, output low, recorded as preprocessed signal D, get its inverse to get preprocessed signal d; Second step: sampling switch capacitor C2 voltage is defined as uC2, while defining a voltage uCref lower than the photovoltaic cell PV, the voltage uC2 of switch capacitor C2 and the set reference voltage uCref hysteresis control to get preprocessed signal E, get its inverse to get preprocessed signal e; Step 3: Perform AND operations on the inverted signal a of preprocessed signal A with preprocessed signal B, and on the inverted signal c of preprocessed signal C with preprocessed signal D and preprocessed signal E respectively. Then perform an OR operation on the results of the two AND operations to obtain the drive signals ug1 and ug7 for switching transistors S1 and S7. Perform AND operations on the inverted signal b of preprocessed signal B with preprocessed signal C, and on the inverted signal c of preprocessed signal C with preprocessed signal D and on the inverted signal e of preprocessed signal E respectively. Then perform an OR operation on the results of the two AND operations with the inverted signal e of preprocessed signal D. The inverted signal d is ORed to obtain the drive signal ug2 for switch S2; the inverted signals a and c of preprocessed signal A, and the inverted signals c, D, and E of preprocessed signal C are ANDed, and the results of the two AND operations are ORed to obtain the drive signal ug3 for switch S3; the inverted signal b of preprocessed signal B and preprocessed signal C are ANDed, and the result of the AND operation is ORed with preprocessed signal A to obtain the drive signal ug for switch S4.

4. Perform a bitwise AND operation on the inverted signal c of preprocessed signal C, preprocessed signal D, and preprocessed signal E. Then, perform an OR operation on the result of the AND operation with the inverted signal d of preprocessed signal A and preprocessed signal D to obtain the drive signal ug5 for switch S5. Perform a bitwise AND operation on the inverted signal c of preprocessed signal C, preprocessed signal D, and preprocessed signal E to obtain the drive signal ug6 for switch S6. Perform a bitwise AND operation on the inverted signal a of preprocessed signal A and preprocessed signal B to obtain the drive signal ug for switch S8. 8; Perform AND operations on the inverted signal a of preprocessed signal A and preprocessed signal B, the inverted signal c of preprocessed signal C and preprocessed signal D and preprocessed signal E respectively, and then perform an OR operation on the result of the two AND operations with preprocessed signal A to obtain the drive signal ug9 of switch S9; Perform AND operations on the inverted signal c of preprocessed signal C, preprocessed signal D and preprocessed signal E, and then perform an OR operation on the result of the AND operation with the inverted signal d of preprocessed signal D to obtain the drive signal ug10 of switch S10.

2. The control method of a double negative one state single phase common ground type five-level inverter according to claim 1, characterized in that, The dual-negative-one-state single-phase common-ground five-level inverter topology includes a photovoltaic cell PV, a five-level inverter circuit capable of negative-one-state selection, a single-phase output LC filter circuit, and a single-phase load. The five-level inverter includes a DC-side input filter capacitor Cdc, two switching capacitors C1 and C2, and ten switching transistors S1 to S10. Switches S2, S4, S5, and S9 are IGBTs with freewheeling diodes, while the remaining switches are IGBTs without freewheeling diodes. The single-phase output LC filter circuit and single-phase load include a filter inductor Lf, a filter capacitor Cf, and a single-phase load Ro. The positive terminal of the photovoltaic cell PV is connected to the positive terminal of the DC-side input filter capacitor Cdc, the collector of switching transistor S1, and the collector of switching transistor S3. The emitter of switching transistor S1 is connected to the positive terminal of switching capacitor C1, the collector of switching transistor S2, and the collector of switching transistor S4. The following connections are made: the negative terminal of the switching capacitor C1 is connected to the emitter of the switching transistor S5, the emitter of the switching transistor S6, and the collector of the switching transistor S7; the emitter of the switching transistor S3 is connected to the positive terminal of the switching capacitor C2, the collector of the switching transistor S5, and the collector of the switching transistor S8; the negative terminal of the switching capacitor C2 is connected to the emitter of the switching transistor S9 and the emitter of the switching transistor S10; the emitter of the switching transistor S4 is connected to the collector of the switching transistor S6, the emitter of the switching transistor S8, the collector of the switching transistor S10, and one end of the filter inductor Lf; the other end of the filter inductor Lf is connected to the positive terminal of the filter capacitor Cf and one end of the single-phase load Ro; the negative terminal of the photovoltaic cell PV is connected to the negative terminal of the DC-side output filter capacitor Cdc, the emitter of the switching transistor S2, the emitter of the switching transistor S7, the collector of the switching transistor S9, the negative terminal of the filter capacitor Cf, and the other end of the single-phase load Ro.

3. The control method of a double negative one state single phase common ground type five-level inverter according to claim 2, characterized in that: The six operating modes are as follows: Mode one: the switch state of the inverter is [0, 0, 0, 1, 1, 0, 0, 0, 1, 0], the switch tubes S4, S5 and S9 are in the conducting state, the switch tubes S1, S2, S3, S6, S7, S8 and S10 are in the off state, at this time, the inverter works in the positive two-state, the switch capacitors C1 and C2 are in the discharging state, and the output SPWM voltage is 2U PV ; Mode two: the switch state of the inverter is [1, 0, 1, 0, 0, 0, 1, 1, 1, 0], the switch tubes S1, S3, S7, S8, S9 are in the on state, and the switch tubes S2, S4, S5, S6, S10 are in the off state, at this time, the inverter works in the positive one state, the switch capacitors C1, C2 are in the charging state, and the output SPWM voltage is U PV ; Mode 3: The inverter's switching state is [0,1,0,1,0,0,0,0,0,0], with switching transistors S2 and S4 in the on state and switching transistors S1, S3, S5, S6, S7, S8, S9, and S10 in the off state. At this time, the inverter operates in the zero state, the switching capacitors C1 and C2 are floating, and the output SPWM voltage is 0. Mode four: the switch state of the inverter is [1, 0, 0, 0, 1, 0, 1, 0, 0, 1], the switch tubes S1, S5, S7 and S10 are in the on state, the switch tubes S2, S3, S4, S6, S8 and S9 are in the off state, at this time, the inverter works in the negative one state, the switch capacitor C1 is in the charging state, the switch capacitor C2 is in the discharging state, and the output SPWM voltage is -U PV ; Modality five: the switch state of the inverter is [0, 1, 1, 0, 0, 1, 0, 0, 1, 0], the switch tubes S2, S3, S6 and S9 are in the conducting state, the switch tubes S1, S4, S5, S7, S8 and S10 are in the off state, at this time, the inverter works in the negative one state, the switch capacitor C1 is in the discharging state, the switch capacitor C2 is in the charging state, and the output SPWM voltage is -U PV ; Mode six: the switch state of the inverter is [0, 1, 0, 0, 1, 0, 0, 0, 0, 1], the switch tubes S2, S5 and S10 are in the conducting state, the switch tubes S1, S3, S4, S6, S7, S8 and S9 are in the off state, at this time, the inverter works in the negative two state, the switch capacitors C1 and C2 are in the discharging state, and the output SPWM voltage is -2U PV .

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