Multi-channel signal buffering and centralized scheduling extraction method

Abstract

The application belongs to the technical field of satellite communication and relates to a multi-channel signal buffering and centralized scheduling extraction method.The method comprises the following steps: a three-layer storage architecture is adopted to cooperate with a centralized scheduling extractor to realize buffering and scheduling extraction of multi-channel signals; asynchronous FIFO is used for cross-clock domain processing by a FIFO cross-clock domain buffer layer; a channel management table is constructed by using an on-chip RAM through a RAM channel management table layer to store metadata and state information of all satellite communication signal channels; a continuous address space is allocated for each effective satellite communication signal channel in a DDR memory through a DDR ring buffer layer; and a write arbiter in the centralized scheduling extractor polls the FIFO state of each channel. The application cooperatively realizes a complete link of high-speed and reliable input, efficient metadata scheduling and large-capacity batch storage, and guarantees low-delay transmission of high-priority services and long-term bandwidth fairness of ordinary service channels.

Description

Technical Field

[0001] This invention belongs to the field of satellite communication technology, specifically relating to a method for multi-channel signal buffering and centralized scheduling extraction. Background Technology

[0002] Modern satellite communication systems need to simultaneously support multiple types of services, including emergency telemetry and control, voice communication, broadband data, broadcast transmission, and operation and maintenance management. This requires multiple independent radio frequency signal channels, each continuously generating a data stream at an independent sampling rate. The hardware resources of the onboard payload are severely constrained by power consumption, size, and weight. The computing power, storage bandwidth, and capacity of the backend digital signal processing unit also have limitations, making it impossible to process the full-speed data streams from all channels simultaneously.

[0003] Against this backdrop, multi-channel signal buffering and scheduling retrieval mechanisms are crucial for ensuring no data loss, timing alignment, and efficient resource allocation across multiple channels. Existing multi-channel buffering and scheduling schemes often suffer from the following drawbacks: (1) The front-end RF sampling clock and the back-end system master clock usually belong to different clock domains. Some solutions directly access the sampling data into the master clock domain for storage, which is prone to metastability risk and data corruption. Some solutions only use simple multi-level register synchronization, which can only adapt to low-speed sampling scenarios and cannot meet the sampling reliability requirements of high-speed multi-channel satellite signals. Furthermore, they cannot absorb the jitter and frequency offset of the sampling clock. (2) The metadata such as the write pointer, read pointer, effective data volume and running status of the channel need to be updated and queried every clock cycle. Most solutions store the metadata and business data together in the DDR memory. However, DDR has the characteristics of high random access latency, refresh cycle blocking and large cross-line access overhead, which cannot realize single-cycle metadata response and seriously limits the running clock frequency of the scheduling system. (3) Existing solutions mostly adopt pure priority scheduling or pure round-robin scheduling, which can easily lead to low-priority service channels not being served for a long time, resulting in extremely poor bandwidth allocation fairness. They cannot guarantee the low latency requirements of high-priority services such as emergency signaling and real-time measurement and control, and are difficult to adapt to the differentiated service quality requirements of satellite communication services. (4) Satellite communication systems usually need to operate continuously for a long time. The dynamic allocation and release of channels will gradually generate DDR storage space fragmentation, resulting in a reduction of continuous available space and a decrease in space utilization. When a sudden influx of data causes the buffer to overflow, most solutions adopt a unified data discarding strategy instead of processing according to service priority, which can easily lead to the loss of critical service data. In summary, there is an urgent need for a multi-channel signal caching and centralized scheduling extraction scheme with a clear hierarchical architecture, reasonable scheduling strategy, and sound operation and maintenance mechanism, which can simultaneously achieve reliable transmission across clock domains, high scheduling efficiency, differentiated service quality, and long-term stable operation under the constraints of limited hardware resources in satellite communication systems. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention provides a solution. This invention offers a multi-channel signal buffering and centralized scheduling extraction method, employing a three-layer storage architecture in conjunction with a centralized scheduling extractor to achieve multi-channel signal buffering and scheduling extraction; the three-layer storage architecture includes a FIFO cross-clock domain buffer layer, a RAM channel management table layer, and a DDR ring buffer layer. The method includes: For each satellite communication signal channel, an asynchronous FIFO is used in the FIFO cross-clock domain buffer layer for cross-clock domain processing. On the write side, the signal sampling clock drives the writing of sampled data, and on the read side, the system master clock drives the reading, thus completing the isolation between the signal clock domain and the system clock domain and absorbing sampling jitter. The RAM channel management table layer constructs a channel management table through on-chip RAM, storing metadata and status information of all satellite communication signal channels, and performs single-cycle queries and updates as DDR access channels; The DDR ring buffer layer is organized into a DDR ring buffer by allocating an independent, contiguous address space for each valid satellite communication signal channel in the DDR memory; The write arbitrator in the centralized scheduler polls the FIFO status of each channel and writes the data to be written in the FIFO in batches into the DDR ring buffer of the corresponding satellite communication signal channel according to the scheduling rules. After receiving the extraction request from the backend, the centralized scheduling extractor reads data in batches from the corresponding DDR circular buffer according to the metadata of the channel management table, assembles it, and outputs it to the backend processing unit.

[0005] In some optional embodiments, the on-chip RAM is an on-chip dual-port BRAM of the FPGA; the dual-port BRAM includes a first port and a second port of the FPGA; the first port is used for write-side access to update channel metadata; the second port is used for read-side access to query channel metadata; for shared fields in the channel management table, atomic operations are used to resolve dual-port read-write conflicts.

[0006] In some optional embodiments, each record in the channel management table contains all the metadata of the corresponding channel. The channel management table stores idle channel status information and is used for idle channel retrieval during channel allocation and resource return management during channel release.

[0007] In some optional embodiments, the DDR ring buffer is stored as follows: data from the same satellite communication signal channel is mapped to the same physical row of the DDR; when the write address crosses the end of the ring buffer space, a split write operation is performed to complete the ring wrap-around process.

[0008] In some optional embodiments, the DDR ring buffer layer allocates an independent contiguous address space for each valid satellite communication signal channel in the DDR memory, including: when signal data from a new satellite communication signal channel arrives, querying the channel management table to confirm the channel identity, allocating DDR storage space for the satellite communication signal channel, and filling in the metadata and status information of the corresponding satellite communication signal channel in the channel management table.

[0009] In some optional embodiments, channel release is also included, including: The inspection thread periodically scans the idle status of all satellite communication signal channels. When it detects that a satellite communication signal channel has timed out of idle time, it marks the channel status of that satellite communication signal channel as being released. Empty the remaining data in the FIFO corresponding to the satellite communication signal channel and wait for the DDR write operation of the satellite communication signal channel to be completed. Return the DDR address space of the satellite communication signal channel to the free address pool, update the channel management table, and set the channel status of the satellite communication signal channel to free; The historical records of idle timeouts of satellite communication signal channels are statistically analyzed. If there are sufficient historical records, the average historical timeout plus a fixed threshold is used as the updated timeout threshold; if there are insufficient historical records, the default timeout threshold is used.

[0010] In some optional embodiments, the data to be written in the FIFO is written in batches to the DDR circular buffer of the corresponding satellite communication signal channel according to the scheduling rules, including: After the write arbitrator starts, it checks the FIFO status of each channel in a preset polling order. If the FIFO of the current channel is not empty, it calculates the writable data length of the channel and queries the channel management table to obtain the write pointer and remaining DDR storage space of the channel. If the remaining storage space is sufficient, it performs a DDR burst write operation to write the data in the FIFO to the corresponding DDR circular buffer. After the write is completed, it updates the write pointer and valid data volume of the channel in the channel management table. If the remaining storage space is insufficient, it triggers a space full self-cleaning process.

[0011] In some optional embodiments, after receiving the extraction request from the backend, the centralized scheduling extractor reads data in batches from the corresponding DDR circular buffer according to the metadata of the channel management table, including: After receiving a data extraction request, the centralized scheduling extractor verifies the operating status of the target channel; After the running status verification is passed, the channel management table is queried to obtain the effective data volume of the target channel, and the address range of this read is calculated; Determine whether the current read range crosses the boundary of the circular buffer. If so, perform split read and data concatenation operations; otherwise, perform a single DDR burst read operation. The read data is assembled and output, and the read address information of the channel in the channel management table is updated at the same time.

[0012] In some optional embodiments, the space-full self-cleaning employs a hierarchical cleanup strategy, performing different space reclamation operations according to channel priority, including: The channel priority is divided into first-level channels, second-level channels, third-level channels, and fourth-level channels. For first-level channels, write operations are paused. For second-level channels, cached data of one burst length is cleared. For third-level channels, cached data of a first predetermined proportion is cleared. For fourth-level channels, cached data of a second predetermined proportion is cleared. After data clearing is completed, storage space is reclaimed, buffer level status is updated, and normal write scheduling is restored.

[0013] In some optional embodiments, DDR memory space defragmentation is also included, comprising: when insufficient DDR memory space is detected, first checking the available space of the DDR free address pool; if the free address pool space is insufficient, scanning all channels in an idle state and reclaiming their DDR space to the free address pool; if the space is still insufficient after reclamation, sorting all active channels by DDR base address and eliminating memory space fragmentation by data migration; updating the base address and read / write pointer of each active channel, and merging the last consecutive free space to the free address pool.

[0014] The beneficial effects of this invention are: (1) The present invention adopts a three-level hierarchical architecture, which collaboratively realizes a complete link of high-speed and reliable input, efficient metadata scheduling and large-capacity batch storage, and is suitable for multi-channel high-speed scenarios of satellite communication; (2) The present invention adopts a hybrid scheduling mechanism that combines preemptive priority scheduling and deficit polling scheduling. It ensures low-latency transmission of high-priority services such as emergency measurement and control and key signaling through preemptive priority scheduling, and ensures long-term bandwidth fairness of ordinary service channels through deficit polling mechanism. It perfectly adapts to the characteristics of satellite communication with multiple services coexisting and different service quality requirements. (3) This invention can reduce the risk of overflow, eliminate the differentiated loss based on priority in extreme scenarios, solve the resource degradation problem of long-term operation through fragmentation, improve the flexibility of resource utilization by setting an adaptive timeout threshold, and ensure that the system can operate continuously and stably for a long time, meeting the unattended operation and maintenance requirements of the spaceborne system. (4) The three-level hierarchical architecture can be implemented based on mainstream FPGAs without the need for additional dedicated hardware. The logic and storage resources are controllable and meet the stringent constraints of power consumption, size and weight of satellite payloads. The number of channels can be flexibly configured by expanding the channel management table entries, adapting to satellite communication systems of different scales. It has high engineering reference and reuse value for various high-speed multi-channel signal acquisition and data scheduling systems. Attached Figure Description

[0015] Figure 1 This is a flowchart of the multi-channel signal buffering and centralized scheduling extraction method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of channel allocation; Figure 3 This is a schematic diagram of the read / write relationship of the circular buffer; Figure 4 This is a flowchart of the channel release process; Figure 5 This is a flowchart for writing to the scheduling arbitration process; Figure 6 This is a flowchart of the reading and scheduling extraction process; Figure 7 This is a flowchart of the automatic clearing process when the space is full. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0017] Example 1 As an example, to address the problems existing in the prior art, this embodiment provides a multi-channel signal buffering and centralized scheduling extraction method.

[0018] The implementation details of the method in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0019] The multi-channel signal caching and centralized scheduling extraction method provided in this embodiment employs a three-layer storage architecture in conjunction with a centralized scheduling extractor to achieve multi-channel signal caching and scheduling extraction. The three-layer storage architecture includes a FIFO cross-clock domain buffer layer, a RAM channel management table layer, and a DDR ring buffer layer. This invention adopts a three-level layered architecture, balancing reliability and efficiency. The first layer solves the cross-clock domain metastability problem at the physical level through an asynchronous FIFO, absorbing sampling jitter and ensuring the reliability of high-speed data input. The second layer decouples high-frequency metadata from large-capacity service data through the RAM channel management table, significantly improving scheduling efficiency by utilizing the single-cycle access characteristics of on-chip memory. The third layer provides sufficient cache capacity through a DDR ring buffer, tolerating backend processing jitter and scheduling latency. The three-layer architecture collaboratively realizes a complete link of high-speed reliable input, efficient metadata scheduling, and large-capacity batch storage, adapting to multi-channel high-speed scenarios in satellite communication.

[0020] As attached Figure 1 As shown, the multi-channel signal buffering and centralized scheduling extraction method includes steps 110-150.

[0021] Step 110: For each satellite communication signal channel, the FIFO cross-clock domain buffer layer uses an asynchronous FIFO for cross-clock domain processing. On the write side, the signal sampling clock drives the writing of sampled data, and on the read side, the system master clock drives the reading, thus completing the isolation between the signal clock domain and the system clock domain and absorbing sampling jitter.

[0022] The FIFO write port operates in the signal sampling clock domain, receiving digital signal data sampled by the front end; the FIFO read port operates in the system master clock domain, controlled by the scheduling system for reading. The asynchronous FIFO isolates the two clock domains. Because the write and read clocks are completely asynchronous, the asynchronous FIFO uses mechanisms such as Gray code pointer synchronization and empty / full flag generation to avoid metastability issues in cross-clock domain transmission, ensuring a safe and reliable transition of data from the signal clock domain to the system clock domain. It also absorbs jitter and minor frequency offsets from the front-end sampling clock, smoothing the data stream input. The front-end ADC sampling clock may have minor periodic jitter, or there may be slight frequency offsets between sampling clocks from different channels. The storage depth of the asynchronous FIFO can smooth out these instantaneous rate fluctuations, preventing data misalignment or interruptions in the back-end scheduling. In engineering implementations, the FIFO depth can be configured according to the sampling rate and scheduling cycle, typically set to accommodate 2-4 bursts of data to effectively absorb common jitter.

[0023] Step 120: The RAM channel management table constructs a channel management table through on-chip RAM, storing metadata and status information of all satellite communication signal channels, and performs single-cycle queries and updates as DDR access channels.

[0024] A global channel management table is constructed using the on-chip dual-port BRAM of the FPGA. Metadata such as the base address, read / write pointer, effective data volume, running status, priority, and idle timer of all channels are stored in this table.

[0025] The on-chip RAM handles metadata management for all channels, resolving the issues of high latency in DDR random access and the inability to meet high-frequency metadata updates.

[0026] In this embodiment, the on-chip RAM is an FPGA on-chip dual-port BRAM; the dual-port BRAM includes a first port and a second port of the FPGA; the first port is used for write-side access to update channel metadata; the second port is used for read-side access to query channel metadata; for shared fields in the channel management table, atomic operations are used to resolve dual-port read-write conflicts.

[0027] Specifically, the dual-port BRAM uses port A for writing to update metadata and port B for reading metadata, enabling single-cycle access response and serving as a high-frequency, fast access channel for large-capacity DDR storage. Atomic operations are used for shared fields to resolve read / write conflicts between the two ports.

[0028] Specifically, in this embodiment, the dual-port BRAM has two completely independent read / write ports, which can perform read / write operations simultaneously. The access latency is a single system clock cycle, perfectly matching the high-speed operation requirements of the scheduling system. Port A connects to the write scheduling link and is used to update write-side metadata such as the write pointer, valid data volume, and channel status; Port B connects to the read scheduling link and is used to query read-side metadata such as the read pointer, valid data volume, and channel status.

[0029] The channel management table uses an entry-based storage method, with each channel corresponding to a fixed-length record. Each record contains the following core fields: channel ID, DDR base address, write pointer offset, read pointer offset, number of valid data bytes, channel operating status, service priority, idle timer, and configuration parameters. In addition to channel records, the BRAM also maintains global management information such as the idle channel stack and global space statistics for rapid allocation and reclamation of channel resources. To address read / write conflicts when two ports simultaneously access the same address, this invention employs an atomic operation mechanism for shared fields such as valid data volume and status: when one side is performing a write operation, the read operation on the other side will be delayed by one cycle or return to the stable value of the previous cycle, avoiding reading erroneous data in an intermediate state and ensuring metadata consistency.

[0030] In some optional embodiments, each record in the channel management table contains all the metadata of the corresponding channel. The channel management table stores idle channel status information and is used for idle channel retrieval during channel allocation and resource return management during channel release.

[0031] Step 130: The DDR ring buffer layer is organized into a DDR ring buffer by allocating an independent contiguous address space for each valid satellite communication signal channel in the DDR memory.

[0032] In this embodiment, the DDR circular buffer layer provides a large-capacity data cache space. Storage space reuse is achieved through the cyclic movement of read and write pointers. The DDR memory cache area is divided into multiple independent subspaces, with each active channel occupying a contiguous address space, organized into a circular buffer structure. The circular buffer is managed by two pointers: a write pointer indicates the location of the next data to be written, and a read pointer indicates the location of the next data to be read. When either the write or read pointer reaches the end address of the buffer, it automatically wraps back to the starting address, cyclically utilizing the storage space. When the write pointer catches up with the read pointer, the buffer is full, and no more data can be written; when the read pointer catches up with the write pointer, the buffer is empty, and no data can be read.

[0033] In some optional embodiments, the DDR ring buffer layer allocates an independent contiguous address space for each valid satellite communication signal channel in the DDR memory, including: when signal data from a new satellite communication signal channel arrives, querying the channel management table to confirm the channel identity, allocating DDR storage space for the satellite communication signal channel, and filling in the metadata and status information of the corresponding satellite communication signal channel in the channel management table.

[0034] Channel allocation is the entry process for incorporating a new channel into the system scheduling, as shown in the attached document. Figure 2 As shown, the specific implementation steps for channel allocation are as follows: After the front end detects the signal input of a new channel, it sends a channel establishment request to the centralized scheduling extractor, which carries information such as channel ID, service priority and expected rate. After receiving a request, the channel management unit queries the channel management table to confirm whether the channel ID already exists. If the channel already exists and is active, the active time is updated and existing resources are reused. If it is a brand new channel, an idle channel entry is first taken from the idle channel stack and a channel index is allocated. Then, the DDR free address pool is queried, a contiguous storage space matching the channel rate is allocated, and the starting base address and total length of the space are obtained. Initialize the fields of the corresponding entry in the channel management table: set the base address to the allocated DDR starting address, clear the write pointer and read pointer offsets to zero, clear the effective data volume to zero, set the channel status to active, set the priority to the level specified in the request, and clear the idle timer to zero. Once initialization is complete, the channel is officially included in the write and read scheduling scope, and the front end can begin writing data to the corresponding FIFO, thus completing the channel allocation process.

[0035] As attached Figure 3 The diagram illustrates the read / write relationship of a circular buffer. The buffer is divided into two areas: a free storage area and a valid data storage area. Data is transferred from the free area to the valid data area during a write operation, and data is released back to the free area during a read operation. When an address reaches the end of the buffer, a loopback logic jumps to the beginning of the free area, achieving circular reuse of storage space. Independent write and read address pointers are used to manage the write and read positions respectively: the write address pointer follows the write operation, and the read address pointer follows the read operation, synchronously mapping the data distribution state within the buffer. In a full buffer state: the write address pointer catches up with the read address pointer, there is no remaining free space, and writing cannot continue; in an empty buffer state: the read address pointer catches up with the write address pointer, there is no valid data, and a read operation cannot be performed.

[0036] Optimize for DDR access characteristics: map data of the same channel to the same physical row of DDR to reduce cross-row access overhead; design a ring wrap-around split write logic to handle scenarios where the write address crosses the end of the buffer.

[0037] When the write address crosses the end of the circular buffer space, a split write operation is performed to complete the circular wraparound. Because the beginning and end of the circular buffer are not contiguous, when the length of a burst write exceeds the distance from the write pointer to the end of the buffer, the write operation is split into two segments: the first segment writes from the current write pointer to the end of the buffer, and the second segment writes the remaining length from the beginning address of the buffer. The write scheduler automatically performs address calculation and splitting, transparent to the upper-level scheduler, ensuring logical continuity of the data.

[0038] In some alternative embodiments, as shown in the appendix Figure 4 As shown, the method also includes channel release, including: The inspection thread periodically scans the idle status of all satellite communication signal channels. When it detects that a satellite communication signal channel has timed out of idle time, it marks the channel status of that satellite communication signal channel as being released. Empty the remaining data in the FIFO corresponding to the satellite communication signal channel and wait for the DDR write operation of the satellite communication signal channel to be completed. Return the DDR address space of the satellite communication signal channel to the free address pool, update the channel management table, and set the channel status of the satellite communication signal channel to free; The historical records of idle timeouts of satellite communication signal channels are statistically analyzed. If there are sufficient historical records, the average historical timeout plus a fixed threshold is used as the updated timeout threshold; if there are insufficient historical records, the default timeout threshold is used.

[0039] Step 140: The write arbitrator in the centralized scheduler polls the FIFO status of each channel and writes the data to be written in the FIFO in batches into the DDR ring buffer of the corresponding satellite communication signal channel according to the scheduling rules.

[0040] As attached Figure 5 As shown, the data to be written in the FIFO is written in batches to the DDR circular buffer of the corresponding satellite communication signal channel according to the scheduling rules, including: After the write arbitrator starts, it checks the FIFO status of each channel in a preset polling order. If the FIFO of the current channel is not empty, it calculates the writable data length of the channel and queries the channel management table to obtain the write pointer and remaining DDR storage space of the channel. If the remaining storage space is sufficient, it performs a DDR burst write operation to write the data in the FIFO to the corresponding DDR circular buffer. After the write is completed, it updates the write pointer and valid data volume of the channel in the channel management table. If the remaining storage space is insufficient, it triggers a space full self-cleaning process.

[0041] The space-full self-cleaning mechanism employs a tiered cleanup strategy, performing different space reclamation operations based on channel priority, including: The channel priority is divided into first-level channels, second-level channels, third-level channels, and fourth-level channels. For first-level channels, write operations are paused. For second-level channels, cached data of one burst length is cleared. For third-level channels, cached data of a first set percentage (e.g., 20%) is cleared. For fourth-level channels, cached data of a second set percentage (e.g., 50%) is cleared. After data clearing is completed, storage space is reclaimed, buffer level status is updated, and normal write scheduling is restored.

[0042] Step 150: After receiving the extraction request from the backend, the centralized scheduling extractor reads data in batches from the corresponding DDR circular buffer according to the metadata of the channel management table, assembles it, and outputs it to the backend processing unit.

[0043] As attached Figure 6 As shown, after receiving the extraction request from the backend, the centralized scheduling extractor reads data in batches from the corresponding DDR circular buffer based on the metadata of the channel management table, including: After receiving a data extraction request, the centralized scheduling extractor verifies the operating status of the target channel; After the running status verification is passed, the channel management table is queried to obtain the effective data volume of the target channel, and the address range of this read is calculated; Determine whether the current read range crosses the boundary of the circular buffer. If so, perform split read and data concatenation operations; otherwise, perform a single DDR burst read operation. The read data is assembled and output, and the read address information of the channel in the channel management table is updated at the same time.

[0044] As attached Figure 7 As shown, the method also includes DDR memory space defragmentation, including: when insufficient DDR memory space is detected, first check the available space of the DDR free address pool; if the free address pool space is insufficient, scan all channels in an idle state and reclaim their DDR space to the free address pool; if the space is still insufficient after reclamation, sort all active channels according to DDR base address and eliminate memory space fragmentation by data migration; update the base address and read / write pointer of each active channel, and merge the consecutive free space at the end to the free address pool.

[0045] This method employs a hybrid scheduling mechanism that combines preemptive priority scheduling and deficit polling scheduling. Preemptive priority scheduling ensures low-latency transmission of high-priority services such as emergency telemetry and control and critical signaling, while deficit polling guarantees long-term bandwidth fairness for ordinary service channels. This approach perfectly adapts to the characteristics of satellite communication, which features multiple services coexisting and varying quality of service requirements.

[0046] This invention constructs a fully closed-loop space operation and maintenance system, from water level monitoring and back pressure flow control to hierarchical self-cleaning, fragmentation defragmentation, and adaptive channel management: back pressure flow control reduces the risk of overflow from the source; hierarchical self-cleaning differentiates losses according to priority in extreme scenarios to minimize the impact on business; fragmentation defragmentation solves the problem of resource degradation in long-term operation; and adaptive timeout thresholds improve the flexibility of resource utilization. The entire mechanism ensures that the system can operate continuously and stably for a long time, meeting the unattended operation and maintenance requirements of spaceborne systems.

[0047] The three-tiered architecture can be implemented based on mainstream FPGAs without the need for additional dedicated hardware. The logic and storage resources are controllable, fully complying with the stringent constraints of power consumption, size, and weight of spaceborne payloads. The number of channels can be flexibly configured by expanding the channel management table entries, adapting to satellite communication systems of different scales. It has high engineering reference and reuse value for various high-speed multi-channel signal acquisition and data scheduling systems.

[0048] This invention achieves efficient caching and centralized scheduling of multi-channel satellite communication signals with limited hardware resources through a three-layer storage architecture, hybrid scheduling strategy, and fully closed-loop operation and maintenance mechanism. It balances high throughput, low latency, fairness, and high reliability, fully adapts to the stringent constraints of spaceborne systems, and has high engineering application value.

[0049] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-channel signal buffering and centralized scheduling extraction method, characterized in that, A three-tier storage architecture combined with a centralized scheduler extractor is used to achieve buffering and scheduling extraction of multi-channel signals; The three-tier memory architecture includes a FIFO cross-clock domain buffer layer, a RAM channel management table layer, and a DDR ring buffer layer. The method includes: For each satellite communication signal channel, an asynchronous FIFO is used in the FIFO cross-clock domain buffer layer for cross-clock domain processing. On the write side, the signal sampling clock drives the writing of sampled data, and on the read side, the system master clock drives the reading, thus completing the isolation between the signal clock domain and the system clock domain and absorbing sampling jitter. The RAM channel management table layer constructs a channel management table through on-chip RAM, storing metadata and status information of all satellite communication signal channels, and performs single-cycle queries and updates as DDR access channels; The DDR ring buffer layer is organized into a DDR ring buffer by allocating an independent, contiguous address space for each valid satellite communication signal channel in the DDR memory; The write arbitrator in the centralized scheduler polls the FIFO status of each channel and writes the data to be written in the FIFO in batches into the DDR ring buffer of the corresponding satellite communication signal channel according to the scheduling rules. After receiving the extraction request from the backend, the centralized scheduling extractor reads data in batches from the corresponding DDR circular buffer according to the metadata of the channel management table, assembles it, and outputs it to the backend processing unit.

2. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, The on-chip RAM is a dual-port BRAM on the FPGA. The dual-port BRAM includes the first port and the second port of the FPGA. The first port is used for write-side access to update channel metadata. The second port is used for read-side access to query channel metadata. For shared fields in the channel management table, atomic operations are used to resolve dual-port read-write conflicts.

3. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1 or 2, characterized in that, Each record in the channel management table contains all the metadata for the corresponding channel. The channel management table stores the status information of idle channels and is used for the management of idle channel retrieval during channel allocation and resource return during channel release.

4. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, The storage method of the DDR ring buffer is as follows: data from the same satellite communication signal channel is mapped to the same physical row of the DDR; when the write address crosses the end of the ring buffer space, a split write operation is performed to complete the ring wrap-around process.

5. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, The DDR ring buffer layer allocates an independent, contiguous address space for each valid satellite communication signal channel in the DDR memory. This includes: when signal data from a new satellite communication signal channel arrives, querying the channel management table to confirm the channel identity, allocating DDR storage space for the satellite communication signal channel, and filling in the corresponding satellite communication signal channel's metadata and status information in the channel management table.

6. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, It also includes channel release, including: The inspection thread periodically scans the idle status of all satellite communication signal channels. When it detects that a satellite communication signal channel has timed out of idle time, it marks the channel status of that satellite communication signal channel as being released. Empty the remaining data in the FIFO corresponding to the satellite communication signal channel and wait for the DDR write operation of the satellite communication signal channel to be completed. Return the DDR address space of the satellite communication signal channel to the free address pool, update the channel management table, and set the channel status of the satellite communication signal channel to free; The historical records of idle timeouts of satellite communication signal channels are statistically analyzed. If there are sufficient historical records, the average historical timeout plus a fixed threshold is used as the updated timeout threshold; if there are insufficient historical records, the default timeout threshold is used.

7. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, According to the scheduling rules, the data to be written in the FIFO is written in batches to the DDR circular buffer of the corresponding satellite communication signal channel, including: After the write arbitrator starts, it checks the FIFO status of each channel in a preset polling order. If the FIFO of the current channel is not empty, it calculates the writable data length of the channel and queries the channel management table to obtain the write pointer and remaining DDR storage space of the channel. If the remaining storage space is sufficient, it performs a DDR burst write operation to write the data in the FIFO to the corresponding DDR circular buffer. After the write is completed, it updates the write pointer and valid data volume of the channel in the channel management table. If the remaining storage space is insufficient, it triggers a space full self-cleaning process.

8. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, After receiving the extraction request from the backend, the centralized scheduler extractor reads data in batches from the corresponding DDR circular buffer based on the metadata of the channel management table, including: After receiving a data extraction request, the centralized scheduling extractor verifies the operating status of the target channel; After the running status verification is passed, the channel management table is queried to obtain the effective data volume of the target channel, and the address range of this read is calculated; Determine whether the current read range crosses the boundary of the circular buffer. If so, perform split read and data concatenation operations; otherwise, perform a single DDR burst read operation. The read data is assembled and output, and the read address information of the channel in the channel management table is updated at the same time.

9. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, The space-full self-cleaning mechanism employs a tiered cleanup strategy, performing different space reclamation operations based on channel priority, including: The channel priority is divided into first-level channels, second-level channels, third-level channels, and fourth-level channels. For first-level channels, write operations are paused. For second-level channels, cached data of one burst length is cleared. For third-level channels, cached data of a first predetermined proportion is cleared. For fourth-level channels, cached data of a second predetermined proportion is cleared. After data clearing is completed, storage space is reclaimed, buffer level status is updated, and normal write scheduling is restored.

10. The multi-channel signal buffering and centralized scheduling extraction method according to claim 1, characterized in that, It also includes DDR memory space defragmentation, including: when insufficient DDR memory space is detected, first check the available space in the DDR free address pool; if the free address pool space is insufficient, scan all channels in an idle state and reclaim their DDR space to the free address pool; if the space is still insufficient after reclamation, sort all active channels by DDR base address and eliminate memory space fragmentation by data migration; update the base address and read / write pointer of each active channel, and merge the last consecutive free space to the free address pool.

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