A high-conductivity high-heat-dissipation vertical NPN power device based on heterojunction bonding and a preparation method thereof

Abstract

The application provides a high-conductivity and high-heat-dissipation vertical NPN power device based on heterojunction and a preparation method. The device comprises a substrate layer, a low-concentration N-type doped layer, a P-type doped layer, a high-concentration N-type doped layer, a source trench, a gate trench, a gate dielectric layer, a source metal, a gate metal and a drain metal. The high-concentration N-type doped layer is integrated by wafer bonding or low-temperature hetero-epitaxy, thereby avoiding threshold shift and subthreshold characteristic degradation caused by uncontrollable passivation degree in a traditional scheme. The high-conductivity and high-heat-dissipation high-concentration N-type doped layer is covered on the active region of the device, thereby reducing the steady-state and transient junction temperature of the device under high current density and / or high switching frequency conditions, alleviating the deterioration of carrier mobility and gate dielectric reliability caused by self-heating effect, and widening the safe working area and power density upper limit of the device.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor power devices, and in particular to a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) vertical power devices possess advantages such as high breakdown field strength, high electron mobility, uniform current conduction, and decoupling between breakdown voltage and chip area, making them considered core devices for next-generation high-efficiency power electronics. In a typical vertical GaN power device, an n-type drain layer, a p-type base layer, and an n-type source layer form a vertical NPN stacked structure from bottom to top. Among these, the p-type base layer is the key region for the formation of the gate-controlled conductive channel, and its hole concentration directly determines the device's threshold voltage, channel mobility, and switching characteristics.

[0003] The aforementioned structure faces unavoidable process challenges in actual fabrication. In the hydrogen-rich environment of metal-organic chemical vapor deposition (MOCVD) growth, the magnesium acceptor in p-GaN readily forms Mg-H complexes with hydrogen, resulting in passivation and a high-resistivity state. Therefore, high-temperature annealing at 700℃~900℃ is necessary after epitaxy to break the Mg-H bonds, remove hydrogen atoms, and activate p-type conductivity. To form n... + For p-GaN source layers, a second MOCVD epitaxial growth is typically required after the p-GaN has been activated. This step also takes place in a hydrogen-rich environment, where the activated magnesium acceptors recombine with hydrogen, resulting in large-area repassivation and a sharp decrease in the hole concentration near the p-GaN interface. Simultaneously, n + The high temperatures required for GaN regrowth (typically above 1000℃) also cause magnesium atoms to migrate towards n atoms. + Layer diffusion and silicon atoms diffuse into the p-layer, forming a non-ideal gradually compensating junction, which significantly degrades the steepness and blocking ability of the pn junction.

[0004] If ion implantation is used to form n + - To avoid a hydrogen-rich environment, GaN sources require activation annealing at temperatures of 1100℃~1300℃ to induce damage, far exceeding the thermal decomposition critical point of GaN under normal pressure. This easily leads to surface nitrogen escape and irreversible lattice damage. Therefore, traditional methods struggle to achieve both optimal performance in the "activation-passivation-reactivation" cycle. The conflict between thermal budget and hydrogen environment constitutes a major obstacle to the practical application of vertical GaN power devices.

[0005] Furthermore, GaN itself has low thermal conductivity (approximately 1.3 W / (cm·K)), resulting in significant self-heating effects in devices at high power densities. Traditional n... +The GaN source layer covers the device surface and is located precisely on the main path of heat dissipation. Its low thermal conductivity and limited electron mobility further exacerbate the vicious cycle between on-state voltage drop and junction temperature rise. Summary of the Invention

[0006] The purpose of this invention is to provide a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding, which can simultaneously achieve good heat dissipation and source region series resistance without being subject to p-type dopant repassivation and high-temperature thermal diffusion damage, and its fabrication method.

[0007] The first aspect of this invention provides a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding, comprising: a substrate layer, a low-concentration N-type doped layer, a P-type doped layer, a high-concentration N-type doped layer, a source trench, a gate trench, a gate dielectric layer, a source metal, a gate metal, and a drain metal; the low-concentration N-type doped layer is homoepitaxially epitaxially formed on the upper surface of the substrate layer; the P-type doped layer is homoepitaxially formed on the upper surface of the low-concentration N-type doped layer; the high-concentration N-type doped layer is heteroepitaxially formed on the upper surface of the P-type doped layer via wafer bonding / low-temperature heteroepitaxial formation, used to suppress the outward diffusion of dopants in the P-type doped layer; wherein, the high-concentration N-type doped layer has high thermal conductivity and high electron density. A wide-bandgap N-type semiconductor material with high mobility; a source trench perpendicularly penetrating the high-concentration N-type doped layer and extending to the P-type doped layer; a gate trench perpendicularly penetrating the high-concentration N-type doped layer and the P-type doped layer and extending to the low-concentration N-type doped layer; a gate dielectric layer covering the sidewalls and bottom of the gate trench; a source metal filling the source trench and electrically connected to the high-concentration N-type doped layer and the P-type doped layer respectively; a gate metal filling the gate trench and is isolated from the high-concentration N-type doped layer, the P-type doped layer and the low-concentration N-type doped layer respectively through the gate dielectric layer; and a drain metal formed on the lower surface of the substrate layer.

[0008] Preferably, the high-concentration N-type doped layer is 3C-SiC.

[0009] Preferably, the high-concentration N-type doped layer is any one or more combinations of 4H-SiC, 6H-SiC, n-type diamond, and c-BN.

[0010] Preferably, the nitrogen doping concentration of the high-concentration N-type doped layer is 1×10⁻⁶. 18 cm -3 -5×10 18 cm -3 .

[0011] Preferably, the substrate is a GaN substrate, and the low-concentration N-type doped layer is an n-type doped layer. - -GaN drift layer, the n -The silicon doping concentration of the GaN drift layer is 1×10⁻⁶. 16 cm -3 -5×10 16 cm -3 .

[0012] Preferably, the p-type doped layer is a p-GaN layer, and the magnesium doping concentration of the p-GaN layer is 1×10⁻⁶. 17 cm -3 -5×10 17 cm -3 .

[0013] Preferably, the substrate layer is a Ga2O3 substrate layer, and the low-concentration N-type doped layer is an n - -Ga2O3 drift layer, wherein the p-type doped layer is a p-Ga2O3 layer; or, the substrate layer is an AlN substrate layer, wherein the low-concentration N-type doped layer is an n - -AlN drift layer, wherein the p-type doped layer is a p-AlN layer.

[0014] Preferably, the gate dielectric layer is one of SiO2 insulating dielectric layer, Si3N4 insulating dielectric layer or Al2O3 insulating dielectric layer.

[0015] A second aspect of this invention provides a method for fabricating a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding, comprising: A wide bandgap semiconductor material is prepared as a substrate layer, and a low-concentration N-type doped layer and a P-type doped layer are sequentially homoepitaxially epitaxially formed on the upper surface of the substrate layer. A high-concentration N-type doped layer is formed on the upper surface of the P-type doped layer by wafer bonding / low-temperature heteroepitaxialization. The high-concentration N-type doped layer is an N-type wide bandgap semiconductor material with high thermal conductivity and high electron mobility. By using a mask to etch gate trenches, the gate trenches vertically penetrate the high-concentration N-type doped layer and the P-type doped layer and extend to the low-concentration N-type doped layer; A gate dielectric layer is covered on the sides and bottom of the gate trench; By using a mask to etch source trenches, the source trenches vertically penetrate the high-concentration N-type doped layer and extend to the P-type doped layer; Deposit source metal into the source trench, so that the source metal is electrically connected to the high-concentration N-type doped layer and the P-type doped layer respectively; Deposit gate metal into a gate trench, such that the gate metal is isolated from the high-concentration N-type doped layer, the P-type doped layer, and the low-concentration N-type doped layer through the gate dielectric layer, respectively; Drain metal is deposited onto the lower surface of the substrate.

[0016] Preferably, the operating temperature for wafer bonding / low-temperature heteroepitaxialization of the upper surface of the P-type doped layer to produce a high-concentration N-type doped layer is below 800°C, and the operating environment is an inert atmosphere free of hydrogen.

[0017] The beneficial effects of this plan are as follows: 1) This invention uses a high-concentration N-type doped layer directly as the source region of the device, eliminating the process step of secondary epitaxial regeneration of the n-type semiconductor layer on the activated P-type doped layer; the high-concentration N-type doped layer is integrated through wafer bonding or low-temperature heteroepitaxial integration, without exposing the P-type doped layer to a high-temperature hydrogen-rich environment throughout the process, thus fundamentally eliminating the physical mechanism of magnesium acceptor being passivated again, ensuring that the P-type doped layer maintains a high hole concentration after acceptor activation, so that the gate's control over the channel is fully realized, the device threshold voltage is precisely controllable, and the batch consistency is good, avoiding the threshold drift and subthreshold characteristic degradation caused by the uncontrollable passivation degree of traditional solutions.

[0018] 2) A high-concentration N-type doped layer with high thermal conductivity and high electron mobility covers the active region of the device, which is located on the main path of heat conduction from the channel to the package shell. This is equivalent to integrating a high thermal conductivity channel on the surface of the active region, which can reduce the steady-state and transient junction temperature of the device under high current density and / or high switching frequency conditions, alleviate the degradation of carrier mobility and gate dielectric reliability caused by self-heating effect, and broaden the safe operating area and power density limit of the device.

[0019] 3) Materials with high concentration of N-type doped layers have wide bandgap, high electron mobility and high doping efficiency, and can provide low resistivity electron sources. This heterogeneous source structure significantly reduces the series resistance component of the source region, reduces the on-state voltage drop, and improves the current driving capability and power conversion efficiency.

[0020] The above three performance improvements are achieved simultaneously by the core structural change of "replacing the regenerated n-type source layer with a high-concentration N-type doped layer by wafer bonding or low-temperature heteroepitaxial integration", which makes the fabrication process shorter, the process compatibility stronger, and the device performance better. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding. Figure 2 A schematic diagram of steps S1-S2 in the fabrication method of a vertical NPN power device; Figure 3 A schematic diagram of step S3 in the fabrication method of a vertical NPN power device; Figure 4 A schematic diagram of step S4 in the fabrication method of a vertical NPN power device; Figure 5A schematic diagram of step S5 in the fabrication method of a vertical NPN power device; Figure 6 A schematic diagram of step S6 in the fabrication method of a vertical NPN power device; Figure 7 This is a flowchart illustrating steps S7-8 of the method for fabricating a vertical NPN power device.

[0022] Explanation of reference numerals in the attached figures: 1. Substrate layer; 2. Low-concentration N-type doped layer; 3. P-type doped layer; 4. High-concentration N-type doped layer; 5. Source trench; 6. Gate trench; 7. Gate dielectric layer; 8. Source metal; 9. Gate metal; 10. Drain metal. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention; the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "joined" should be interpreted broadly, for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal communication of two components. For those skilled in the art, the specific meaning of the terms in this invention can be understood according to the specific circumstances.

[0025] Vertical NPN power devices refer to power semiconductor devices that consist of an n-type source region, a p-type base region, and an n-type drain region arranged in a vertical stack. Their typical implementation is a vertical trench gate metal-oxide-semiconductor field-effect transistor (MOSFET).

[0026] Wafer bonding refers to the integration method of directly or through an intermediate layer to bond a mother wafer with a high concentration of N-type doped layer to a wafer with a P-type doped layer. This includes, but is not limited to, direct bonding, surface activation bonding, metal intermediary bonding, and smart lift-off (ion cutting) bonding transfer.

[0027] Low-temperature heteroepitaxial growth refers to the process of heterogeneously growing a high-concentration N-type doped layer on the surface of a P-type doped layer at temperatures below 800°C without the introduction of hydrogen. This includes, but is not limited to, molecular beam epitaxy, chemical vapor deposition using nitrogen or argon as the carrier gas and without hydrogen source precursors, magnetron sputtering or pulsed laser deposition combined with low-temperature solid-state crystallization, etc.

[0028] A high-concentration N-type doped layer refers to a semiconductor layer that is predominantly N-type doped with a higher doping concentration than a low-concentration N-type doped layer. It serves as the source region of a device, covering the P-type doped layer. On the one hand, it provides a low-resistance source electron path, and on the other hand, it acts as a capping layer in subsequent thermal processes to suppress the outward diffusion of acceptor dopants (such as magnesium) in the P-type doped layer, thus maintaining the steepness of the pn junction interface.

[0029] A low-concentration N-type doped layer refers to a drift layer with a low doping concentration, used to withstand the reverse voltage of a device.

[0030] Example 1 See Figure 1 This embodiment provides a high conductivity and high heat dissipation vertical NPN power device based on heterobonding. The device is a trench gate vertical structure device, which includes, from bottom to top, a substrate layer 1, a low concentration N-type doped layer 2, a P-type doped layer 3 and a high concentration N-type doped layer 4, as well as a source trench 5, a gate trench 6, a gate dielectric layer 7, a source metal 8, a gate metal 9 and a drain metal 10.

[0031] Substrate layer 1 is an n-type heavily doped GaN single crystal substrate (silicon doped), with a doping concentration of approximately 2 × 10⁻⁶. 18 cm -3 (The selectable range is 1×10) 18 cm -3 ~5×10 18 cm -3 The thickness is approximately 350 μm (selectable range is 300 μm~400 μm). The low-concentration N-type doped layer 2 is formed by homoepitaxial growth on the surface of substrate layer 1 via hydride vapor phase epitaxy (HVPE). - -GaN drift layer, approximately 7 μm thick, with a doping concentration of approximately 2 × 10⁻⁶. 16 cm -3 (The selectable range is 1×10) 16 cm -3 ~8×10 17 cm -3 1×10 is preferred 16 cm -3 ~5×10 16 cm -3The p-type doped layer 3 serves as the breakdown voltage drift region of the device. It is a p-GaN layer formed by homoepitaxial growth on the surface of the low-concentration N-type doped layer 2 via MOCVD, with a thickness of approximately 400 nm (selectable range 100 nm to 1000 nm) and a magnesium doping concentration of approximately 5 × 10⁻⁶. 17 cm -3 (The selectable range is 1×10) 17 cm -3 ~5×10 17 cm -3 The magnesium acceptor is activated by annealing at 700℃~900℃ in a nitrogen atmosphere, serving as the p-type base region (P-body) of the device.

[0032] The high-concentration N-type doped layer 4 is a nitrogen-doped 3C-SiC layer, integrated onto the upper surface of the P-type doped layer 3 via wafer bonding or low-temperature heteroepitaxial growth. Its thickness is approximately 200 nm (selectable range: 100 nm to 300 nm), and the nitrogen doping concentration is approximately 2 × 10⁻⁶. 18 cm -3 (The selectable range is 1×10) 18 cm -3 ~5×10 18 cm -3 The thermal conductivity of 3C-SiC is approximately 3.6 W / (cm·K), which is 2.8 times that of GaN, and it also exhibits high electron mobility and good doping efficiency. The high-concentration N-type doped layer 4 serves two purposes: firstly, it reduces the source contact resistance as a source region; secondly, it acts as a protection / stop layer in the trench etching process; and thirdly, it suppresses the outward diffusion of magnesium from the P-type doped layer 3 in subsequent thermal processes.

[0033] The gate trench 6 starts from the surface of the high-concentration N-type doped layer 4, vertically penetrates the high-concentration N-type doped layer 4 and the P-type doped layer 3, and extends to the low-concentration N-type doped layer 2 (it may terminate at the surface of the low-concentration N-type doped layer 2, or extend inward by 50 nm to 100 nm to enhance gate control). The gate dielectric layer 7 covers the sidewalls and bottom of the gate trench 6, for example, it is an Al2O3 insulating dielectric layer formed by atomic layer deposition (ALD), or it may be a SiO2 insulating dielectric layer or a Si3N4 insulating dielectric layer, with a thickness of about 30 nm (optionally ranging from 20 nm to 50 nm). The gate metal 9 fills the gate trench 6, for example, it is a Ni / Au metal stack with a thickness of about 150 nm to 200 nm; the gate metal 9 is insulated and isolated from the high-concentration N-type doped layer 4, the P-type doped layer 3, and the low-concentration N-type doped layer 2 through the gate dielectric layer 7, and is used to control the opening and closing of the channel.

[0034] The source trench 5 vertically penetrates the high-concentration N-type doped layer 4 and extends into the P-type doped layer 3 (e.g., extending 50 nm to 150 nm into the P-type doped layer 3). The source metal 8 fills the source trench 5 and is electrically connected (ohmic contact) to both the high-concentration N-type doped layer 4 and the P-type doped layer 3, thereby achieving source extraction while short-circuiting the p-type base region to the source, suppressing the turn-on of the parasitic bipolar transistor. The source metal 8 is, for example, a Ti / Al / Ni / Au metal stack with a total thickness of approximately 200 nm (selectable range is 100 nm to 300 nm). The drain metal 10 is formed on the lower surface of the substrate layer 1, for example, a Ti / Al / Ni / Au metal stack (each layer thickness is, for example, 20 nm / 100 nm / 30 nm / 50 nm), and forms an ohmic contact with the substrate layer 1 after rapid thermal annealing.

[0035] In operation, a forward bias is applied to the drain metal 10, and the source metal 8 is grounded. When the voltage on the gate metal 9 is greater than the threshold voltage, the surface of the P-type doped layer 3 at the sidewall of the gate trench 6 inverts to form a conductive channel. Current flows from the source metal 8 through the high-concentration N-type doped layer 4, the channel, the low-concentration N-type doped layer 2, and the substrate layer 1 to the drain metal 10. When the gate voltage is lower than the threshold voltage, the channel is pinched off, and the device is turned off. Because the high-concentration N-type doped layer 4 covers the active region and has high thermal conductivity, the heat generated in the channel during device operation can be quickly conducted outward through the high-concentration N-type doped layer 4, and the junction temperature is effectively controlled.

[0036] With existing n + Compared to traditional vertical GaN MOSFETs where GaN is regrown as the source region, this invention introduces a 3C-SiC / p-GaN / n-GaN heterojunction NPN structure, completely replacing the n-GaN with a 3C-SiC source layer. + -GaN regrowing of the source electrode brings the following significant advantages and technical effects: 1. This invention uses the 3C-SiC layer directly as the device source region, eliminating the need for n-type polarization on top of the activated p-GaN in traditional solutions. + - The GaN secondary MOCVD regeneration process involves a long step. The 3C-SiC layer is integrated using wafer bonding or low-temperature heteroepitaxial growth (<800°C), eliminating the need for p-GaN to be exposed to a high-temperature, hydrogen-rich environment throughout the process. This structure-process decoupling design fundamentally eliminates the physical mechanism of magnesium acceptor re-passivation, ensuring that the p-GaN base region maintains a high carrier concentration after initial activation. The technical benefits are: precise and controllable device threshold voltage with good batch consistency; and full realization of the gate's ability to regulate the channel conductivity path, fundamentally solving the threshold drift and subthreshold characteristic degradation problems caused by uncontrollable passivation in traditional solutions.

[0037] 2. The thermal conductivity of 3C-SiC is approximately 3.6 W / cm·K, which is 2.8 times that of GaN (approximately 1.3 W / cm·K). This invention uses 3C-SiC as the source layer, covering the active region of the device directly above it, precisely along the main path of heat conduction from the channel to the package shell. This is equivalent to integrating a highly thermally conductive heat dissipation channel on the surface of the active region. Compared to traditional n... + The GaN source-based thermal bottleneck structure of this invention can effectively reduce the steady-state and transient junction temperature of the device under high current density and / or high switching frequency conditions, alleviate the deterioration effect of self-heating on carrier mobility and gate dielectric reliability, and directly broaden the safe operating area boundary and practical power density upper limit of the device.

[0038] 3. 3C-SiC possesses characteristics such as wide bandgap, high electron mobility, and high doping efficiency. This invention uses it as the source electron source, compared to n-type electrons which are limited by mobility and doping concentration. + -GaN offers lower resistivity. This heterogeneous source structure significantly reduces the contribution of the source region series resistance to the total on-resistance during device conduction, thereby lowering the on-state voltage drop and ohmic losses. This resistive advantage is even more pronounced in high-current applications, directly translating into higher current drive capability and power conversion efficiency, making it particularly suitable for high-frequency power conversion and compact power supply systems sensitive to conduction losses.

[0039] The three performance improvements mentioned above—passivation removal, enhanced heat dissipation, and reduced resistance—are not simply the sum of independent technical measures, but rather a result of "replacing n with 3C-SiC". + The synergistic effect achieved simultaneously by the single core structural change of "GaN regeneration source electrode" demonstrates the high degree of integration of the solution: the device fabrication process eliminates n + The process time is significantly shortened by reducing the GaN regrowth and related repair steps, resulting in a substantial reduction in the process thermal budget. At the same time, the 3C-SiC / p-GaN heterointerface is independent of the activation history of p-GaN in terms of process, making the interface quality easier to control. This helps to suppress performance degradation under long-term high temperature and high field stress, providing structural assurance for the device to meet the stringent reliability requirements of automotive-grade or industrial-grade power electronics.

[0040] Example 2 See Figure 2-7 This embodiment provides a method for fabricating the above-mentioned vertical NPN power device, including steps S1 to S8.

[0041] S1. Provide a semiconductor epitaxial wafer with an activated p-type doped layer. A heavily n-type doped GaN single-crystal substrate (silicon doped, approximately 2 × 10⁻⁶) is selected. 18 cm -3 (Approximately 350 μm thick), an n-type substrate approximately 7 μm thick was epitaxially grown on its upper surface using HVPE.- -GaN drift layer (silicon doped, approximately 2 × 10⁻⁶) 16 cm -3 Then, MOCVD is used in n - A p-GaN layer (magnesium-doped, approximately 5 × 10⁻⁶ nm thick) is grown on the surface of the GaN drift layer. 17 cm -3 Subsequently, the p-GaN layer was annealed at 700℃~900℃ in a nitrogen atmosphere to break the Mg-H bonds and remove hydrogen atoms, thus completing the magnesium acceptor activation.

[0042] S2. Integrate a high-concentration N-type doped layer on the upper surface of the P-type doped layer. Either of the following two methods can be used: Method 1 (Wafer Bonding): Prepare an additional nitrogen-doped 3C-SiC wafer (doping concentration approximately 2 × 10⁻⁶). 18 cm -3 The 3C-SiC layer is then surface-activated and bonded to the already activated p-GaN surface (by activating the bonding surface with an argon ion beam in a vacuum environment followed by room temperature pressing), or bonded using a metal interlayer bonding method or smart lift-off (ion cutting) bonding transfer method. Subsequently, the 3C-SiC layer is thinned and chemically mechanically polished to control its thickness to 100 nm–300 nm (e.g., 200 nm). The bonding and thinning process is carried out at temperatures below 800 °C in a vacuum or an inert atmosphere free of hydrogen, such as nitrogen or argon.

[0043] High-concentration N-type doped layers (such as SiC) and P-type layers (such as GaN) are bonded together using wafer bonding technology. During the bonding process, the surface atoms of the two crystals undergo interdiffusion and rebonding under pressure and heat treatment, inevitably forming an amorphous transition layer with a thickness of only a few nanometers at the interface.

[0044] This amorphous transition layer is composed of atoms from both sides of the material and lacks a long-range ordered lattice arrangement. This structural feature allows it to act as a stress buffer layer between two semiconductor materials with different lattice constants. Traditional heteroepitaxy produces high-density dislocations because the atoms in the newly grown layer are forced to "align" with the lattice points of the underlying crystal. The difference in lattice constants accumulates stress in the vertical direction, eventually releasing it as dislocations. However, the amorphous transition layer in this scheme breaks this forced continuation of the lattice period, fundamentally resolving the interfacial stress caused by the lattice mismatch between GaN and SiC, thus preventing severe defects in the crystals on either side.

[0045] Meanwhile, since the thickness of the amorphous transition layer is controlled at only a few nanometers, electrons can easily pass through the layer through tunneling or hopping conduction mechanisms, and the conductivity is almost unaffected. Thermally, the extremely thin interface layer also keeps the interface thermal resistance at an extremely low level, without affecting the overall vertical heat dissipation capability of the device.

[0046] Method 2 (Low-Temperature Heteroepitaxy): On the acceptor-activated p-GaN surface, a nitrogen-doped 3C-SiC layer is heteroepitaxically grown at a temperature below 800℃ in an inert atmosphere (nitrogen or argon carrier gas) without hydrogen. The thickness is 100 nm to 300 nm (e.g., 200 nm), and the doping concentration is 1 × 10⁻⁶. 18 cm -3 ~5×10 18 cm -3 (e.g. 2×10) 18 cm -3 ).

[0047] Since the integration temperature is below 800℃ and there is no hydrogen throughout the process, the activated magnesium acceptors in p-GaN will not undergo repassivation; at the same time, the high-concentration N-type doped layer covering the p-GaN surface can suppress the outward diffusion of magnesium in subsequent thermal processes.

[0048] S3. Gate trench etching. Photoresist is coated on the surface of the high-concentration N-type doped layer, and the gate etching window is defined by photolithography and development. The high-concentration N-type doped layer 4 and P-type doped layer 3 are etched sequentially using the photoresist as a mask. The etching depth is controlled by endpoint detection, so that the gate trench 6 vertically penetrates the high-concentration N-type doped layer 4 and P-type doped layer 3 and extends to the low-concentration N-type doped layer 2.

[0049] S4. Forming the gate dielectric layer. An Al2O3 gate dielectric layer (or SiO2, Si3N4) is deposited on the device surface using atomic layer deposition (ALD) with a thickness of approximately 30 nm (optional 20 nm~50 nm), so that the gate dielectric layer 7 covers the sidewalls and bottom of the gate trench 6.

[0050] S5. Source trench etching. Photoresist is coated and photolithography is performed to define the source window above the high-concentration N-type doped layer 4; etching is performed using photoresist as a mask (e.g., ICP-RIE) to penetrate the high-concentration N-type doped layer 4 and extend 50 nm to 150 nm into the P-type doped layer 3 to form the source trench 5; the photoresist is then removed.

[0051] S6. Deposit source metal. Coat the surface of the high-concentration N-type doped layer with photoresist to define the source metal region; deposit a Ti / Al / Ni / Au metal stack (total thickness approximately 200 nm, optionally 100 nm~300 nm) by electron beam evaporation or magnetron sputtering to fill the source trench 5. Then, remove excess metal outside the trench through a lift-off or planarization process, allowing the source metal 8 to fill the source trench 5 and electrically connect with the high-concentration N-type doped layer 4 and the P-type doped layer 3. Optionally, perform rapid thermal annealing at 500℃~700℃ in a nitrogen atmosphere to improve the source ohmic contact.

[0052] S7. Deposit gate metal. Coat photoresist and define the gate metal region. Deposit gate metal (Ni / Au stack, total thickness approximately 150 nm~200 nm) to fill the gate trench 6. Then, strip or planarize to remove excess metal outside the gate trench. The gate metal 9 is kept insulated from the high-concentration N-type doped layer 4, the P-type doped layer 3, and the low-concentration N-type doped layer 2 through the gate dielectric layer 7.

[0053] S8. Backside Thinning and Drain Metal Deposition. The backside of the wafer is mechanically thinned to 200 μm~300 μm; drain metal 10 (Ti / Al / Ni / Au, with layer thicknesses of, for example, 20 nm / 100 nm / 30 nm / 50 nm) is deposited on the lower surface of the thinned substrate layer 1; rapid thermal annealing is performed under a nitrogen atmosphere at an annealing temperature of approximately 850℃ (optionally 800℃~900℃) to form an ohmic contact between the drain metal 10 and the substrate layer 1, completing the device fabrication. Optionally, source ohmic contact annealing can be combined with this step.

[0054] In other embodiments, the ratio T1:T2 of the thickness T1 of the high-concentration N-type doped layer 4 to the thickness T2 of the P-type doped layer 3 can be selected in the range of 1:10 to 10:1, and the doping concentration of the high-concentration N-type doped layer 4 can be 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The range is selected to balance the source ohmic contact resistance and the device breakdown characteristics.

[0055] The material of the high-concentration N-type doped layer 4 is not limited to 3C-SiC. In other embodiments, the high-concentration N-type doped layer 4 can be any one of 4H-SiC, 6H-SiC, n-type diamond, c-BN, or a stacked structure formed by at least two of these materials; all of the above materials have high thermal conductivity, high electron mobility and wide bandgap characteristics, and can be integrated by wafer bonding or low-temperature heteroepitaxial growth.

[0056] The substrate system is not limited to GaN. In other embodiments, substrate 1 can be a Ga2O3 substrate (n-type doped), and the low-concentration N-type doped layer 2 can be an n-type doped layer accordingly. - -Ga2O3 drift layer (such as Si or Sn doping), p-type doped layer is p-Ga2O3 layer;; or, substrate 1 is AlN substrate, and low-concentration N-type doped layer 2 is n-type substrate. - -AlN drift layer (such as Si doping), P-type doped layer is p-AlN layer.

[0057] The integration method of the high-concentration N-type doped layer 4 is not limited to the examples above. Any process path that can satisfy the requirement of "integrating the high-concentration N-type doped layer in a low-temperature process that does not expose the P-type doped layer to a hydrogen-containing environment after the P-type doped layer is activated by the master, such as direct wafer bonding, surface activation bonding, smart lift-off transfer bonding, metal-intermediate bonding, and various low-temperature heteroepitaxial processes, can be used in this invention.

[0058] Furthermore, the core concept of this invention, namely replacing the regrown n-type source layer with a high thermal conductivity, high mobility N-type wide bandgap semiconductor layer through wafer bonding or low-temperature heteroepitaxial integration, can also be extended to other device configurations such as planar gate vertical power devices, current aperture vertical power devices, and even heterojunction bipolar transistors. All equivalent substitutions within the scope of this invention should be considered to fall within the protection scope of this invention.

[0059] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding, characterized in that, include: Substrate layer, A low-concentration N-type doped layer is homoepitaxially epitaxially formed on the upper surface of the substrate layer; A p-type doped layer is homoepitaxially formed on the upper surface of the low-concentration n-type doped layer; A high-concentration N-type doped layer is formed on the upper surface of the P-type doped layer by wafer bonding / low-temperature heteroepitaxial growth to suppress the outward diffusion of dopants in the P-type doped layer; wherein, the high-concentration N-type doped layer is an N-type wide-bandgap semiconductor material with high thermal conductivity and high electron mobility; The source trench vertically penetrates the high-concentration N-type doped layer and extends into the P-type doped layer; The gate trench vertically penetrates the high-concentration N-type doped layer and the P-type doped layer and extends to the low-concentration N-type doped layer; A gate dielectric layer covers the sidewalls and bottom of the gate trench; The source metal is filled in the source trench and electrically connected to the high-concentration N-type doped layer and the P-type doped layer, respectively. Gate metal is filled in the gate trench and isolated from the high-concentration N-type doped layer, the P-type doped layer and the low-concentration N-type doped layer respectively through the gate dielectric layer; Drain metal is formed on the lower surface of the substrate layer.

2. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 1, characterized in that, The high-concentration N-type doped layer is 3C-SiC.

3. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 1, characterized in that, The high-concentration N-type doped layer is any one or more combinations of 4H-SiC, 6H-SiC, n-type diamond, and c-BN.

4. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 1, characterized in that, The nitrogen doping concentration of the high-concentration N-type doped layer is 1×10⁻⁶. 18 cm -3 -5×10 18 cm -3 .

5. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 1, characterized in that, The substrate is a GaN substrate, and the low-concentration N-type doped layer is an n-type doped layer. - -GaN drift layer, the n - The silicon doping concentration of the GaN drift layer is 1×10⁻⁶. 16 cm -3 -5×10 16 cm -3 .

6. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 5, characterized in that, The p-type doped layer is a p-GaN layer, and the magnesium doping concentration of the p-GaN layer is 1×10⁻⁶. 17 cm -3 -5×10 17 cm -3 .

7. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 1, characterized in that, The substrate is a Ga2O3 substrate, and the low-concentration N-type doped layer is an n - -Ga2O3 drift layer, wherein the p-type doped layer is a p-Ga2O3 layer; or, the substrate layer is an AlN substrate layer, wherein the low-concentration N-type doped layer is an n - -AlN drift layer, wherein the p-type doped layer is a p-AlN layer.

8. The high conductivity and high heat dissipation vertical NPN power device based on heterobonding according to claim 1, characterized in that, The gate dielectric layer is one of SiO2 insulating dielectric layer, Si3N4 insulating dielectric layer or Al2O3 insulating dielectric layer.

9. A method for fabricating a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding, characterized in that, include: A wide bandgap semiconductor material is prepared as a substrate layer, and a low-concentration N-type doped layer and a P-type doped layer are sequentially homoepitaxially epitaxially formed on the upper surface of the substrate layer. A high-concentration N-type doped layer is formed on the upper surface of the P-type doped layer by wafer bonding / low-temperature heteroepitaxialization. The high-concentration N-type doped layer is an N-type wide bandgap semiconductor material with high thermal conductivity and high electron mobility. By using a mask to etch gate trenches, the gate trenches vertically penetrate the high-concentration N-type doped layer and the P-type doped layer and extend to the low-concentration N-type doped layer; A gate dielectric layer is covered on the sides and bottom of the gate trench; By using a mask to etch source trenches, the source trenches vertically penetrate the high-concentration N-type doped layer and extend to the P-type doped layer; Deposit source metal into the source trench, so that the source metal is electrically connected to the high-concentration N-type doped layer and the P-type doped layer respectively; Deposit gate metal into a gate trench, such that the gate metal is isolated from the high-concentration N-type doped layer, the P-type doped layer, and the low-concentration N-type doped layer through the gate dielectric layer, respectively; Drain metal is deposited onto the lower surface of the substrate.

10. The method for fabricating a high-conductivity, high-heat-dissipation vertical NPN power device based on heterobonding according to claim 9, characterized in that, The operating temperature for wafer bonding / low-temperature heteroepitaxialization of the upper surface of the P-type doped layer to produce a high-concentration N-type doped layer is below 800°C, and the operating environment is an inert atmosphere free of hydrogen.

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