Transistor, array substrate and display panel

Abstract

The application discloses a transistor, an array substrate and a display panel. The transistor comprises an active layer, a source-drain electrode layer, a first insulating layer and a second insulating layer. The active layer comprises at least two metal-oxide semiconductor layers. The active layer comprises a first surface and a second surface arranged oppositely along the thickness direction of the semiconductor layer. The source-drain electrode layer is in contact with the second surface of the active layer. The first insulating layer covers at least the first surface of the active layer and comprises at least two silicon oxide layers. The second insulating layer covers at least the second surface of the active layer and the source-drain electrode layer and comprises at least two silicon oxide layers. The molar content of hydrogen atoms in at least one silicon oxide layer in the first insulating layer is less than or equal to 5%. The application effectively improves the problem of threshold voltage negative bias of the transistor, and significantly improves the stability and process adaptability of the transistor while maintaining high mobility.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a transistor, an array substrate, and a display panel. Background Technology

[0002] In recent years, with the gradual maturation of Metal Oxide Thin Film Transistor (TFT) technology, it has become compatible with an increasing number of display technology specifications, and traditional silicon-based semiconductor display panels are gradually being replaced by TFT technology. However, in high-specification display products with ultra-high refresh rates, high resolutions, and narrow bezels, Low Temperature Polycrystalline Silicon (LTPS) backplane technology is still the primary choice. This is mainly due to the ultra-high carrier mobility and stability of LTPS, which can meet the driving performance requirements of high-end display products. However, limited by the Excimer Laser Annealing (ELA) process, LTPS backplane technology is currently difficult to achieve efficient mass production on large-generation production lines, resulting in relatively high manufacturing costs.

[0003] Currently, large-generation production lines in the industry have successively achieved conventional indium gallium zinc oxide (IGZO) with a mobility of approximately 10 cm⁻¹. 2 / V·s) and high-mobility oxides (mobility approximately 30cm) 2 Mass production delivery of ( / V·s). To further reduce the manufacturing cost of ultra-high specification display products while meeting high performance requirements, ultra-high mobility oxide thin-film transistors (mobility approximately 50 cm⁻¹) are being developed. 2 / V·s) has become an important research and development direction for next-generation display backplane technology.

[0004] However, compared to conventional IGZO or indium gallium zinc tin oxide (IGZTO) devices, ultra-high mobility oxide thin film transistors (UTCs) present greater challenges in terms of threshold voltage control and device stability. They are highly sensitive to environmental factors and the presence of water vapor and hydrogen (H) in the manufacturing process, resulting in a narrower process window and higher requirements for process condition control during production, which increases the difficulty of large-scale manufacturing. Summary of the Invention

[0005] This application provides a transistor, an array substrate, and a display panel, which effectively improves the problem of the threshold voltage of the transistor being easily negatively biased, and significantly improves the stability and process adaptability of the transistor while maintaining high mobility.

[0006] To achieve the above objectives, according to a first aspect of this application, a transistor is provided, comprising: An active layer includes at least two stacked semiconductor layers; the semiconductor layers are made of metal oxide, and the active layer includes a first surface and a second surface disposed opposite to each other along the thickness direction of the semiconductor layers; The source / drain electrode layer is in contact with the second surface of the active layer; A first insulating layer covers at least the first surface of the active layer and includes at least two stacked silicon oxide layers. The second insulating layer covers at least the second surface of the active layer and the source / drain electrode layer, and includes at least two stacked silicon oxide layers. Wherein, in the first insulating layer and the second insulating layer, the molar content of hydrogen atoms in at least one layer of the silicon oxide in the first insulating layer is less than or equal to 5%.

[0007] Optionally, the first insulating layer includes a first silicon oxide layer and a second silicon oxide layer stacked together, wherein the second silicon oxide layer is located between the first silicon oxide layer and the active layer; The molar content of hydrogen atoms in the first silicon oxide layer is less than or equal to 3%, and the molar content of hydrogen atoms in the second silicon oxide layer is less than 5%; or, the molar content of hydrogen atoms in the first silicon oxide layer is less than 5%, and the molar content of hydrogen atoms in the second silicon oxide layer is less than or equal to 3%.

[0008] Optionally, at least one of the first silicon oxide layer and the second silicon oxide layer has an etching rate of less than 15 Å / s under a dry etching process.

[0009] Optionally, the second insulating layer includes a third silicon oxide layer and a fourth silicon oxide layer stacked together, wherein the third silicon oxide layer is located between the active layer and the fourth silicon oxide layer; The molar content of hydrogen atoms in at least one of the third silicon oxide layer and the fourth silicon oxide layer is less than or equal to 5%, or the molar content of hydrogen atoms in at least one of the third silicon oxide layer and the fourth silicon oxide layer is greater than or equal to 3% and less than or equal to 8%.

[0010] Optionally, the thickness of the third silicon oxide layer and / or the fourth silicon oxide layer ranges from 500 Å to 2500 Å; the thickness of the second insulating layer ranges from 2500 Å to 4000 Å.

[0011] Optionally, the molar content of hydrogen atoms in the third silicon oxide layer is less than or equal to 5%, or the molar content of hydrogen atoms in the third silicon oxide layer is greater than or equal to 3% and less than or equal to 8%; the etching rate of the fourth silicon oxide layer under dry etching process is less than 15 Å / s.

[0012] Optionally, the transistor further includes a third insulating layer located on the side of the first insulating layer opposite to the active layer, and a fourth insulating layer located on the side of the second insulating layer opposite to the active layer, wherein both the third insulating layer and the fourth insulating layer include at least one silicon nitride layer.

[0013] Optionally, the fourth insulating layer includes a first silicon nitride layer and a second silicon nitride layer stacked together, wherein the first silicon nitride layer is located between the second insulating layer and the second silicon nitride layer; In the first silicon nitride layer and the second silicon nitride layer, at least the molar content of hydrogen atoms in the first silicon nitride layer is less than 5%.

[0014] Optionally, the source / drain electrode layer is in contact with the second surface of the active layer, and the second insulating layer covers the first insulating layer, the source / drain electrode layer, and the second surface; The transistor further includes a gate located on the side of the third insulating layer opposite to the first insulating layer and aligned with the active layer.

[0015] Optionally, the active layer includes a first semiconductor layer and a second semiconductor layer stacked together, wherein the second semiconductor layer is located between the first semiconductor layer and the source / drain electrode layer; Both the first semiconductor layer and the second semiconductor layer are made of metal oxides. The first semiconductor layer contains at least indium, and the second semiconductor layer contains at least zinc.

[0016] Optionally, the material of the first semiconductor layer includes at least one of indium oxide, indium zinc oxide, indium gallium oxide, indium zinc tin oxide, and indium gallium zinc tin oxide; And / or, the material of the second semiconductor layer includes at least one of indium gallium zinc oxide, gallium zinc oxide, and zinc oxide.

[0017] Optionally, the first semiconductor layer further contains zinc, and the molar ratio of indium to zinc in the first semiconductor layer is greater than or equal to 2. And / or, the first semiconductor layer further contains gallium, and in the first semiconductor layer, the molar ratio of indium to gallium is greater than or equal to 2; And / or, the first semiconductor layer further contains tin, and the molar percentage of tin in the metal elements of the first semiconductor layer is less than or equal to 5%.

[0018] Optionally, the first semiconductor layer further contains doping elements, including any one or more of iron, praseodymium, terbium, dysprosium, lanthanum, and aluminum, and / or, in the metal elements of the first semiconductor layer, the molar percentage of the doping element is less than or equal to 2%.

[0019] Optionally, the second semiconductor layer further contains indium, and the molar ratio of indium to zinc in the second semiconductor layer is less than or equal to 1:5.

[0020] Optionally, the thickness of the first semiconductor layer ranges from 50 Å to 200 Å, and the thickness of the second semiconductor layer ranges from 100 Å to 300 Å.

[0021] Optionally, the active layer further includes a third semiconductor layer located between the first semiconductor layer and the second semiconductor layer, wherein the material of the third semiconductor layer is a metal oxide; The third semiconductor layer contains at least indium and gallium, and the molar ratio of indium to gallium in the third semiconductor layer is less than or equal to 1:1.

[0022] Optionally, the material of the third semiconductor layer includes at least one of indium gallium zinc oxide and indium gallium zinc tin oxide; And / or, the thickness of the third semiconductor layer ranges from 100 Å to 500 Å.

[0023] Optionally, the carrier mobility of the transistor is greater than 45 cm⁻¹. 2 / V·s, and less than 60 cm 2 / V·s; And / or, the threshold voltage of the transistor is greater than or equal to 0V.

[0024] According to a second aspect of this application, an array substrate is provided, the array substrate comprising the transistors described above.

[0025] According to a third aspect of this application, a display panel is also provided, the display panel comprising the transistors described above, or the display panel comprising the array substrate described above.

[0026] In the transistors, array substrates, and display panels provided in this application embodiment, the active layer of the transistor is a multilayer metal oxide semiconductor layer, which is beneficial to improving the carrier mobility of the transistor, such as achieving high mobility or ultra-high mobility. Furthermore, the first and second surfaces of the active layer are each provided with at least two stacked silicon oxide layers, and the source and drain electrode layers are disposed on the second surface of the active layer. Therefore, by controlling the molar content of hydrogen atoms in at least one silicon oxide layer in the first insulating layer located at least on the first surface to be less than or equal to 5%, the first insulating layer contains at least one silicon oxide layer with low hydrogen content. This design can effectively block water vapor and hydrogen from the periphery of the first surface of the active layer, thereby enhancing the protection effect of the active layer against water vapor or hydrogen in the environment or process from the device structure. It optimizes the problem of difficult threshold voltage control of high (or ultra-high) mobility transistors, widens the process debugging window of high (or ultra-high) mobility transistors, and effectively improves the problem of easy negative bias of the threshold voltage of transistors. While maintaining high (or ultra-high) mobility, it significantly improves the stability and process adaptability of transistors. Therefore, the transistors provided in this application embodiment are suitable for manufacturing on large-generation production lines and can provide a technical foundation for the industrial application of next-generation display backplane technology and ultra-high-end display products.

[0027] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0030] Figure 1 This is a schematic cross-sectional view of an exemplary back-channel etched ultra-high mobility thin-film transistor provided in this application; Figure 2 yes Figure 1 The drain current-gate voltage characteristic curve of the ultra-high mobility thin film transistor is shown. Figure 3 This is a schematic diagram of a cross-sectional structure of a transistor provided in an embodiment of this application; Figure 4 yes Figure 3 A schematic diagram illustrating the fabrication process of a transistor; Figure 5 This is a schematic diagram of the structure for forming the gate in the transistor fabrication method provided in this application embodiment; Figure 6 This is a schematic diagram of the structure in which the third insulating layer and the first insulating layer are formed in the transistor fabrication method provided in this application embodiment; Figure 7 This is a schematic diagram of the structure for forming the active layer and source / drain electrode layers in the transistor fabrication method provided in this application embodiment; Figure 8 This is a schematic diagram of the structure for forming the second insulating layer in the transistor fabrication method provided in this application embodiment; Figure 9 yes Figure 3 The diagram shows the drain current-gate voltage characteristic curve of the transistor. Figure 10 This is a schematic cross-sectional view of an array substrate provided in an embodiment of this application; Figure 11 This is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of this application.

[0031] Explanation of reference numerals in the attached figures: 10. Substrate layer; 20. Gate; 30. Silicon nitride gate insulating layer; 40. Silicon oxide gate insulating layer; 50. Active layer; 51'. First metal oxide semiconductor layer; 51. First semiconductor layer; 52'. Second metal oxide semiconductor layer; 52. Third semiconductor layer; 53'. Third metal oxide semiconductor layer; 53. Second semiconductor layer; 54. First surface; 55. Second surface; 60. Source / drain electrode layer; 61. Source; 62. Drain; 70. Silicon oxide passivation layer; 80. Silicon nitride passivation layer; 100, Transistor; 110, First insulating layer; 111, First silicon oxide layer; 112, Second silicon oxide layer; 120, Second insulating layer; 121, Third silicon oxide layer; 122, Fourth silicon oxide layer; 130, Third insulating layer; 140, Fourth insulating layer; 141, First silicon nitride layer; 142, Second silicon nitride layer; 200, Array substrate; 210, Pixel electrode; 220, Organic planarization layer; 300. Display panel; 310. Light-emitting layer. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0033] Because ultra-high mobility oxide layers are extremely sensitive to water vapor or hydrogen, conventional film layer fabrication methods for the front and rear channels of ultra-high mobility thin-film transistors (UHMTs) cannot meet the protection requirements of UHMTs against water vapor or hydrogen, resulting in a decrease in the threshold voltage V of the UHMT. th Significant negative bias and lack of process adjustment window increase the difficulty of production process control, resulting in the inability to meet the production and usage requirements of display panels.

[0034] like Figure 1 As shown, an exemplary back channel etch (BCE) type ultra-high mobility thin-film transistor includes, from bottom to top, a substrate layer (e.g., a glass substrate) 10, a gate 20, a silicon nitride gate insulating layer 30, a silicon oxide gate insulating layer 40, an active layer 50, a source / drain electrode layer 60, a silicon oxide passivation layer 70, and a silicon nitride passivation layer 80. The silicon nitride gate insulating layer 30, the silicon oxide gate insulating layer 40, the silicon oxide passivation layer 70, and the silicon nitride passivation layer 80 are all single-layer structures. The active layer 50 includes a first metal oxide semiconductor layer 51', a second metal oxide semiconductor layer 52', and a third metal oxide semiconductor layer 53' sequentially stacked on the silicon oxide gate insulating layer 40. The first metal oxide semiconductor layer 51' is a transport layer, the second metal oxide semiconductor layer 52' ​​is a buffer layer, and the third metal oxide semiconductor layer 53' is a protective layer. The source and drain electrode layer 60 includes a source electrode 61 and a drain electrode 62 spaced apart. The source electrode 61, the drain electrode 62 and the active layer 50 are formed in the same photomask process.

[0035] Figure 1 The drain current-gate voltage characteristic curve of the ultra-high mobility thin-film transistor is shown in Figure 1. Figure 2 As shown, Figure 2 The curve data shown were collected from 20 different locations (sample space) on the same glass substrate under the same process conditions.

[0036] according to Figure 2 It can be seen that the threshold voltage V of this ultra-high mobility thin-film transistor is... th The mean value was -1.48V, and the range reached 9.92V, indicating significant dispersion in the characteristic curve, with some test points approaching a short-circuit state. The inventors discovered that the main reason for this result is that the ultra-high mobility oxide layer is highly sensitive to water vapor and hydrogen. The single-layer structure of the silicon nitride gate insulating layer 30, silicon oxide gate insulating layer 40, silicon oxide passivation layer 70, and silicon nitride passivation layer 80 cannot effectively block water vapor / hydrogen, allowing water vapor or hydrogen to diffuse into the ultra-high mobility oxide layer, thus increasing the threshold voltage V. thSignificant negative drift was observed. Due to the severe negative bias of the threshold voltage and its wide distribution range, the device lacked an effective process debugging window, ultimately resulting in the electrical characteristics of this ultra-high mobility thin-film transistor failing to meet the application requirements of display panels.

[0037] It should be noted that the drain current-gate voltage characteristic curve described in the embodiments of this application is also called the Ids-Vgs characteristic curve, that is, the relationship curve between drain current Ids and gate voltage Vgs. The horizontal axis represents the gate voltage Vgs in volts (V); the vertical axis represents the drain current Ids in amperes (A), and is expressed on a logarithmic scale.

[0038] To address the threshold voltage V of ultra-high mobility oxide thin-film transistors th To address the negative bias issue, this application has specifically optimized the process and structure of each key film layer, as described in the following embodiments.

[0039] like Figure 3 As shown, this application provides a transistor 100, which includes an active layer 50, a source / drain electrode layer 60, a first insulating layer 110, and a second insulating layer 120.

[0040] Specifically, the active layer 50 includes at least two stacked semiconductor layers, the semiconductor layers being made of metal oxide. The active layer 50 includes a first surface 54 and a second surface 55 disposed opposite each other along the thickness direction of the semiconductor layers, and the source / drain electrode layer 60 is in contact with the second surface 55 of the active layer 50. A first insulating layer 110 at least covers the first surface 54 of the active layer 50 and includes at least two stacked silicon oxide (SiO2) layers. x The second insulating layer 120 covers at least the second surface 55 of the active layer 50 and the source / drain electrode layer 60, and includes at least two stacked silicon oxide layers.

[0041] In the first insulating layer 110 and the second insulating layer 120, the molar content of hydrogen atoms in at least one silicon oxide layer in the first insulating layer 110 is less than or equal to 5%.

[0042] It is understood that the active layer 50 provided in this application embodiment is composed of at least two semiconductor layers made of metal oxide material, and the corresponding transistor 100 is a metal oxide transistor.

[0043] In some embodiments, the transistor 100 provided in this application is a thin-film transistor, but is not limited thereto.

[0044] Specifically, by employing multiple metal-oxide-semiconductor (MOS) layers as the active layer 50, the carrier concentration, oxygen vacancy content, and band structure of different MOS layers can be synergistically controlled, thereby balancing device mobility and stability. For example, a portion of the MOS layers in the active layer 50 can serve as a transport layer, providing higher electron mobility to enhance carrier transport capability and improve the driving performance of the transistor 100. Simultaneously, another portion of the MOS layers in the active layer 50 can serve as a protective or buffer layer, suppressing the diffusion of external water vapor, hydrogen, and impurity ions into the transport layer, reducing the interface defect state density, and improving the interface bandgap matching, thereby reducing threshold voltage drift and improving device stability and reliability. Furthermore, this portion of the MOS layers can also protect the channel region of the transistor 100 during wet etching of other film layers such as the source / drain electrode layers 60, reducing corrosion damage to the channel from etching solutions such as copper acid, thereby improving device consistency and process reliability.

[0045] Understandably, the source / drain electrode layer 60 includes a source electrode 61 and a drain electrode 62 spaced apart, and the source electrode 61 and the drain electrode 62 are in contact with the first surface 54 or the second surface 55 of the active layer 50, respectively. The portion of the active layer 50 corresponding to the region between the source electrode 61 and the drain electrode 62 can be referred to as a channel.

[0046] Understandably, a silicon oxide layer with a hydrogen atom molar content of less than or equal to 5% can be called a low-hydrogen (H) layer, that is, a film layer with a low H content.

[0047] Specifically, by controlling the molar content of hydrogen atoms in at least one silicon oxide layer in the first insulating layer 110 of the active layer 50 to be less than or equal to 5%, the hydrogen content in the first insulating layer 110 can be reduced. At the same time, the first insulating layer 110 can block water vapor and hydrogen in other film layers, preventing water vapor and hydrogen from invading into the active layer 50 through the first surface 54, thereby enhancing the protective effect of the active layer 50 against water vapor or hydrogen in the environment or process.

[0048] Understandably, the molar content of hydrogen atoms in at least one silicon oxide layer in the second insulating layer 120 can be controlled to be less than or equal to 5%, thereby reducing the hydrogen content in the second insulating layer 120. At the same time, the second insulating layer 120 can block water vapor and hydrogen in other film layers, preventing water vapor and hydrogen from invading into the active layer 50 through the second surface 55, thereby further enhancing the protective effect of the active layer 50 against water vapor or hydrogen in the environment or process.

[0049] In this embodiment, since the active layer 50 of transistor 100 is composed of multiple metal oxide semiconductor layers, it is beneficial to improve the carrier mobility and stability of transistor 100, such as achieving high mobility or ultra-high mobility. Furthermore, the first surface 54 and the second surface 55 of the active layer 50, which are arranged opposite to each other, are each provided with at least two layers of silicon oxide. The source and drain electrode layers 60 are disposed on the second surface 55 of the active layer. Therefore, by controlling the molar content of hydrogen atoms in at least one layer of silicon oxide in the first insulating layer 110 located at least on the first surface 54 to be less than or equal to 5%, the first insulating layer 110 contains at least one layer of silicon oxide with low hydrogen content. This design can effectively block water vapor and hydrogen from the periphery of the first surface 54 of the active layer 50. From the device structure, it enhances the protection effect of the active layer 50 against water vapor or hydrogen in the environment or process, optimizes the problem of difficult threshold voltage control of high (or ultra-high) mobility transistor 100, and widens the process debugging window of high (or ultra-high) mobility transistor 100. This effectively improves the problem of easy negative bias of threshold voltage of transistor 100, and significantly improves the stability and process adaptability of transistor 100 while maintaining high (or ultra-high) mobility. Therefore, the transistor 100 provided in this application embodiment is suitable for manufacturing on large-generation production lines and can provide a technical foundation for the industrial application of next-generation display backplane technology and ultra-high-end display products.

[0050] It should be noted that the process window described in the embodiments of this application refers to the range of allowable fluctuations in various process parameters (such as temperature, pressure, gas flow rate, time, impurity concentration, etc.) during the manufacturing process. If the process window is narrow, the range of allowable fluctuations in various process parameters during the manufacturing process is very limited, which increases the difficulty of production process control and is not conducive to large-generation production lines.

[0051] In some embodiments, the first insulating layer 110 includes a first silicon oxide layer 111 and a second silicon oxide layer 112 stacked together, with the second silicon oxide layer 112 located between the first silicon oxide layer 111 and the active layer 50. The molar content of hydrogen atoms in the first silicon oxide layer 111 is less than or equal to 3%, and the molar content of hydrogen atoms in the second silicon oxide layer 112 is less than 5%; or, the molar content of hydrogen atoms in the first silicon oxide layer 111 is less than 5%, and the molar content of hydrogen atoms in the second silicon oxide layer 112 is less than or equal to 3%.

[0052] It is understood that either the first silicon oxide layer 111 or the second silicon oxide layer 112 in the first insulating layer 110 can be a low-H layer. In this embodiment, a silicon oxide layer with a hydrogen atom molar content of less than or equal to 3% is referred to as the first low-H layer, and a silicon oxide layer with a hydrogen atom molar content of less than or equal to 5% is referred to as the second low-H layer. That is, the first low-H layer requires an even lower H content.

[0053] Since the first insulating layer 110 covers the first surface 54 of the active layer 50, the low-H layer in the first insulating layer 110 can improve the protection of the area where the first surface 54 of the active layer 50 is located against moisture or hydrogen in the environment or process. Especially when the first surface 54 of the active layer 50 is more sensitive to hydrogen, the presence of a first low-H layer with an even lower H content in the first insulating layer 110 further enhances the protection of the area where the first surface 54 of the active layer 50 is located against moisture or hydrogen in the environment or process.

[0054] In some embodiments, at least one of the first silicon oxide layer 111 and the second silicon oxide layer 112 has an etching rate of less than 15 Å / s under a dry etching process. That is, the first silicon oxide layer 111 and / or the second silicon oxide layer 112 have high density, which further improves the blocking effect of the first insulating layer 110 on water vapor or hydrogen.

[0055] Specifically, the dry etching process described in this application refers to an etching process performed using inductively coupled plasma (ICP) etching mode. During the etching process, parameters are calculated based on the glass substrate area. The process gases include CF4, O2, and Ar, wherein the CF4 gas flow rate can be set to 120 sccm / m³. 2 ~150sccm / m 2 The O2 gas flow rate can be set to 180 sccm / m 2 ~220sccm / m 2 The Ar gas flow rate can be set to 150 sccm / m 2 ~190sccm / m 2 The etching chamber pressure can be controlled from 10 mTorr to 30 mTorr, and the source power can be set to 4000 W / m. 2 ~4600W / m 2 The bias power can be set to 3500W / m 2 ~4000W / m 2 .

[0056] It should be noted that, under the same etching process, the etching rate of conventional SiO2 is typically in the range of 50 Å / s to 83 Å / s. However, the etching rate of the first silicon oxide layer 111 and / or the second silicon oxide layer 112 in this embodiment is less than 15 Å / s, far lower than the etching rate of conventional SiO2, indicating that the first silicon oxide layer 111 and / or the second silicon oxide layer 112 provided in this embodiment have high density and strong etching resistance. In this embodiment, the film layer with an etching rate of less than 15 Å / s under dry etching process is referred to as a high-density layer.

[0057] In one specific embodiment, both the first silicon oxide layer 111 and the second silicon oxide layer 112 have high density.

[0058] In some embodiments, the film formation process of the first silicon oxide layer 111 and the second silicon oxide layer 112 includes chemical vapor deposition (CVD) process, but is not limited thereto.

[0059] In one specific embodiment, the first silicon oxide layer 111 is a first low-H layer, and the second silicon oxide layer 112 is a second low-H layer. In this case, during the CVD deposition process of the first silicon oxide layer 111, the SiH4 / N2O (gas flow rate ratio) is greater than 1:100 and less than 1:50, and during the CVD deposition process of the second silicon oxide layer 112, the SiH4 / N2O ratio is greater than 1:70. Furthermore, both the first silicon oxide layer 111 and the second silicon oxide layer 112 require high-temperature deposition (deposition temperature greater than or equal to 300°C) to ensure that the formed first silicon oxide layer 111 and the second silicon oxide layer 112 have high density.

[0060] It is understandable that SiH4 / N2O refers to the ratio of gas flow rates during CVD film formation, and can also represent the Si:O ratio of the reaction gases.

[0061] In other embodiments, the second silicon oxide layer 112 is a first low-H layer, and the first silicon oxide layer 111 is a second low-H layer. In this case, the CVD film formation process of the first silicon oxide layer 111 and the second silicon oxide layer 112 can be reversed from the above embodiment.

[0062] It should be noted that one of the silicon oxide layers in the first insulating layer 110 is a first low-H layer to reduce the hydrogen content in the first insulating layer 110 and to block hydrogen from other film layers. However, the oxygen (O) content in the silicon oxide layer formed by the low-H process is relatively high. If multiple silicon oxide layers in the first insulating layer 110 are all first low-H layers, it may lead to an imbalance in the oxygen content inside the first insulating layer 110, thereby increasing the risk of interface oxidation, abnormal film stress, or oxygen erosion of the active layer, affecting device stability and lifespan. Therefore, in some embodiments, another silicon oxide layer in the first insulating layer 110 can be set as a second low-H layer or a non-low-H layer. By combining film layers with different oxygen contents, the overall elemental ratio of the first insulating layer 110 can be adjusted and balanced, thereby reducing the risk of device failure caused by oxygen enrichment. Therefore, the structure of the first insulating layer 110 not only retains the advantages of the low-H layer in suppressing hydrogen diffusion and improving threshold stability, but also improves the interface compatibility and structural stability between film layers, further improving the long-term reliability and production yield of the transistor 100 device.

[0063] It should be noted that the specific number of silicon oxide layers in the first insulating layer 110 is not limited in this application embodiment. It can be two layers, or it can be adjusted to three or even more layers as needed.

[0064] In some embodiments, the second insulating layer 120 includes a third silicon oxide layer 121 and a fourth silicon oxide layer 122 stacked together, with the third silicon oxide layer 121 located between the active layer 50 and the fourth silicon oxide layer 122. The molar content of hydrogen atoms in at least one of the third silicon oxide layer 121 and the fourth silicon oxide layer 122 is less than or equal to 5%. That is, at least one silicon oxide layer in the second insulating layer 120 is a second low-H layer.

[0065] Understandably, since the second insulating layer 120 covers the second surface 55 of the active layer 50, by controlling the hydrogen atom content in the third silicon oxide layer 121 and the fourth silicon oxide layer 122 in the second insulating layer 120, the protection effect of the area where the second surface 55 of the active layer 50 is located against water vapor or hydrogen in the environment or process can be improved.

[0066] In some embodiments, the film formation process of the third silicon oxide layer 121 and the fourth silicon oxide layer 122 includes a CVD process, but is not limited thereto.

[0067] In some embodiments, the third silicon oxide layer 121 is a second low-H layer or a low-damage layer. If the third silicon oxide layer 121 is a second low-H layer, the molar content of hydrogen atoms in the third silicon oxide layer 121 is less than or equal to 5%. If the third silicon oxide layer 121 is a low-damage layer, the molar content of hydrogen atoms in the third silicon oxide layer 121 is greater than or equal to 3% and less than or equal to 8%, and the total gas flow rate in the CVD film deposition process of the third silicon oxide layer 121 as a low-damage layer is at least 10% lower than the total gas flow rate in the CVD film deposition process of the third silicon oxide layer 121 as a second low-H layer; the film deposition power in the CVD film deposition process of the third silicon oxide layer 121 as a low-damage layer is at least 10% lower than the film deposition power in the CVD film deposition process of the third silicon oxide layer 121 as a second low-H layer; and the SiH4 / N2O ratio in the CVD film deposition process of the third silicon oxide layer 121 as a low-damage layer is less than 1:50. Since the third silicon oxide layer 121 is in direct contact with the second surface 55 of the active layer 50, this process condition design can ensure that the H content in the area of ​​the second surface 55 of the active layer 50 that is not covered by the source / drain electrode layer 60 is low, and improve the protection capability of the second surface 55 of the active layer 50 against H.

[0068] It should be noted that, as will be explained below, the semiconductor layer disposed near the first surface 54 of the active layer 50 is a transport layer, and the semiconductor layer disposed near the second surface 55 is a protective layer, resulting in the first surface 54 of the active layer being more sensitive to hydrogen (H) than the second surface 55. Therefore, by differentiating the H content range of the low-H layer in the first insulating layer 110 disposed near the first surface 54 and the second insulating layer 120 disposed near the second surface 55 in this embodiment of the application, water vapor and hydrogen can be effectively blocked from intruding into the active layer 50 through the first surface 54 and the second surface 55, thereby enhancing the protective effect of the active layer 50 against water vapor or hydrogen in the environment or process.

[0069] In some embodiments, the fourth silicon oxide layer 122 is a highly dense layer; for example, the etching rate of the fourth silicon oxide layer 122 under a dry etching process is less than 15 Å / s. This design ensures the protection of the second surface 55 of the active layer 50 against water vapor and hydrogen.

[0070] Understandably, the conditions for the dry etching process here are the same as those for the aforementioned dry etching process, and will not be repeated here.

[0071] In some embodiments, when the third silicon oxide layer 121 is a low-damage layer, the film formation power of the third silicon oxide layer 121 is 40% to 60% lower than that of the fourth silicon oxide layer 122, which is a high-density layer, to reduce the bombardment of the back channel. Furthermore, the N2O flow rate during the film formation of the third silicon oxide layer 121 needs to be at least 10% lower than that during the film formation of the fourth silicon oxide layer 122, which is a high-density layer, to reduce oxygen injection.

[0072] It should be noted that when the third silicon oxide layer 121 is the second low-H layer, it can reduce the leakage risk in the channel region of the active layer 50 and provide oxygen to the active layer 50; when the third silicon oxide layer 121 is a low-damage layer, it can reduce the damage to the channel region caused by the film deposition process. Both of the above-mentioned third silicon oxide layers 121 can protect the channel region of the active layer 50 and prevent damage to the channel of the active layer 50 caused by other film deposition processes. The fourth silicon oxide layer 122 has high density. Due to its high dissociation power during deposition, it can form a more dense SiOx film, thereby effectively improving the barrier ability of the channel region of the active layer 50 against water vapor and hydrogen, thus improving the stability and reliability of the transistor 100.

[0073] Furthermore, the high-density SiOx film layer is prone to causing significant damage to the channel of the active layer 50 during deposition, making it unsuitable for use as the second insulating layer 120 alone. This embodiment combines the third silicon oxide layer 121 with the fourth silicon oxide layer 122, utilizing the moisture-blocking, hydrogen-blocking, and protective properties of the low-hydrogen SiOx layer or the low-damage SiOx layer, while also reducing damage to the channel of the active layer 50 through the high-density SiOx layer. This balances the stability of the transistor 100, leakage current control, and process reliability.

[0074] Specifically, in the CVD film deposition process, the film deposition power of the fourth silicon oxide layer 122 is 1.2 to 2 times that of the third silicon oxide layer 121, in order to ensure that the fourth silicon oxide layer 122 has high density and improves its ability to block water vapor and hydrogen.

[0075] In some embodiments, the thickness of the third silicon oxide layer 121 and / or the fourth silicon oxide layer 122 ranges from 500 Å to 2500 Å; the thickness of the second insulating layer 120 ranges from 2500 Å to 4000 Å. This thickness design is beneficial for improving the film formation effect of the third silicon oxide layer 121 and the fourth silicon oxide layer 122, as well as improving the barrier ability of the second insulating layer 120 against water vapor and hydrogen.

[0076] In some embodiments, the second insulating layer 120 also covers the sidewall of the active layer 50 and the first insulating layer 110. In this case, the first insulating layer 110 and the second insulating layer 120 can provide all-round protection for the active layer 50, which can more effectively improve the protection effect of the active layer 50 against water vapor and hydrogen.

[0077] It should be noted that the specific number of silicon oxide layers in the second insulating layer 120 is not limited in this application embodiment. It can be two layers, or it can be adjusted to three or even more layers as needed.

[0078] In some embodiments, the transistor 100 further includes a third insulating layer 130 located on the side of the first insulating layer 110 away from the active layer 50, and a fourth insulating layer 140 located on the side of the second insulating layer 120 away from the active layer 50, wherein the third insulating layer 130 and the fourth insulating layer 140 each include at least one silicon nitride (SiNx) layer.

[0079] Specifically, the silicon nitride layers in the third insulating layer 130 and the fourth insulating layer 140 can block metal elements (such as Cu) in the metal layer, preventing them from diffusing into the active layer 50. A first insulating layer 110 is disposed between the third insulating layer 130 and the active layer 50, such that the silicon oxide layer in the first insulating layer 110 can block hydrogen (H) from the silicon nitride layer in the third insulating layer 130, preventing it from diffusing into the active layer 50. A second insulating layer 120 is disposed between the active layer 50 and the fourth insulating layer 140, such that the silicon oxide layer in the second insulating layer 120 can block hydrogen (H) from the silicon nitride layer in the fourth insulating layer 140, preventing it from diffusing into the active layer 50.

[0080] In some embodiments, the fourth insulating layer 140 is a single-layer silicon nitride layer used to block metal elements (e.g., Cu) in the metal layer from diffusing into the active layer 50.

[0081] In other embodiments, the fourth insulating layer 140 includes a first silicon nitride layer 141 and a second silicon nitride layer 142 stacked together, with the first silicon nitride layer 141 located between the second insulating layer 120 and the second silicon nitride layer 142. In the first silicon nitride layer 141 and the second silicon nitride layer 142, the molar content of hydrogen atoms in at least the first silicon nitride layer 141 is less than 5%. It is understood that the fourth insulating layer 140 includes at least one silicon nitride layer with a low H content.

[0082] To distinguish it from the case where the silicon oxide layer is used as a low-H layer, the embodiments of this application refer to the silicon nitride layer with a molar content of less than 5% of hydrogen atoms as the third low-H layer.

[0083] Understandably, at least the first silicon nitride layer 141 is the third low-H layer. Controlling the first silicon nitride to be the third low-H layer can block H in the second silicon nitride layer 142 and prevent it from invading the active layer 50.

[0084] In some embodiments, the third insulating layer 130 is a single layer of silicon nitride, but is not limited thereto.

[0085] In one specific embodiment, the source / drain electrode layer 60 is in contact with the second surface 55 of the active layer 50, and the second insulating layer 120 covers the first insulating layer 110, the source / drain electrode layer 60, and the second surface 55. The transistor 100 also includes a gate 20, which is located on the side of the third insulating layer 130 opposite to the first insulating layer 110 and is aligned with the active layer 50.

[0086] Understandably, the third insulating layer 130 can block metal elements in the gate 20, preventing them from diffusing into the active layer 50 and affecting device performance.

[0087] In some embodiments, the transistor 100 further includes a substrate layer 10, on which a gate 20, a third insulating layer 130, a first insulating layer 110, an active layer 50, a source / drain electrode layer 60, a second insulating layer 120, and a fourth insulating layer 140 are sequentially stacked. The substrate layer 10 may be a flexible substrate layer 10 or a rigid substrate layer 10. For example, the substrate layer 10 may be a polyimide substrate or a glass substrate, but is not limited thereto.

[0088] In one specific embodiment, transistor 100 is a back-channel etch (BCE) type thin-film transistor. That is, the source 61 and drain 62 in the source-drain electrode layer 60 are patterned in the same photomask process as the active layer 50. For example, the projections of the source 61 and drain 62 in the thickness direction of the first insulating layer 110 are located in the projection of the active layer 50 in the thickness direction of the first insulating layer 110, and the sidewalls of the source 61 and the drain 62 are respectively aligned with the sidewalls of the active layer 50.

[0089] Understandably, when transistor 100 is a BCE-type thin-film transistor, one photomask process can be saved. In this case, the portion of the channel of the active layer 50 near the second surface 55 can be called the back channel, and the portion near the first surface 54 can be called the front channel. The first insulating layer 110 and the third insulating layer 130 can be called the gate insulating layer, and the second insulating layer 120 and the fourth insulating layer 140 can be called the passivation layer.

[0090] It should be noted that the type of transistor 100 is not limited in the embodiments of this application, and the BCE type transistor 100 described above is only an example.

[0091] In some embodiments, the active layer 50 includes a first semiconductor layer 51 and a second semiconductor layer 53 stacked together, with the second semiconductor layer 53 located between the first semiconductor layer 51 and the source / drain electrode layer 60. Both the first semiconductor layer 51 and the second semiconductor layer 53 are made of metal oxide, with the first semiconductor layer 51 containing at least indium and the second semiconductor layer 53 containing at least zinc.

[0092] Specifically, the first semiconductor layer 51 can serve as a transport layer, utilizing the high electron mobility of indium-containing metal oxides to improve the carrier transport capability of the active layer 50, thereby enhancing the driving performance of the transistor 100. The second semiconductor layer 53 can serve as a protective layer, utilizing the low carrier concentration and good chemical stability of zinc-containing metal oxides to protect the first semiconductor layer 51. Through the synergistic effect of the first semiconductor layer 51 and the second semiconductor layer 53, on the one hand, the influence of external moisture, hydrogen, and impurity ions on the channel region of the active layer 50 can be reduced, decreasing threshold voltage drift and improving device stability; on the other hand, during the wet etching process in the formation of the source / drain electrode layer 60, the second semiconductor layer 53 can also reduce the corrosion damage to the channel region of the active layer 50 caused by etching solutions such as copper acid, thereby improving device consistency and process reliability.

[0093] In some embodiments, the material of the first semiconductor layer 51 includes at least one selected from indium oxide (InOx), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), and indium gallium zinc tin oxide (IGZTO). The indium-containing metal oxides listed above all possess high electron mobility, which is beneficial for improving carrier transport capabilities, thereby achieving high or ultra-high mobility. In particular, indium-containing metal oxides can provide a wider electron transport channel, while the introduction of gallium, zinc, or tin elements can further adjust the oxygen vacancy concentration, improve the band structure, and enhance material stability, thus achieving a balance between high mobility and electrical stability of the device.

[0094] In some embodiments, the first semiconductor layer 51 further contains zinc, and the molar ratio of indium to zinc in the first semiconductor layer 51 is greater than or equal to 2. By increasing the proportion of indium, the electron transport capability of the material can be enhanced, and the electron mobility of the active layer 50 can be improved; at the same time, the introduction of an appropriate amount of zinc helps to optimize the film formation quality and adjust the carrier concentration, thereby balancing the driving performance and stability of the device.

[0095] In some embodiments, the first semiconductor layer 51 further contains gallium, and the molar ratio of indium to gallium in the first semiconductor layer 51 is greater than or equal to 2. The introduction of gallium helps to suppress the formation of oxygen vacancies, reduce carrier concentration fluctuations and leakage current, and improve the electrical stability of transistor 100; while maintaining a high proportion of indium can maintain a high electron mobility on the basis of stability, thereby achieving a balanced optimization of the performance of transistor 100.

[0096] In some embodiments, the first semiconductor layer 51 further contains tin, and the molar percentage of tin in the metal elements of the first semiconductor layer 51 is less than or equal to 5%. By controlling the content of tin, the conductivity and band structure of the semiconductor layer can be improved, while avoiding excessive carrier concentration or increased device off-state leakage current due to excessive tin content, thereby improving the overall electrical performance and operational stability of the transistor 100.

[0097] In some embodiments, the first semiconductor layer 51 further contains doping elements, including any one or more of iron, praseodymium, terbium, dysprosium, lanthanum, and aluminum. By introducing the above-mentioned doping elements, the oxygen vacancy concentration, carrier concentration, and local band structure of the first semiconductor layer 51 can be controlled, thereby improving the electrical and environmental stability of the semiconductor layer. For example, rare earth elements have a strong oxygen binding ability, which helps to suppress the formation of oxygen vacancies and reduce the performance drift of the device under light, bias, or humid and hot environments; while the introduction of aluminum or iron elements helps to improve the thin film density and chemical stability, thereby improving the reliability of the transistor 100.

[0098] In some embodiments, the molar percentage of the dopant element in the metal elements of the first semiconductor layer 51 is less than or equal to 2%. By controlling the content of the dopant element to a low range, the material stability can be improved and the defect state density can be reduced, while avoiding the enhanced carrier scattering or decreased electron mobility caused by excessive doping concentration, thereby achieving both high mobility and high stability of the transistor 100.

[0099] In some embodiments, the material of the second semiconductor layer 53 includes indium gallium zinc oxide (IGZO), gallium zinc oxide (GZO), and zinc oxide (ZnO). x At least one of the following. The aforementioned zinc-containing metal oxides have good chemical stability and low carrier concentration, making them suitable as a protective layer disposed between the first semiconductor layer 51 and the source / drain electrode layer 60. On the one hand, this can reduce the influence of external moisture, hydrogen, and impurity ions on the channel region, reduce the interface defect state density, and improve the stability of the transistor 100; on the other hand, it can also protect the underlying channel region during the wet etching process of the source / drain electrodes, reducing the corrosion damage of etching solutions such as copper acid to the active layer 50, thereby improving device consistency and process reliability.

[0100] In some embodiments, the second semiconductor layer 53 further contains indium, and the molar ratio of indium to zinc in the second semiconductor layer 53 is less than or equal to 1:5. By increasing the zinc content and decreasing the indium content, the carrier concentration of the second semiconductor layer 53 can be effectively reduced, its conductivity weakened, and it made more suitable for use as a protective layer. At the same time, the appropriate introduction of indium can also improve the film formation quality and interlayer interface contact characteristics, thereby ensuring the protective effect while taking into account the overall electrical performance of the transistor 100 device.

[0101] In some embodiments, the thickness of the first semiconductor layer 51 ranges from 50 Å to 200 Å to balance carrier transport capability, device stability, and process adaptability. When the thickness of the first semiconductor layer 51 is less than 50 Å, the continuity and conductivity of the layer may be insufficient, thereby affecting the device mobility and threshold voltage characteristics; while an excessively large thickness may increase the difficulty of controlling the characteristics of the transistor 100.

[0102] In one specific embodiment, the thickness of the first semiconductor layer 51 ranges from 50 Å to 120 Å. Within this thickness range, the first semiconductor layer 51 can effectively reduce the characteristic fluctuations of the transistor 100 while maintaining good carrier transport capability, thereby achieving better mobility performance and threshold voltage stability.

[0103] In some embodiments, the thickness of the second semiconductor layer 53 ranges from 100 Å to 300 Å to balance the protection effect on the active layer 50 and the overall device performance. When the thickness of the second semiconductor layer 53 is small, it may be difficult to provide sufficient back channel protection, thereby affecting the environmental stability of the device; while as the thickness of the second semiconductor layer 53 increases, the barrier effect against water vapor, hydrogen, and external process damage can be effectively improved. When the thickness of the second semiconductor layer 53 exceeds 300 Å, the thicker film may adversely affect the surface morphology of the active layer 50, thereby affecting the interface characteristics and carrier transport performance, and may also weaken the uniformity and effectiveness of protection in the back channel region, which is not conducive to the stable improvement of the device performance and reliability of the transistor 100.

[0104] In some embodiments, the active layer 50 further includes a third semiconductor layer 52 located between the first semiconductor layer 51 and the second semiconductor layer 53, wherein the material of the third semiconductor layer 52 is a metal oxide. The third semiconductor layer 52 contains at least indium and gallium, and the molar ratio of indium to gallium in the third semiconductor layer 52 is less than or equal to 1:1.

[0105] Specifically, the third semiconductor layer 52 can be disposed as a buffer layer between the first semiconductor layer 51 and the second semiconductor layer 53. Because the first semiconductor layer 51 and the second semiconductor layer 53 differ in material composition, carrier concentration, and thin film structure, direct contact between them can easily lead to lattice mismatch or interface defects, thus affecting carrier transport and device stability. By setting a third semiconductor layer 52 with a higher gallium content, the strong oxygen binding ability of gallium can be utilized to improve the stability of the film structure and mitigate the lattice and band differences between the upper and lower layers, thereby reducing the interface defect state density and minimizing carrier scattering and interface trapping effects.

[0106] In addition, the third semiconductor layer 52 can improve the interface bonding quality inside the active layer 50, optimize the interlayer band transition and electric field distribution, thereby improving carrier transport efficiency and further enhancing the mobility, bias stability and device consistency of the transistor 100.

[0107] In some embodiments, the material of the third semiconductor layer 52 includes at least one of indium gallium zinc oxide (IGZO) and indium gallium zinc tin oxide (IGZTO). These metal oxides possess both good structural stability and interface tuning capabilities, making them suitable as a buffer layer disposed between the first semiconductor layer 51 and the second semiconductor layer 53. Gallium helps suppress oxygen vacancy formation and reduce interface defect state density, while tin helps improve film compactness and band structure, thereby mitigating material differences between the upper and lower semiconductor layers and improving interlayer bonding quality and carrier transport characteristics. By providing the third semiconductor layer 52, interface defects and carrier scattering caused by film lattice mismatch or band abrupt changes can be effectively reduced, thereby improving device mobility, bias stability, and display consistency.

[0108] In some embodiments, the thickness of the third semiconductor layer 52 ranges from 100 Å to 500 Å.

[0109] It should be noted that the thickness of the third semiconductor layer 52 has a significant impact on the total number of defect states and the morphology of the active layer 50. When the thickness is within the aforementioned range, the third semiconductor layer 52 can improve the continuity and interface smoothness of the film while ensuring a good buffering effect, thereby reducing the impact of interface trap states and structural defects on carrier transport. If the thickness is too thin, the buffering effect may be insufficient, making it difficult to effectively alleviate lattice or band differences between upper and lower layers; if the thickness is too thick, it may increase the total number of defect states within the film and adversely affect the overall morphology of the active layer 50 and the electrical characteristics of the device. Therefore, by reasonably controlling the thickness of the third semiconductor layer 52, interface stability, carrier transport capability, and the overall performance of the transistor 100 device can be balanced.

[0110] It should be noted that the number of semiconductor layers in the active layer 50 in this embodiment is not limited to the above three layers. The number of semiconductor layers can be adjusted according to the needs of electrical performance in order to achieve better electrical performance.

[0111] In some embodiments, the carrier mobility of transistor 100 is greater than 45 cm⁻¹. 2 / V·s, and less than 60 cm 2 / V·s. This application embodiment, through synergistic optimization of the material composition, interlayer structure, and interface characteristics of the active layer 50, can achieve ultra-high electron mobility while ensuring the stability of the transistor 100 device, thereby enhancing the driving capability of the transistor 100 and meeting the requirements of high-resolution, high-refresh-rate display panels for high-performance driving devices.

[0112] In some embodiments, the threshold voltage (V) of transistor 100 th The voltage is greater than or equal to 0V. By optimizing the structure of the active layer 50 and the first insulating layer 110, the second insulating layer 120 and the fourth insulating layer 140 adjacent to the active layer 50, the negative drift of the threshold voltage can be effectively suppressed, and the fluctuation of the electrical characteristics of the transistor 100 device caused by environmental factors or process factors can be reduced, thereby improving the working stability and product yield of the transistor 100 device.

[0113] In this embodiment, the active layer 50 of the transistor 100 is a multilayer metal oxide semiconductor layer, which is beneficial to improving the carrier mobility of the transistor 100, such as achieving high mobility or ultra-high mobility. Furthermore, the first surface 54 and the second surface 55 of the active layer 50, which are arranged opposite to each other, are each provided with at least two stacked silicon oxide layers. The molar content of hydrogen atoms in at least one silicon oxide layer of the first insulating layer 110 is less than or equal to 5%, or even less than or equal to 3%. This makes the first insulating layer 110 located on the first surface 54 contain at least one silicon oxide layer with low hydrogen content. This design can effectively block water vapor and hydrogen around the active layer 50, thereby enhancing the protection effect of the active layer 50 against water vapor or hydrogen in the environment or process from the device structure. It optimizes the problem of difficult threshold voltage control of high (or ultra-high) mobility transistor 100, and widens the process debugging window of high (or ultra-high) mobility transistor 100. This effectively improves the problem of easy negative bias of threshold voltage of transistor 100, and significantly improves the stability and process adaptability of transistor 100 while maintaining high (or ultra-high) mobility. Therefore, the transistor 100 provided in this application embodiment is suitable for manufacturing on large-generation production lines and can provide a technical foundation for the industrial application of next-generation display backplane technology and ultra-high-end display products.

[0114] like Figure 4As shown, this application embodiment also provides a method for manufacturing the transistor 100 described in the foregoing embodiment, including steps S401 to S405.

[0115] S401: A patterned gate 20 is formed on the substrate layer 10, such as... Figure 5 As shown.

[0116] In some embodiments, the substrate 10 is a glass substrate, but is not limited thereto.

[0117] In some embodiments, S401 includes the following steps: A first metal layer is formed on substrate 10 using physical vapor deposition (PVD) process; A patterned photoresist layer is formed on the first metal layer using a photolithography process; The first metal layer is etched using wet etching to form a patterned gate 20; and Remove the residual photoresist layer.

[0118] S402: A third insulating layer 130 and a first insulating layer 110 are formed on one side of the substrate layer 10 on which the gate 20 is formed, such as Figure 6 As shown; wherein, the material of the third insulating layer 130 is selected from silicon nitride, the first insulating layer 110 includes a first silicon oxide layer 111 and a second silicon oxide layer 112 stacked together, and the molar content of hydrogen atoms in the first silicon oxide layer 111 or the second silicon oxide layer 112 is less than or equal to 3%.

[0119] Specifically, the third insulating layer 130 and the first silicon oxide layer 111 and the second silicon oxide layer 112 in the first insulating layer 110 are all formed by CVD process.

[0120] In one specific embodiment, the molar content of hydrogen atoms in the first silicon oxide layer 111 is less than or equal to 3%, and the molar content of hydrogen atoms in the second silicon oxide layer 112 is less than 5%. That is, the first silicon oxide layer 111 is the aforementioned first low-H layer, and the second silicon oxide layer 112 is the aforementioned second low-H layer. In this case, during the CVD film formation process of the first silicon oxide layer 111, the SiH4 / N2O ratio is greater than 1:100 and less than 1:50, and during the CVD film formation process of the second silicon oxide layer 112, the SiH4 / N2O ratio is greater than 1:70. Furthermore, the film formation temperature of the first silicon oxide layer 111 and the second silicon oxide layer 112 is greater than or equal to 300°C.

[0121] S403: A patterned active layer 50 and source / drain electrode layer 60 are formed on the side of the first insulating layer 110 opposite to the third insulating layer 130, such as... Figure 7As shown; wherein, the active layer 50 includes a first semiconductor layer 51, a third semiconductor layer 52 and a second semiconductor layer 53 stacked sequentially, and the materials of the first semiconductor layer 51, the third semiconductor layer 52 and the second semiconductor layer 53 are all metal oxides.

[0122] It should be noted that the embodiments in this application focus on describing the manufacturing process. For the structure and material characteristics of the film layer, please refer to the description of the foregoing embodiments, which will not be repeated here.

[0123] In some embodiments, the active layer 50 and the source / drain electrode layer 60 are formed by a single photolithography and etching process. For example, S403 includes the following steps: A first metal oxide layer, a second metal oxide layer, a third metal oxide layer, and a second metal layer are sequentially deposited on the first insulating layer 110 using a PVD process; wherein, the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer are annealed before the second metal layer is deposited. A half-tone mask is used, and a patterned photoresist layer is formed on the second metal layer using photolithography. The second metal layer is etched using wet etching to form a patterned source / drain electrode layer 60; Wet etching is continued to simultaneously etch the first metal oxide layer, the second metal oxide layer and the third metal oxide layer to form a patterned active layer 50; Remove the residual photoresist layer.

[0124] In other embodiments, the active layer 50 and the source / drain electrode layer 60 are formed by two photolithography and etching processes; that is, the active layer 50 and the source / drain electrode layer 60 are formed by independent photolithography and etching processes. For example, S403 includes the following steps: A first metal oxide layer, a second metal oxide layer, and a third metal oxide layer are sequentially deposited on the first insulating layer 110 using a PVD process. Annealing is performed on the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer; A patterned photoresist layer is formed on the third metal oxide layer using photolithography. Wet etching is used to simultaneously etch the first metal oxide layer, the second metal oxide layer and the third metal oxide layer to form a patterned active layer 50; Remove the photoresist layer remaining on the active layer 50; A second metal layer is deposited on the first insulating layer 110 and the active layer 50 using a PVD process; A patterned photoresist layer is formed on the second metal layer using photolithography. The second metal layer is etched using wet etching to form a patterned source / drain electrode layer 60; and Remove the photoresist layer remaining on the source / drain electrode layer 60.

[0125] S404: Form a second insulating layer 120 covering the first insulating layer 110, the source / drain electrode layer 60, and the active layer 50, such as Figure 8 As shown; wherein, the second insulating layer 120 includes a third silicon oxide layer 121 and a fourth silicon oxide layer 122 stacked sequentially.

[0126] Specifically, the third silicon oxide layer 121 and the fourth silicon oxide layer 122 are formed by CVD process, and annealing is required after film formation.

[0127] In some embodiments, the third silicon oxide layer 121 is the aforementioned second low-H layer or low-damage layer. If the third silicon oxide layer 121 is the second low-H layer, the molar content of hydrogen atoms in the third silicon oxide layer 121 is less than or equal to 5%. If the third silicon oxide layer 121 is the low-damage layer, the molar content of hydrogen atoms in the third silicon oxide layer 121 is greater than or equal to 3% and less than or equal to 8%, and the total gas flow rate in the CVD film deposition process of the third silicon oxide layer 121 as the low-damage layer is at least 10% lower than the total gas flow rate in the CVD film deposition process of the third silicon oxide layer 121 as the second low-H layer; the film deposition power in the CVD film deposition process of the third silicon oxide layer 121 as the low-damage layer is at least 10% lower than the film deposition power in the CVD film deposition process of the third silicon oxide layer 121 as the second low-H layer; and the SiH4 / N2O ratio in the CVD film deposition process of the third silicon oxide layer 121 as the low-damage layer is less than 1:50.

[0128] In some embodiments, the fourth silicon oxide layer 122 is a highly dense layer; for example, the etching rate of the fourth silicon oxide layer 122 under a dry etching process is less than 15 Å / s. In the CVD film deposition process, the film deposition power of the fourth silicon oxide layer 122 is 1.2 to 2 times that of the third silicon oxide layer 121.

[0129] In some embodiments, the thickness of the third silicon oxide layer 121 and the fourth silicon oxide layer 122 is in the range of 500 Å to 2500 Å; the thickness of the second insulating layer 120 is in the range of 2500 Å to 4000 Å.

[0130] S405: Form a fourth insulating layer 140 covering the second insulating layer 120, such as Figure 3 As shown; wherein, the fourth insulating layer 140 includes a first silicon nitride layer 141 and a second silicon nitride layer 142 stacked sequentially, and the molar content of hydrogen atoms in the first silicon nitride layer 141 is less than 5%.

[0131] Specifically, the first silicon nitride layer 141 and the second silicon nitride layer 142 are formed using a CVD process.

[0132] The structure of the transistor 100 prepared by the above method is as follows: Figure 3 As shown, the drain current-gate voltage characteristic curve of the transistor 100 is as follows: Figure 9 . Figure 9 The curve data shown were collected from 20 different locations (sample space) on the same glass substrate under the same process conditions.

[0133] according to Figure 9 It can be seen that, as Figure 3 The threshold voltage V of the transistor 100 shown th The voltage is 0.27V, its range is only 0.88V, and its mobility is 46.14cm. 2 / V·s. Therefore, it can be seen that the transistor 100 provided in this embodiment has ultra-high mobility, and the threshold voltage V of the transistor 100 is... th The process window is effectively widened, and the current-gate voltage characteristic curves of drain 62 and gate 20 are converged. Therefore, the novel ultra-high mobility oxide transistor 100 provided in this application embodiment can meet the product requirements of high-specification display panel 300.

[0134] In this embodiment, the active layer 50 is formed by three different metal oxide semiconductor layers, which effectively reduces the defect state density of the active layer 50, enabling the transistor 100 to have ultra-high mobility. At the same time, by designing a stacked structure for the silicon oxide insulating layers at both the front and back channels of the active layer 50 and controlling the hydrogen atom content in the silicon oxide insulating layers, the protection capability of the ultra-high mobility oxide transistor 100 against water vapor and hydrogen is effectively improved. While ensuring ultra-high mobility, the threshold voltage negative bias problem is significantly improved, which effectively widens the process window and enables the application of ultra-high mobility products.

[0135] like Figure 10 As shown, this application embodiment also provides an array substrate 200, which includes the transistor 100 described in the above embodiments.

[0136] In some embodiments, the array substrate 200 further includes a pixel electrode 210 located on the side of the fourth insulating layer 140 opposite to the second insulating layer 120, and the pixel electrode 210 is electrically connected to the drain electrode 62 in the source-drain electrode layer 60 through a via penetrating the fourth insulating layer 140 and the second insulating layer 120.

[0137] In some embodiments, the array substrate 200 further includes at least one organic planarization layer 220 located between the fourth insulating layer 140 and the pixel electrode 210, but is not limited thereto.

[0138] In this embodiment, since the array substrate 200 contains the transistor 100 of the aforementioned embodiment, the transistor 100 has ultra-high mobility and forward bias threshold voltage, which can effectively improve the conduction performance and driving capability of the device, thereby improving the overall display performance and stability of the display panel 300 on which the array substrate 200 is applied.

[0139] like Figure 11 As shown, this application embodiment also provides a display panel 300, which includes the transistor 100 described in the above embodiments, or the display panel 300 includes the array substrate 200 described in the above embodiments.

[0140] It should be noted that the transistor 100 described in the foregoing embodiments can be applied to the driving circuit of the display panel 300, but is not limited thereto.

[0141] In some embodiments, the display panel 300 includes the array substrate 200 described in the above embodiments and a light-emitting layer 310 disposed on the array substrate 200. The light-emitting layer 310 is selected from any one of OLED devices, LED devices, Micro-LED devices and Mini-LED devices, but is not limited thereto.

[0142] In another embodiment, the display panel 300 includes the array substrate 200, the liquid crystal layer and the opposing substrate described in the above embodiments, wherein the array substrate 200 and the opposing substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate 200 and the opposing substrate.

[0143] It should be noted that the type of display panel 300 is not limited in this application embodiment. Any application that uses the transistor 100 or array substrate 200 of the aforementioned embodiments is within the protection scope of this application.

[0144] In this embodiment, since the display panel 300 contains the transistor 100 described in the foregoing embodiment, the transistor 100 has ultra-high mobility and a forward bias threshold voltage, which can effectively improve the conduction performance and driving capability of the device, thereby improving the overall display performance and stability of the display panel 300.

[0145] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0146] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0147] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0148] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A transistor, characterized in that, include: An active layer includes at least two semiconductor layers stacked together. The semiconductor layer is made of metal oxide, and the active layer includes a first surface and a second surface disposed opposite to each other along the thickness direction of the semiconductor layer. The source / drain electrode layer is in contact with the second surface of the active layer; A first insulating layer covers at least the first surface of the active layer and includes at least two stacked silicon oxide layers. The second insulating layer covers at least the second surface of the active layer and the source / drain electrode layer, and includes at least two stacked silicon oxide layers. Wherein, in the first insulating layer and the second insulating layer, the molar content of hydrogen atoms in at least one layer of the silicon oxide in the first insulating layer is less than or equal to 5%.

2. The transistor according to claim 1, characterized in that, The first insulating layer includes a first silicon oxide layer and a second silicon oxide layer stacked together, wherein the second silicon oxide layer is located between the first silicon oxide layer and the active layer; The molar content of hydrogen atoms in the first silicon oxide layer is less than or equal to 3%, and the molar content of hydrogen atoms in the second silicon oxide layer is less than 5%; or, the molar content of hydrogen atoms in the first silicon oxide layer is less than 5%, and the molar content of hydrogen atoms in the second silicon oxide layer is less than or equal to 3%.

3. The transistor according to claim 2, characterized in that, At least one of the first silicon oxide layer and the second silicon oxide layer has an etching rate of less than 15 Å / s under a dry etching process.

4. The transistor according to claim 1, characterized in that, The second insulating layer includes a third silicon oxide layer and a fourth silicon oxide layer stacked together, wherein the third silicon oxide layer is located between the active layer and the fourth silicon oxide layer; The molar content of hydrogen atoms in at least one of the third silicon oxide layer and the fourth silicon oxide layer is less than or equal to 5%, or the molar content of hydrogen atoms in at least one of the third silicon oxide layer and the fourth silicon oxide layer is greater than or equal to 3% and less than or equal to 8%.

5. The transistor according to claim 4, characterized in that, The thickness of the third silicon oxide layer and / or the fourth silicon oxide layer ranges from 500 Å to 2500 Å; the thickness of the second insulating layer ranges from 2500 Å to 4000 Å.

6. The transistor according to claim 4, characterized in that, The molar content of hydrogen atoms in the third silicon oxide layer is less than or equal to 5%, or the molar content of hydrogen atoms in the third silicon oxide layer is greater than or equal to 3% and less than or equal to 8%; the etching rate of the fourth silicon oxide layer under dry etching process is less than 15 Å / s.

7. The transistor according to claim 1, characterized in that, The transistor further includes a third insulating layer located on the side of the first insulating layer opposite to the active layer, and a fourth insulating layer located on the side of the second insulating layer opposite to the active layer, wherein both the third insulating layer and the fourth insulating layer include at least one silicon nitride layer.

8. The transistor according to claim 7, characterized in that, The fourth insulating layer includes a first silicon nitride layer and a second silicon nitride layer stacked together, with the first silicon nitride layer located between the second insulating layer and the second silicon nitride layer. In the first silicon nitride layer and the second silicon nitride layer, at least the molar content of hydrogen atoms in the first silicon nitride layer is less than 5%.

9. The transistor according to claim 7, characterized in that, The source / drain electrode layer is in contact with the second surface of the active layer, and the second insulating layer covers the first insulating layer, the source / drain electrode layer, and the second surface; The transistor further includes a gate located on the side of the third insulating layer opposite to the first insulating layer and aligned with the active layer.

10. The transistor according to any one of claims 1 to 9, characterized in that, The active layer includes a first semiconductor layer and a second semiconductor layer stacked together, wherein the second semiconductor layer is located between the first semiconductor layer and the source / drain electrode layer; Both the first semiconductor layer and the second semiconductor layer are made of metal oxides. The first semiconductor layer contains at least indium, and the second semiconductor layer contains at least zinc.

11. The transistor according to claim 10, characterized in that, The material of the first semiconductor layer includes at least one of indium oxide, indium zinc oxide, indium gallium oxide, indium zinc tin oxide, and indium gallium zinc tin oxide; And / or, the material of the second semiconductor layer includes at least one of indium gallium zinc oxide, gallium zinc oxide, and zinc oxide.

12. The transistor according to claim 10, characterized in that, The first semiconductor layer also contains zinc, and the molar ratio of indium to zinc in the first semiconductor layer is greater than or equal to 2. And / or, the first semiconductor layer further contains gallium, and in the first semiconductor layer, the molar ratio of indium to gallium is greater than or equal to 2; And / or, the first semiconductor layer further contains tin, and the molar percentage of tin in the metal elements of the first semiconductor layer is less than or equal to 5%.

13. The transistor according to claim 10, characterized in that, The first semiconductor layer further contains doping elements, including any one or more of iron, praseodymium, terbium, dysprosium, lanthanum and aluminum, and / or, in the metal elements of the first semiconductor layer, the molar percentage of the doping element is less than or equal to 2%.

14. The transistor according to claim 10, characterized in that, The second semiconductor layer also contains indium, and the molar ratio of indium to zinc in the second semiconductor layer is less than or equal to 1:

5.

15. The transistor according to claim 10, characterized in that, The thickness of the first semiconductor layer ranges from 50 Å to 200 Å, and the thickness of the second semiconductor layer ranges from 100 Å to 300 Å.

16. The transistor according to claim 10, characterized in that, The active layer further includes a third semiconductor layer located between the first semiconductor layer and the second semiconductor layer, wherein the material of the third semiconductor layer is a metal oxide. The third semiconductor layer contains at least indium and gallium, and the molar ratio of indium to gallium in the third semiconductor layer is less than or equal to 1:

1.

17. The transistor according to claim 16, characterized in that, The material of the third semiconductor layer includes at least one of indium gallium zinc oxide and indium gallium zinc tin oxide; And / or, the thickness of the third semiconductor layer ranges from 100 Å to 500 Å.

18. The transistor according to claim 16, characterized in that, The carrier mobility of the transistor is greater than 45 cm⁻¹. 2 / V·s, and less than 60 cm 2 / V·s; And / or, the threshold voltage of the transistor is greater than or equal to 0V.

19. An array substrate, characterized in that, The array substrate includes transistors as described in any one of claims 1 to 18.

20. A display panel, characterized in that, The display panel includes a transistor as described in any one of claims 1 to 18, or the display panel includes an array substrate as described in claim 19.

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