Three-dimensional memory device and manufacturing method thereof

Abstract

The invention discloses a three-dimensional memory device and a manufacturing method thereof. A semiconductor structure includes a plurality of layers of a transistor stacked in a vertical direction. Each layer of transistors includes: a first array of transistors sharing a first common first type of terminal line; and a second transistor array sharing a second common first type terminal line. The first transistor array and the second transistor array share a common second type terminal line. The semiconductor structure further includes a first common first type terminal contact structure coupled with the first common first type terminal line in the first first type terminal contact region, a second common first type terminal contact structure coupled with the second common first type terminal line in the second first type terminal contact region; and a common second type terminal contact structure coupled with the common second type terminal line in the common second type terminal contact region.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to three-dimensional (3D) random access memory (RAM) devices and methods of fabricating the same. Background Art

[0002] As memory devices are shrinking to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells is challenging due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells. Summary of the invention

[0003] Embodiments of 3D memory devices and methods of fabrication are described in this disclosure.

[0004] One aspect of the present disclosure provides a semiconductor structure, comprising: a plurality of layers of transistors stacked in a vertical direction, each layer of the transistors comprising: a first transistor array sharing a first common first-type terminal line; a second transistor array sharing a second common first-type terminal line, wherein the first transistor array and the second transistor array share a common second-type terminal line; and a plurality of contact structures, the contact structures comprising: a first common first-type terminal contact structure coupled to the first common first-type terminal line in a first first-type terminal contact region located on a first lateral side of the first transistor array away from the second transistor array, a second common first-type terminal contact structure coupled to the second common first-type terminal line in a second first-type terminal contact region located on a second lateral side of the second transistor array away from the first transistor array, and a common second-type terminal contact structure coupled to the common second-type terminal line in a common second-type terminal contact region between the first transistor array and the second transistor array.

[0005] In some embodiments, the transistor is a ferroelectric field effect transistor (FeFET).

[0006] In some embodiments, each FeFET includes: a channel layer, a ferroelectric layer having ferroelectricity and surrounded by the channel layer in a horizontal plane, and a gate surrounded by the ferroelectric layer in a horizontal plane.

[0007] In some embodiments, the channel layer includes a metal oxide semiconductor material.

[0008] In some embodiments, the channel layer of each FeFET has an elliptical ring shape in a horizontal plane.

[0009] In some embodiments, a first portion of the channel layer at the second end of the long diameter of the elliptical shape contacts the first common first type terminal line or the second common first type terminal line; and a second portion of the channel layer at the first end of the long diameter of the elliptical shape contacts the common second type terminal line.

[0010] In some embodiments, the first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; the second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

[0011] In some embodiments, the first type terminal is a drain terminal; the second type terminal is a source terminal; the first common first type terminal contact structure is connected to the first bit line; the second common first type terminal contact structure is connected to the second bit line, and the common second type terminal contact structure is connected to the source line.

[0012] In some embodiments, each contact structure of the plurality of contact structures is located in the dielectric stack in a first first type terminal contact region or a second first type terminal contact region, or a common second type terminal contact region.

[0013] In some embodiments, the first common first type terminal lines of multiple layers of transistors overlap in the vertical direction; the second common first type terminal lines of multiple layers of transistors overlap in the vertical direction; and the common second type terminal lines of multiple layers of transistors overlap in the vertical direction.

[0014] In some embodiments, a contact structure of an intermediate stack of transistors includes: a conductive via extending vertically in a dielectric stack located above the intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from a terminal line of an upper transistor located above the intermediate stack of transistors; and an enlarged conductive end that is laterally electrically contacted with a corresponding terminal line of the intermediate stack of transistors.

[0015] In some embodiments, the semiconductor structure also includes: a first isolation wall located between the first first type terminal contact area and the first transistor array to isolate the first common first type terminal line from the common second type terminal line; and a second isolation wall located between the second first type terminal contact area and the second transistor array to isolate the second common first type terminal line from the common second type terminal line.

[0016] Another aspect of the present disclosure provides a semiconductor structure comprising: a plurality of layers of transistors stacked in a vertical direction, each layer of the transistor comprising: a first transistor array sharing a first common first type terminal line; a second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and a plurality of contact structures, each of the plurality of contact structures being coupled to the first common first type terminal line, the second common first type terminal line, or the common second type terminal line; wherein each of the plurality of contact structures electrically coupled to an intermediate stack of the transistors passes through a dielectric stack located above the intermediate stack of the transistors.

[0017] In some embodiments, the transistor is a ferroelectric field effect transistor (FeFET).

[0018] In some embodiments, each FeFET includes: a channel layer, a ferroelectric layer having ferroelectricity and surrounded by the channel layer in a horizontal plane, and a control gate surrounded by the ferroelectric layer in a horizontal plane.

[0019] In some embodiments, the channel layer includes a metal oxide semiconductor material.

[0020] In some embodiments, the channel layer of each FeFET cell has an elliptical ring shape in a horizontal plane.

[0021] In some embodiments, a first portion of the channel layer at the second end of the long diameter of the elliptical shape contacts the first common first type terminal line or the second common first type terminal line; and a second portion of the channel layer at the first end of the long diameter of the elliptical shape contacts the common second type terminal line.

[0022] In some embodiments, the first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; the second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

[0023] In some embodiments, multiple contact structures include: a first common first type terminal contact structure coupled to a first common first type terminal line in a first first type terminal contact region located on a first lateral side of the first transistor array away from the second transistor array, a second common first type terminal contact structure coupled to a second common first type terminal line in a second first type terminal contact region located on a second lateral side of the second transistor array away from the first transistor array, and a common second type terminal contact structure coupled to a common second type terminal line in a common second type terminal contact region located between the first transistor array and the second transistor array.

[0024] In some embodiments, the first type terminal is a drain terminal; the second type terminal is a source terminal; the first common first type terminal contact structure is connected to the first bit line; the second common first type terminal contact structure is connected to the second bit line, and the common second type terminal contact structure is connected to the source line.

[0025] In some embodiments, each contact structure includes: a conductive via extending vertically in a dielectric stack located above an intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from a terminal line of an upper transistor located above the intermediate stack of transistors; and an enlarged conductive end that is laterally electrically contacted with a corresponding terminal line of the intermediate stack of transistors.

[0026] In some embodiments, the first common first type terminal lines of multiple layers of transistors overlap in the vertical direction; the second common first type terminal lines of multiple layers of transistors overlap in the vertical direction; and the common second type terminal lines of multiple layers of transistors overlap in the vertical direction.

[0027] In some embodiments, the semiconductor structure also includes: a first isolation wall located between the first first type terminal contact area and the first transistor array to isolate the first common first type terminal line from the common second type terminal line; and a second isolation wall located between the second first type terminal contact area and the second transistor array to isolate the second common first type terminal line from the common second type terminal line.

[0028] Another aspect of the present disclosure provides a method for forming a semiconductor structure, comprising: forming a dielectric stack, the dielectric stack comprising a plurality of first dielectric layers and a second dielectric layer alternately stacked in a vertical direction; forming a plurality of through holes in the dielectric stack; forming a plurality of sacrificial through structures in the plurality of through holes; replacing a portion of the second dielectric layer with a conductive line; replacing the plurality of sacrificial through structures with a plurality of transistor structures; and forming a plurality of contact structures, each of the plurality of contact structures being coupled to a corresponding conductive line and penetrating the remaining portion of the dielectric stack located above the corresponding conductive line.

[0029] In some embodiments, forming the plurality of sacrificial through structures includes: removing portions of the second dielectric layer exposed by the plurality of through holes to form a plurality of recesses on sidewalls of the plurality of through holes; and depositing a sacrificial material to fill the plurality of recesses and the plurality of through holes.

[0030] In some embodiments, replacing multiple sacrificial through-structures with multiple transistor structures includes: removing multiple sacrificial through-structures from multiple recesses and multiple through-holes; forming multiple channel layers in the multiple recesses; forming a ferroelectric layer on the sidewall of each through-hole, wherein the ferroelectric layer has ferroelectricity and is laterally surrounded by the channel layer; and forming a gate structure in each through-hole, wherein the gate structure is laterally surrounded by the ferroelectric layer.

[0031] In some embodiments, the channel layer includes a metal oxide semiconductor material in direct contact with the conductive layer.

[0032] In some embodiments, the metal oxide semiconductor material is indium gallium zinc oxide (IGZO).

[0033] In some embodiments, replacing portions of the second dielectric layer with conductive lines includes: forming a plurality of gaps extending through the dielectric stack; removing portions of the second dielectric layer from the plurality of gaps to form a plurality of horizontal openings; forming conductive lines in the plurality of horizontal openings; and filling the plurality of gaps with a dielectric material.

[0034] In some embodiments, forming the plurality of through holes includes forming each of the through holes to have an elliptical shape in a horizontal plane.

[0035] In some embodiments, the method also includes: forming an isolation wall vertically extending through the dielectric stack, so that the conductive line formed in each stack is divided by the isolation wall to include: a first common first type terminal line shared by a first array of ferroelectric field effect transistor (FeFET) units in the layer; a second common first type terminal line shared by a second transistor array in the layer; and a common second type terminal line shared by the first transistor array and the second transistor array.

[0036] In some embodiments, a first portion of the channel layer at a first end of the long diameter of the elliptical shape is formed to contact a common second type terminal line; and a second portion of the channel layer at a second end of the long diameter of the elliptical shape is formed to contact a first common first type terminal line or a second common first type terminal line.

[0037] In some embodiments, the first common first type terminal line is formed to include a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; the second common first type terminal line is formed to include a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the second transistor array.

[0038] In some embodiments, multiple contact structures are formed, including: forming a first common first type terminal contact structure coupled to a first common first type terminal line and located on a first lateral side of the first transistor array away from a second transistor array, forming a second common first type terminal contact structure coupled to a second common first type terminal line and located on a second lateral side of the second transistor array away from the first transistor array, and forming a common second type terminal contact structure coupled to a common second type terminal line and located between the first transistor array and the second transistor array.

[0039] In some embodiments, forming a contact structure among multiple contact structures includes: forming a contact hole, which penetrates an upper portion of a remainder of a dielectric stack and stops at a second dielectric layer located at the same horizontal plane as a corresponding conductive line; forming a dielectric filling structure to fill the contact hole; performing punch etching to remove a portion of the dielectric filling structure to expose a portion of a second dielectric layer adjacent to a corresponding conductive line; removing a portion of a second dielectric layer to expose a corresponding conductive line; and depositing a conductive material in the contact hole to form a contact structure, so that the contact structure is isolated from the conductive line located above the corresponding conductive line and is electrically contacted with the corresponding conductive line in a lateral direction.

[0040] In some embodiments, the first common first type terminal lines in multiple layers of conductive wires are formed to overlap in the vertical direction; the second common first type terminal lines in multiple layers of conductive wires are formed to overlap in the vertical direction; and the common second type terminal lines in multiple layers of conductive wires are formed to overlap in the vertical direction.

[0041] Other aspects of the present disclosure can be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0043] Figure 1 A schematic cross-section of a FeFET according to some embodiments of the present disclosure is shown.

[0044] Figure 2 Charge distribution in the storage film of a 3D FeFET RAM cell during erase and program operations according to some embodiments of the present disclosure is shown.

[0045] Figure 3 A schematic top view of a 3D FeFET according to some embodiments of the present disclosure is shown.

[0046] Figure 4 A schematic top view of a pattern design of a 3D memory array structure according to some embodiments of the present disclosure is shown.

[0047] Figure 5 According to some embodiments of the present disclosure, Figure 4 Schematic circuit diagram of the pattern design of the 3D memory array structure shown in FIG.

[0048] Figure 6A-6C A schematic top view of a pattern design of a 3D memory structure according to some embodiments of the present disclosure is shown.

[0049] Figure 7 According to some embodiments of the present disclosure, Figure 6A-6C Schematic circuit diagram of another pattern design of the 3D memory array structure shown in .

[0050] Figure 8 A flow chart of a method of forming a 3D memory structure according to some embodiments of the present disclosure is shown.

[0051] Fig.9A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0052] Fig. 9B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0053] Fig.10 According to some embodiments of the present disclosure, Figure 8Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0054] Fig.11A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0055] Fig. 11B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0056] Fig. 12A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0057] Fig. 12B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0058] Fig.13A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0059] Fig. 13B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0060] Fig.14A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0061] Fig. 14B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0062] Fig.15A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0063] Fig. 15B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0064] Fig.16A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0065] Fig. 16B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0066] Fig.17A According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional side view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0067] Fig. 17B According to some embodiments of the present disclosure, Figure 8 Schematic top view of a 3D memory structure at a specific manufacturing stage of the method shown in .

[0068] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements throughout the drawings. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference numeral.

[0069] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0070] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0071] Note that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment must include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0072] Typically, a term can be understood, at least in part, from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage. In addition, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors, but can allow for the presence of additional factors that are not necessarily explicitly described.

[0073] It should be readily understood that the meaning of "on", "over", and "on" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween. Furthermore, "over" or "on" not only means "over something" or "on something", but can also include the meaning of "over something" or "on something" with no intervening features or layers therebetween (i.e., directly on something).

[0074] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0075] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is usually where the semiconductor device is formed, and therefore, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic or sapphire wafers.

[0076] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire lower layer or overlying structure, or can have a range less than the range of the lower layer or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure, which has a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided on it, above it and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect channels (VIA) are formed) and one or more dielectric layers.

[0077] In the present disclosure, for ease of description, "tier" is used to refer to elements having substantially the same height in the vertical direction. For example, a word line and an underlying gate dielectric layer may be referred to as a "tier", a word line and an underlying insulating layer may be referred to as a "tier" together, word lines having substantially the same height may be referred to as a "tier of word lines", and so on.

[0078] As used herein, the term "nominal / nominal" refers to an expected or target value for a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may indicate a value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0079] In this disclosure, the term “horizontal / horizontally / lateral / laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical / vertically” means nominally perpendicular to a lateral surface of a substrate.

[0080] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a string of vertically oriented memory cell transistors (referred to herein as a "memory string") on a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0081] In 3D NAND memory, memory cells can be programmed for data storage based on charge capture technology. The storage information of the memory cell depends on the amount of charge captured in the storage layer. Although 3D NAND memory can be high-density and cost-effective, it has problems of low write speed and high power consumption at the system level due to the required peripheral devices (e.g., charge pump). On the other hand, phase change memory generally has large leakage current and high power consumption. Therefore, there is a need to develop a new high-speed and high-density storage class memory (SCM).

[0082] Ferroelectric field effect transistor (FeFET) random access memory (RAM) is a high-performance and low-power non-volatile memory that can combine the advantages of conventional non-volatile memory (e.g., flash memory and EEPROM) and high-speed RAM (e.g., SRAM and DRAM). The performance of FeFET RAM can be better than existing memories such as EEPROM and flash memory, with lower power consumption, faster response speed, and higher durability for multiple read and write operations. Traditional planar FeFET RAM is difficult to scale down. By replacing the charge trapping storage layer in 3D NAND flash memory with ferroelectric materials (e.g., Si:HfO2), FeFET RAM with a 3D NAND-like architecture can achieve scalable size without performance loss. However, due to the smaller size of the source and drain contacts in the existing 3D FeFET RAM architecture, it is difficult to separate the source and drain to achieve separate access to each memory cell. Therefore, it is expected to develop a new 3D architecture for FeFET RAM.

[0083] Figure 1 A schematic cross section of a FeFET 100 according to some embodiments of the present disclosure is shown. The FeFET 100 may include a control gate 110, a storage film 120, a channel layer 130, and source / drain electrodes 140.

[0084] In the FeFET 100, the storage film 120 may be located between the control gate 110 and the channel layer 130, and may include a barrier layer 122, a ferroelectric layer 124, an electrode layer 126, and an interface layer 128. In some embodiments, the barrier layer 122 is located between the control gate 110 and the ferroelectric layer 124. The control gate 110 may be a metal layer or a polysilicon layer. The barrier layer 122 may be used to block the interaction between the ferroelectric layer 124 and the control gate 110. The barrier layer 122 may have a thickness in a range between about 5 nm and about 50 nm. The barrier layer may include titanium nitride (TiN), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2O2N), a high-k dielectric material (e.g., HfO2, Al2O3), and / or any combination thereof. The barrier layer 122 may be formed by any suitable physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0085] In some embodiments, the ferroelectric layer 124 may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). In some embodiments, the ferroelectric layer 124 may include a high-k (i.e., high dielectric constant) dielectric material, which may include a transition metal oxide, such as hafnium zirconium oxide (HZO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof. In some embodiments, the high-k dielectric material may be doped to improve the ferroelectric properties. For example, the ferroelectric layer 124 may be HZO or HfO2 doped with silicon (Si), (yttrium) Y, gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof. In some embodiments, the ferroelectric layer 124 may include zirconate titanate (PZT), strontium bismuth tantalate (SrBi2Ta2O9), barium titanate (BaTiO3), PbTiO3, and BLT ((Bi,La)4Ti3O 12 ) or any combination thereof.

[0086] In some embodiments, the ferroelectric layer 124 can be disposed by chemical vapor deposition (CVD) (e.g., metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.). The ferroelectric layer 124 can also be disposed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof. In some embodiments, the ferroelectric layer 124 can have a thickness in a range between 5 nm and 100 nm.

[0087] In some embodiments, the interface layer 128 can be located between the ferroelectric layer 124 and the channel layer 130. The interface layer 128 can be used to reduce the possibility of material mixing between the ferroelectric layer 124 and the channel layer 130. In this example, the effective gate dielectric of the FeFET is a combination of the ferroelectric layer 124 and the interface layer 128. A thinner effective gate dielectric can provide better control of the channel layer 130 from the control gate 110. Therefore, the thickness of the interface layer 128 can be in a range between about 5nm and about 50nm. In some embodiments, the interface layer 128 can be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material (e.g., HfO2, HfAlO, Al2O3) and / or any combination thereof. The interface layer 128 can be formed by any suitable film deposition technique, such as ALD, CVD, sputtering, evaporation and / or any combination thereof. The interface layer 128 can also be formed by oxidation, nitridation and / or a combination thereof.

[0088] In some embodiments, the storage film 120 may further include an electrode layer 126 between the ferroelectric layer 124 and the interface layer 128. Thus, the control gate 110, the ferroelectric layer 124, and the electrode layer 126 form a metal-insulator-metal (MIM) capacitor 161, which is connected in series with a floating gate transistor (FG-MOSFET) 163 in which the electrode layer 126 serves as a floating gate and the interface layer 128 serves as a gate dielectric.

[0089] In some embodiments, the channel layer 130 may include amorphous silicon, polycrystalline silicon, single crystal silicon, and / or any combination thereof. The channel layer 130 may be formed by any suitable thin film deposition technique (e.g., ALD, CVD, sputtering, etc.). In some embodiments, a portion of the channel layer 130 may be doped to form a source / drain electrode 140 on each side of the channel layer 130, respectively. In some other embodiments, the source / drain electrode 140 may be a metal layer formed on the channel layer 130.

[0090] refer to Figure 2 , shows the charge distribution in the storage film of a FeFET during erase and program operations according to some embodiments of the present disclosure. It should be noted that for simplicity, Figure 3 The barrier layer 222, electrode layer 226 and interface layer 228 of the FeFET are omitted.

[0091] In such Figure 2 During the programming operation shown in the left figure, the programming voltage V applied to the control gate 210 p Provide a positive voltage (V p >V c), the ferroelectric film 224 may have a positive remnant polarization P r , which is directed from the control gate 210 to the channel layer 230. As a result, the top surface charge near the control gate 210 is negative, while the bottom surface charge near the channel layer 230 is positive. The positive bottom surface charge near the channel layer 230 can reduce the threshold voltage V th Therefore, the corresponding capacitor control by the FeFET can be programmed to a low threshold voltage V th_L , and is set to logic state "1".

[0092] In such Figure 2 During the erase operation shown in the figure on the right, the erase voltage -V p (eg, a negative voltage) is applied to the control gate 210, which is greater than the reverse coercive voltage (ie, |-V p |>|-V c |), the ferroelectric film 224 can be negatively polarized to have a reverse remnant polarization -P r , which is directed from the channel layer 230 to the control gate 210. The top surface charge near the control gate 210 is positive, while the bottom surface charge near the channel layer 230 is negative. The negative bottom surface charge near the channel layer 230 can increase the threshold voltage V th Therefore, the corresponding capacitor control by the FeFET can be programmed to a high threshold voltage V th_H , and is reset to logic state “0”.

[0093] It should be noted that the coercive field E c , coercive voltage V c , programming voltage V p and the remnant polarization P r Not necessarily symmetric around zero. Positive and negative values ​​can have different magnitudes. To simplify the following discussion, assume the magnitudes are the same in the reverse direction. One of ordinary skill in the art should be able to apply the following method to general conditions.

[0094] As discussed above, by applying an appropriate voltage pulse on the control gate 210, the polarization direction of the ferroelectric film 224 can be switched, and the threshold voltage of the FeFET can be changed, which affects the conductance of the channel layer 230 and the on / off state of the FeFET. The logic state (or storage data) of the corresponding capacitor control performed by the FeFET can be determined accordingly.

[0095] In some embodiments, during a read operation (in Figure 2During the period (not shown in FIG), the conductance of the channel layer 230 can be measured from the source / drain electrodes 240 of the FeFET by applying a read voltage Vread on the control gate 210. The logic state or threshold voltage of the corresponding DRAM memory cell including the FeFET and the corresponding capacitor control performed by the FeFET can be verified. Compared to the traditional NAND cell that operates based on charge trapping in the storage film, the FeFET RAM cell can be controlled by polarization in the ferroelectric film 224 instead.

[0096] It should be pointed out that Figure 1 The electrode layer 126 shown in the figure may be optional. During the operation of the FeFET, the voltage of the electrode layer 126 is determined by the amount of bottom surface charge of the ferroelectric film 124 / 224. By switching the polarization direction in the ferroelectric layer 124 / 224, the amount of bottom surface charge can be changed, and the voltage of the electrode layer 126 can be changed accordingly. Therefore, the threshold voltage of the FeFET can be changed. The electrode layer 126 in the FeFET can provide a function similar to that of a floating gate in a conventional NAND memory cell, except that the voltage of the electrode layer 126 is controlled by the polarization of the ferroelectric layer 124 / 224. The voltage applied to the control gate 110 / 210 is distributed between the MIM capacitor 161 and the FG-MOSFET 163. As a result, a relatively large voltage is required to switch the polarization of the ferroelectric layer 124 / 224. In order to reduce the write voltage, a thinner ferroelectric layer 124 / 224 can be used in some embodiments. By scaling the thickness of the ferroelectric layer 124 / 224 , the MIM capacitor 161 may have a larger capacitance so that a larger portion of the applied voltage may be dropped across the MIM capacitor 161 .

[0097] refer to Figure 3 , showing a schematic top view of a 3D FeFET according to some embodiments of the present disclosure. The 3DFeFET 300 may include a control gate 310, a barrier layer 322, a ferroelectric film 324, an interface layer 328, a channel layer 330, and a source / drain electrode 340. It should be noted that the source electrode and the drain electrode 340 are separated by an insulating layer, which is omitted for simplicity. The channel layer 330 may be in physical contact with the source / drain electrode 340 and may surround the interface layer 328 in the cross-sectional XY plane. The interface layer 328 may surround the ferroelectric film 324 in the cross-sectional XY plane. The ferroelectric film 324 may surround the barrier layer 322 in the cross-sectional XY plane. The barrier layer 322 may surround the control gate 310 in the cross-sectional XY plane.

[0098] In some embodiments, the control gate 310, the barrier layer 322, the ferroelectric film 324, the interface layer 328, and the channel layer 330 may form a through-structure 380 located in a through-hole extending in a vertical direction perpendicular to the horizontal XY plane. The cross-section of the through-hole in the horizontal XY plane may be as follows: Figure 4 . In some embodiments, the ratio between the long diameter L1 of the through structure 380 and the short diameter L2 of the through structure 380 is greater than 1. In some embodiments, the long diameter L1, the short diameter L2, and the ratio L1 / L2 can be determined based on the total number of 3D FeFET RAM cells in each memory string in the vertical direction. For example, when the total number of 3D FeFET RAM cells in each memory string increases, the size of the long diameter L1 and the short diameter L2 and the ratio L1 / L2 can be increased. In some embodiments, the long diameter L1 of the through structure 380 can provide an option for an increased contact area and / or multiple contact areas for landing a control gate contact. In this way, the gate control capability of the 3D memory device can be enhanced.

[0099] refer to Figure 4 , shows a schematic top view of a pattern design of a 3D memory array structure 400 according to some embodiments of the present disclosure. In the XY plane, the 3D memory array structure 400 may include a plurality of through structures 480 arranged in an array. Figure 3 As shown in , each of the plurality of through structures 480 may have an elliptical shape in a cross section in a horizontal XY plane. The short diameter of each through structure 480 may be along a first lateral direction (e.g., X direction), and the long diameter of each through structure 480 may be along a second lateral direction (e.g., Y direction). The array of through structures 480 may share a common source line 442 and a common bit line 444. It should be noted that in Figure 4 In FIG. 4 , for illustration purposes and for simplicity, five through structures 480 are shown in each row. In some embodiments, the number “n” of through structures 480 in each row can be greater than five to increase storage capacity.

[0100] like Figure 4As shown in , both the source line 442 and the bit line 444 may include a trunk line (also referred to as a "common source trunk line" and a "common bit trunk line") extending in the Y direction and located on each side of the array of the through structure 480, respectively, and may also include a plurality of branches (also referred to as "common source branches" and "common bit branches") located between adjacent rows of through structures 480 in an alternating and staggered manner. In some embodiments, each branch of the source line 442 or the bit line 444 may have a U-shaped portion or a single strip shape and extend along the X direction. That is, both the source line 442 and the bit line 444 may have a comb shape and may be placed in a face-to-face manner by means of single strip teeth that are alternately staggered with each other. The source line 442 and the bit line 444 are separated by an insulating layer 434.

[0101] The through structures 480 of each row are arranged between the source line 442 and the adjacent branches of the bit line 444. That is, there is a common source branch and a common bit branch between the through structures 480 of adjacent rows. The lower ends of the multiple through structures 480 in each row can be in common contact with one branch of the source line 442, and the upper ends of the multiple through structures 480 in each row can be in common contact with an adjacent branch of the source line 442. In this way, the channel layers (for example, Figure 3 The channel layer 330 shown in FIG. 4A ) may be in physical contact with the common source line 442 and the common bit line 444 .

[0102] In addition, if Figure 4 As shown in , the 3D memory array structure 400 may include a plurality of gate lines 416 (also referred to as “word lines”) arranged in parallel with each other and extending along a second lateral direction (e.g., the Y direction). Since there are two rows of through structures 480 in each finger, two gate lines 416 may be arranged for each column of two through structures 480, wherein one gate line 416 may be connected to the control gate of the through structure 480 in the first row via the first control gate contact 412 (e.g., as Figure 3 310), and another gate line 416 can be connected to the control gate of the through structure 480 in the second row via the second control gate contact 414. Figure 3 As discussed, the elliptical shape of the through structure 480 in the XY plane may provide options for increased contact area and / or multiple contact regions for landing the first control gate contact 412 or the second control gate contact 414 .

[0103] Figure 5 Shown as Figure 4Schematic circuit diagram of the pattern design of the 3D memory array structure 400 shown in FIG. It should be noted that the schematic circuit diagram 500 corresponds to a 3D FeFET RAM cell of a layer in the 3D memory array structure in the XY plane. Figure 5 As shown in , each row of FeFETs includes a number "n" of FeFETs. The array of FeFETs shares a common source line SL_1 and a common bit line BL_1. A number "2n" of gate lines GL_1, ..., GL_2n can each be connected to a corresponding FeFET, so that a number "2n" of FeFETs can be independently controlled. Therefore, each memory cell of the 3D memory array structure 500 can be randomly accessed.

[0104] refer to Fig. 6A , showing a schematic top view 600A of a pattern design of a 3D memory structure according to some embodiments of the present disclosure. Figure 6B , showing the AA' line according to some embodiments of the present disclosure Fig. 6A Schematic cross-sectional side view of a 3D memory structure shown in 600B. Figure 6C , showing the BB' line, CC' line, or DD' line according to some embodiments of the present disclosure Fig. 6A 600C is a cross-sectional side view of the 3D memory structure shown in FIG.

[0105] like Figure 6B As shown in , the 3D memory array structure includes a substrate 610 and a film stack 620 located on the substrate 620. In some embodiments, the substrate 620 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal silicon single-layer substrate, a polycrystalline silicon (poly-Si) single-layer substrate, a poly-Si and metal multi-layer substrate, etc. In a vertical direction (i.e., Z direction) perpendicular to the top surface of the substrate 610, the film stack 620 may include a first dielectric layer 622 and a second dielectric layer 624 alternately stacked. Figure 6A-6C As shown in FIG. 6 , a plurality of conductive lines 640 (including 642, 644, 646) may be located on the same horizontal plane as the second dielectric layer 624. The conductive lines 640 and the second dielectric layer 624 are sandwiched between adjacent first dielectric layers 622.

[0106] In a first lateral direction (i.e., X direction), the 3D memory array structure includes a first contact region 671 located at a first lateral side of the 3D memory array structure, a second contact region 673 located at a second lateral side of the 3D memory array structure, and a third contact region 675 located in the middle of the 3D memory array structure. The 3D memory array structure also includes a first transistor array 691 located between the first contact region 671 and the third contact region 675, and a second transistor array 699 located between the second contact region 673 and the third contact region 675.

[0107] In the vertical direction (i.e., Z direction), the first transistor array 691 and the second transistor array 699 include a plurality of storage strings formed in a plurality of through holes each extending through the film stack 620. The through hole can be formed by removing a portion of the first dielectric layer 622, the second dielectric layer 624 and the conductive line 640, so that the inner sidewalls of the first dielectric layer 622, the second dielectric layer 644 and the conductive line 640 are exposed by the through hole. A through structure 680 can be formed in each through hole. In some embodiments, the through structure 680 may include a channel layer located on the sidewall of the through hole, a storage film located on the sidewall of the channel layer, and a core control gate surrounded by the storage film. In this way, the through structure 680 and the plurality of conductive lines 640 in the film stack 620 can form a column of 3D FeFETs stacked in the vertical direction (Z direction).

[0108] like Fig. 6A As shown in , the FeFETs of each layer in the lateral XY plane may include a first transistor array 691 sharing a first common first type terminal line 642 extending into the first contact region 671, and a second transistor array 699 sharing a second common first type terminal line 644 extending into the second contact region 673. The first transistor array 691 and the second transistor array 699 may share a common second type terminal line 646 extending into the third contact region 675. In some embodiments, a first portion of the channel layer located at the second end of the long diameter of the elliptical-shaped through structure 680 contacts the first common first type terminal line 642 or the second common first type terminal line 644. A second portion of the channel layer located at the first end of the long diameter of the elliptical-shaped through structure 680 contacts the common second type terminal line 646. The second type terminal may be a source terminal, and thus, as shown in FIG. Fig. 6A As shown in , the common second type terminal line can serve as a common source line for each row of transistors.

[0109] In some embodiments, the first common first type terminal line 642 includes a first U-shaped portion located between adjacent rows of the first transistor array 691 and having a first opening facing away from the second transistor array 699. The second common first type terminal line 644 includes a second U-shaped portion located between adjacent rows of the second transistor array 699 and having a second opening facing away from the first transistor array 691. In some embodiments, the first type terminal can be a drain terminal, so the first common first type terminal line 642 can be used as a common drain line of the first transistor array 691, and the second common first type terminal line 644 can be used as a common drain line of the second transistor array 699.

[0110] like Figure 6B As shown in the figure, the first common first type terminal lines 642 of multiple layers of transistors overlap in the vertical direction, and the second common first type terminal lines 644 of multiple layers of transistors overlap in the vertical direction. Although not shown, the common second type terminal lines 646 of multiple layers of transistors overlap in the vertical direction.

[0111] like Figure 6A-6C As shown in , the 3D memory array structure includes a plurality of contact structures 650 (including 652, 654, 656). The first common first type terminal contact structure 652 can be coupled with the first common first type terminal line 642 and is located in the first first type terminal contact area 671, which is located at the first lateral side of the first transistor array 691 away from the second transistor array 699. The second common first type terminal contact structure 654 can be coupled with the second common first type terminal line 644 and is located in the second first type terminal contact area 673, which is located at the second lateral side of the second transistor array 699 away from the first transistor array 691. The common second type terminal contact structure 656 can be coupled with the common second type terminal line 646 and is located in the common second type terminal contact area 675, which is located between the first transistor array 691 and the second transistor array 699.

[0112] In some embodiments, each first common first type terminal contact structure 652 coupled to the corresponding first common first type terminal line 642 may be connected between a first bit line (not shown) and a drain terminal of a first transistor array 691 in the same layer of the corresponding first common first type terminal line 642. Each second common first type terminal contact structure 654 coupled to the corresponding second common first type terminal line 644 may be connected between a second bit line (not shown) and a drain terminal of a second transistor array 699 in the same layer of the corresponding second common first type terminal line 644. Each common second type terminal contact structure 656 coupled to the corresponding common second type terminal line 646 may be connected between a source line (not shown) and a source terminal of a row of transistors in the same layer of the corresponding second common first type terminal line 646.

[0113] like Figure 6C As shown in , the contact structure 650 may include a conductive via extending vertically in the dielectric stack 620. The conductive via may include a conductive layer 674 located on the sidewalls and bottom surface of the contact hole and a conductive filling structure 676 filling the contact hole. The conductive via may also include an enlarged conductive end 679 that is laterally electrically contacted with the corresponding terminal line 640. The contact structure 650 may also include a spacer layer 672 that laterally surrounds the conductive via to isolate the conductive via from other terminal lines 640.

[0114] In some embodiments, Figure 6A-6B As shown in , the 3D memory array structure further includes a first isolation wall 629 located between the first first type terminal contact region 671 and the first transistor array 691 to isolate the first common first type terminal line 642 from the common second type terminal line 646. The 3D memory array structure further includes a second isolation wall 649 located between the second first type terminal contact region 673 and the second transistor array 699 to isolate the second common first type terminal line 644 from the common second type terminal line 646.

[0115] Figure 7 It shows that according to Figure 6A-6C Schematic circuit diagram 700 of a 3D memory array structure with a pattern design shown in FIG. It should be noted that the schematic circuit diagram 700 corresponds to a 3D FeFET of a layer in a 3D memory array structure in an XY plane. Figure 7As shown in , the FeFETs in the first row share a first common source line SL_1, and the FeFETs in the second row share a second common source line SL_2. The array of FeFETs on the left share a first common bit line BL_1, and the array of FeFETs on the right share a second common bit line BL_2. The number of gate lines GL_1, ..., GL_2n can each be connected to a corresponding FeFET, so that the number of FeFETs in two adjacent rows can be independently controlled. Therefore, each FeFET in the 3D storage array structure can be randomly accessed.

[0116] Figure 8 A flow chart of a method 800 of forming a 3D memory structure according to some embodiments of the present disclosure is shown. Figure 9A-9B , Fig.10 , Figure 11A-11B , Figure 12A-12B , Figure 13A-13B , Figure 14A-14B , Figure 15A-15B , Figure 16A-16B and Figure 17A-17B According to some embodiments of the present disclosure, Figure 8 Schematic cross-sectional views and / or top views of a 3D memory structure at a particular manufacturing stage of method 800 shown in FIG. 8. It should be understood that the operations shown in method 800 are not exhaustive, and other operations may also be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously or in parallel. Figure 8 The order shown in the figure is different from the order in which it is executed.

[0117] like Figure 8 As shown in , method 800 begins at operation 802 , where a dielectric stack may be formed on a substrate and a plurality of vias and gaps may be formed in the dielectric stack. Fig.9A The invention shows some embodiments of the present invention. Fig. 9B FIG. 8 is a schematic cross-sectional view of the 3D memory structure after operation 802 , showing the FF′ line. FIG. Fig. 9B The invention shows some embodiments of the present invention. Fig.9A EE′ line is a schematic top view of the 3D memory structure after operation 802 .

[0118] In some embodiments, the substrate 910 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal silicon single layer substrate, a polycrystalline silicon (poly-Si) single layer substrate, a poly-Si and metal multi-layer substrate, etc. In such an embodiment, the dielectric stack 920 may be formed directly on the semiconductor substrate 910. In some other embodiments, the substrate 910 may be a carrier substrate, which may include any suitable semiconductor material or a non-conductive material such as glass, plastic, or sapphire wafer. In such an embodiment, the dielectric stack 920 may be formed directly on a temporary substrate, and in a subsequent operation, a flipping process will be performed, the carrier substrate 910 may be formed in the dielectric stack 920, and then the temporary substrate may be removed.

[0119] According to some embodiments, Fig.9A As shown in FIG. 1 , a dielectric stack 920 including a plurality of dielectric layer pairs may be formed on a substrate 910. Each dielectric layer pair of the dielectric stack 920 may include an alternating stack of a first dielectric layer 922 and a second dielectric layer 924 different from the first dielectric layer 922. In some embodiments, portions of the first dielectric layer 922 and the second dielectric layer 924 may be used as an insulating layer, while other portions of the second dielectric layer 924 may be used as a sacrificial layer to be removed in a subsequent process.

[0120] The plurality of first dielectric layers 922 and second dielectric layers 924 extend in a lateral direction parallel to the surface of the substrate 910. In some embodiments, there are more layers than pairs of dielectric layers made of different materials and having different thicknesses in the dielectric stack 920. The dielectric stack 920 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0121] In some embodiments, the first dielectric layer 922 may be an oxide layer, and the second dielectric layer 924 may be a nitride layer. That is, the dielectric stack 920 may include a plurality of oxide / nitride layer pairs. It should be noted that the oxide layer 922 and / or the nitride layer 924 may include any suitable oxide material and / or nitride material. In some embodiments, the oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer. Multiple oxide / nitride layer pairs are also referred to herein as "oxide / nitride stacks". That is, in the dielectric stack 920, multiple oxide layers 922 and multiple nitride layers 924 alternate in the vertical direction. In other words, except for the top and bottom layers of a given alternating oxide / nitride stack, each of the other oxide layers 922 may be sandwiched between two adjacent nitride layers 924, and each nitride layer in the nitride layer 924 may be sandwiched between two adjacent oxide layers 922.

[0122] The oxide layers 922 may each have the same thickness or different thicknesses. For example, the thickness of each oxide layer may be in the range of from about 10 nm to about 150 nm. Similarly, the nitride layers 924 may each have the same thickness or different thicknesses. For example, the thickness of each nitride layer may be in the range of from about 10 nm to about 150 nm. In some embodiments, the total thickness of the dielectric stack 920 may be greater than 1000 nm. It should be noted that the thickness ranges are provided for illustration and should not be interpreted as limiting the scope of the appended claims.

[0123] The dielectric stack 920 can include any suitable number of oxide layers 922 and nitride layers 924. In some embodiments, the total number of oxide layers 922 and nitride layers 924 in the dielectric stack 920 is equal to or greater than 16. That is, the number of oxide / nitride layer pairs can be equal to or greater than 8. In some embodiments, the alternating oxide / nitride stack includes more oxide layers or more nitride layers having different materials and / or thicknesses than the oxide / nitride layer pairs. For example, the bottom and top layers in the dielectric stack 920 can be oxide layers 922.

[0124] like Figure 9A-9B As shown in , a plurality of through holes 940 may be formed in a dielectric stack 920. In some embodiments, a first array of through holes 940 may be formed in a first array region 991 of the dielectric stack 920, and a second array of through holes 940 may be formed in a second array region 994 of the dielectric stack 920. Each through hole 940 may extend vertically through the dielectric stack 920 and expose the substrate 910. In some embodiments, the through hole 940 may have a high aspect ratio and may be formed by etching the dielectric stack 920 and a subsequent cleaning process. The etching process for forming the through hole 940 may include wet etching, dry etching, or a combination thereof. In some embodiments, each through hole 940 may have an elliptical shape in the XY plane. The long diameter of each through hole 940 may be along the second lateral direction (e.g., the Y direction), and the short diameter of each through hole 940 may be along the first lateral direction (e.g., the X direction).

[0125] like Fig. 9BAs shown in , a plurality of first slits 928 may be formed on both sides of a plurality of through holes 940. Each slit 928 may extend laterally along a second lateral direction (e.g., Y direction) and vertically pass through the dielectric stack 920 and expose the substrate 910. In some embodiments, the first slit 928 may have a high aspect ratio and may be formed by etching the dielectric stack 920 and a subsequent cleaning process. The etching process for forming the first slit 928 may include wet etching, dry etching, or a combination thereof. In some embodiments, the through hole 940 and the first slit 928 may be formed simultaneously in the same process.

[0126] refer to Figure 8 , the method 800 proceeds to operation 804 , where a sacrificial through structure may be formed in the through hole, and an isolation wall may be formed in the gap. Fig.10 The invention shows some embodiments of the present invention. Fig. 9B Schematic cross-sectional view of the 3D memory structure during an intermediate step of operation 802 . Fig.11A The invention shows some embodiments of the present invention. Fig. 11B FIG. 8 is a schematic cross-sectional view of the 3D memory structure after operation 804 , of the FF′ line. Fig. 11B The invention shows some embodiments of the present invention. Fig.11A EE′ line is a schematic top view of the 3D memory structure after operation 804 .

[0127] like Fig.10 As shown in FIG. 8 , operation 804 may include a recess etching process to remove portions of the second dielectric layer 924 of the dielectric stack 920 exposed by the plurality of vias 940 . In this way, a plurality of recesses 1040 may be formed on the sidewalls of each via 940 .

[0128] In some embodiments, the portion of the second dielectric layer 924 of the dielectric stack 920 on the sidewalls of each through-hole 940 can be removed by using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process can have a sufficiently high etching selectivity for the material of the second dielectric layer 924 relative to the material of the first dielectric layer 922, so that the etching process can have minimal impact on the first dielectric layer 922. The isotropic dry etching and / or wet etching can remove the portion of the second dielectric layer 924 exposed by the plurality of through-holes 940. In this way, a plurality of recesses 1040 can be formed on the sidewalls of each through-hole 940.

[0129] In some embodiments, each recess 1140 may have a horizontal hollow annular shape, the outer sidewall of which is the second dielectric layer 924 and the top and bottom walls are the adjacent first dielectric layer 922. That is, after the recess etching process, each through hole 940 may have an uneven sidewall. In some embodiments, the size of the second dielectric layer 924 etched back may be in a range from about 5 nm to about 20 nm.

[0130] like Fig.11A As shown in , operation 804 may also include a deposition process to form a plurality of sacrificial through structures 1140 in the through hole 940. In some embodiments, the sacrificial through structures 1140 may be formed to fill the through hole 940 and the plurality of recesses 1040 on the sidewalls of the through hole 940. In some embodiments, forming the sacrificial through structures 1140 may include filling a sacrificial material (e.g., polysilicon) into the through hole 940 by using any suitable deposition process (e.g., ALD, CVD, PVD, etc.).

[0131] like Fig. 11B As shown in , operation 804 may further include a deposition process to form a plurality of spacers 1133 in the first gap 928. In some embodiments, the sacrificial spacers 1133 may include any suitable insulating material (e.g., silicon oxide) and may be formed to fill the first gap 928 by using any suitable deposition process (e.g., ALD, CVD, PVD, etc.).

[0132] refer to Figure 8 , method 800 proceeds to operation 806 , where a plurality of conductive lines may be formed. Fig. 12A The invention shows some embodiments of the present invention. Fig. 12B Schematic cross-sectional view of the 3D memory structure between FF′ lines at the first intermediate step of operation 806 . Fig. 12B The invention shows some embodiments of the present invention. Fig. 12A Schematic top view of the 3D memory structure between lines EE′ at the first intermediate step of operation 806 . Fig.13A The invention shows some embodiments of the present invention. Fig. 13B A schematic cross-sectional view of the 3D memory structure between FF′ lines at the second intermediate step of operation 806 . Fig. 13B The invention shows some embodiments of the present invention. Fig.13A A schematic top view of the 3D memory structure between lines EE′ at the second intermediate step of operation 806 . Fig.14A The invention shows some embodiments of the present invention. Fig. 14B FIG. 8 is a schematic cross-sectional view of the 3D memory structure after operation 806 , of the FF′ line. Fig. 14B The invention shows some embodiments of the present invention. Fig.14A EE′ line is a schematic top view of the 3D memory structure after operation 806 .

[0133] like Figure 12A-12B As shown in , operation 806 may include removing portions of the dielectric stack 920 to form a plurality of slits 1260. The pattern of the second slit 1260 in the lateral XY plane may be predetermined by the conductive lines formed in subsequent steps. In the vertical direction (e.g., the Z direction), the second slit 1260 may be formed to penetrate the dielectric stack 920. In some embodiments, the second slit 1260 may be formed by forming a mask layer (not shown) on the dielectric stack 920 and patterning the mask layer using (e.g.) photolithography to form openings corresponding to the plurality of slits in the patterned mask layer. An appropriate etching process, such as dry etching and / or wet etching, may be performed to remove portions of the dielectric stack 920 exposed by the openings until the slit 1260 exposes the substrate 910. The mask layer may be removed after forming the plurality of slits 1260.

[0134] like Figure 13A-13B As shown in , operation 806 may also include replacing the portion of the second dielectric layer 924 of the dielectric stack 920 exposed by the plurality of second slits 1260 by the conductive lines 1320 (including 1322, 1324, 1326). In some embodiments, the portion of the second dielectric layer 924 of the dielectric layer stack 920 exposed by the plurality of slits 1260 may be removed to form a plurality of horizontal trenches (not shown). In some embodiments, the exposed portion of the second dielectric layer 924 may be removed by using any suitable recess etching process (e.g., isotropic dry etching or wet etching). The etching process may have a sufficiently high etching selectivity to the material of the second dielectric layer 924 relative to the material of the first dielectric layer 922 of the dielectric stack 920 and the sacrificial through structure 1140, so that the etching process may have minimal impact on the first dielectric layer 922 and the sacrificial through structure 1140.

[0135] In some embodiments, the recess etching process can remove portions of the second dielectric layer 924 in various directions through the plurality of slits 1260. As such, a plurality of horizontal trenches (not shown) can then be formed extending in a horizontal direction to a specific depth recessed from the sidewalls of the plurality of slits 1260. After removing portions of the second dielectric layer 924, the plurality of slits 1260 and the plurality of horizontal trenches can be cleaned by using any appropriate cleaning process.

[0136] After the cleaning process, in some embodiments, the Figure 13A-13BConductive lines 1320 (including 1322, 1324, 1326) are formed in the multiple horizontal grooves shown in . Conductive lines 1320 (including 1322, 1324, 1326) can be formed by filling the multiple horizontal grooves with any suitable conductive material (for example, tungsten, aluminum, copper, cobalt, or any combination thereof). The conductive material can be deposited into the horizontal grooves using a suitable deposition method (for example, CVD, PVD, plasma enhanced CVD (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD) and / or ALD). In some embodiments, according to some embodiments of the present disclosure, the formed conductive lines 1320 (including 1322, 1324, 1326) can be used as source terminals and drain terminals of FeFETs formed in subsequent processes. In some embodiments, as Fig. 13B As shown in , the first / second common first type terminal lines 1322 / 1324 can be isolated from the common second type terminal line 1326 by the isolation wall 1133 .

[0137] like Figure 14A-14B As shown in , operation 806 may also include forming a filling structure 1462 to fill the plurality of second gaps 1260. In some embodiments, after forming the conductive lines 1320 (including 1322, 1324, 1326), the plurality of second gaps 1260 may be filled with a dielectric material using any suitable deposition method (e.g., CVD, PVD, and / or ALD). In some embodiments, the dielectric material of the filling structure 1462 may be a low temperature oxide material. In some embodiments, the dielectric material of the filling structure 1462 may include the same dielectric material as the first dielectric layer 922, such as silicon oxide.

[0138] refer to Figure 8 , the method 800 may proceed to operation 808 where a plurality of contact structures may be formed in the contact region. Fig.15A The invention shows some embodiments of the present invention. Fig. 15B Schematic cross-sectional view of the 3D memory structure after operation 808 . Fig. 15B The invention shows some embodiments of the present invention. Fig.15A EE′ line is a schematic top view of the 3D memory structure after operation 808 .

[0139] like Figure 15A-15BAs shown in , a plurality of contact structures 1580 (including 1582, 1584, 1586) may be formed in contact regions 1501, 1503, and 1505. A first common first type terminal contact structure 1582 may be formed to contact the first common first type terminal line 1322 and is located in the first first type terminal contact region 1501, which is located at a first lateral side of the first array region 991 away from the second array region 999. A second common first type terminal contact structure 1584 may be formed to contact the second common first type terminal line 1324 and is located in the second first type terminal contact region 1503, which is located at a second lateral side of the second array region 999 away from the first array region 991. The common second type terminal contact structure 1586 may be formed to contact the common second type terminal line 1326 and be located in a common second type terminal contact region 1505 located between the first array region 991 and the second array region 999 .

[0140] like Fig.15A As shown in , forming the contact structure 1580 may include forming a plurality of contact holes, each of which penetrates the upper portion of the dielectric stack 920 and stops at a corresponding second dielectric layer 924. A dielectric filling structure may be formed by any suitable deposition process to fill each contact hole. Punch etching may be performed to remove a portion of the dielectric filling structure to expose a corresponding second dielectric layer 924 in each contact hole. The remaining portion of the dielectric filling structure forms a spacer layer 1572 on the sidewall of each contact hole. A portion of a corresponding second dielectric layer 924 may be removed by any suitable etching process to expose a corresponding conductive line 1320 located at the same level as the corresponding second dielectric layer 924. A conductive layer 1574 may be formed by any suitable thin film deposition process to cover the spacer layer 1572 and the bottom surface of each contact hole and contact a corresponding conductive line 1320 in the lateral direction. A second conductive material may then be filled in the contact hole to form a conductive filling structure 1576. Conductive layer 1574 and conductive fill structure 1576 may form a conductive via isolated from other conductive lines 1320 by spacer layer 1572 .

[0141] refer to Figure 8 , the method 800 may proceed to operation 810 , where the plurality of sacrificial through-structures may be replaced by a plurality of transistor structures. Fig.16A The invention shows some embodiments of the present invention. Fig. 16B A schematic cross-sectional view of a 3D memory structure between FF′ lines at an intermediate step of operation 810 . Fig. 16BThe invention shows some embodiments of the present invention. Fig.16A Schematic top view of the 3D memory structure between the EE′ lines at the intermediate step of operation 810 . Fig.17A The invention shows some embodiments of the present invention. Fig. 17B 8 is a schematic cross-sectional view of the 3D memory structure after operation 810 . Fig. 17B The invention shows some embodiments of the present invention. Fig.17A EE′ line is a schematic top view of the 3D memory structure after operation 810 .

[0142] like Figure 16A-16B As shown in , operation 810 may include removing the sacrificial through structure 1140 to reopen the plurality of through holes 940 and the plurality of recesses 1040 on the sidewalls of the through holes 940. In some embodiments, the sacrificial through structure 1140 may be removed by using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process may have a sufficiently high etching selectivity to the material of the sacrificial through structure 1140 relative to the material of the first dielectric layer 922 and the conductive line 1320, so that the etching process may have minimal impact on the first dielectric layer 922 and the conductive line 1320. After removing the sacrificial through structure 1140, the plurality of through holes 940 and the plurality of recesses 1040 on the sidewalls of the through holes 940 may be reformed. That is, as Fig.16A As shown in , new via 1640 may have uneven sidewalls and expose conductive line 1320 .

[0143] like Figure 17A-17B As shown in , operation 810 may also include forming a transistor structure 1770 in the new via 1640. In some embodiments, the transistor structure 1770 may include a control gate 1730 extending vertically through the new via 1640, a ferroelectric layer 1720 laterally surrounding the control gate 1730, and a plurality of channel layers 1710 laterally surrounding the ferroelectric layer 1720.

[0144] The channel layer 1710 may be formed in the plurality of recesses 1040 of each new through hole 1640. In some embodiments, forming the channel layer 1710 may include a deposition process of forming a silicon layer to cover the sidewalls of the plurality of new through holes 1640. The silicon layer may be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process (e.g., ALD, CVD, PVD, or any other suitable process). In some embodiments, forming the channel layer 1710 may also include an etching process of removing a portion of the silicon layer attached to the sidewalls of the first dielectric layer 922. In this way, as shown in FIG. Fig.17A As shown in , the remaining portions of the silicon layer in the plurality of recesses 1040 may form a channel layer 1710 .

[0145] In some embodiments, Fig. 17B As shown in , each layer in the channel layer 1710 can be in contact with the first / second common first type terminal line 1322 / 1324, and in contact with the common second type terminal line 1326. The first / second common first type terminal line 1322 / 1324 can be in contact with the channel layer 1710 at one end of the long diameter of each through structure 1770 (for example, the lower end of the through structure 1770 of the first row and the upper end of the through structure 1770 of the second row). The common second type terminal line 1326 can be in contact with the channel layer 1710 of each through structure 1770 at the other end of the long diameter of each through structure 1770 (for example, the upper end of the through structure 1770 of the first row and the lower end of the through structure 1770 of the second row). Therefore, the first / second common first type terminal line 1322 / 1324 and the common second type terminal line 1326 can be used as a common bit line and a common source line, respectively.

[0146] In some embodiments, a memory film may be formed in each new through hole 1640. In some embodiments, the memory film may include a barrier layer (not shown), a ferroelectric layer 1720, and an interface layer (not shown).

[0147] In some embodiments, an interface layer 1668 can be formed on the sidewalls and bottom of each new through hole 1640. The sidewalls of the interface layer can be in contact with the first dielectric layer 922 and the channel layer 1710. The bottom side of the interface layer can be in contact with the substrate 910. The interface layer can be used to reduce the possibility of material mixing between the ferroelectric layer 1720 and the channel layer 1710. In some embodiments, the interface layer can be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material (e.g., HfO2, HfAlO, Al2O3), and / or any combination thereof. The interface layer can be formed by any suitable film deposition technique (e.g., ALD, CVD, sputtering, evaporation, and / or any combination thereof), or by oxidation, nitridation, and / or a combination thereof. The thickness of the interface layer can be in a range between about 5 nm and about 50 nm.

[0148] In some embodiments, the ferroelectric layer 1720 can be formed to cover the interface layer. In some embodiments, the ferroelectric layer 124 can include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). In some embodiments, the ferroelectric layer 1720 can include a high-k (i.e., high dielectric constant) dielectric material, which can include a transition metal oxide, such as hafnium zirconium oxide (HZO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3) and / or any combination thereof.

[0149] In some embodiments, the ferroelectric layer 1720 can be disposed by chemical vapor deposition (CVD) (e.g., metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.). The ferroelectric layer 1720 can also be disposed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof. In some embodiments, the ferroelectric layer 1720 can have a thickness in a range between 5 nm and 100 nm.

[0150] In some embodiments, the high-k dielectric material of the ferroelectric layer 1720 may be doped to improve the ferroelectric properties. For example, the ferroelectric layer 1720 may be HZO or HfO2 doped with silicon (Si), (yttrium) Y, gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof. In some embodiments, the ferroelectric film 224 may include zirconate titanate (PZT), strontium bismuth tantalate (SrBi2Ta2O9), barium titanate (BaTiO3), PbTiO3, and BLT ((Bi,La)4Ti3O 12 ) or any combination thereof.

[0151] In some embodiments, the barrier layer can be formed to cover the ferroelectric layer 1720. The barrier layer can be used to block the interaction between the ferroelectric layer 1720 and the control gate formed in the subsequent process. The barrier layer may include titanium nitride (TiN), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2O2N), high-k dielectric materials (e.g., HfO2, Al2O3) and / or any combination thereof. The barrier layer can be formed by any suitable physical vapor deposition (PVD) or chemical vapor deposition (CVD). The barrier layer may have a thickness in the range between about 5 nm and about 50 nm.

[0152] In some embodiments, Fig.17AAs shown in , a control gate 1730 may be formed in each new through hole 1640 to cover the storage film and fill the new through hole 1640. In some embodiments, the control gate 1730 may be a metal filling structure or a polysilicon filling structure formed by using any suitable deposition process (e.g., ALD, CVD, PVD, etc.). In some embodiments, a subsequent chemical mechanical planarization (CMP) process may be performed to remove the storage film and the portion of the control gate 1710 located outside the new through hole 1640.

[0153] Accordingly, a three-dimensional (3D) ferroelectric field effect transistor (FeFET) random access memory (RAM) device and a method for manufacturing the same are described in the present disclosure. The disclosed 3D FeFET RAM device is a high-speed, high-density non-volatile memory that changes the threshold voltage and stores data by using ferroelectric polarity. The graphics of the memory cell can be designed to be an elliptical shape to increase the gate length, thereby improving the gate control capability while increasing the storage density. In addition, a common source line and a common drain line can be formed to enable random access to each memory cell. The source line and drain line of each layer can be electrically connected by using a through contact, which simplifies the source-drain contact process. The drain / source electrodes of the FeFET can be connected to the common drain / source line to reduce the step area. Ferroelectric materials such as IGZO can be filled into the through hole from the front or back as the channel material of the FeFET, thereby improving the reliability of the ferroelectric material.

[0154] The foregoing description of specific embodiments will so completely reveal the general nature of the present disclosure that others can easily modify and / or adjust such specific embodiments for various applications by applying knowledge within the technical scope of the art, without undue experimentation, and without departing from the overall concept of the present disclosure. Therefore, based on the disclosure and guidance given herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It will be understood that the words or terms herein are for descriptive purposes rather than for limiting purposes, so that the terms or terms of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0155] The embodiments of the present disclosure have been described above with the help of functional building blocks that illustrate the embodiments of specific functions and their relationships. For the convenience of description, the limits of these functional building blocks have been arbitrarily defined herein. As long as the specified functions and their relationships are properly performed, alternative limits can be defined.

[0156] The Summary and Abstract sections may set forth one or more, but not all, embodiments of the present disclosure contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0157] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor structure comprising: A plurality of layers of transistors, wherein the plurality of layers of transistors are stacked in a vertical direction, each layer of the transistors comprising: a first transistor array, the first transistor array sharing a first common first-type terminal line; a second transistor array, the second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and A plurality of contact structures, the plurality of contact structures comprising: a first common first type terminal contact structure, the first common first type terminal contact structure being coupled to the first common first type terminal line in a first first type terminal contact region, the first first type terminal contact region being located at a first lateral side of the first transistor array away from the second transistor array, a second common first type terminal contact structure, the second common first type terminal contact structure being coupled to the second common first type terminal line in a second first type terminal contact region, the second first type terminal contact region being located at a second lateral side of the second transistor array away from the first transistor array, and A common second type terminal contact structure is coupled with the common second type terminal line in a common second type terminal contact region, the common second type terminal contact region being located between the first transistor array and the second transistor array.

2. The semiconductor structure according to claim 1, wherein: The transistor is a ferroelectric field effect transistor (FeFET).

3. The semiconductor structure according to claim 2, wherein: Each FeFET consists of: Channel layer; a ferroelectric layer having ferroelectricity and surrounded by the channel layer in a horizontal plane; and A gate is surrounded by the ferroelectric layer in the horizontal plane.

4. The semiconductor structure according to claim 3, wherein: The channel layer includes a metal oxide semiconductor material.

5. The semiconductor structure according to claim 3, wherein: The channel layer of each FeFET has an elliptical ring shape in a horizontal plane.

6. The semiconductor structure of claim 5, wherein: a first portion of the channel layer at a second end of the long diameter of the elliptical shape contacts the first common first type terminal line or the second common first type terminal line; and A second portion of the channel layer at a first end of the major diameter of the elliptical shape is in contact with the common second type terminal line.

7. The semiconductor structure of claim 1, wherein: The first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; and The second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

8. The semiconductor structure of claim 1, wherein: The first type of terminal is a drain terminal; The second type terminal is a source terminal; The first common first type terminal contact structure is connected to a first bit line; The second common first type terminal contact structure is connected to a second bit line; and The common second type terminal contact structure is connected to a source line.

9. The semiconductor structure of claim 1, wherein: Each contact structure of the plurality of contact structures is located in the dielectric stack in the first first type terminal contact area or the second first type terminal contact area or the common second type terminal contact area.

10. The semiconductor structure of claim 9, wherein: The first common first type terminal lines of the plurality of layers of the transistor overlap in the vertical direction; The second common first type terminal lines of the plurality of layers of the transistor overlap in the vertical direction; and The common second type terminal lines of the plurality of layers of the transistor overlap in the vertical direction.

11. The semiconductor structure according to claim 10, wherein: A contact structure of the middle stack of transistors includes: a conductive via extending vertically in the dielectric stack above an intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from terminal lines of an upper transistor located above the intermediate stack of transistors; and An enlarged conductive end is laterally electrically contacted with a corresponding terminal line of the middle stack of transistors.

12. The semiconductor structure of claim 9, further comprising: a first isolation wall, the first isolation wall being located between the first first-type terminal contact region and the first transistor array to isolate the first common first-type terminal line from the common second-type terminal line; as well as A second isolation wall is located between the second first type terminal contact area and the second transistor array to isolate the second common first type terminal line from the common second type terminal line.

13. A semiconductor structure comprising: A plurality of layers of transistors, wherein the plurality of layers of transistors are stacked in a vertical direction, each layer of the transistors comprising: a first transistor array, the first transistor array sharing a first common first-type terminal line; a second transistor array, the second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and a plurality of contact structures, each of the plurality of contact structures being coupled to the first common first type terminal line, the second common first type terminal line, or the common second type terminal line; Each of the plurality of contact structures electrically coupled to the intermediate stack of transistors penetrates the dielectric stack located above the intermediate stack of transistors.

14. The semiconductor structure according to claim 13, wherein: The transistor is a ferroelectric field effect transistor (FeFET).

15. The semiconductor structure according to claim 14, wherein: Each FeFET consists of: Channel layer; a ferroelectric layer having ferroelectricity and surrounded by the channel layer in a horizontal plane; and A control gate is surrounded by the ferroelectric layer in the horizontal plane.

16. The semiconductor structure according to claim 15, wherein: The channel layer includes a metal oxide semiconductor material.

17. The semiconductor structure according to claim 15, wherein: The channel layer of each FeFET cell has an elliptical ring shape in a horizontal plane.

18. The semiconductor structure of claim 17, wherein: a first portion of the channel layer at a second end of the long diameter of the elliptical shape contacts the first common first type terminal line or the second common first type terminal line; and A second portion of the channel layer at a first end of the major diameter of the elliptical shape is in contact with the common second type terminal line.

19. The semiconductor structure of claim 13, wherein: The first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; and The second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

20. The semiconductor structure of claim 13, wherein: The plurality of contact structures include: a first common first type terminal contact structure, the first common first type terminal contact structure being coupled to the first common first type terminal line in a first first type terminal contact region, the first first type terminal contact region being located at a first lateral side of the first transistor array away from the second transistor array, a second common first type terminal contact structure, the second common first type terminal contact structure being coupled to the second common first type terminal line in a second first type terminal contact region, the second first type terminal contact region being located at a second lateral side of the second transistor array away from the first transistor array, and A common second type terminal contact structure is coupled with the common second type terminal line in a common second type terminal contact region, the common second type terminal contact region being located between the first transistor array and the second transistor array.

21. The semiconductor structure of claim 13, wherein: The first type of terminal is a drain terminal; The second type terminal is a source terminal; The first common first type terminal contact structure is connected to a first bit line; The second common first type terminal contact structure is connected to a second bit line; and The common second type terminal contact structure is connected to a source line.

22. The semiconductor structure of claim 13, wherein: Each contact structure consists of: a conductive via extending vertically in the dielectric stack above an intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from terminal lines of an upper transistor located above the intermediate stack of transistors; and An enlarged conductive end is laterally electrically contacted with a corresponding terminal line of the middle stack of transistors.

23. The semiconductor structure of claim 13, wherein: The first common first type terminal lines of the plurality of layers of the transistor overlap in the vertical direction; The second common first type terminal lines of the plurality of layers of the transistor overlap in the vertical direction; and The common second type terminal lines of the plurality of layers of the transistor overlap in the vertical direction.

24. The semiconductor structure of claim 20, further comprising: a first isolation wall, the first isolation wall being located between the first first-type terminal contact region and the first transistor array to isolate the first common first-type terminal line from the common second-type terminal line; as well as A second isolation wall is located between the second first type terminal contact area and the second transistor array to isolate the second common first type terminal line from the common second type terminal line.

25. A method of forming a semiconductor structure, comprising: forming a dielectric stack including a plurality of first dielectric layers and second dielectric layers alternately stacked in a vertical direction; forming a plurality of through holes in the dielectric stack; forming a plurality of sacrificial through structures in the plurality of through holes; replacing a portion of the second dielectric layer with a conductive line; replacing the plurality of sacrificial through-structures with a plurality of transistor structures; as well as A plurality of contact structures are formed, each of the plurality of contact structures being coupled to a corresponding conductive line and penetrating a remaining portion of the dielectric stack above the corresponding conductive line.

26. The method according to claim 25, wherein: Forming the plurality of sacrificial through structures comprises: removing portions of the second dielectric layer exposed by the plurality of through holes to form a plurality of recesses on sidewalls of the plurality of through holes; and A sacrificial material is deposited to fill the plurality of recesses and the plurality of vias.

27. The method according to claim 26, wherein: Replacing the plurality of sacrificial through-structures with a plurality of transistor structures includes: removing the plurality of sacrificial through structures from the plurality of recesses and the plurality of through holes; forming a plurality of channel layers in the plurality of recesses; forming a ferroelectric layer on a sidewall of each through hole, wherein the ferroelectric layer has ferroelectricity and is laterally surrounded by the channel layer; and A gate structure is formed in each via, wherein the gate structure is laterally surrounded by the ferroelectric layer.

28. The method according to claim 27, wherein: The channel layer includes a metal oxide semiconductor material in direct contact with the conductive layer.

29. The method according to claim 28, wherein: The metal oxide semiconductor material is indium gallium zinc oxide (IGZO).

30. The method of claim 25, wherein: Replacing the portion of the second dielectric layer with the conductive line comprises: forming a plurality of gaps through the dielectric stack; removing the portion of the second dielectric layer from the plurality of slits to form a plurality of horizontal openings; forming the conductive lines in the plurality of horizontal openings; and The plurality of gaps are filled with a dielectric material.

31. The method of claim 25, wherein: Forming the plurality of through holes includes forming each of the through holes to have an elliptical shape in a horizontal plane.

32. The method of claim 29, further comprising: forming a partition wall vertically penetrating the dielectric stack so that the conductive line formed in each stack is divided by the partition wall to include: a first common first type terminal line shared by a first array of ferroelectric field effect transistor (FeFET) cells in the layer; a second common first type terminal line shared by a second transistor array in the layer; and A common second type terminal line is shared by the first transistor array and the second transistor array.

33. The method of claim 32, wherein: A first portion of the channel layer at a first end of a long diameter of the elliptical shape is formed in contact with the common second type terminal line; and A second portion of the channel layer at a second end of the long diameter of the elliptical shape is formed to contact the first common first type terminal line or the second common first type terminal line.

34. The method of claim 32, wherein: The first common first type terminal line is formed to include a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; and The second common first type terminal line is formed to include a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the second transistor array.

35. The method of claim 32, wherein: Forming the plurality of contact structures comprises: forming a first common first type terminal contact structure coupled to the first common first type terminal line and located at a first lateral side of the first transistor array away from the second transistor array; forming a second common first type terminal contact structure coupled to a second bit line and located at a second lateral side of the second transistor array away from the first transistor array; and A common second type terminal contact structure is formed that is coupled to the common second type terminal line and is located between the first transistor array and the second transistor array.

36. The method of claim 25, wherein: Forming a contact structure among the plurality of contact structures comprises: forming a contact hole penetrating an upper portion of the remaining portion of the dielectric stack and stopping at a second dielectric layer located at the same level of the corresponding one of the conductive lines; forming a dielectric filling structure to fill the contact hole; performing punch etching to remove a portion of the dielectric filling structure to expose a portion of the one second dielectric layer adjacent to the one corresponding conductive line; removing the portion of the one second dielectric layer to expose the one corresponding conductive line; and A conductive material is deposited in the contact hole to form the one contact structure, so that the contact structure is isolated from the conductive line located above the one corresponding conductive line and is in electrical contact with the one corresponding conductive line in a lateral direction.

37. The method of claim 32, wherein: The first common first type terminal lines in the plurality of layers of the conductive lines are formed to overlap in the vertical direction; The second common first type terminal lines in the plurality of layers of the conductive lines are formed to overlap in the vertical direction; and The common second type terminal lines in the plurality of layers of the conductive lines are formed to overlap in the vertical direction.

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