A semiconductor device, a manufacturing method thereof, and a semiconductor apparatus

Abstract

The application relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor device and a manufacturing method thereof and a semiconductor device, which comprises a substrate; a first stack unit and a second stack unit which are arranged in a vertical direction on the substrate; the first stack unit and the second stack unit respectively comprise an upper transistor and a lower transistor, and the upper transistor and the lower transistor are arranged in a staggered mode in a direction parallel to the substrate; the upper transistor and the lower transistor respectively comprise an upper nanowire / sheet stack and a lower nanowire / sheet stack which extend in a first direction, an upper gate which extends in a second direction and surrounds the upper nanowire / sheet stack, and a lower gate which surrounds the lower nanowire / sheet stack; and the second stack unit is arranged adjacent to the first stack unit in the first direction. The upper and lower stacked transistors are staggered and separated in a horizontal direction, and an additional SDB isolation structure is not needed, so that the electrical isolation requirement between adjacent devices can be met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor device and its manufacturing method and equipment. Background Technology

[0002] As semiconductor process technology continues to evolve towards advanced nodes of 2nm and below, the Complementary Field Effect Transistor (CFET) stacks NMOS and PMOS transistors vertically, with the upper and lower devices sharing a lateral gate array channel. This significantly reduces the lateral size of standard cells and greatly improves chip integration density, making it the next-generation core device architecture.

[0003] In CFET device arrays, two active regions are vertically stacked within the same lateral gate pitch (CPP) channel. Strong lateral electric field coupling occurs between the gate, nanosheet active region, and source / drain diffusion regions of adjacent transistor cells, leading to reliability and performance defects such as increased inter-gate parasitic capacitance, device threshold voltage drift, and aggravated channel leakage. To block electrical coupling between adjacent devices and achieve effective isolation between cells, existing CFET processes commonly employ virtual gate isolation band schemes, specifically including two types of structures: double virtual gate isolation boundary (DDB) and single virtual gate isolation boundary (SDB).

[0004] The DDB isolation structure consists of two independent virtual gates combined with a complete nanosheet dicing region, occupying a lateral space of 3 gate pitches (3×CPP). The dual virtual gates can form a double-layer electrostatic shielding wall, which can effectively suppress coupling leakage and proximity effect. However, its isolation region has a large lateral width, which significantly reduces the effective layout area of ​​the standard cell.

[0005] The SDB isolation structure uses only a single virtual gate and occupies two gate pitches (2×CPP) of lateral space, which reduces the area overhead by one CPP compared to the DDB structure, thus improving the cell integration density to some extent. However, the electrostatic shielding capability of a single virtual gate is limited, and the problems of electric field penetration between adjacent devices and gate parasitic coupling cannot be fully suppressed, making it difficult to meet the performance requirements of high-frequency, low-noise circuits.

[0006] Furthermore, both DDB and SDB isolation structures are compensatory isolation schemes that involve inserting redundant virtual gates into the device array layout. They do not address the core contradiction of isolation relying on large space at the root of CFET device stacking topology and gate structure. Even with the use of a split gate to alleviate vertical gate coupling, in traditional aligned CFETs, the active regions of the upper nFET and the lower pFET are completely aligned laterally, and significant lateral electric field coupling still exists in the active regions. Therefore, the SDB isolation band still needs to be retained in the circuit layout.

[0007] To address this issue, existing technologies have further proposed staggered CFETs (SCFETs), which arrange the upper and lower active regions in a laterally staggered manner. However, existing conventional SCFET structures do not have segmented isolation designs for the gate / active region, and a dielectric barrier layer of a certain width is still required between adjacent devices, which still cannot completely avoid the area occupation defects caused by the isolation area.

[0008] In view of this, the present invention is proposed. Summary of the Invention

[0009] The purpose of this invention is to provide a semiconductor device and its manufacturing method. This invention achieves electrical isolation between adjacent devices by horizontally separating stacked transistors without introducing additional isolation structures such as SDB.

[0010] In a first aspect, the present invention provides a semiconductor device, including a substrate; The first stacking unit and the second stacking unit are respectively stacked on the substrate in a vertical direction; The first stacking unit and the second stacking unit each include an upper transistor and a lower transistor, and the upper transistor and the lower transistor are staggered in a direction parallel to the substrate; The upper transistor and the lower transistor respectively include an upper nanowire / sheet stack and a lower nanowire / sheet stack extending along a first direction, an upper gate extending along a second direction and surrounding the upper nanowire / sheet stack, and a lower gate surrounding the lower nanowire / sheet stack. The second stacking unit is disposed adjacent to the first stacking unit along the first direction.

[0011] As a preferred embodiment of this technical solution, the upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the second stacking unit are located in a first plane perpendicular to the substrate; The lower nanowire / sheet stack of the first stacking unit and the upper nanowire / sheet stack of the second stacking unit are located in a second plane perpendicular to the substrate.

[0012] In a preferred embodiment of this technical solution, the upper gate and lower gate of the first stacked unit are located in a third plane perpendicular to the substrate; The upper and lower gates of the second stacked cell are located in a fourth plane perpendicular to the substrate.

[0013] In a preferred embodiment of this technical solution, the upper nanowire / sheet stack of the first stacking unit and the upper nanowire / sheet stack of the second stacking unit are parallel to each other on the substrate. The lower nanowire / sheet stack of the first stacking unit and the orthographic projection of the lower nanowire / sheet stack of the second stacking unit onto the substrate are parallel to each other.

[0014] In a preferred embodiment of this technical solution, the upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the first stacking unit are parallel to each other on the substrate. The upper nanowire / sheet stack of the second stacking unit and the lower nanowire / sheet stack of the second stacking unit are parallel to each other on the substrate.

[0015] In a preferred embodiment of this technical solution, the upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the second stacking unit are aligned on the orthographic projection of the second nanowire / sheet stack on the substrate. The lower nanowire / sheet stack of the first stacking unit is aligned with the orthographic projection of the upper nanowire / sheet stack of the second stacking unit onto the substrate.

[0016] In a preferred embodiment of this technical solution, the upper transistor and the lower transistor respectively include an upper source-drain region and a lower source-drain region disposed on both sides of the upper gate and the lower gate; The end of the upper source drain region of the first stacking unit near the side of the second stacking unit is aligned with or has a first gap from the end of the upper source drain region of the second stacking unit near the side of the first stacking unit.

[0017] As a preferred embodiment of this technical solution, the end of the lower source / drain region of the first stacking unit near the side of the second stacking unit is aligned with or has a second spacing from the end of the lower source / drain region of the second stacking unit near the side of the first stacking unit.

[0018] As a preferred embodiment of this technical solution, the first spacing may be equal to or different from the second spacing.

[0019] In a preferred embodiment of this technical solution, the horizontal distance between the orthographic projections of the upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the first stacking unit onto the substrate is the first misalignment distance. The horizontal distance between the orthographic projections of the upper nanowire / sheet stack of the second stacking unit and the lower nanowire / sheet stack of the second stacking unit onto the substrate is the second misalignment distance. The first misalignment distance is equal to the second misalignment distance.

[0020] In a preferred embodiment of this technical solution, the upper gate of the first stacking unit and the lower gate of the first stacking unit are continuously or spaced apart in the vertical direction. And / or, the upper gate of the second stacked unit and the lower gate of the second stacked unit are arranged continuously or spaced apart in the vertical direction.

[0021] As a preferred embodiment of this technical solution, an insulating layer is included below the upper nanowire / sheet stack and above the lower nanowire / sheet stack, and a first insulating structure is included below the upper nanowire / sheet stack, wherein the first insulating structure has the same width and length as the upper nanowire / sheet stack.

[0022] As a preferred embodiment of this technical solution, a second insulating structure is provided above the lower nanowire / sheet stack, which is placed on the insulating layer. The width of the second insulating structure is the same as the gate length of the lower gate, and the length of the second insulating structure is less than or equal to the width of the lower gate.

[0023] Secondly, the present invention also discloses a method for manufacturing a semiconductor device, comprising the following steps: Provide substrate; A first fin stack and a second fin stack are formed on a substrate in a horizontally parallel and spaced manner. The first fin stack and the second fin stack are each formed by alternating stacking of a first semiconductor layer and a second semiconductor layer. The middle part of the first fin stack and the second fin stack also includes a sacrificial layer, which divides the first fin stack and the second fin stack into an upper part and a lower part, respectively. The upper part of the first fin stack and the second fin stack is etched, wherein the upper part of the first fin stack retains a first position and the upper part of the second fin stack retains a second position, and the first position and the second position are respectively located at positions that are staggered from each other in the first fin stack and the second fin stack. A sacrificial gate and a sidewall are formed across the first and second positions, respectively. The first fin stack and the second fin stack are etched using the sacrificial gate and the sidewall as a mask to remove the portion of the first fin stack except for the fin stack below the first position of the first fin stack, and the portion of the second fin stack except for the fin stack below the second position of the second fin stack, to form the corresponding nanowire / sheet stack. Remove the fin stack below the first position of the first fin stack and the fin stack below the second position of the second fin stack; Source and drain regions are epitaxially formed on both sides of the corresponding nanowire / sheet stack; The sacrificial gate and the second semiconductor layer are removed to form a gate trench, and a replacement gate is formed in the gate trench.

[0024] As a preferred embodiment of this technical solution, the removal of the fin stack below the first position of the first fin stack and the fin stack below the second position of the second fin stack includes: After the corresponding nanowire / sheet stack is formed, a protective layer is formed on the surface of the entire device, and the protective layer needs to expose the ends and surfaces of the fin stack below the first position in the first fin stack and the ends and surfaces of the fin stack below the second position in the second fin stack. Etching is performed on the fin stack below the first position in the first fin stack and the fin stack below the second position in the second fin stack, starting from the end and the surface.

[0025] As a preferred embodiment of this technical solution, before removing the fin stack below the first position of the first fin stack and the fin stack below the second position of the second fin stack, the method further includes: removing the sacrificial layer in the middle of the first fin stack and the second fin stack.

[0026] As a preferred embodiment of this technical solution, after etching the fin stack below the first position in the first fin stack and the fin stack below the second position in the second fin stack starting from the end and the surface, the method further includes: removing the protective layer and etching the second semiconductor layer inward to form an inner sidewall groove; depositing an isolation medium in the inner sidewall groove, the cavity formed after removing the sacrificial layer, and the cavity formed after etching the fin stacks below the first and second positions, thereby forming an inner sidewall, an isolation layer, and a first insulating structure.

[0027] As a preferred embodiment of this technical solution, the formation of the replacement gate includes: first forming a replacement gate for the lower transistor, then etching back the metal gate layer of the lower transistor to the top of the lower gate, and depositing a dielectric layer in the groove formed by the etching back; then forming a replacement gate for the upper transistor, wherein the metal gate layer of the upper transistor and the metal gate layer of the lower transistor are isolated by a dielectric layer to form a split gate structure. By further etching back the dielectric layer, the gates of the upper and lower transistors are connected to form a common gate structure.

[0028] As a preferred embodiment of this technical solution, after the alternative gate is formed, a second insulating structure is formed above the lower fin stack retained by the second fin stack and above the lower fin stack retained by the first fin stack to disconnect the gate of the adjacent device.

[0029] Thirdly, the present invention also discloses an electronic device of the above-mentioned semiconductor device, the electronic device including a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device or power bank.

[0030] The semiconductor device of the present invention has at least the following beneficial effects: This invention achieves direct electrical isolation between adjacent devices by horizontally misaligning the upper and lower transistors of the first stacked unit, horizontally misaligning the upper and lower transistors of the second stacked unit, and horizontally misaligning the upper and lower transistors of the first and second stacked units. This invention eliminates the need for an additional SDB isolation structure to meet the electrical isolation requirements between adjacent devices, avoiding the additional layout area occupied by traditional SDB structures, such as RO circuits. Furthermore, isolation achieved through misalignment eliminates the need to etch deep isolation trenches between adjacent devices, simplifying the manufacturing process. Attached Figure Description

[0031] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a three-dimensional structural schematic diagram of the semiconductor device of the present invention; Figure 2 This is one of the top views of the semiconductor device of the present invention; Figure 3 This is a second top view of the semiconductor device of the present invention; Figure 4 This is a top view of the semiconductor device of the present invention (third view). Figure 5 This is a left view of the semiconductor device of the present invention; Figure 6 This is a right view of the semiconductor device of the present invention; Figure 7 This is another schematic diagram of the three-dimensional structure of the semiconductor device of the present invention; Figure 8This is another schematic diagram of the three-dimensional structure of the semiconductor device of the present invention; Figure 9 This is another schematic diagram of the three-dimensional structure of the semiconductor device of the present invention; Figure 10-22 This is a flowchart of the manufacturing method of the semiconductor device of the present invention; Figure 23 This is a comparison diagram of the layout area of ​​the semiconductor device of the present invention and the conventional CFET device.

[0033] Explanation of reference numerals in the attached figures: 100: First stacking unit; 101: First upper transistor; 102: First lower transistor; 103: First upper source / drain region; 104: First lower source / drain region; 105: First spacing; 106: First misalignment distance; 107: First plane; 108: Third plane; 109: First position; 200: Second stacking unit; 201: Second upper transistor; 202: Second lower transistor; 203: Second upper source / drain region; 204: Second lower source / drain region; 205: Second spacing; 206: Second misalignment distance; 207: Second plane; 208: Fourth plane; 209: Second position; 300: Substrate; 301: Channel layer; 302: Channel sacrificial layer; 303: Shallow trench isolation region; 304: Sacrificial layer; 305: Protective layer; 306: First insulating structure. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0035] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0036] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0038] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0039] In existing FinFET and CFET manufacturing processes, SDB structures are typically introduced to achieve electrical isolation between adjacent devices. SDBs achieve electrical isolation by forming shallow trench isolation (STI) between adjacent devices to cut off the active region. With the continuous advancement of technology nodes, SDBs have become an essential means of realizing high-density integrated circuits in advanced processes. However, the formation of SDB structures faces severe process challenges: SDBs require the formation of high aspect ratio isolation trenches within a very small space, placing stringent requirements on the alignment accuracy of the etching process; furthermore, SDB structures occupy a significant amount of space, increasing the layout area.

[0040] To address the aforementioned problems, this invention provides a semiconductor device and its manufacturing method. By horizontally separating stacked transistors, the electrical isolation requirements between adjacent devices can be met without the need for additional isolation structures such as SDBs, thereby significantly reducing the layout area and simplifying the process flow.

[0041] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0042] Firstly, such as Figure 1-9 As shown, an embodiment of the present invention provides a semiconductor device, including a substrate 300, and a first stacking unit 100 and a second stacking unit 200 stacked on the substrate 300 in a vertical direction.

[0043] The first stacking unit 100 includes a first upper transistor 101 and a first lower transistor 102, and the second stacking unit 200 includes a second upper transistor 201 and a second lower transistor 202. In any stacking unit, the upper transistor and the lower transistor are staggered in a direction parallel to the substrate 300 (i.e., their orthogonal projections on the substrate 300 do not overlap). Simultaneously, in any stacking unit, the upper transistor and the lower transistor are also staggered in a direction perpendicular to the substrate 300. In any stacking unit, the upper transistor and the lower transistor each include an upper nanowire / sheet stack and a lower nanowire / sheet stack extending along a first direction (the first direction being the channel length direction), and an upper gate extending along a second direction and surrounding the upper nanowire / sheet stack and a lower gate surrounding the lower nanowire / sheet stack (the second direction being the direction of gate extension). The second stacking unit 200 is disposed adjacent to the first stacking unit 100 along the first direction.

[0044] Here, "nanowire / sheet stacking" refers to a channel stacking structure composed of nanowires or nanosheets. For a nanosheet gate-around transistor, the channel layer 301 is nanosheet-shaped, with multiple nanosheets stacked vertically; for a nanowire gate-around transistor, the channel layer 301 is nanowire-shaped, with multiple nanowires stacked vertically. In embodiments of the present invention, the upper and lower nanowire / sheet stacks can have the same or different structures. For example, the upper nanowire / sheet stack can use a nanosheet structure, while the lower nanowire / sheet stack can use a nanowire structure, depending on the actual device performance requirements.

[0045] Figure 2-4 for Figure 1 A top view of a semiconductor device in the first direction. (e.g.) Figure 2As shown, the first upper nanowire / sheet stack of the first stacking unit 100 and the second lower nanowire / sheet stack of the second stacking unit 200 are located within a first plane 107 perpendicular to the substrate 300; the first lower nanowire / sheet stack of the first stacking unit 100 and the second upper nanowire / sheet stack of the second stacking unit 200 are located within a second plane 207 perpendicular to the substrate 300. That is, the upper channel of the first stacking unit 100 and the lower channel of the second stacking unit 200 are spatially coplanar, differing only in height, while the lower channel of the first stacking unit 100 and the upper channel of the second stacking unit 200 are spatially coplanar, differing only in height. This arrangement results in a staggered, cross-arrangement of the four channels in the two stacking units in the vertical direction. Because the upper and lower transistors in the first stacked cell 100 and the second stacked cell 200 are horizontally staggered, and the upper channel layer of the first stacked cell 100 and the lower channel layer of the second stacked cell 200 are located on the same plane but at different heights, and the lower channel layer of the first stacked cell 100 and the upper channel layer of the second stacked cell 200 are located on the same plane but at different heights, electrical isolation can be achieved between the first stacked cell 100 and the second stacked cell 200 without the need for an additional SDB structure. Compared to traditional CFETs, which require the introduction of an additional SDB structure between adjacent devices to achieve effective isolation, this invention achieves device isolation through the staggered separation structural feature itself, without requiring additional active area.

[0046] Figure 5-6 They are respectively Figure 1 The left and right views of the semiconductor device are provided by Figure 5-6 It is known that the upper and lower gates of the first stacking unit 100 are located within a third plane 108 perpendicular to the substrate 300; the upper and lower gates of the second stacking unit 200 are located within a fourth plane 208 perpendicular to the substrate 300. It should be noted that the third plane 108 and the fourth plane 208 are two parallel planes. Since the upper and lower transistors are misaligned in the direction parallel to the substrate 300 in any stacking unit, this means that the upper and lower gates of the first stacking unit 100 are horizontally misaligned (i.e., their orthogonal projections onto the substrate 300 are parallel), and the upper and lower gates of the second stacking unit 200 are also horizontally misaligned. However, the gates of the first stacking unit 100 and the gates of the second stacking unit 200 are horizontally misaligned, meaning there is a horizontal offset between the third plane 108 and the fourth plane 208. This gate layout, which involves "inter-group misalignment and inter-group misalignment," causes the nanowires / sheets of the two stacked units to be staggered in the first direction, and the source and drain regions are also staggered and separated, thereby achieving device isolation without the need for SDB.

[0047] Based on the above, this invention further describes the layout of the semiconductor device of the present invention, which is staggered within the group and staggered between groups, from the perspective of nanowire / wafer stacking.

[0048] Specifically, the orthographic projections of the upper nanowire / sheet stack of the first stacking unit 100 and the upper nanowire / sheet stack of the second stacking unit 200 onto the substrate 300 are parallel to each other; the orthographic projections of the lower nanowire / sheet stack of the first stacking unit 100 and the lower nanowire / sheet stack of the second stacking unit 200 onto the substrate 300 are parallel to each other. This means that the orthographic projections of channel stacks at the same height in the vertical direction (i.e., between two upper channel stacks and between two lower channel stacks) onto the substrate 300 are parallel to each other.

[0049] Based on this, the orthographic projections of the upper nanowire / sheet stack of the first stacking unit 100 and the lower nanowire / sheet stack of the first stacking unit 100 onto the substrate 300 are parallel to each other; the orthographic projections of the upper nanowire / sheet stack of the second stacking unit 200 and the lower nanowire / sheet stack of the second stacking unit 200 onto the substrate 300 are parallel to each other. That is to say, the orthographic projections of the upper and lower channels within the same stacking unit onto the substrate 300 are also parallel to each other.

[0050] Based on this, the orthographic projections of the upper nanowire / sheet stack of the first stacking unit 100 and the lower nanowire / sheet stack of the second stacking unit 200 onto the substrate 300 are aligned; the orthographic projections of the lower nanowire / sheet stack of the first stacking unit 100 and the upper nanowire / sheet stack of the second stacking unit 200 onto the substrate 300 are also aligned. Here, "alignment" means that in the first direction, the positions of the two orthographic projections are approximately the same, that is, their center lines in the horizontal direction are basically coincident. This arrangement ensures that the upper channel of the first stacking unit 100 and the lower channel of the second stacking unit 200 correspond one-to-one in the vertical direction, and the lower channel of the first stacking unit 100 and the upper channel of the second stacking unit 200 correspond one-to-one in the vertical direction, forming a spatially cross-symmetrical structure, which is beneficial for further reducing the layout area.

[0051] In this embodiment of the invention, "misalignment" means that the positions of two elements are offset from each other in the horizontal direction, that is, their orthogonal projections on the substrate 300 do not overlap; while "alignment" means that the positions of two elements are approximately the same in the horizontal direction, that is, their orthogonal projections on the substrate 300 overlap or substantially overlap.

[0052] Based on the above technical solution, in any stacked unit, the upper transistor and lower transistor of the present invention respectively include upper source-drain regions and lower source-drain regions disposed on both sides of the upper gate and the lower gate. That is, the first upper transistor 101 and the first lower transistor 102 respectively include a first upper source-drain region 103 and a first lower source-drain region 104 disposed on both sides of the first upper gate and the first lower gate, and the second upper transistor 201 and the second lower transistor 202 respectively include a second upper source-drain region 203 and a second lower source-drain region 204 disposed on both sides of the second upper gate and the second lower gate. The following further explains the layout of the semiconductor device of the present invention with intra-group and inter-group misalignment from the perspective of source-drain regions.

[0053] Specifically, the orthographic projections of the upper source / drain regions of the first stacked unit 100 and the upper source / drain regions of the second stacked unit 200 onto the substrate 300 are parallel to each other; the orthographic projections of the lower source / drain regions of the first stacked unit 100 and the lower source / drain regions of the second stacked unit 200 onto the substrate 300 are parallel to each other.

[0054] Based on this, the upper source / drain region of the first stacked unit 100 and the lower source / drain region of the first stacked unit 100 are parallel to each other on the substrate 300; the upper source / drain region of the second stacked unit 200 and the lower source / drain region of the second stacked unit 200 are parallel to each other on the substrate 300.

[0055] Based on this, the upper source / drain region of the first stacked cell 100 and the lower source / drain region of the second stacked cell 200 are aligned on the substrate 300 by their orthogonal projections; the lower source / drain region of the first stacked cell 100 and the upper source / drain region of the second stacked cell 200 are aligned on the substrate 300 by their orthogonal projections. Here, alignment refers to the alignment of the source / drain regions on their outer sides in the second direction.

[0056] Regarding the misalignment spacing between two adjacent devices, the present invention further describes it through the spacing between the ends of the source and drain regions.

[0057] Specifically, such as Figure 2-4 As shown, the end of the upper source / drain region of the first stacking unit 100 near the second stacking unit 200 is aligned with or has a first spacing of 105 to the end of the upper source / drain region of the second stacking unit 200 near the first stacking unit 100; the end of the lower source / drain region of the first stacking unit 100 near the second stacking unit 200 is aligned with or has a second spacing of 205 to the end of the lower source / drain region of the second stacking unit 200 near the first stacking unit 100; the first spacing 105 and the second spacing 205 may be equal or unequal.

[0058] It should be noted that the term "spacing" as used in this invention should be interpreted broadly. It includes not only the case where there is a physical gap in the horizontal direction between the ends of the two source / drain regions (i.e., a gap filled with dielectric material between them), but also the case where the ends of the two source / drain regions extend, intersect, or partially overlap each other in the horizontal direction. This broad interpretation of "spacing" can be positive (there is a physical gap between them), zero (the ends of the two regions are exactly aligned), or negative (they extend and intersect each other).

[0059] This "aligned or spaced" design allows for different spatial arrangements between the two stacked cells in the horizontal direction, depending on actual needs. These arrangements can be completely separated gaps or complementary, staggered arrangements. When staggered, the source and drain regions of the two stacked cells interlock horizontally, further improving layout area utilization. Simultaneously, since the staggered separation itself achieves electrical isolation between adjacent devices, the gap (or staggered) region between the two stacked cells does not need to be filled with high aspect ratio isolation trenches as in traditional SDB structures; conventional dielectric filling is sufficient to meet isolation requirements. By rationally designing the values ​​of the first spacing 105 and the second spacing 205 (e.g., making both less than a contact gate spacing CPP), the layout area can be compressed to the maximum extent while ensuring device isolation.

[0060] Regarding the misalignment spacing between upper and lower transistors within the same device, this invention illustrates it by describing the horizontal distance between the orthogonal projections of upper and lower nanowires / sheets stacked on the substrate 300.

[0061] Specifically, such as Figure 5-6 As shown, the horizontal distance between the orthographic projections of the upper nanowire / sheet stack and the lower nanowire / sheet stack of the first stacking unit 100 onto the substrate 300 is the first misalignment distance 106, and the horizontal distance between the orthographic projections of the upper nanowire / sheet stack and the lower nanowire / sheet stack of the second stacking unit 200 onto the substrate 300 is the second misalignment distance 206. The first misalignment distance 106 and the second misalignment distance 206 are equal. It should be noted that the first misalignment distance 106 and the second misalignment distance 206 can be equal or unequal. When they are equal, the degree of misalignment within the two stacking units is consistent, which is beneficial for forming a regular layout and simplifying process control.

[0062] In a preferred embodiment, the upper gate and lower gate of the first stacking unit 100 are continuously arranged in the vertical direction (i.e., forming a common gate structure); or, the upper gate and lower gate of the first stacking unit 100 are spaced apart in the vertical direction (i.e., forming a split gate structure). Similarly, the upper gate and lower gate of the second stacking unit 200 can be continuously arranged or spaced apart in the vertical direction. This feature allows the semiconductor device of the present invention to flexibly adapt to different circuit design requirements: in scenarios requiring common gate control, a continuously arranged common gate structure can be used to simplify interconnection; in scenarios requiring independent control of upper and lower transistors, a spaced split gate structure can be used to increase the flexibility of circuit design.

[0063] It is worth noting that even with a common gate structure, the common gate structure of the first stacking unit 100 and the common gate structure of the second stacking unit 200 are misaligned in the horizontal direction, and will not form a fully aligned traditional CFET common gate layout.

[0064] Based on the above technical solution, the present invention further includes insulating layers below the upper nanowire / sheet stack and above the lower nanowire / sheet stack. Below the upper nanowire / sheet stack, a first insulating structure is disposed within the insulating layer, the first insulating structure having the same width and length as the upper nanowire / sheet stack. Above the lower nanowire / sheet stack, a second insulating structure is disposed within the insulating layer, the width of the second insulating structure being the same as the gate length of the lower gate, and the length of the second insulating structure being less than or equal to the width of the lower gate.

[0065] The first insulating structure is essentially an isolation filling structure formed after removing redundant devices. Its dimensions in the horizontal direction are identical to those of the upper nanowire / sheet stack, serving to support the upper channel. The second insulating structure is formed after the gate is formed through a gate dicing process. Its width is the same as the gate length of the lower gate, and its length is less than or equal to the width of the lower gate. It is used to divide the continuously arranged gate structure into independent, separate gate structures. The materials of the first and second insulating structures can be the same or different; for example, a low-dielectric-constant dielectric material can be used to reduce parasitic capacitance.

[0066] It should also be noted that when using a "mutually extending and interleaved" source-drain region layout, the second insulation structure can be correspondingly disposed between the interleaved regions of adjacent source-drain regions to further ensure electrical isolation between devices. This design enables the technical solution of the present invention to maintain good isolation effect and process compatibility even with an interleaved source-drain region layout.

[0067] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention is the same as that of the semiconductor device provided in the first aspect. Therefore, the beneficial effects of the second aspect and its various implementations in the present invention can be analyzed with reference to the beneficial effects in the first aspect and its various implementations, and will not be repeated here.

[0068] The following will be based on Figures 10 to 22 The illustrated cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps: First, such as Figure 10 As shown, a substrate 300 is provided. The substrate 300 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or other semiconductor substrates. A first fin stack and a second fin stack arranged parallel and spaced apart in a horizontal direction are formed on the substrate 300. The first fin stack and the second fin stack are each formed by alternating stacks of a first semiconductor layer and a second semiconductor layer. The first semiconductor layer serves as a subsequent channel layer 301, and its material may include silicon (Si); the second semiconductor layer serves as a channel sacrificial layer 302, and its material may include silicon germanium (SiGe), wherein the germanium content can be any value between 10% and 60%.

[0069] The first and second fin stacks also include a sacrificial layer 304 in the middle, which divides the first and second fin stacks into upper and lower parts, respectively. The sacrificial layer 304 mainly serves as a pre-placement layer; subsequently, by removing the sacrificial layer 304 and depositing an isolation dielectric, an MDI isolation structure is formed between the upper and lower transistors. The material of the sacrificial layer 304 may include germanium silicon with a high germanium content (e.g., germanium content greater than 30%) to achieve high etch selectivity with adjacent semiconductor layers.

[0070] Specifically, when forming the first fin stack and the second fin stack, a lower channel layer 301 / channel sacrificial layer 302, a middle sacrificial layer 304, and an upper channel layer 301 / channel sacrificial layer 302 can be epitaxially grown sequentially on the substrate 300. Then, the fins are patterned using sidewall transfer technology to form at least two spaced fin structures. Furthermore, a shallow trench isolation region 303 (STI) for defining the active region is formed between two adjacent fin stack structures.

[0071] Next, as Figure 11 As shown, the upper part of the first fin stack and the second fin stack is etched. The upper part of the first fin stack retains a first position 109, and the upper part of the second fin stack retains a second position 209. The first position 109 and the second position 209 are located at positions that are staggered between each other in the first fin stack and the second fin stack, respectively.

[0072] Specifically, an etching mask layer can be formed over the first and second fin stacks, covering the first position 109 and the second position 209 while exposing the remaining area. Then, anisotropic etching is performed to remove the exposed upper fin stack portion. The offset distance between the first position 109 and the second position 209 determines the subsequent misalignment distance between the upper and lower transistors, that is, it determines the horizontal offset between the upper and lower nanowire / sheet stacks in the first stacking unit 100 and the second stacking unit 200.

[0073] Next, as Figure 12 As shown, a sacrificial gate and a sidewall are formed across the first position 109 and the second position 209, respectively. The first fin stack and the second fin stack are etched using the sacrificial gate and the sidewall as a mask. The portion of the first fin stack except for the fin stack below the first position 109 of the first fin stack is removed, as well as the portion of the second fin stack except for the fin stack below the second position 209 of the second fin stack, to form the corresponding nanowire / sheet stack.

[0074] Specifically, after forming the sacrificial gate and sidewalls, anisotropic etching is performed using them as a mask to remove the exposed fin stack (i.e., the portion not covered by the sacrificial gate and sidewalls). However, the fin stack below the first position 109 and the fin stack below the second position 209 must be retained to ultimately form a nanowire / sheet stack. At this point, the fin stack below the first position 109 and the fin stack below the second position 209 in the first fin stack are temporarily retained. After further etching, the first insulating structure 306 is filled in these areas.

[0075] Next, as Figure 12 As shown, the fin stack below the first position 109 of the first fin stack and the fin stack below the second position 209 of the second fin stack are removed. This step is a key process for achieving the separation of the upper and lower transistors.

[0076] Specifically, the sacrificial layer 304 in the middle of the first and second fin stacks is first removed. The removal of the sacrificial layer 304 can be performed using isotropic etching (such as wet etching or vapor phase etching), utilizing the high etching selectivity between the sacrificial layer 304 and adjacent semiconductor layers to precisely remove the sacrificial layer 304 without damaging the surrounding channel layer 301. After removing the sacrificial layer 304, a laterally extending cavity is formed in the middle. This cavity will subsequently be filled with an isolation dielectric to form an MDI isolation structure.

[0077] Then, as Figure 13As shown, after the formation of the corresponding nanowire / sheet stack, a protective layer 305 is formed on the surface of the entire device. The protective layer 305 needs to expose the ends and surfaces of the fin stack below the first position 109 in the first fin stack, and the ends and surfaces of the fin stack below the second position 209 in the second fin stack. The material of the protective layer 305 may include silicon nitride or silicon oxide, and it can be formed by deposition and anisotropic etching, so that the protective layer 305 covers the areas that do not need to be removed, while exposing the areas that need to be removed.

[0078] Furthermore, such as Figure 14 As shown, etching is performed on the fin stack below the first position 109 in the first fin stack and the fin stack below the second position 209 in the second fin stack, starting from the ends and surfaces. Since the ends and surfaces of the fin stacks below the first position 109 and the fin stacks below the second position 209 are exposed, while the remaining portions are covered by the protective layer 305, etching can begin from the ends and surfaces, gradually removing the exposed fin stack portions, thereby achieving precise removal of specific areas.

[0079] After the above etching is completed, the protective layer 305 is removed, and the second semiconductor layer (channel sacrificial layer 302) is etched inward to form an inner sidewall groove.

[0080] Finally, as Figure 15 As shown, an isolation medium is deposited in the inner wall groove, the cavity formed after removing the sacrificial layer 304, and the cavity formed after etching the fin stack below the first position 109 and the second position 209, simultaneously forming the inner wall, the MDI isolation structure, and the first insulating structure. The first insulating structure 306 fills the position of the removed fin stack, and is refilled after the protective layer 305 is subsequently removed. Therefore, in a cross-section parallel to the substrate direction, the length and width of the first insulating structure 306 are the same as the length and width of the nanowire / sheet stack of the above device.

[0081] The formation process of the inner sidewall includes: isotropic etching (such as wet etching) to create a lateral recess in the channel sacrificial layer 302 relative to the channel layer 301, forming a controllable lateral groove; then depositing the inner sidewall dielectric (such as silicon nitride or a low dielectric constant material) in the lateral groove and etching back to form the inner sidewall. The inner sidewall is mainly used to isolate the subsequently formed gate and source / drain regions to prevent leakage.

[0082] The MDI isolation structure is formed in the cavity created after removing the sacrificial layer 304, and its function is to form electrical isolation between the upper and lower transistors. The first insulating structure is formed in the cavity created after removing the fin stack below the first position 109 and the second position 209. Its width and length are the same as the upper nanowire / sheet stack, and it serves to support and isolate the upper channel.

[0083] Next, as Figure 16 As shown, source and drain regions are epitaxially formed on both sides of the corresponding nanowire / sheet stack.

[0084] Specifically, different source / drain epitaxial regions are defined using photolithographic masks, and source / drain semiconductor materials are grown at both ends of the nanowire / sheet stack. For N-type transistors, the source / drain region material can include phosphorus-doped silicon (Si:P); for P-type transistors, the source / drain region material can include boron-doped silicon germanium (SiGe:B). Epitaxial growth can be achieved using processes such as metal-organic chemical vapor deposition, molecular beam epitaxy, or vapor phase epitaxy.

[0085] Here, the method of defining different source and drain epitaxial regions using photolithographic masks to achieve source and drain region epitaxial growth can not only realize the layout of misalignment within and between groups as in this invention, but also realize the design of the upper and lower transistors having the same or different source and drain polarities.

[0086] The specific steps for forming the source / drain regions may include: defining different source / drain epitaxial regions using a photolithographic mask; employing a selective epitaxial process to simultaneously grow source / drain semiconductor materials at both ends of the exposed nanowire / wafer stack; after completing the epitaxial growth of the source / drain regions, depositing an interlayer dielectric layer on the device surface, filling the gaps between adjacent source / drain regions and the voids between the source / drain regions and the gate sidewalls, and covering the top of the source / drain regions to achieve electrical isolation between the device structures.

[0087] Next, as Figure 17 As shown, a gate trench is formed by removing the sacrificial gate and the second semiconductor layer (channel sacrificial layer 302), and a replacement gate is formed in the gate trench.

[0088] Specifically, by utilizing the etch selectivity between the sacrificial gate material and the surrounding material, the sacrificial gate is precisely removed without damaging the sidewalls and the channel layer 301; by utilizing the high etch selectivity between SiGe and Si, the channel layer 301 is released, providing space for subsequent metal gate filling.

[0089] After the gate trench is formed, a gate dielectric layer and a metal gate layer are sequentially formed on the surface of the released nanowire / sheet stack.

[0090] Next, as Figure 17-21 As shown, after forming the replacement gate, the metal gate layer of the lower transistor is etched back to the top of the lower gate, and then a dielectric layer is deposited in the groove formed by the etch-back. Further, a metal gate layer of the upper transistor is formed around and above the upper nanowire / sheet stack. Since the top of the lower gate is covered by the dielectric layer, the upper gate metal gate layer and the lower gate metal gate layer are physically separated by the dielectric layer in the vertical direction, forming electrical isolation between them, thereby realizing a separate gate structure where the upper and lower gates are separated from each other.

[0091] By further etching back the dielectric layer, the upper and lower gates can be connected to form a common-gate structure. Therefore, this invention can simultaneously implement both common-gate and split-gate structures on the same chip, meeting the needs of different circuit modules. Figure 22 The structure within the dashed box is the common-gate structure.

[0092] Furthermore, after forming the split-gate structure or the common-gate structure, a second insulating structure needs to be formed above the lower fin stack retained from the second fin stack and above the lower fin stack retained from the first fin stack to disconnect the gates of adjacent devices. Specifically, after forming the split-gate structure or the common-gate structure, the metal gate layers between different devices can be separated by photolithography, cutting, or other methods, and then the isolation dielectric material can be deposited and etched back to realize the second insulating structure. Alternatively, the second insulating structure can be formed by implanting oxygen into the metal gate layer to achieve isolation between adjacent devices. The width of the second insulating structure is the same as the gate length of the lower gate, and the length is less than or equal to the width of the lower gate, used to isolate the gates of adjacent devices from each other. The sidewalls of the second insulating structure are gate sidewalls, and outside the gate sidewalls is the aforementioned other dielectric layer.

[0093] Figure 23 This is a comparison diagram of the layout area of ​​the semiconductor device of this invention and the conventional CFET device. Figure 23 As can be seen, the present invention does not require the introduction of structures such as SDB to achieve isolation between devices, and significantly reduces the layout area compared with traditional CFET devices, such as RO circuits.

[0094] The manufacturing method provided by this invention is based on mature processes such as fin stacking, replacement metal gate (RMG), and sidewall transfer, and is highly compatible with mainstream CMOS manufacturing processes. Specifically, the method of this invention retains mutually offset first positions 109 and second positions 209 on the upper part of the first and second fin stacks, and selectively etches away redundant parts of the lower fin stack using sacrificial gates and sidewalls as masks. Combined with the protection layer 305 for the protection and selective etching of non-target areas, the method efficiently achieves the misalignment separation of the upper and lower transistors.

[0095] Thirdly, embodiments of the present invention provide an electronic device, which includes a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank. The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0096] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Including substrate; The first stacking unit and the second stacking unit are respectively stacked on the substrate in a vertical direction; The first stacking unit and the second stacking unit each include an upper transistor and a lower transistor, and the upper transistor and the lower transistor are staggered in a direction parallel to the substrate; The upper transistor and the lower transistor respectively include an upper nanowire / sheet stack and a lower nanowire / sheet stack extending along a first direction, an upper gate extending along a second direction and surrounding the upper nanowire / sheet stack, and a lower gate surrounding the lower nanowire / sheet stack. The second stacking unit is disposed adjacent to the first stacking unit along the first direction.

2. The semiconductor device according to claim 1, characterized in that, The upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the second stacking unit are located in a first plane perpendicular to the substrate; The lower nanowire / sheet stack of the first stacking unit and the upper nanowire / sheet stack of the second stacking unit are located in a second plane perpendicular to the substrate.

3. The semiconductor device according to claim 1, characterized in that, The upper gate and lower gate of the first stacked cell are located in a third plane perpendicular to the substrate; The upper and lower gates of the second stacked cell are located in a fourth plane perpendicular to the substrate.

4. The semiconductor device according to claim 1, characterized in that, The upper nanowire / sheet stack of the first stacking unit and the upper nanowire / sheet stack of the second stacking unit are parallel to each other on the substrate; The lower nanowire / sheet stack of the first stacking unit and the orthographic projection of the lower nanowire / sheet stack of the second stacking unit onto the substrate are parallel to each other.

5. The semiconductor device according to claim 1, characterized in that, The upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the first stacking unit are parallel to each other on the substrate. The upper nanowire / sheet stack of the second stacking unit and the lower nanowire / sheet stack of the second stacking unit are parallel to each other on the substrate.

6. The semiconductor device according to claim 1, characterized in that, The upper nanowire / sheet stack of the first stacking unit is aligned with the orthographic projection of the lower nanowire / sheet stack of the second stacking unit onto the substrate; The lower nanowire / sheet stack of the first stacking unit is aligned with the orthographic projection of the upper nanowire / sheet stack of the second stacking unit onto the substrate.

7. The semiconductor device according to claim 1, characterized in that, The upper transistor and the lower transistor respectively include an upper source-drain region and a lower source-drain region disposed on both sides of the upper gate and the lower gate; The end of the upper source drain region of the first stacking unit near the side of the second stacking unit is aligned with or has a first gap from the end of the upper source drain region of the second stacking unit near the side of the first stacking unit.

8. The semiconductor device according to claim 7, characterized in that, The end of the lower source / drain region of the first stacking unit near the side of the second stacking unit is aligned with or has a second spacing from the end of the lower source / drain region of the second stacking unit near the side of the first stacking unit.

9. The semiconductor device according to claim 7 or 8, characterized in that, The first spacing may be equal to or different from the second spacing.

10. The semiconductor device according to claim 1, characterized in that, The horizontal distance between the orthographic projections of the upper nanowire / sheet stack of the first stacking unit and the lower nanowire / sheet stack of the first stacking unit onto the substrate is the first misalignment distance. The horizontal distance between the orthographic projections of the upper nanowire / sheet stack of the second stacking unit and the lower nanowire / sheet stack of the second stacking unit onto the substrate is the second misalignment distance. The first misalignment distance is equal to the second misalignment distance.

11. The semiconductor device according to claim 1, characterized in that, The upper gate and the lower gate of the first stacked unit are either continuously or spaced apart in the vertical direction. And / or, the upper gate of the second stacked unit and the lower gate of the second stacked unit are arranged continuously or spaced apart in the vertical direction.

12. The semiconductor device according to claim 1, characterized in that, An insulating layer is included below the upper nanowire / sheet stack and above the lower nanowire / sheet stack, and a first insulating structure is included below the upper nanowire / sheet stack, the first insulating structure having the same width and length as the upper nanowire / sheet stack.

13. The semiconductor device according to claim 12, characterized in that, Above the lower nanowire / sheet stack, there is a second insulating structure placed on the insulating layer, the width of the second insulating structure being the same as the gate length of the lower gate, and the length of the second insulating structure being less than or equal to the width of the lower gate.

14. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: Provide substrate; A first fin stack and a second fin stack are formed on a substrate in a horizontally parallel and spaced manner. The first fin stack and the second fin stack are each formed by alternating stacking of a first semiconductor layer and a second semiconductor layer. The middle part of the first fin stack and the second fin stack also includes a sacrificial layer, which divides the first fin stack and the second fin stack into an upper part and a lower part, respectively. The upper part of the first fin stack and the second fin stack is etched, wherein the upper part of the first fin stack retains a first position and the upper part of the second fin stack retains a second position, and the first position and the second position are respectively located at positions that are staggered from each other in the first fin stack and the second fin stack. A sacrificial gate and a sidewall are formed across the first and second positions, respectively. The first fin stack and the second fin stack are etched using the sacrificial gate and the sidewall as a mask to remove the portion of the first fin stack except for the fin stack below the first position of the first fin stack, and the portion of the second fin stack except for the fin stack below the second position of the second fin stack, to form the corresponding nanowire / sheet stack. Remove the fin stack below the first position of the first fin stack and the fin stack below the second position of the second fin stack; Source and drain regions are epitaxially formed on both sides of the corresponding nanowire / sheet stack; The sacrificial gate and the second semiconductor layer are removed to form a gate trench, and a replacement gate is formed in the gate trench.

15. The manufacturing method according to claim 14, characterized in that, The removal of the fin stack below the first position of the first fin stack and the fin stack below the second position of the second fin stack includes: After the corresponding nanowire / sheet stack is formed, a protective layer is formed on the surface of the entire device, and the protective layer needs to expose the ends and surfaces of the fin stack below the first position in the first fin stack and the ends and surfaces of the fin stack below the second position in the second fin stack. Etching is performed on the fin stack below the first position in the first fin stack and the fin stack below the second position in the second fin stack, starting from the end and the surface.

16. The manufacturing method according to claim 15, characterized in that, Before removing the fin stack below the first position of the first fin stack and the fin stack below the second position of the second fin stack, the method further includes: removing the sacrificial layer in the middle of the first fin stack and the second fin stack.

17. The manufacturing method according to claim 15, characterized in that, After etching the fin stack below the first position in the first fin stack and the fin stack below the second position in the second fin stack starting from the end and the surface, the method further includes: removing the protective layer and etching the second semiconductor layer inward to form an inner sidewall groove; depositing an isolation medium in the inner sidewall groove, the cavity formed after removing the sacrificial layer, and the cavity formed after etching the fin stacks below the first and second positions, thereby forming an inner sidewall, an isolation layer, and a first insulating structure.

18. The manufacturing method according to claim 15, characterized in that, The process of forming the alternative gate includes: first forming an alternative gate for the lower transistor, then etching back the metal gate layer of the lower transistor to the top of the lower gate, and depositing a dielectric layer in the groove formed by the etching back; then forming an alternative gate for the upper transistor, wherein the metal gate layer of the upper transistor and the metal gate layer of the lower transistor are isolated by a dielectric layer to form a split gate structure. By further etching back the dielectric layer, the gates of the upper and lower transistors are connected to form a common gate structure.

19. The manufacturing method according to claim 15, characterized in that, After the alternative gate is formed, a second insulating structure is formed above the lower fin stack retained by the second fin stack and above the lower fin stack retained by the first fin stack to disconnect the gate of the adjacent device.

20. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1 to 13; Electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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