Silicon-germanium alloy-based avalanche photodiode, preparation method and array detector

Abstract

The application discloses an avalanche photodiode based on a silicon germanium alloy, a preparation method and an array detector. The method comprises the following steps: obtaining a substrate layer; epitaxially growing a first i-Si layer on the substrate layer; performing P-type doping on the first i-Si layer to form a P-Si charge layer and an i-Si multiplication layer; epitaxially growing a second i-Si layer on the P-Si charge layer; performing selective injection on the second i-Si layer to form a P+ shielding layer; epitaxially growing an i-Si buffer layer and an i-SiGe layer on the P+ shielding layer; performing P-type doping on the i-SiGe layer to form a P++ SiGe alloy contact layer and an i-SiGe light absorption layer; forming an electrode to obtain the APD based on the silicon germanium alloy. The application takes advantage of the characteristics that the SiGe alloy has a high absorption coefficient in the near-infrared waveband, realizes efficient detection of wavelengths such as 1064 nm, and makes up for the defects that the existing APD has insufficient detection efficiency in the long waveband.

Description

Technical Field

[0001] This invention belongs to the field of silicon-based photodetector technology, specifically relating to an avalanche photodiode based on silicon-germanium alloy, its fabrication method, and an array detector. Background Technology

[0002] With the rapid development of technologies such as LiDAR, quantum communication, and fiber optic sensing, the demand for high-performance, low-cost, and easily integrated near-infrared detectors is becoming increasingly urgent. Among numerous detection technologies, avalanche photodiodes (APDs) have become a core solution for solid-state detectors due to their high gain, fast response, and compatibility with semiconductor processes.

[0003] Currently, the mainstream APDs mainly include silicon APDs (Si-APD), indium gallium arsenide APDs (InGaAs-APD), and germanium-on-silicon APDs (Ge-APD). Among them, silicon APDs have limitations in their absorption spectrum due to the large bandgap of silicon, making efficient detection of wavelengths above 1000nm and below 400nm impossible. Furthermore, silicon APDs typically require bias voltages of hundreds of volts (e.g., 80-200V) to operate, far exceeding those of ordinary photodiodes. Indium gallium arsenide APDs have a material system incompatible with mainstream silicon-based CMOS processes, leading to difficulties in heterogeneous integration, high costs, and low yields, hindering large-scale production and application. Germanium-on-silicon APDs can utilize mature silicon manufacturing processes to integrate the detection function and signal processing circuitry on a single chip, significantly reducing system cost and size. However, a significant lattice mismatch exists between pure Ge and Si, resulting in numerous defects at the interface and increased dark current.

[0004] Pan Dong et al. published a discussion on the progress of germanium-silicon APD detectors in *Micro-Nano Electronics & Intelligent Manufacturing*, 2019, 1(03):68-74, including research on 10 GHz and 25 GHz Ge / Si APD detectors. (See [link to article]). Figure 1 The APD detector comprises, in order of stacking from bottom to top, a substrate, an N+ contact layer, a Si multiplication layer, a Si charge layer, a Ge absorber layer, a P+ contact layer, and an anti-reflection layer. The 10G Ge / Si APD achieves a room-temperature sensitivity of -29.5 dBm at 1310 nm wavelength; the 25G device exhibits a breakdown voltage temperature coefficient of only 0.055% / ℃, demonstrating insensitivity to temperature and simplifying the adjustment of the optical module's bias voltage. However, because this research uses a silicon-germanium alloy as the anode, and the absorber layer material is still silicon, the following limitations exist. Firstly, due to the low absorption coefficient of silicon at 1064 nm, the APD's sensitivity is relatively low, requiring higher optical power to obtain a sufficient signal. Secondly, as the gain increases, the avalanche duration also increases, which can affect the device's high-speed performance.

[0005] Liao Yaxiang et al. disclosed the design and simulation analysis of SiGe / Si single-photon avalanche photodiodes in Infrared and Laser Engineering, 2016, 45(05):94-97. (See [link to article]). Figure 2 The proposed APD employs a SACM (Separate Absorption and Charge Multiplication) structure, using Si as the multiplication region and SiGe multi-quantum wells as the absorption region. This design is compatible with silicon processes and improves detection performance at a wavelength of 1.064 micrometers. At 1.064 micrometers, the SiGe detector achieves a quantum efficiency of 4.2%, a four-fold improvement over the Si detector. However, compared to traditional silicon avalanche photodiodes, the SiGe / Si multi-quantum wells structure in this design is more complex, requiring epitaxial growth of the SiGe multi-quantum wells, which increases manufacturing difficulty and cost. Furthermore, the presence of defects and recombination centers in the silicon-germanium multi-quantum wells can lead to increased dark current, limiting device performance.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides an avalanche photodiode based on silicon-germanium alloy, its fabrication method, and an array detector. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating an avalanche photodiode based on a silicon-germanium alloy, comprising the following steps: S1. Obtain the substrate layer; S2. N-type doping is performed on a preset electrode region on one side of the substrate to form an N++ region; a first i-Si layer is epitaxially grown in the non-N++ region of the substrate. S3. P-type doping is performed on the side of the first i-Si layer away from the substrate layer to form a P-Si charge layer on the side of the first i-Si layer away from the substrate layer, and an i-Si multiplication layer is formed on the undoped side of the first i-Si layer close to the substrate layer. S4. Epitaxially grow a second i-Si layer on the side of the P-Si charge layer away from the substrate layer; S5. Selective injection is performed on the second i-Si layer using a circular template to form an annular P+ shielding layer; the P+ shielding layer includes an i-Si region located at the center and a shielding ring surrounding the i-Si region; S6. An i-Si buffer layer is epitaxially grown above the shielding ring and the i-Si region; S7. An i-SiGe layer is epitaxially grown on the side of the i-Si buffer layer away from the substrate layer; S8. P-type doping is performed on the side of the i-SiGe layer away from the substrate layer, and a P++SiGe alloy contact layer is formed on the side of the i-SiGe layer away from the substrate layer. An undoped layer on the side of the i-SiGe layer close to the substrate layer is formed as an i-SiGe light absorption layer. S9. An electrode is formed above the P++SiGe alloy contact layer and in the preset electrode region of the substrate layer to obtain an avalanche photodiode based on silicon-germanium alloy.

[0008] In one embodiment of the present invention, step S1, obtaining the substrate layer includes: Obtain an SOI substrate; the SOI substrate comprises a bottom silicon layer, an intermediate insulating layer, and a top silicon layer stacked sequentially from bottom to top; The top silicon layer is N-type doped with a doping concentration of 1×10⁻⁶. 19 ~1.2×10 19 cm –3 ; The bottom silicon layer and the intermediate insulating layer were removed by chemical mechanical polishing to obtain an N-type Si substrate as the substrate layer; the thickness of the substrate layer was 280 nm to 350 nm.

[0009] In one embodiment of the present invention, in step S2, the N-type doping concentration of the preset electrode region on one side of the substrate layer is 1×10⁻⁶. 19 ~1.2×10 19 cm –3 .

[0010] In one embodiment of the present invention, in step S3, the thickness of the i-Si multiplication layer is 350 nm to 400 nm; the doping concentration of the P-Si charge layer is 1 × 10⁻⁶. 17 ~1.2×10 17 cm –3 The thickness of the P-Si charge layer is 100 nm to 140 nm.

[0011] In one embodiment of the present invention, in step S5, the thickness of the P+ shielding layer is 100 nm to 120 nm, and the doping concentration is 0.8 × 10⁻⁶. 18 ~1.2×10 18 cm –3 .

[0012] In one embodiment of the present invention, in step S6, the thickness of the i-Si buffer layer is 100 nm to 120 nm.

[0013] In one embodiment of the present invention, in step S8, the thickness of the i-SiGe light-absorbing layer is 350 nm to 400 nm; The doping concentration of the P++SiGe alloy contact layer is 1×10⁻⁶. 19 ~1.2×10 19 cm –3 The thickness is 120nm to 160nm.

[0014] In a second aspect, the present invention provides an avalanche photodiode based on silicon-germanium alloy, comprising a substrate layer, an i-Si multiplication layer, a P-Si charge layer, a P+ shielding layer, an i-Si buffer layer, an i-SiGe light absorption layer, and a P++SiGe alloy contact layer stacked sequentially. The P+ shielding layer includes a P++Si shielding ring on the outer side and an i-Si region inside the P++Si shielding ring. The i-Si buffer layer is located above the P++Si shielding ring and the i-Si region.

[0015] In one embodiment of the present invention, in the i-SiGe light-absorbing layer and the P++SiGe alloy contact layer, the general formula of the SiGe alloy is Si. 1-x Ge x , where x is 0.2 to 0.75.

[0016] Secondly, the present invention provides an array detector based on silicon-germanium alloy, comprising the aforementioned avalanche photodiodes based on silicon-germanium alloy arranged in an array.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The avalanche photodiode based on silicon-germanium alloy provided by this invention uses an i-SiGe light-absorbing layer as the light-absorbing region. Utilizing the high absorption coefficient of SiGe alloy in the near-infrared band, it can achieve efficient detection at wavelengths such as 1064nm, overcoming the shortcomings of existing silicon-based APDs in terms of insufficient detection efficiency at longer wavelengths. A P+ shielding layer surrounding the i-Si region effectively suppresses edge electric field concentration effects, reduces edge leakage current, and improves the uniformity of the device's breakdown voltage. An i-Si buffer layer is placed between the P+ shielding layer and the i-SiGe light-absorbing layer, which reduces the dislocation density in the SiGe epitaxial layer, lowers dark current, and improves the overall performance of the device.

[0018] 2. The preparation method provided by this invention forms a P+ shielding layer through selective injection using a circular template, eliminating the need for additional photolithography and etching steps and simplifying the process flow. Through multiple epitaxial growth processes, an i-Si multiplication layer, a P-Si charge layer, a second i-Si layer, an i-Si buffer layer, and an i-SiGe layer are formed, with clear interfaces between each layer, allowing for precise control of doping concentration and thickness.

[0019] 3. The array detector provided by this invention includes multiple avalanche photodiodes arranged in an array. Each avalanche photodiode is independent of the others and can simultaneously respond to light signals from different positions, thus realizing the area array detection function. Each avalanche photodiode in the array detector uses the same fabrication process, resulting in good process compatibility and facilitating large-scale mass production.

[0020] 4. This invention uses Si material to fabricate the multiplication region. Si material has a high breakdown field strength and a low tunneling probability, enabling high avalanche gain at a low bias voltage and reducing device power consumption. Compared with SiGe multi-quantum-well structures, this invention uses a single-layer i-SiGe as the light-absorbing layer, resulting in a simpler structure, reduced epitaxial growth difficulty, and lower fabrication costs. It also avoids the increased dark current caused by defects and recombination centers that may exist in multi-quantum-well structures.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0022] Figure 1 This is a cross-sectional schematic diagram of the Ge-on-Si APD structure in related technologies; Figure 2 This is a schematic diagram of a Geiger-mode avalanche photodiode with a CMOS process-compatible guard ring structure in related technologies. Figure 3 This is a schematic cross-sectional view of an avalanche photodiode based on silicon-germanium alloy provided in an embodiment of the present invention. Figure 4 This is a top-view scanning electron microscope image of the avalanche photodiode based on silicon-germanium alloy provided in Embodiment 1 of the present invention; Figure 5 This is a cross-sectional scanning electron microscope image of the avalanche photodiode based on silicon-germanium alloy provided in Embodiment 1 of the present invention; Figure 6 This is a comparison chart of the performance results of avalanche photodiodes prepared in Embodiment 1, Embodiment 2 and the comparative example of the present invention; Figure 7 This is a schematic diagram of the microstructure of an array detector provided in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the simulation performance results of an array detector provided in an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures: 100 - Avalanche photodiode; 1 - Substrate layer; 2 - i-Si multiplication layer; 3 - P-Si charge layer; 4 - P+ shielding layer; 5 - i-Si buffer layer; 6 - i-SiGe light absorption layer; 7 - P++SiGe alloy contact layer; 8 - Electrode. Detailed Implementation

[0024] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of an avalanche photodiode based on silicon-germanium alloy, its preparation method, and an array detector proposed according to the present invention.

[0025] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0026] It should be noted that, in this document, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed.

[0027] This invention provides an avalanche photodiode based on a silicon-germanium alloy, such as... Figure 3As shown, the avalanche photodiode 100 includes a substrate layer 1, an i-Si multiplication layer 2, a P-Si charge layer 3, a P+ shielding layer 4, an i-Si buffer layer 5, an i-SiGe light-absorbing layer 6, and a P++SiGe alloy contact layer 7, which are stacked sequentially. The P+ shielding layer 4 includes an outer P++Si shielding ring and an i-Si region inside the P++Si shielding ring; the i-Si buffer layer 5 is located above the P++Si shielding ring and the i-Si region. In this APD, the i-SiGe light-absorbing layer 6 and the P++SiGe alloy contact layer 7 are made of SiGe alloy. The SiGe alloy contacts the i-Si buffer layer 5 to minimize dislocations and further reduce dark current. Incident light enters from the top, generating photogenerated carriers in the i-SiGe light-absorbing layer 6. Subsequently, under the action of an electric field, the photogenerated carriers enter the i-Si multiplication layer 2 for avalanche multiplication. The P-Si charge layer 3 acts as a charge layer, optimizing and adjusting the electric field to make the electric field of the i-SiGe light absorption layer 6 smaller and the electric field of the i-Si multiplication layer 2 larger. The P+ shielding layer 4, as a ring-shaped shielding layer, can prevent edge breakdown.

[0028] In some examples, in the i-SiGe light-absorbing layer 6 and the P++SiGe alloy contact layer 7, the general formula of the SiGe alloy is Si. 1-x Ge x , where x is 0.2 to 0.75.

[0029] This invention also provides a method for fabricating an avalanche photodiode based on a silicon-germanium alloy, comprising the following steps: S1. Obtain substrate layer 1. Specifically, this includes: S11. Obtain the SOI substrate; the SOI substrate comprises a bottom silicon layer, an intermediate insulating layer, and a top silicon layer stacked sequentially from bottom to top. The intermediate insulating layer is typically a silicon dioxide layer.

[0030] S12. Perform N-type doping on the top silicon layer, with a doping concentration of 1×10¹⁹~1.2×10¹⁹cm⁻³. N-type doping can use elements such as phosphorus or arsenic as doping sources, and can be achieved through ion implantation or diffusion processes.

[0031] S13. The bottom silicon layer and intermediate insulating layer are removed using chemical mechanical polishing (CMP) to obtain an N-type Si substrate as substrate layer 1. CMP is a commonly used wafer thinning technique that combines abrasive particles in the polishing slurry with chemical action to precisely control the removal thickness. After removing the bottom silicon layer and intermediate insulating layer, the remaining layer is the N-type doped top silicon layer, which serves as the substrate layer for subsequent epitaxial growth. The thickness of substrate layer 1 is 280 nm to 350 nm, specifically 300 nm, 320 nm, or 340 nm.

[0032] S2. N-type doping is performed on a preset electrode region on one side of substrate layer 1 to form an N++ region; the first i-Si layer is epitaxially grown in the non-N++ region of substrate layer 1.

[0033] This step involves two operations. First, N-type doping is achieved in the preset electrode region using an ion implantation process, with a doping concentration of 1 × 10⁻⁶. 19 ~1.2×10 19 cm –3 This can be achieved through ion implantation. Next, a first i-Si layer is epitaxially grown in the non-N++ region of substrate layer 1. Epitaxial growth can be achieved using techniques such as molecular beam epitaxy (MBE), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The epitaxial growth conditions need to be precisely controlled to obtain a high-quality single-crystal silicon layer. The thickness of the first i-Si layer needs to be sufficiently large to accommodate the subsequently formed i-Si multiplication layer 2 and P-Si charge layer 3.

[0034] S3. P-type doping is performed on the side of the first i-Si layer away from the substrate layer 1 to form a P-Si charge layer 3 on the side of the first i-Si layer away from the substrate layer 1, and the undoped layer on the side of the first i-Si layer close to the substrate layer 1 forms an i-Si multiplication layer 2.

[0035] The concentration and depth of p-type doping need to be precisely controlled to form the desired concentration of the p-Si charge layer 3. The doping concentration of the p-Si charge layer 3 is 1 × 10⁻⁶. 17 ~1.2×10 17 cm –3 The thickness is 100nm to 140nm. On the side of the first i-Si layer closest to the substrate layer 1, an intrinsic i-Si multiplication layer 2 is formed due to the lack of doping. The thickness of the i-Si multiplication layer 2 is the total thickness of the first i-Si layer minus the thickness of the P-Si charge layer 3, ranging from 350nm to 400nm. It should be noted that the P-type doping in step S3 can be achieved through ion implantation. The energy and dose of the ion implantation need to be optimized according to the required doping concentration and depth.

[0036] S4. Epitaxially grow a second i-Si layer on the side of the P-Si charge layer 3 away from the substrate layer 1.

[0037] S5. Selective injection is performed on the second i-Si layer using a circular template to form an annular P+ shielding layer 4; the P+ shielding layer 4 includes an i-Si region located at the center and a shielding ring surrounding the i-Si region.

[0038] Specifically, a circular template can be placed over the surface of the second i-Si layer, followed by high-concentration P-type ion implantation. Boron can be used as the dopant source for P-type doping, with a doping concentration of 0.8 × 10⁻⁶. 18 ~1.2×1018 cm –3 The thickness is 100 nm to 120 nm. After ion implantation, the circular template is removed, and annealing is performed under appropriate conditions to form a P++Si shielding ring. The region surrounded by the P++Si shielding ring is not implanted and remains intrinsic Si material, i.e., the i-Si region.

[0039] S6. An i-Si buffer layer 5 is epitaxially grown above the shielding ring and the i-Si region; the i-Si buffer layer 5 is an undoped intrinsic silicon layer with a thickness of 100 nm to 120 nm.

[0040] S7. An i-SiGe layer is epitaxially grown on the side of the i-Si buffer layer 5 away from the substrate layer 1. The i-SiGe layer is epitaxially grown using a mixed source of Si and Ge, for example, by chemical vapor deposition (CVD). The general formula of the SiGe alloy in the i-SiGe layer is Si. 1-x Ge x , where x is 0.2 to 0.75.

[0041] S8. Perform P-type doping on the side of the i-SiGe layer away from the substrate layer 1, forming a P++SiGe alloy contact layer 7 on this side. Boron can be used as the dopant source for the P-type doping, with a doping concentration of 1×10⁻⁶. 19 ~1.2×10 19 cm –3 The thickness is 120nm to 160nm.

[0042] On the side of the i-SiGe layer near the substrate layer 1, since no doping is performed, an intrinsic i-SiGe light-absorbing layer 6 is formed; the thickness of the i-SiGe light-absorbing layer 6 is 350 nm to 400 nm.

[0043] S9. An electrode 8 is formed above the P++SiGe alloy contact layer 7 and in the preset electrode region of the substrate layer 1 to obtain an avalanche photodiode based on silicon-germanium alloy.

[0044] Electrode 8 can be formed using metal evaporation or metal sputtering processes, followed by patterning through photolithography and etching to form the desired electrode pattern. For example, the material of the metal electrode can be a Ti / Au layered structure.

[0045] This invention also provides an array detector based on silicon-germanium alloy, comprising an array of multiple silicon-germanium alloy-based avalanche photodiodes 100 arranged in an array. The structure of each avalanche photodiode 100 is the same as in the aforementioned embodiments, and each avalanche photodiode 100 includes a substrate layer 1, an i-Si multiplication layer 2, a P-Si charge layer 3, a P+ shielding layer 4, an i-Si buffer layer 5, an i-SiGe light absorption layer 6, and a P++SiGe alloy contact layer 7, which are sequentially stacked.

[0046] In the array detector, each avalanche photodiode 100 is independent of the others, and each avalanche photodiode 100 can work independently, responding to the light signal at its corresponding position. When incident light shines on the surface of the array detector, the light signal is received by each avalanche photodiode 100, and after avalanche multiplication, it is converted into an electrical signal output, thereby realizing the area array detection function.

[0047] The avalanche photodiode based on silicon-germanium alloy provided by the present invention will be further described below with reference to specific embodiments.

[0048] Example 1 (1) SOI substrate pretreatment An SOI substrate was used, and the top silicon layer was N-type doped by ion implantation to a doping concentration of 1.2 × 10⁻⁶. 19 cm –3 An N-type low-resistivity Si substrate with a thickness of 300 nm was obtained by removing the bottom silicon layer and the intermediate insulating layer (SiO2) using chemical mechanical polishing (CMP). This substrate was used as substrate layer 1.

[0049] (2) Preparation of N++ regions N-type heavy doping was performed on a predetermined region on one side of substrate layer 1 via ion implantation to form an N++ region with a doping concentration of 1.2 × 10⁻⁶. 19 cm –3 This serves as the basis for subsequent electrode fabrication.

[0050] (3) Epitaxial growth of intrinsic Si layer An intrinsic Si layer with a thickness of 400 nm is grown on the non-N++ region on one side of the substrate layer 1 using epitaxial growth technology, serving as the first intrinsic silicon layer (first i-Si layer).

[0051] (4) Preparation of charge layer P-type doping was performed above the first i-Si layer via ion implantation to form a thin, highly doped P-Si charge layer 3 with a thickness of 120 nm and a doping concentration of 1 × 10⁻⁶. 17 cm –3 The undoped portion of the first i-Si layer forms i-Si multiplication layer 2, with a thickness of 400 nm.

[0052] (5) Growth of p++Si shielding ring Above the P-Si charge layer 3, a circular template is used for selected area ion implantation to form a p++Si shielding ring. The doping concentration is higher than that of the P-Si charge layer 3, at 1×10⁻⁶. 18 cm –3 The thickness of the p++Si shielding ring is 100 nm.

[0053] (6) Growth of i-Si buffer layer 5 An i-Si buffer layer 5 with a thickness of 120 nm is epitaxially grown above the p++Si shielding ring, serving as a buffer transition layer between the SiGe and Si materials.

[0054] (7) Growth of i-SiGe alloy layer An intrinsic SiGe alloy layer is epitaxially grown above the i-Si buffer layer 5, serving as the i-SiGe layer. In the i-SiGe layer, the SiGe alloy composition is Si. 0.65 Ge 0.35 .

[0055] (8) Preparation of P++SiGe alloy contact layer 7 P-type heavy doping was performed on the i-SiGe layer via ion implantation to form a P++SiGe alloy contact layer 7 with a thickness of 150 nm and a doping concentration of 1×10⁻⁶. 19 cm –3 An i-SiGe light-absorbing layer 6 with a thickness of 350 nm is formed in the undoped portion of the i-SiGe layer.

[0056] (9) Photolithography and hard mask etching A SiO2 hard mask layer is formed on the surface of the device prepared in step (8). This SiO2 hard mask layer completely covers the upper surface of the device. Photoresist is coated on the surface of the P++SiGe contact layer, and a mesa region with a diameter of 25 μm is defined by photolithography.

[0057] The hard mask layer (such as SiO2) was etched using reactive ion etching (RIE) technology. The etching gas was SF6, the passivation gas was C4F8, the etching depth was 1000 nm, the etching power was 200 W, and the cavity pressure was 20 mTorr.

[0058] (10) SiO2 growth A 200 nm thick SiO2 layer was grown on the etched surface of the structure as a passivation protective layer.

[0059] (11) Etching and Metallization The SiO2 layer in the mesa region was removed by photolithography and etching to expose the P++SiGe contact layer. A Ti / Au metal electrode was deposited using electron beam evaporation, followed by a lift-off process to remove excess metal electrodes and form ohmic contacts, thus completing the device fabrication.

[0060] The avalanche photodiode based on silicon-germanium alloy prepared in Example 1 is defined as Si 0.65 Ge 0.35 APD.

[0061] Example 2 The difference between this embodiment and Embodiment 1 is that in the i-SiGe layer formed in step (7), the SiGe alloy composition is Si. 0.25 Ge 0.75 .

[0062] The remaining operations are the same as in Example 1. The avalanche photodiode based on silicon-germanium alloy prepared in Example 2 is defined as Si 0.25 Ge 0.75 APD.

[0063] Comparative Example The difference between the comparative example and Example 1 is that the i-Ge layer is formed in step (7), and the i-Ge light absorption layer and P++Ge alloy contact layer are formed in step (8).

[0064] The remaining operations are the same as in Example 1, and the avalanche photodiode based on silicon-germanium alloy prepared in the comparative example is defined as Geon Si APD.

[0065] Performance testing: 1. Si prepared according to Example 1 0.65 Ge 0.35 For example, APD Figure 4 The image shows Si 0.65 Ge 0.35 A top-view SEM image (scanning electron microscope image) of an APD, illustrating a mesa-cylindrical structure on a silicon substrate; as shown in the image. Figure 5 The image shows Si 0.65 Ge 0.35 A cross-sectional SEM image of the APD, showing a SiO2 material layer, Si, and Si from top to bottom. 0.65 Ge 0.35 Material layer, Si material layer; SiO2 as a passivation layer to protect and isolate the device, Si 0.65 Ge 0.35 The alloy grows smoothly on the surface of the Si material layer.

[0066] 2. Regarding the Si prepared in Example 1 0.65 Ge 0.35APD, Si prepared in Example 2 0.25 Ge 0.75 Simulations were performed on the APD and the Geon Si APD in the comparative example, and the results are as follows: Figure 6 As shown. The simulation was performed using Sentaururus software from Synopsys. Figure 6 (a) shows the specific detectivity comparison chart. At 905 nm, Si 0.65 Ge 0.35 APD compared to Si 0.25 Ge 0.75 The APD has a higher specific detectivity; at 1064nm, the two are roughly the same, but at 1310nm, Si... 0.65 Ge 0.35 APDi is more than Si 0.25 Ge 0.75 The lower detectivity of the APD indicates that the absorption in the SWIR band becomes stronger with increasing germanium content. In practical applications, the wavelength range of absorbed light can be changed by adjusting the germanium content. The results also show that a silicon-germanium alloy with 35% germanium content can effectively absorb light at the 1064nm wavelength of the silicon absorption band edge. Figure 6 (b) shows a comparison of response rates near the breakdown point; Figure 6 (c) is a gain comparison chart. In Example 1, Si 0.65 Ge 0.35 When an APD uses a silicon-germanium (35% germanium) alloy as the absorber layer, the device gain is an order of magnitude greater than that of a device using pure germanium as the absorber layer. Figure 6 The middle (d) graph shows the responsivity comparison at the punch-through point. As can be seen from the graph, by adjusting the SiGe composition (such as increasing the Ge content to 0.65), the avalanche multiplication capability of the device can be effectively improved. High gain means that extremely weak optical signals can be amplified, which is suitable for scenarios that require high internal amplification but may have slightly higher noise tolerance.

[0067] 3. To further verify the performance of the APD prepared in this invention, the Si prepared in Example 1 was used... 0.65 Ge 0.35 APDs, through subsequent processes such as chip dicing, mounting, wire bonding, and optical hermetically sealed assembly, integrate individual devices (such as... Figure 3 ) is prepared into a 1×8 APD array, such as Figure 7 The image shown is an electron microscope image of the APD array. A simulation of this 1×8 APD array was performed; the results are shown below. Figure 8 (a) is a schematic diagram of the dark current consistency results of devices in the same array; (b) is a schematic diagram of the gain consistency results of devices in the same array; (c) is a schematic diagram of the responsivity consistency results of devices in the same array. The results show that, in the same array, the dark current (D1-dark to D8-dark corresponding to...) Figure 7 The array (from left to right), gain, and responsivity (R) show good consistency, indicating that the array device is stable. The punch-through voltage Vpt is stable at around -8.1V, and the avalanche voltage Vbr is stable at around -16V.

[0068] The above results indicate that in the avalanche photodiode based on silicon-germanium alloy provided by this invention, the silicon-germanium (SiGe) alloy, as the absorption layer material, can alleviate the lattice mismatch problem to a certain extent (by reducing the Ge composition) and reduce dark current. The band gap of SiGe increases with decreasing Ge composition, and its absorption edge also blue-shifts accordingly. When the Ge composition is 0.2~0.4, the absorption edge of SiGe is around 1200~1300 nm. The APD prepared with silicon-germanium alloy with 35% germanium composition has good detection capability at 1064 nm, which is in the strong absorption band of SiGe, enabling high-efficiency detection.

[0069] In the description of this invention, it should be understood that the terms "thickness", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0070] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an avalanche photodiode based on a silicon-germanium alloy, characterized in that, Includes the following steps: S1. Obtain the substrate layer (1); S2. N-type doping is performed on a preset electrode region on one side of the substrate layer (1) to form an N++ region; a first i-Si layer is epitaxially grown in the non-N++ region of the substrate layer (1); S3. P-type doping is performed on the side of the first i-Si layer away from the substrate layer (1), and a P-Si charge layer (3) is formed on the side of the first i-Si layer away from the substrate layer (1). An i-Si multiplication layer (2) is formed on the undoped side of the first i-Si layer close to the substrate layer (1). S4. A second i-Si layer is epitaxially grown on the side of the P-Si charge layer (3) away from the substrate layer (1); S5. Selective injection is performed on the second i-Si layer using a circular template to form an annular P+ shielding layer (4); the P+ shielding layer (4) includes an i-Si region located at the center and a shielding ring surrounding the i-Si region; S6. An i-Si buffer layer (5) is epitaxially grown above the shielding ring and the i-Si region; S7. An i-SiGe layer is epitaxially grown on the side of the i-Si buffer layer (5) away from the substrate layer (1); S8. P-type doping is performed on the side of the i-SiGe layer away from the substrate layer (1), and a P++SiGe alloy contact layer (7) is formed on the side of the i-SiGe layer away from the substrate layer (1). An i-SiGe light absorption layer (6) is formed on the undoped side of the i-SiGe layer close to the substrate layer (1). S9. An electrode is formed above the P++SiGe alloy contact layer (7) and in the preset electrode region of the substrate layer (1) to obtain an avalanche photodiode based on silicon-germanium alloy.

2. The method for fabricating an avalanche photodiode based on silicon-germanium alloy according to claim 1, characterized in that, In step S1, obtaining the substrate layer (1) includes: Obtain an SOI substrate; the SOI substrate comprises a bottom silicon layer, an intermediate insulating layer, and a top silicon layer stacked sequentially from bottom to top; The top silicon layer is N-type doped with a doping concentration of 1×10⁻⁶. 19 ~1.2×10 19 cm –3 ; The bottom silicon layer and the intermediate insulating layer were removed by chemical mechanical polishing to obtain an N-type Si substrate as the substrate layer (1); the thickness of the substrate layer (1) is 280 nm to 350 nm.

3. The method for fabricating an avalanche photodiode based on silicon-germanium alloy according to claim 1, characterized in that, In step S2, the N-type doping concentration of the preset electrode region on one side of the substrate layer (1) is 1×10⁻⁶. 19 ~1.2×10 19 cm –3 .

4. The method for fabricating an avalanche photodiode based on silicon-germanium alloy according to claim 1, characterized in that, In step S3, the thickness of the i-Si multiplication layer (2) is 350 nm to 400 nm; the doping concentration of the P-Si charge layer (3) is 1 × 10⁻⁶. 17 ~1.2×10 17 cm –3 The thickness of the P-Si charge layer (3) is 100nm to 140nm.

5. The method for fabricating an avalanche photodiode based on silicon-germanium alloy according to claim 1, characterized in that, In step S5, the thickness of the P+ shielding layer (4) is 100 nm to 120 nm, and the doping concentration is 0.8 × 10⁻⁶. 18 ~1.2×10 18 cm –3 .

6. The method for fabricating an avalanche photodiode based on silicon-germanium alloy according to claim 1, characterized in that, In step S6, the thickness of the i-Si buffer layer (5) is 100 nm to 120 nm.

7. The method for fabricating an avalanche photodiode based on silicon-germanium alloy according to claim 1, characterized in that, In step S8, the thickness of the i-SiGe light-absorbing layer (6) is 350 nm to 400 nm; The doping concentration of the P++SiGe alloy contact layer (7) is 1×10⁻⁶. 19 ~1.2×10 19 cm –3 The thickness is 120nm to 160nm.

8. An avalanche photodiode based on silicon-germanium alloy, characterized in that, It includes a substrate layer (1), an i-Si multiplication layer (2), a P-Si charge layer (3), a P+ shielding layer (4), an i-Si buffer layer (5), an i-SiGe light absorption layer (6), and a P++SiGe alloy contact layer (7) stacked sequentially. The P+ shielding layer (4) includes a P++Si shielding ring on the outside and an i-Si region inside the P++Si shielding ring. The i-Si buffer layer (5) is located above the P++Si shielding ring and the i-Si region.

9. The avalanche photodiode based on silicon-germanium alloy according to claim 8, characterized in that, In the i-SiGe light-absorbing layer (6) and the P++SiGe alloy contact layer (7), the general formula of the SiGe alloy is Si 1-x Ge x , where x is 0.2 to 0.

75.

10. An array detector based on silicon-germanium alloy, characterized in that, Including the silicon-germanium alloy-based avalanche photodiode (100) of claim 8 or 9 arranged in an array.

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