A nano LED display structure based on MIS junction reflection isolation, crosstalk suppression method and preparation method

Abstract

The application discloses a nano LED display structure based on MIS junction reflection isolation, a crosstalk suppression method and a preparation method. A deep groove with an etching depth less than the thickness of an N-type layer is etched on a GaN-based epitaxial layer, so that the epitaxial layer is divided into a plurality of independent nano LED pixels. The sidewall and the bottom of the deep groove are fully covered with ALD-deposited SiN x An interface insulating layer and a TiN metal reflection electrode layer are arranged only at the bottom of the deep groove to form a MIS junction of metal / insulating layer / N-type GaN. By applying a weak negative bias to the metal electrode, the MIS junction forms a deep depletion layer in the N-type GaN, and the depletion layer extends laterally to block the conduction channel between the N-type layers of adjacent pixels. When the pixel works, the electrons diffused laterally to the bottom of the deep groove are reflected back to the original pixel by the electric field of the depletion layer, and the MIS junction has a small reverse leakage electrode and effectively reduces the crosstalk rate. The metal electrode is only arranged at the groove bottom, and the sidewall is free of metal, so that interference on the P-type layer and the MQW is avoided.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic displays, and in particular to a nano-LED display structure based on MIS junction reflection isolation, a crosstalk suppression method, and a preparation method. Background Technology

[0002] With the rapid development of near-eye display technologies such as augmented reality (AR), virtual reality (VR), and mixed reality (MR), microdisplay chips are evolving towards ultra-high display capacity (4K resolution and above) and ultra-high pixel density (tens of thousands of PPI, pixel pitch ≤1.2μm). Gallium nitride (GaN)-based nano-LEDs are considered a core competitive solution for next-generation microdisplay technology due to their high brightness, high efficiency, long lifespan, and good environmental stability. Compared to organic light-emitting diodes (OLEDs) and micro-LEDs, nano-LEDs can maintain high external quantum efficiency at the sub-micron scale, and inorganic materials have better reliability.

[0003] However, in ultra-high density integration with PPI in the tens of thousands, electrical crosstalk between adjacent nano-LED pixels has become the most critical technical bottleneck limiting display quality. The crosstalk generation mechanism is as follows: When a nano-LED pixel is working normally, electrons in its N-type semiconductor layer (usually n-GaN) are driven by the concentration gradient, not only vertically injected into the multiple quantum well (MQW) light-emitting region, but also laterally diffused in the horizontal direction. In nano-LEDs, since the pixel pitch has been reduced to submicron, the lateral diffusion length of electrons (usually 1-2 μm) exceeds the pixel pitch. Therefore, a large number of diffused electrons can cross the pixel boundary and enter the N-type layer or MQW region of adjacent pixels, causing undesirable light emission or threshold voltage drift in adjacent pixels. This crosstalk effect significantly reduces display contrast, grayscale accuracy, and color gamut purity, and in severe cases, even causes image blurring and ghosting.

[0004] Currently, the existing technologies for addressing crosstalk issues in nano-LED arrays mainly employ the following approaches: (1) Deep trench dielectric filling isolation: Deep trenches (deep enough to penetrate the MQW layer and completely penetrate the n-GaN layer) are etched between adjacent pixels and filled with insulating dielectrics such as SiO2 to form a physical isolation wall. The limitations of this method are: First, due to the etching aspect ratio (usually less than 10:1), the width of the deep trench cannot be reduced indefinitely. The typical isolation wall width is 200-300nm, which means a significant decrease in the light emission aperture ratio for a 1.2μm pixel pitch; Second, dielectric filling is only a physical barrier and cannot actively remove laterally diffused electrons. Some electrons may still bypass the bottom of the trench or enter adjacent pixels through the interface state leakage channel.

[0005] (2) High-resistivity isolation by ion implantation: A high-resistivity region is formed in the pixel gap by ion implantation (such as N⁺, Fe⁺, O⁺) to suppress electron diffusion. Although this method does not occupy extra width, high-energy ion implantation will introduce a large number of lattice defects and non-radiative recombination centers, which will seriously reduce the luminous efficiency of nano LEDs (usually by more than 20%). In addition, the resistivity of the implanted region is difficult to control precisely and the consistency is poor.

[0006] (3) Bandgap electron blocking layer: A wide bandgap electron blocking layer such as AlGaN is designed at the interface between pixels to reflect diffused electrons using the bandgap. This method requires extremely high precision in MOCVD epitaxial growth, makes it difficult to ensure uniformity on large-area wafers, and increases the complexity and cost of the epitaxial structure.

[0007] In summary, existing technologies generally suffer from an inherent contradiction between "suppressing crosstalk" and "maintaining aperture ratio / luminous efficiency," and lack reliable process solutions. Therefore, there is an urgent need for a novel device structure that can actively eliminate laterally diffused carriers, efficiently suppress crosstalk, without sacrificing luminous aperture ratio and efficiency, and with strong process compatibility and high controllability. Summary of the Invention

[0008] In view of some shortcomings of existing technologies, the present invention aims to provide a trench-bottom MIS junction reflective lateral isolation wall structure for nano-LED displays with a PPI of tens of thousands. By placing a metal reflective electrode layer only at the bottom of a deep trench that does not completely penetrate the N-type layer, a MIS junction is formed with the N-type layer. The lateral expansion of the reverse-biased depletion layer is used to reflect laterally diffused electrons, thereby efficiently suppressing crosstalk with almost no loss of luminous efficiency. Simultaneously, the metal electrode completely avoids the P-type layer and the MQW sidewalls, preventing interference with hole injection and luminescence. The present invention also solves the industrial problem of uncontrollable interfaces by stabilizing the natural oxide layer through rapid transfer and low-temperature annealing processes.

[0009] To achieve the above objectives, in a first aspect of the present invention, a nano-LED display structure based on MIS junction reflection isolation is provided, characterized in that it comprises: A substrate; An epitaxial layer is disposed on the substrate, and the epitaxial layer comprises at least an N-type semiconductor layer, a multiple quantum well light-emitting layer, and a P-type semiconductor layer from bottom to top; Multiple deep trenches are etched into the N-type semiconductor layer of the epitaxial layer. The depth of the deep trenches is less than the thickness of the N-type semiconductor layer, and the bottom of the deep trenches is located inside the N-type semiconductor layer. The deep trenches divide the epitaxial layer into multiple isolated nano-LED pixels. An interface insulating layer covers the sidewalls and bottom of the deep trench; the interface insulating layer is SiN deposited by ALD. x ; A metal reflective electrode layer is disposed in the corresponding region of the inner bottom of the deep trench covered by the interface insulating layer and adjacent to the N-type semiconductor layer. The metal reflective electrode layer, the interface insulating layer and the N-type semiconductor layer together constitute a MIS junction. The upper edge of the metal reflective electrode layer is lower than the lower edge of the multi-quantum-well light-emitting layer in the corresponding region. A dielectric filling layer fills the remaining space of the deep trench and covers the metal reflective electrode layer and the interface insulating layer; At least one contact hole penetrates the dielectric filling layer and extends downward to the metal reflective electrode layer; A potential transmission bus is electrically connected to the metal reflective electrode layer through the contact hole; A bias voltage generating circuit, connected to the potential transmission bus, is used to apply a negative bias voltage relative to the potential of the N-type semiconductor layer to the metal reflective electrode layer, so that the MIS junction is in a deep depletion state.

[0010] In one specific embodiment, the depth of the deep trench is 200nm-350nm, the thickness of the N-type semiconductor layer is 150nm-300nm, the depth of the deep trench is less than the thickness of the N-type semiconductor layer and the depth into the N-type semiconductor layer is 50nm-150nm; the width of the deep trench is 70nm-150nm, and the sidewall inclination angle is 80°-88°.

[0011] In one specific embodiment, the SiN of the interface insulating layer x Atomic layer deposition was employed, with BTBAS / NH3 plasma as the precursor. The deposition temperature was 300℃-400℃, and the thickness was controlled to be 1.5nm-2.5nm by the number of cycles.

[0012] In one specific embodiment, the metal reflective electrode layer is TiN, which is deposited using atomic layer deposition. The precursor is TiCl4 / NH3, the deposition temperature is 350℃, and the thickness is 20nm.

[0013] A second aspect of the present invention provides a crosstalk suppression method based on the structure of claim 1, comprising the following steps: The bias generation circuit applies a negative bias voltage relative to the potential of the N-type semiconductor layer to the metal reflective electrode layer, the absolute value of which is 0.3V-1.2V, so that the MIS junction is in a deep depletion state. The MIS junction forms a depletion layer in the N-type semiconductor layer, and the depletion layer extends downward and laterally from the bottom of the deep trench to form a high-resistivity isolation region in the N-type semiconductor layer between adjacent pixels; When the first pixel emits light normally, electrons in its N-type semiconductor layer diffuse laterally to the depletion layer region, are repelled by the electric field of the depletion layer, and are reflected back into the N-type semiconductor layer of the first pixel. The reflected electrons continue to diffuse into the multi-quantum-well luminescent layer and participate in luminescent recombination; The reverse leakage current density of the MIS junction is less than 10. -11 With an aperture of A / μm, the number of electrons entering the metal reflective electrode layer is negligible, thereby achieving crosstalk suppression without significantly sacrificing luminous efficiency.

[0014] In one specific implementation, the absolute value of the negative bias voltage is dynamically adjusted according to the display refresh rate: when the refresh rate is ≥120Hz, the absolute value of the bias voltage is 0.8V-1.0V; when the refresh rate is 60Hz-120Hz, the absolute value of the bias voltage is 0.6V-0.8V; when the refresh rate is ≤60Hz, the absolute value of the bias voltage is 0.5V-0.6V.

[0015] A third aspect of the present invention provides a method for preparing the structure provided in the first aspect of the present invention, comprising the following steps: Step S1: Epitaxially grow an N-type semiconductor layer, a multi-quantum-well light-emitting layer, and a P-type semiconductor layer on the substrate to form a continuous epitaxial layer; Step S2: Deposit a hard mask and define the deep trench pattern using photolithography; Step S3: Inductively coupled plasma etching is used to form deep trenches. The deep trenches are etched into the interior of the N-type semiconductor layer, with a depth less than the thickness of the N-type semiconductor layer, thereby dividing the continuous epitaxial layer into multiple isolated nano-LED pixels. Step S4: Remove photoresist and clean the sidewalls and bottom of the deep trench; Step S4a: Quickly transfer the wafer to the ALD device in a clean environment, controlling the air exposure time to be less than 5 minutes, so that the thickness of the natural oxide layer on the sidewalls and bottom is less than 1 nm; Step S4b: Perform low-temperature annealing in the ALD chamber at 300°C in a N2 atmosphere for 10 minutes to densify the natural oxide layer and stabilize its composition. Step S5: Deposit SiN on the sidewalls and bottom of the deep trench using atomic layer deposition. x Interface insulating layer, thickness 1.5nm-2.5nm; Step S6: Atomic layer deposition is performed on SiN x A TiN metal layer with a thickness of 10nm-30nm is deposited on the layer. Step S7: Selectively remove the TiN metal layer on the sidewall of the deep trench, retain the TiN metal layer at the bottom of the deep trench, and form a metal reflective electrode layer; Step S8: Fill the SiO2 medium with plasma-enhanced chemical vapor deposition and perform chemical mechanical polishing for planarization; Step S9: Etch contact holes at the edge of the display array and fill them with metal plugs; Step S10: Deposit and pattern the metal bus, and connect the contact holes; Step S11: Integrate the bias generation circuit and connect it to the bus; Step S12: Fabricate the pixel anode and cathode.

[0016] In one specific embodiment, the selective removal of the TiN metal layer on the sidewall of the deep trench in step S7 includes the following sub-steps: Spin-coating photoresist to a thickness of 300nm allows the photoresist to fill the deep trench and retain a relatively thick layer of photoresist at the bottom of the trench. Plasma etching is used to remove the photoresist from the sidewalls and surface of the deep trench, leaving only the photoresist at the bottom of the deep trench. The exposed sidewall TiN was removed by Cl2 / Ar-based dry etching, while the bottom TiN was retained due to the protection of the photoresist. Remove any remaining photoresist.

[0017] In one specific embodiment, SiN in step S5 x The deposition conditions are: temperature 350℃, precursor BTBAS and NH3 plasma, and 20-35 cycles; the deposition conditions of TiN in step S6 are: temperature 350℃, precursor TiCl4 and NH3, and 80 cycles.

[0018] In one specific embodiment, the etching conditions for the deep trench in step S3 are: etching gas Cl2 / BCl3 = 30 / 10 sccm, pressure 10 mTorr, source power 300 W, bias power 100 W, etching time 80 s-120 s, and depth 200 nm-350 nm.

[0019] The beneficial effects of this invention are as follows: 1) By setting a MIS junction at the bottom of the deep trench and applying a weak negative bias, a deep depletion layer is formed in the N-type semiconductor layer. After the depletion layer expands laterally, it can form a continuous high-resistivity isolation region between adjacent pixels, effectively blocking the lateral diffusion path of electrons. At the same time, the electric field in the depletion layer generates a repulsive force on the diffused electrons, reflecting them back to the original pixel, thereby fundamentally eliminating the possibility of electrons entering adjacent pixels and achieving efficient crosstalk suppression. 2) An interface insulating layer is provided between the metal reflective electrode layer and the N-type semiconductor layer. The reverse leakage current of the MIS junction is extremely small under weak reverse bias, so the metal electrode hardly extracts electrons from the N-type layer. The reflected electrons can still continue to diffuse to the multi-quantum-well light-emitting layer and recombine with holes to emit light, and the loss of luminous efficiency is negligible. This is fundamentally different from the scheme where the efficiency drops significantly due to the introduction of lattice defects in the ion implantation high-resistivity region. 3) The metal reflective electrode layer is only located at the bottom of the deep trench, and no metal is placed on the sidewalls of the deep trench (especially in the region corresponding to the P-type semiconductor layer and the multi-quantum-well light-emitting layer). This completely avoids direct or indirect contact between the metal electrode and the P-type layer and MQW sidewalls, without affecting the lateral transport of holes or introducing additional non-radiative recombination centers into the MQW sidewalls, thus ensuring the original electrical and optical performance of the light-emitting device. 4) In the structure of this invention, the depth of the deep trench is less than the thickness of the N-type semiconductor layer, so it is not necessary to etch through the entire N-type layer. The requirement for the etching aspect ratio is relatively low, which is beneficial to maintaining process feasibility and structural integrity even when the pixel pitch is further reduced. Since the N-type semiconductor layer is not etched through, the overall etching depth is reduced, and the width of the deep trench can be made narrower than that of the traditional dielectric-filled isolation trench. Moreover, it is not necessary to set up a large isolation structure in the pixel gap, and the area ratio of the pixel light-emitting region is significantly improved. Under the same pixel pitch, this invention can achieve a higher light-emitting aperture ratio, which is beneficial to improving display brightness and reducing power consumption. 5) Since the depletion layer width of the MIS junction increases monotonically with the increase of bias voltage, the crosstalk suppression effect is positively correlated with the bias voltage. Therefore, the absolute value of the negative bias voltage applied to the metal reflective electrode layer can be dynamically adjusted according to the different refresh rates or brightness requirements of the displayed content, so as to reduce power consumption as much as possible while ensuring crosstalk suppression effect and achieve an optimal balance between performance and energy consumption. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a nano-LED display structure based on MIS junction reflection isolation provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the fabrication process of a nano-LED display structure based on MIS junction reflection isolation, according to an embodiment of the present invention. Detailed Implementation

[0021] The embodiments of this patent are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this patent, and should not be construed as limiting this patent.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0023] Example 1 like Figures 1-2 As shown, in the first embodiment of the present invention, a nano-LED display structure based on MIS junction reflection isolation is provided, comprising: A substrate 100; in this embodiment, the substrate 100 may be a Si (111), sapphire (Al2O3) or GaN self-supporting substrate 100, with a thickness of 300μm-1000μm.

[0024] An epitaxial layer 200 is disposed on the substrate 100, and the epitaxial layer 200 includes, from bottom to top, at least an N-type semiconductor layer 201, a multiple quantum well light-emitting layer 202, a P-type semiconductor layer 203; a buffer layer (such as an AlN / AlGaN superlattice, 100-300 nm thick, used to reduce dislocation density); and the N-type semiconductor layer 201 (n-GaN, Si doping concentration 5 × 10⁻⁶). 18 cm -3 -5×10 19 cm -3 Thickness 150nm-300nm); Multi-quantum well light-emitting layer 202 (InGaN / GaN MQW, 3-10 periods, well thickness 2nm-4nm, barrier thickness 5nm-10nm); P-type semiconductor layer 203 (p-GaN, Mg doping concentration 1×10⁻⁶). 19 cm -3 -1×10 20 cm -3 (Thickness 20nm-50nm).

[0025] Multiple deep trenches 300 are etched into the N-type semiconductor layer 201 of the epitaxial layer 200. The depth of the deep trenches 300 is less than the thickness of the N-type semiconductor layer 201, and the bottom of the deep trenches 300 is located inside the N-type semiconductor layer 201. The deep trenches 300 divide the epitaxial layer 200 into multiple isolated nano-LED pixels 204. Typically, the spacing between adjacent pixels is less than 1.2 μm. The depth of the deep trenches 300 (200 nm-350 nm) is less than the thickness of the N-type semiconductor layer 201, therefore the bottom of the deep trenches 300 is located inside the N-type semiconductor layer 201 and does not penetrate the layer. The deep trenches 300 divide the continuous epitaxial layer 200 into multiple isolated nano-LED pixels 204, with the spacing between adjacent pixels not exceeding 1.2 μm (corresponding to a pixel density ≥20000 PPI). The width of the deep trenches 300 is 70 nm-150 nm, and the sidewall tilt angle is 80°-88°.

[0026] An interface insulating layer 400 covers the sidewalls and bottom of the deep trench 300, wherein the interface insulating layer 400 is SiN deposited by ALD. x The thickness is 1.5nm-2.5nm; A metal reflective electrode layer 500 is disposed in the corresponding region of the inner bottom of the deep trench 300, which is covered by the interface insulating layer 400, and adjacent to the N-type semiconductor layer 201. The metal reflective electrode layer 500, the interface insulating layer 400, and the N-type semiconductor layer 201 together constitute a MIS junction. The upper edge of the metal reflective electrode layer 500 is lower than the lower edge of the multi-quantum-well light-emitting layer 202 in the corresponding region. The material of the metal reflective electrode layer 500 is TiN, TaN, or W, and its thickness is 10nm-30nm. The metal reflective electrode layer 500 is disposed at the bottom of the deep trench 300 and covers the interface insulating layer 400, but does not cover the sidewalls of the deep trench 300. Preferably, TiN (resistivity approximately 20μΩ·cm, work function approximately 4.7eV) is used.

[0027] A dielectric filling layer 600 fills the remaining space of the deep trench 300 and covers the metal reflective electrode layer 500 and the interface insulating layer 400; the dielectric filling layer 600 is made of SiO2 or SiN. x With a thickness of 30nm-80nm, it serves to flatten and provide insulation protection.

[0028] At least one contact hole penetrates the dielectric filling layer 600 and extends downward to the metal reflective electrode layer 500; the contact hole can be disposed between pixels or at the edge region of the display array (e.g., the four corners), penetrating the dielectric filling layer 600 and extending downward to the metal reflective electrode layer 500. The contact hole has a diameter of 150nm-300nm and is filled with W or TiN metal plugs.

[0029] A potential transmission bus is electrically connected to the metal reflective electrode layer 500 through the contact hole; the potential transmission bus is electrically connected to the metal reflective electrode layer 500 through the contact hole, arranged around at least one side of the display array, and is made of Al, Ti / Al alloy or Cu, with a width of 1μm-10μm and a thickness of 200nm-500nm.

[0030] A bias voltage generating circuit, connected to the potential transmission bus, is used to apply a negative bias voltage relative to the potential of the N-type semiconductor layer 201 to the metal reflective electrode layer 500, so that the MIS junction is in a deep depletion state. The specific negative bias voltage can be set according to the actual device conditions; typically, the absolute value of the negative bias voltage is 0.5V-1.0V. The bias generation circuit can be integrated on the chip (typically located on the CMOS driver wafer), with its output connected to the potential transfer bus. It applies a negative bias voltage relative to the potential of the N-type semiconductor layer 201 to the metal reflective electrode layer 500, with an absolute value of 0.5V-1.0V. This circuit is preferably an on-chip charge pump (Dickson type or cross-coupled type), with an input voltage of 1.8V-3.3V, an adjustable output voltage, and an output ripple of less than 10mV.

[0031] In this embodiment, the depth of the deep trench 300 is 200nm-350nm, the thickness of the N-type semiconductor layer 201 is 150nm-300nm, the depth of the deep trench 300 is less than the thickness of the N-type semiconductor layer 201 and the depth into the N-type semiconductor layer 201 is 50nm-150nm; the width of the deep trench 300 is 70nm-150nm, and the sidewall tilt angle is 80°-88°.

[0032] In this embodiment, the SiN of the interface insulating layer 400 x Atomic layer deposition was employed, with BTBAS / NH3 plasma as the precursor. The deposition temperature was 300℃-400℃, and the thickness was controlled to be 1.5nm-2.5nm by the number of cycles. This insulating layer is continuous and free of pinholes, has a dielectric constant of approximately 7, and exhibits high breakdown field strength.

[0033] Optionally, the metal reflective electrode layer 500 is TiN, deposited using atomic layer deposition, with TiCl4 / NH3 as the precursor, a deposition temperature of 350℃, and a thickness of 20nm.

[0034] Optionally, the bias generation circuit is an on-chip charge pump with adjustable output voltage and output ripple of less than 10mV.

[0035] Optionally, the transverse partition wall may be strip-shaped, grid-shaped, or ring-shaped on the map.

[0036] Meanwhile, in the first embodiment of the present invention, a method for suppressing crosstalk in a nano-LED display structure is also provided, comprising the following steps: The bias generation circuit applies a negative bias voltage relative to the potential of the N-type semiconductor layer 201 to the metal reflective electrode layer 500, the absolute value of which is 0.3V-1.2V, so that the MIS junction is in a deep depletion state. The MIS junction forms a depletion layer in the N-type semiconductor layer 201. The depletion layer extends downward and laterally from the bottom of the deep trench 300, forming a high-resistivity isolation region in the N-type semiconductor layer 201 between adjacent pixels. When the first pixel emits light normally, electrons in its N-type semiconductor layer 201 diffuse laterally to the depletion layer region, are repelled by the electric field of the depletion layer, and are reflected back into the N-type semiconductor layer 201 of the first pixel. The reflected electrons continue to diffuse into the multi-quantum-well light-emitting layer 202 and participate in light-emitting recombination; The reverse leakage current density of the MIS junction is less than 10. -11 With an aperture of A / μm, the number of electrons entering the metal reflective electrode layer 500 is negligible, thereby achieving crosstalk suppression without significantly sacrificing luminous efficiency.

[0037] In this embodiment, the absolute value of the negative bias voltage is dynamically adjusted according to the display refresh rate: when the refresh rate is ≥120Hz, the absolute value of the bias voltage is 0.8V-1.0V; when the refresh rate is 60Hz-120Hz, the absolute value of the bias voltage is 0.6V-0.8V; when the refresh rate is ≤60Hz, the absolute value of the bias voltage is 0.5V-0.6V.

[0038] The shape of the deep groove 300 on the layout can be strip (extending continuously only along the column direction or only along the row direction), grid (extending continuously in both columns and rows to form a closed grid around each pixel), or ring (an independent annular groove around each pixel), among which the grid shape has the best effect in suppressing crosstalk.

[0039] Working principle The working principle of this embodiment is based on the deep depletion effect and electron reflection mechanism of the MIS junction, as detailed below: Formation of the MIS junction: Metal reflective electrode layer (TiN) / Interface insulating layer (SiN) x The MIS capacitor structure is composed of an N-type semiconductor layer (n-GaN). The interface insulating layer is thin enough (1.5-2.5nm) to allow the formation of a space charge region on the n-GaN surface when a bias voltage is applied, while blocking DC leakage current.

[0040] Weak reverse bias: A negative voltage (absolute value 0.5V-1.0V) relative to the n-GaN potential is applied to the metal reflective electrode layer through a bias voltage generation circuit, causing the MIS junction to be in a deep depletion state. At this time, the majority carriers (electrons) on the n-GaN surface are depleted, forming a depletion layer, and a strong inversion layer (hole accumulation) has not yet formed. The width of the depletion layer is proportional to the square root of the bias voltage, with a typical value of 15nm-40nm.

[0041] Lateral expansion of the depletion layer: Since the bottom of the deep trench is located inside the n-GaN layer, the depletion layer not only extends vertically towards the bottom of the n-GaN layer, but also laterally in all directions. When the trench spacing (pixel spacing) is small enough (≤1.2μm), the depletion layers between adjacent pixels will connect with each other, forming a continuous high-resistivity isolation region in the N-type layer between pixels. This region has almost no free electrons, thus cutting off the path for electrons to diffuse laterally from one pixel to another.

[0042] Electron reflection: When the first pixel emits light normally, electrons in its N-type layer diffuse outwards driven by the concentration gradient. When these electrons reach the edge of the depletion layer, they experience a force opposite to this electric field (directed from the positive charge region to the negative charge region) due to the electric field pointing from the interior of the n-GaN to the metal electrode. This repulsive force points inwards towards the n-GaN. Therefore, the electrons are reflected back into the original pixel's N-type layer, as if hitting an electron wall. These reflected electrons still have a chance to diffuse back into the MQW region and recombine with holes to emit light, thus the luminous efficiency is almost unaffected.

[0043] No net current: Due to the barrier effect of the interface insulating layer and the bias voltage being lower than the strong inversion threshold, the reverse leakage current of the MIS junction is extremely small (typically <10). -11 With a wall length of A / μm, almost no electrons tunnel into the metal reflective electrode layer. Therefore, this structure does not draw electrons from the N-type layer, does not generate additional power consumption, and does not cause a loss of luminous efficiency.

[0044] Crosstalk suppression: Since the laterally diffused electrons are reflected back to the original pixel, and the N-type layer between pixels is isolated by the depleted high-resistivity region, adjacent pixels do not receive additional electrons, and their undesired luminescence is greatly reduced.

[0045] Compared to deep trench dielectric filling (passive blocking), this invention suppresses crosstalk through active electric field reflection, while significantly reducing the dielectric filling width and achieving a higher aperture ratio. Compared to sidewall Schottky junction collection schemes, this invention places the metal electrode at the bottom of the trench, completely avoiding the P-type layer and MQW sidewalls, thus avoiding interference with hole injection and luminescence; simultaneously, it utilizes depletion layer reflection instead of electron absorption, resulting in no efficiency loss. Compared to ion implantation in high-resistivity regions, this invention does not introduce lattice damage, ensuring no loss of luminescence efficiency.

[0046] Example 2 In a second embodiment of the present invention, a method for fabricating a nano-LED display structure based on MIS junction reflection isolation is provided, comprising the following steps: Step S1: Epitaxially grow an N-type semiconductor layer, a multi-quantum-well light-emitting layer, and a P-type semiconductor layer on the substrate to form a continuous epitaxial layer; The following layers were sequentially grown on the substrate using an MOCVD apparatus: a buffer layer (AlN / AlGaN superlattice, 200 nm), and an n-GaN layer (150 nm-300 nm thick, Si-doped 1×10⁻⁶). 19 cm -3 InGaN / GaN multiple quantum wells (3-10 periods, well 2-4 nm, barrier 5-10 nm), p-GaN layer (thickness 20-50 nm, Mg doped 5×100 nm) 19 cm -3 In-situ annealing after growth activates Mg acceptors.

[0047] In practice, epitaxial wafers can be purchased directly in actual production; this embodiment does not limit whether the epitaxial wafers are produced or purchased independently.

[0048] Step S2: Deposit a hard mask and define the deep trench pattern using photolithography; A 200nm thick SiO2 hard mask layer was deposited using PECVD.

[0049] Spin-coat electron beam resist (such as HSQ) or deep ultraviolet photoresist, and define deep trench patterns (strip, grid, or ring, linewidth 70-150nm) by electron beam lithography or deep ultraviolet lithography.

[0050] The pattern was transferred into a SiO2 hard mask using CF4 / Ar-based ICP etching.

[0051] Step S3: Inductively coupled plasma etching is used to form deep trenches. The deep trenches are etched into the interior of the N-type semiconductor layer, with a depth less than the thickness of the N-type semiconductor layer, thereby dividing the continuous epitaxial layer into multiple isolated nano-LED pixels. Using patterned SiO2 as a mask, the epitaxial layer was etched using an ICP etching system. The etching gas was Cl2 / BCl3 (flow ratio 30 / 10 sccm), pressure 10 mTorr, source power 300 W, and bias power 100 W. The etching time was adjusted according to the required depth (typically 80-120 s) to achieve a trench depth of 200 nm-350 nm, penetrating 50-150 nm into the n-GaN layer (without penetrating). After etching, the sidewall tilt angle was approximately 85°, and the width met the design value.

[0052] The deep trench divides the continuous epitaxial layer into multiple independent nano-LED pixel islands, and the n-GaN, MQW, and p-GaN of each pixel are completely isolated in the horizontal direction.

[0053] Step S4: Remove photoresist and clean the sidewalls and bottom of the deep trench; The SiO2 hard mask was removed by wet etching (BOE solution). Oxygen plasma ashing (300W, 5min) was used to remove residual photoresist, followed by immersion in diluted HCl (1:10) for 30s to remove etching residues and metal contaminants, and then rinsed with deionized water and dried with N2.

[0054] Step S4a: Quickly transfer the wafer to the ALD device in a clean environment, controlling the air exposure time to be less than 5 minutes, so that the thickness of the natural oxide layer on the sidewalls and bottom is less than 1 nm; The cleaned wafers are rapidly transferred to the loading chamber of the ALD device in a cleanroom environment (Class 100, temperature 22°C, humidity <30%). An N2 gas shield is used along the transfer path, and air exposure time is strictly controlled to be less than 5 minutes. This step aims to control the thickness of the natural Ga2O3 layer to below 1 nm (typically 0.5-0.9 nm).

[0055] Step S4b: Perform low-temperature annealing in the ALD chamber at 300°C in a N2 atmosphere for 10 minutes to densify the natural oxide layer and stabilize its composition. After the wafer enters the ALD reaction chamber, it is evacuated to below 0.1 Torr, and high-purity N2 (100 sccm) is introduced. The sample stage is heated to 300°C and held for 10 minutes. This annealing transforms the metastable Ga2O3 in the natural oxide layer into a denser, stoichiometrically stable Ga2O3, while simultaneously desorbing surface-adsorbed water vapor and hydrocarbon contaminants. After annealing, it is naturally cooled to SiN. x Deposition temperature (350°C), without breaking the vacuum during the process.

[0056] Step S5: Deposit SiN on the sidewalls and bottom of the deep trench using atomic layer deposition. x Interface insulating layer, thickness 1.5nm-2.5nm; Atomic layer deposition (ALD) was employed, using BTBAS (bis(tert-butylamino)silane) and NH3 plasma as precursors. The deposition temperature was 350°C, and the cycle was as follows: BTBAS pulse 0.5s → N2 purge 10s → NH3 plasma pulse (300W) 0.3s → N2 purge 10s. The number of cycles was 20-35, corresponding to a thickness of 1.5-2.5 nm (calibrated using an ellipsometry). SiN x The layer conformally covers the sidewalls and bottom of the deep trench, with a thickness uniformity of ≥95%.

[0057] Step S6: Atomic layer deposition is performed on SiN x A TiN metal layer with a thickness of 10nm-30nm is deposited on the layer. In the same ALD apparatus, the precursors were switched to TiCl4 and NH3. The deposition temperature was 350°C, and the cycle was as follows: TiCl4 pulse 0.2s → Ar purge 10s → NH3 pulse 0.3s → Ar purge 10s. The cycle count was 80 times, and the thickness was 20nm (range 10-30nm). The TiN layer covered the SiN. x On top of that, a MIS stack is formed.

[0058] Step S7: Selectively remove the TiN metal layer on the sidewall of the deep trench, retain the TiN metal layer at the bottom of the deep trench, and form a metal reflective electrode layer; Objective: To retain only the TiN at the bottom of the deep trench as a metal reflective electrode, remove the TiN on the sidewalls, and avoid contact between the metal and the P-type layer and the MQW sidewalls.

[0059] Specific sub-steps: (a) Spin-coating i-line photoresist (e.g., AZ5214) to a thickness of 300 nm, followed by soft baking at 90°C for 90 s. The photoresist fills the deep trench, and because the aspect ratio of the deep trench is >2, the photoresist thickness at the bottom of the trench is greater than that on the sidewalls and the surface.

[0060] (b) Plasma etching: Using an O2 (50 sccm) / Ar (20 sccm) mixed gas, pressure 50 mTorr, RF power 100 W, processing time 60 s. This step removes the photoresist on the surface and sidewalls, but approximately 100 nm of photoresist remains at the bottom of the deep trench due to its thicker layer. (c) Dry etching of TiN: Using Cl2 / Ar (30 / 10 sccm) plasma, pressure 10 mTorr, source power 150 W, bias power 50 W, etching time 30 s. Exposed sidewall TiN is completely removed, while bottom TiN is retained due to photoresist protection.

[0061] (d) Degumming: After oxygen plasma ashing (300W, 5min), soak in N-methylpyrrolidone (NMP) at 70°C for 10min, rinse with deionized water, and dry with N2.

[0062] Step S8: Fill the SiO2 medium with plasma-enhanced chemical vapor deposition and perform chemical mechanical polishing for planarization; SiO2 (precursor TEOS / O2) was deposited using PECVD at 300°C, a deposition rate of 5 nm / s, and a deposition time of 12 s, resulting in a SiO2 layer with a thickness of approximately 60 nm, completely filling the remaining space in the deep trench (covering the bottom TiN and the sidewall SiN). xPlanarization was performed using chemical mechanical polishing (CMP): a SiO2-based polishing slurry (pH=10) was used at a polishing pressure of 2 psi, a rotation speed of 60 rpm, and a polishing time of approximately 3 minutes, until the upper surface of the p-type GaN layer was exposed, and excess SiO2 and hard mask residue were removed from the surface. The final SiO2-filled layer was flush with the p-GaN surface, with a surface roughness RMS < 0.5 nm.

[0063] Step S9: Etch contact holes at the edge of the display array and fill them with metal plugs; In the edge regions of the display array (e.g., the four corners), the locations of contact holes (200 nm in diameter, located below the potential transfer bus) are defined by photolithography. Vertical holes are formed using ICP etching of SiO2 (CF4 / Ar = 20 / 10 sccm, pressure 50 mTorr, power 150 W, time 60 s) until the surface of the underlying TiN metal layer is exposed. ALD deposition of W metal plugs (precursor WF6 / SiH4) at 300°C for 200 cycles completely fills the contact holes. Excess W on the surface is then removed by CMP, leaving only the W plugs within the holes.

[0064] Step S10: Deposit and pattern the metal bus, and connect the contact holes; An Al layer with a thickness of 300 nm was deposited by magnetron sputtering. A bus pattern (2 μm wide, closed around the display array) was patterned by photolithography, and Al was wet-etched (H3PO4 / HNO3 / H2O = 16:1:1, 45°C, 60 s) to form the bus. The bus was electrically connected to the top of the W plugs in each contact hole.

[0065] Step S11: Integrate the bias generation circuit and connect it to the bus; On the CMOS driver wafer, a Dickson-type charge pump is integrated using standard CMOS technology. It has an input voltage of 1.8V, an adjustable negative voltage of -0.5V to 1.0V in 0.1V steps, an output ripple of <10mV, and an output current capability >1mA. A dynamic bias control module is also integrated to receive the refresh rate signal from the display controller. The nano-LED wafer and the CMOS driver wafer are interconnected via hybrid bonding. The charge pump output on the CMOS wafer is connected to the potential transfer bus on the nano-LED wafer via bonding pads.

[0066] Step S12: Fabricate the pixel anode and cathode.

[0067] A transparent anode electrode, ITO / Ni / Au (50 / 5 / 50 nm), is deposited on the planarized p-GaN surface via electron beam evaporation and rapidly thermally annealed (500°C, 1 min) in an N2 atmosphere to form an ohmic contact. This anode serves as the common electrode, connecting the top of all pixels.

[0068] The light-emitting area (0.8 μm in diameter) of each pixel is defined by photolithography and ICP etching, forming an independent pixel mesa (the mesa are isolated from each other by deep trenches and dielectric filling layers).

[0069] Individual cathode electrodes (Ni / Au, 20 / 80nm) are deposited on the sidewall or back of the pixel mesa by electron beam evaporation. After stripping, they form individual cathodes for each pixel and are connected to the output of the corresponding driving TFT on the CMOS driving wafer.

[0070] At this point, the fabrication of the complete nano-LED display device is finished.

[0071] Optionally, the selective removal of the TiN metal layer on the sidewall of the deep trench in step S7 includes the following sub-steps: Spin-coating photoresist to a thickness of 300nm allows the photoresist to fill the deep trench and retain a relatively thick layer of photoresist at the bottom of the trench. Plasma etching is used to remove the photoresist from the sidewalls and surface of the deep trench, leaving only the photoresist at the bottom of the deep trench. The exposed sidewall TiN was removed by Cl2 / Ar-based dry etching, while the bottom TiN was retained due to the protection of the photoresist. Remove any remaining photoresist.

[0072] In this embodiment, SiN in step S5 x The deposition conditions are: temperature 350℃, precursor BTBAS and NH3 plasma, and 20-35 cycles; the deposition conditions of TiN in step S6 are: temperature 350℃, precursor TiCl4 and NH3, and 80 cycles.

[0073] In this embodiment, the etching conditions for the deep trench in step S3 are: etching gas Cl2 / BCl3 = 30 / 10 sccm, pressure 10mTorr, source power 300W, bias power 100W, etching time 80s-120s, and depth 200nm-350nm.

[0074] Optionally, in step S8, after SiO2 filling, the surface is planarized by chemical mechanical polishing until the upper surface of the P-type semiconductor layer is exposed, with a surface roughness RMS of less than 0.5 nm.

[0075] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A nano-LED display structure based on MIS junction reflection isolation, characterized in that, include: A substrate; An epitaxial layer is disposed on the substrate, and the epitaxial layer comprises at least an N-type semiconductor layer, a multiple quantum well light-emitting layer, and a P-type semiconductor layer from bottom to top; Multiple deep trenches are etched into the N-type semiconductor layer of the epitaxial layer. The depth of the deep trenches is less than the thickness of the N-type semiconductor layer, and the bottom of the deep trenches is located inside the N-type semiconductor layer. The deep trenches divide the epitaxial layer into multiple isolated nano-LED pixels. An interface insulating layer covers the sidewalls and bottom of the deep trench; the interface insulating layer is SiN deposited by ALD. x ; A metal reflective electrode layer is disposed in the inner bottom of the deep trench covered by the interface insulating layer, in a corresponding region adjacent to the N-type semiconductor layer. The metal reflective electrode layer, the interface insulating layer, and the N-type semiconductor layer together constitute a MIS junction. The upper edge of the metal reflective electrode layer is lower than the lower edge of the multi-quantum-well light-emitting layer in the corresponding region. A dielectric filling layer fills the remaining space of the deep trench and covers the metal reflective electrode layer and the interface insulating layer; At least one contact hole penetrates the dielectric filling layer and extends downward to the metal reflective electrode layer; A potential transmission bus is electrically connected to the metal reflective electrode layer through the contact hole; A bias voltage generating circuit, connected to the potential transmission bus, is used to apply a negative bias voltage relative to the potential of the N-type semiconductor layer to the metal reflective electrode layer, so that the MIS junction is in a deep depletion state.

2. The structure according to claim 1, characterized in that, The trench has a depth of 200nm-350nm, the N-type semiconductor layer has a thickness of 150nm-300nm, the trench has a depth less than the N-type semiconductor layer and a depth of 50nm-150nm into the N-type semiconductor layer, the trench has a width of 70nm-150nm, and the sidewall inclination is 80°-88°.

3. The structure according to claim 1, characterized in that, The SiN interface insulating layer x Atomic layer deposition was employed, with BTBAS / NH3 plasma as the precursor. The deposition temperature was 300℃-400℃, and the thickness was controlled to be 1.5nm-2.5nm by the number of cycles.

4. The structure according to claim 1, characterized in that, The metal reflective electrode layer is TiN, deposited by atomic layer deposition, with TiCl4 / NH3 as the precursor, a deposition temperature of 350℃, and a thickness of 20nm.

5. A crosstalk suppression method based on the structure described in claim 1, characterized in that, Includes the following steps: The bias generation circuit applies a negative bias voltage relative to the potential of the N-type semiconductor layer to the metal reflective electrode layer, the absolute value of which is 0.3V-1.2V, so that the MIS junction is in a deep depletion state. The MIS junction forms a depletion layer in the N-type semiconductor layer, and the depletion layer extends downward and laterally from the bottom of the deep trench to form a high-resistivity isolation region in the N-type semiconductor layer between adjacent pixels; When the first pixel emits light normally, electrons in its N-type semiconductor layer diffuse laterally to the depletion layer region, are repelled by the electric field of the depletion layer, and are reflected back into the N-type semiconductor layer of the first pixel. The reflected electrons continue to diffuse into the multi-quantum-well luminescent layer and participate in luminescent recombination; The reverse leakage current density of the MIS junction is less than 10. -11 With an aperture of A / μm, the number of electrons entering the metal reflective electrode layer is negligible, thereby achieving crosstalk suppression without significantly sacrificing luminous efficiency.

6. The method according to claim 5, characterized in that, The absolute value of the negative bias voltage is dynamically adjusted according to the display refresh rate: when the refresh rate is ≥120Hz, the absolute value of the bias voltage is 0.8V-1.0V; when the refresh rate is 60Hz-120Hz, the absolute value of the bias voltage is 0.6V-0.8V; when the refresh rate is ≤60Hz, the absolute value of the bias voltage is 0.5V-0.6V.

7. A method for preparing the structure of claim 1, characterized in that, Includes the following steps: Step S1: Epitaxially grow an N-type semiconductor layer, a multi-quantum-well light-emitting layer, and a P-type semiconductor layer on the substrate to form a continuous epitaxial layer; Step S2: Deposit a hard mask and define the deep trench pattern using photolithography; Step S3: Inductively coupled plasma etching is used to form deep trenches. The deep trenches are etched into the interior of the N-type semiconductor layer, with a depth less than the thickness of the N-type semiconductor layer, thereby dividing the continuous epitaxial layer into multiple isolated nano-LED pixels. Step S4: Remove photoresist and clean the sidewalls and bottom of the deep trench; Step S4a: Quickly transfer the wafer to the ALD device in a clean environment, controlling the air exposure time to be less than 5 minutes, so that the thickness of the natural oxide layer on the sidewalls and bottom is less than 1 nm; Step S4b: Perform low-temperature annealing in the ALD chamber at 300°C in a N2 atmosphere for 10 minutes to densify the natural oxide layer and stabilize its composition. Step S5: Deposit SiN on the sidewalls and bottom of the deep trench using atomic layer deposition. x Interface insulating layer, thickness 1.5nm-2.5nm; Step S6: Atomic layer deposition is performed on SiN x A TiN metal layer with a thickness of 10nm-30nm is deposited on the layer. Step S7: Selectively remove the TiN metal layer on the sidewall of the deep trench, retain the TiN metal layer at the bottom of the deep trench, and form a metal reflective electrode layer; Step S8: Fill the SiO2 medium with plasma-enhanced chemical vapor deposition and perform chemical mechanical polishing for planarization; Step S9: Etch contact holes at the edge of the display array and fill them with metal plugs; Step S10: Deposit and pattern the metal bus, and connect the contact holes; Step S11: Integrate the bias generation circuit and connect it to the bus; Step S12: Fabricate the pixel anode and cathode.

8. The method according to claim 7, characterized in that, The selective removal of the TiN metal layer on the sidewall of the deep trench in step S7 includes the following sub-steps: Spin-coating photoresist to a thickness of 300nm allows the photoresist to fill the deep trench and retain a relatively thick layer of photoresist at the bottom of the trench. Plasma etching is used to remove the photoresist from the sidewalls and surface of the deep trench, leaving only the photoresist at the bottom of the deep trench. The exposed sidewall TiN was removed by Cl2 / Ar-based dry etching, while the bottom TiN was retained due to the protection of the photoresist. Remove any remaining photoresist.

9. The method according to claim 7, characterized in that, In step S5, SiN x The deposition conditions are: temperature 350℃, precursor BTBAS and NH3 plasma, and 20-35 cycles; the deposition conditions of TiN in step S6 are: temperature 350℃, precursor TiCl4 and NH3, and 80 cycles.

10. The method according to claim 7, characterized in that, The etching conditions for the deep trench in step S3 are as follows: etching gas Cl2 / BCl3 = 30 / 10 sccm, pressure 10mTorr, source power 300W, bias power 100W, etching time 80s-120s, and depth 200nm-350nm.

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