Etching method of single crystal silicon, single crystal silicon having a trench, and semiconductor device

Abstract

The application discloses a single crystal silicon etching method, single crystal silicon with a groove and a semiconductor device. The single crystal silicon etching method comprises the following steps: providing single crystal silicon; forming a mask layer on one side of the single crystal silicon, the mask layer having at least one opening, the opening exposing the surface of the single crystal silicon; performing isotropic dry etching on the single crystal silicon to form a groove with a preset shape by taking the mask layer as a mask; wherein the ratio of the depth of the groove to the width of the opening is greater than or equal to 4; the groove comprises a first sub-section and a second sub-section which are sequentially away from the mask layer; along the direction away from the mask layer, the width of the first sub-section gradually increases, and the width of the second sub-section gradually decreases; wherein the minimum width of the first sub-section is greater than the width of the opening. The application can realize the shape of the groove which is wide first and narrow later.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an etching method for single-crystal silicon, single-crystal silicon with trenches, and semiconductor devices. Background Technology

[0002] In the semiconductor processing field, etching single-crystal silicon to form trenches is a common and very important technique. Trenched single-crystal silicon has significant application value in areas such as three-dimensional integration and the control of electric field distribution in trench MOSFETs.

[0003] In semiconductor devices with trenches, special trenches with a width that is initially wide and then narrows show great promise. For example, the curved sidewalls and sharp bottom corners of such special trenches can be designed to expose specific crystal planes. In V-groove MOSFET technology, using special trenches to expose preferred orientation crystal planes such as (0338) can increase channel mobility by 2 to 3 times and significantly reduce channel resistance. Furthermore, although the electric field is highly concentrated at the sharp bottom corners of special trenches, if a P+ buried layer is placed at the corner, the P+ buried layer and the N- drift region form a PN junction. The depletion layer can actively take over the high electric field region, transferring the peak electric field in the gate oxide layer to the bulk PN junction, significantly improving gate oxide reliability and extending device lifetime. However, the width of trenches formed by etching methods in related technologies mostly exhibits a monotonically changing width in the depth direction. That is, the trenches are mostly trenches with gradually narrowing widths, trenches with constant widths, or trenches with gradually increasing widths. There is currently no effective method for fabricating special trenches with a width that is initially wide and then narrows. Summary of the Invention

[0004] This invention provides an etching method for single-crystal silicon, a single-crystal silicon with trenches, and a semiconductor device to achieve a trench shape that is wide at the beginning and narrow at the end.

[0005] According to one aspect of the present invention, an etching method for single-crystal silicon is provided, comprising: Provide monocrystalline silicon; A mask layer is formed on one side of the monocrystalline silicon, the mask layer having at least one opening that exposes the surface of the monocrystalline silicon; Using the mask layer as a mask, isotropic dry etching is performed on the single crystal silicon to form trenches of a predetermined shape; wherein the ratio of the depth of the trench to the width of the opening is greater than or equal to 4; the trench includes a first sub-segment and a second sub-segment that are sequentially moved away from the mask layer; along the direction away from the mask layer, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein the minimum width of the first sub-segment is greater than the width of the opening.

[0006] Optionally, providing monocrystalline silicon includes: providing monocrystalline silicon with a crystal orientation of (110); The sidewall of the first sub-segment is defined by the (111) crystal plane in the monocrystalline silicon.

[0007] Optionally, forming a mask layer on one side of the monocrystalline silicon includes: A mask material layer and a photolithography material layer are sequentially formed on one side of the single-crystal silicon. Pattern the photolithography material layer; Using the patterned photolithography material layer as a mask, the mask material layer is patterned to form the mask layer.

[0008] Optionally, the material of the mask layer includes SiO2.

[0009] Optionally, the thickness of the mask layer is greater than or equal to 20,000 angstroms.

[0010] Optionally, the depth of the second sub-segment is greater than or equal to three times the depth of the first sub-segment.

[0011] Optionally, the etching gas used for isotropic dry etching of the single-crystal silicon includes SF6.

[0012] Optionally, the etching gas may also include O2 and CF4.

[0013] Optionally, after using the mask layer as a mask to perform isotropic dry etching on the single-crystal silicon to form trenches of a predetermined shape, the method further includes: Remove the mask layer.

[0014] According to another aspect of the present invention, a single-crystal silicon with trenches is provided, the single-crystal silicon with trenches being formed by an etching method for single-crystal silicon as described above; the single-crystal silicon includes opposing first and second surfaces, the first surface being provided with the trenches, the trenches including a first sub-segment and a second sub-segment sequentially moving away from the first surface; along the direction away from the first surface, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein, the minimum width of the first sub-segment is greater than the width of the opening.

[0015] According to another aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: The single-crystal silicon with trenches as described above; The gate is located within the trench; The source electrode is located on one side of the single-crystal silicon corresponding to the trench; The drain is located on the other side of the single-crystal silicon.

[0016] The technical solution of this invention employs a single-crystal silicon etching method comprising: providing single-crystal silicon; forming a mask layer on one side of the single-crystal silicon, the mask layer having at least one opening exposing the surface of the single-crystal silicon; using the mask layer as a mask, performing isotropic dry etching on the single-crystal silicon to form a trench of a predetermined shape; wherein the ratio of the trench depth to the opening width is greater than or equal to 4; the trench includes a first sub-segment and a second sub-segment; along the direction away from the mask layer, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein the minimum width of the first sub-segment is greater than the width of the opening. Utilizing the isotropy of dry etching and the crystal orientation dependence of single-crystal silicon, an undercut structure is formed, i.e., the first sub-segment is formed; and further, the ratio of the trench depth to the opening width is set to be large, so that the second sub-segment fully converges, thereby forming a trench structure with a special shape. This single-crystal silicon with a special trench shape has significant application value in fields such as trench MOSFETs.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating an etching method for single-crystal silicon provided in an embodiment of the present invention; Figures 2-4 A schematic diagram of the product structure corresponding to the main steps of an etching method for single-crystal silicon provided in an embodiment of the present invention; Figure 5 for Figure 4 Corresponding scanning electron microscope image; Figure 6 A schematic diagram of a single-crystal silicon structure with trenches provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 A flowchart of an etching method for single-crystal silicon provided in an embodiment of the present invention is shown below. Figure 1 Etching methods for single-crystal silicon include: Step S110: Provide monocrystalline silicon; Specifically, in this embodiment, the single-crystal silicon can be a substrate, or a single-crystal silicon epitaxial layer disposed on a supporting substrate, a single-crystal silicon layer on a silicon-on-insulator top layer, or a single-crystal silicon layer in other multilayer structures. The single-crystal silicon can be formed by chemical vapor deposition, molecular beam epitaxy, or other suitable epitaxial growth methods. The supporting substrate can be a silicon substrate, a silicon-on-insulator substrate, a sapphire substrate, or a silicon carbide substrate, etc.

[0023] Monocrystalline silicon is a common type of silicon wafer used in semiconductor manufacturing. Its crystal orientations include (100), (110), and (111) orientations. Monocrystalline silicon refers to silicon materials where silicon atoms are arranged in a periodic and regular pattern in three-dimensional space. Compared to polycrystalline silicon, monocrystalline silicon exhibits significant crystal orientation dependence during etching. Specifically, the atomic density and bonding energy differ in different crystal orientations of monocrystalline silicon, resulting in varying etching rates. Utilizing this characteristic, when etching monocrystalline silicon, the etching sidewalls can naturally terminate at specific crystal planes with extremely low etching rates, thus forming sidewall morphologies with specific angles and contours. This makes it more conducive to forming trenches of special shapes. In contrast, polycrystalline silicon consists of a large number of tiny grains with varying orientations, and there is no unified crystal orientation within it. During the etching process, grains with different orientations are etched simultaneously, and the differences in etching rates in various directions are averaged out, making it impossible to form sidewalls with regular geometric contours defined by specific crystal planes.

[0024] Furthermore, from an application perspective, polycrystalline silicon contains numerous defects and dangling bonds at its grain boundaries, which significantly affect the electrical performance of semiconductor devices made from it, such as reduced carrier mobility and increased leakage current. Therefore, in high-performance devices, monocrystalline silicon is typically used as the active region or structural material. This invention utilizes the unique crystal orientation dependence of monocrystalline silicon to form special trenches with precise geometric contours within monocrystalline silicon, overcoming the limitation of polycrystalline silicon where the random grain orientation makes precise control of etching morphology impossible.

[0025] Step S120: A mask layer is formed on one side of the monocrystalline silicon. The mask layer has at least one opening that exposes the surface of the monocrystalline silicon. Specifically, Figures 2-4 This is a schematic diagram of the product structure corresponding to the main steps of an etching method for single-crystal silicon provided in an embodiment of the present invention. Figure 5 for Figure 4 Corresponding scanning electron microscope image. (Reference) Figures 2 to 5 First, a mask layer 12 can be formed on the single-crystal silicon 11. The single-crystal silicon 11 may include a first surface S1 and a second surface S2 opposite to each other, wherein the mask layer 12 is located on the first surface S1. The number of openings G1 in the mask layer 12 is the same as the number of trenches to be formed, and their positions correspond. In other words, the mask layer 12 is used to protect the areas of the single-crystal silicon not exposed by the openings G1 during subsequent etching, so that etching only occurs in the area of ​​the openings G1 and the region near the openings G1.

[0026] The material of the mask layer 12 is selected from materials that are resistant to etching of the single-crystal silicon 11. During the etching of the single-crystal silicon, the mask layer 12 basically does not participate in the reaction or the reaction rate is extremely slow, thus acting as a physical barrier. In other words, the etching material has a high selectivity for the mask layer 12 during subsequent etching of the single-crystal silicon 11.

[0027] Step S130: Using the mask layer as a mask, isotropic dry etching is performed on the single crystal silicon to form a trench of a preset shape; wherein, the ratio of the depth of the trench to the width of the opening is greater than or equal to 4; the trench includes a first sub-segment and a second sub-segment that move away from the mask layer in sequence; along the direction away from the mask layer, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein, the minimum width of the first sub-segment is greater than the width of the opening.

[0028] Specifically, in this embodiment, the single-crystal silicon 11 is etched using a dry etching method. For example, the entire structure of the single-crystal silicon 11 and the mask layer 12 is placed in the reaction chamber of a plasma etching apparatus, and an etching gas is introduced into the reaction chamber. The type of etching gas will be described later. By applying radio frequency power, the etching gas is electrified into plasma. Some free radicals in this plasma react chemically with the single-crystal silicon 11 to generate volatile gases, thereby removing the single-crystal silicon exposed at the pattern openings of the mask layer 12. It is understood that because the etching gas has a high etching selectivity for the mask layer 12, the single-crystal silicon in the area covered by the mask layer 12 is retained, and etching only occurs at the opening G1.

[0029] Furthermore, the etching in this embodiment is isotropic etching, meaning that etching occurs not only in the vertical direction but also in the lateral direction. As etching progresses, the depth of trench K1 gradually increases, while the single-crystal silicon 11 beneath the mask layer 12 is etched laterally, forming an undercut structure. Under the corresponding etching parameters, the sidewalls of trench K1 do not exhibit a monotonous change but are divided into sections such as… Figure 4 The two parts shown are: trench K1, comprising a first sub-segment K11 and a second sub-segment K12. Along the depth direction of trench K1, the width of the first sub-segment K11 gradually increases, while the width of the second sub-segment K12 gradually decreases. In other words, starting from the first surface S1, the lateral width of trench K1 first gradually increases to its maximum, then gradually decreases, reaching its minimum at the bottom of trench K1. Overall, the trench K1 in this embodiment is heart-shaped. Figure 5 As shown in the scanning electron microscope image, the etching method for single-crystal silicon described in this application can etch heart-shaped trenches. It should be noted, of course, that... Figure 5 Only Figure 4 A portion of the corresponding scanning electron microscope images.

[0030] Because an isotropic etching method is used, after etching begins from the first surface S1, single-crystal silicon is etched not only vertically but also laterally. Consequently, the minimum width of the first segment K11 is greater than the width of the opening G1. In this embodiment, by further controlling the ratio of the depth of the trench K1 to the width of the opening G1, a trench with a specific shape can be obtained. The depth of the trench K1 is controlled by etching parameters; a ratio of the depth of the trench K1 to the width of the opening G1 greater than 4 ensures that the trench K1 has sufficient depth so that the width convergence of the second segment K12 has sufficient vertical space, thereby allowing the bottom of the trench K1 to form a sharp corner or a small arc. In contrast, if the ratio of the depth of the trench K1 to the width of the opening G1 is small, then the second segment K12 does not have enough vertical space to converge, and the bottom of the trench K1 will be too flat.

[0031] It should be noted that, in this field, undercut structures can be formed using methods such as wet etching. This relies heavily on the significant differences in etching rates for different crystal planes achieved by wet etching. Dry etching, on the other hand, is generally considered difficult to combine with crystal orientation to form a heart-shaped trench. The solution in this embodiment utilizes the isotropic nature of dry etching and the crystal orientation dependence of single-crystal silicon, and sets a large ratio between the trench depth and the opening width, allowing the second segment to fully converge, ultimately achieving a heart-shaped trench.

[0032] The technical solution of this embodiment employs a single-crystal silicon etching method comprising: providing single-crystal silicon; forming a mask layer on one side of the single-crystal silicon, the mask layer having at least one opening exposing the surface of the single-crystal silicon; using the mask layer as a mask, performing isotropic dry etching on the single-crystal silicon to form a trench of a predetermined shape; wherein the ratio of the trench depth to the opening width is greater than or equal to 4; the trench includes a first sub-segment and a second sub-segment; along the direction away from the mask layer, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein the minimum width of the first sub-segment is greater than the width of the opening. Utilizing the isotropy of dry etching and the crystal orientation dependence of single-crystal silicon, an undercut structure is formed, i.e., the first sub-segment is formed; and further, the ratio of the trench depth to the opening width is set to be large, so that the second sub-segment fully converges, thereby forming a trench structure with a special shape. This single-crystal silicon with a special trench shape has significant application value in fields such as trench MOSFETs.

[0033] Optionally, in some implementations, the depth of the second segment K12 is greater than or equal to three times the depth of the first segment K11.

[0034] Specifically, in this embodiment, the depth of the second sub-segment K12 is greater than the depth of the first sub-segment K11, so that the second sub-segment K12 has sufficient vertical space to converge and form a bottom sharp corner. For example, the depth of the second sub-segment K12 can be 3 times, 4 times, or 5 times the depth of the first sub-segment K11, etc.

[0035] Optionally, providing monocrystalline silicon includes: providing monocrystalline silicon with a crystal orientation of (110); wherein the sidewall of the first segment K11 is defined by a (111) crystal plane in the monocrystalline silicon.

[0036] Specifically, in single-crystal silicon with a (110) crystal orientation, there exists a family of (111) crystal planes with densely packed atoms. This family of (111) crystal planes has a definite spatial orientation relationship with the (110) surface of single-crystal silicon. During plasma etching, due to the high atomic density and large bonding energy of the (111) crystal planes, their etching rate is significantly lower than that of other crystal planes, thus playing a self-stopping role in the etching process.

[0037] In (110) oriented single-crystal silicon, the (111) crystal plane is neither parallel nor intersecting with the (110) surface. When the etching gas etches to the (111) crystal plane, the etching rate drops sharply, causing the sidewalls of the trench to extend along the (111) crystal plane direction, which forms the sidewalls of the first sub-segment K11. In other words, the sidewalls of the first sub-segment are defined by the (111) crystal plane in the single-crystal silicon, meaning that in the first sub-segment K11, the sidewalls of the trench K1 extend along the (111) crystal plane direction, and their sidewalls are inclined planes, not arcs. Furthermore, due to the spatial distribution characteristics of the (111) crystal plane in (110) oriented single-crystal silicon, the sidewalls of the first sub-segment K11 are inclined away from the center of the trench K1, thereby causing the width of the first sub-segment K11 to gradually increase away from the mask layer.

[0038] It should be noted that, due to the large ratio between the depth of trench K1 and the width of opening G1, the transport of etching reactants and byproducts is restricted after etching reaches a certain depth. The etching rate decreases significantly in the central region at the bottom of the trench, resulting in an aspect ratio-dependent etching effect. Under the influence of this aspect ratio-dependent effect, the sidewalls of the second segment K12 gradually converge towards the center of trench K1 from the end of the first segment K11, ultimately forming a sharp corner or an arc at the bottom of trench K1.

[0039] It should be noted that if other crystal orientations of single-crystal silicon are used (such as (100) crystal orientation or (111) crystal orientation), the tilt angle and extension direction of the sidewall of the first sub-segment will change due to the different spatial orientation relationship between the (111) crystal plane family and the single-crystal silicon surface, making it difficult to form the "heart" shaped trench of this embodiment. Of course, it can be formed by controlling the etching parameters.

[0040] Optionally, forming a mask layer on one side of the monocrystalline silicon includes: A mask material layer and a photolithography material layer are sequentially formed on one side of a single-crystal silicon; a patterned photolithography material layer is then formed. Specifically, such as Figure 2 As shown, a mask material layer 121 can be formed first, using methods including thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), or spin coating. In a preferred embodiment, the material of the mask material layer 121 includes SiO2. Then, a photolithography material layer 14, such as a photoresist layer, is formed on the mask material layer 121. This can be achieved by transferring a pre-defined pattern from a photomask to the photoresist layer using a photolithography process to form a photoresist mask. Then, using the photolithography material layer 14 as a mask, the mask material layer 121 is etched to form the mask layer 12.

[0041] It should be noted that because the etching gas has relatively low selectivity for the photolithography material layer, if the photolithography material layer is directly used as a mask to etch single-crystal silicon, the photolithography material layer is prone to being etched through during long-term etching, leading to etching failure. In contrast, materials such as SiO2 have extremely high etching selectivity for etching gases, allowing them to remain intact during long-term etching processes.

[0042] Optionally, in some embodiments, the mask layer is made of SiO2. In some embodiments, the mask layer may also be made of SiN.

[0043] Optionally, in some implementations, the thickness of the mask layer is greater than or equal to 20,000 angstroms.

[0044] Specifically, as mentioned above, the width of the second segment K12 gradually decreases, relying on the aspect ratio-dependent etching effect, or etching loading effect, that occurs when the etching reaches a deeper stage. This effect requires the trench to have a large aspect ratio from the very beginning. In this embodiment, the mask layer is relatively thick, resulting in a larger initial depth of the etching gas (i.e., the depth of the opening G1) during trench etching. Under the same lateral etching amount, the aspect ratio-dependent etching effect begins to take effect earlier. Therefore, a thicker mask layer is beneficial for the second segment K12 to begin converging at a suitable depth, thus forming a smooth or sharp-cornered trench bottom. In contrast, if the mask layer is insufficiently thick, the depth ratio of the first segment K11 will be large, and the convergence depth of the second segment K12 will be insufficient, ultimately resulting in a flat or rounded trench bottom, i.e., an inability to form a heart-shaped trench.

[0045] Furthermore, during the plasma etching of single-crystal silicon, although the mask layer has a high selectivity for the etching gas, the etching time is longer and the etching power is higher when the trenches are deeper, causing the mask layer to be slowly consumed. Therefore, this embodiment sets a relatively large mask layer thickness to ensure that the mask layer is never completely etched through during the entire etching process.

[0046] Optionally, in some embodiments, the thickness of the mask layer is 20,000 angstroms, 21,000 angstroms, 22,000 angstroms, 23,000 angstroms, 24,000 angstroms, or 25,000 angstroms, etc.

[0047] Optionally, in some embodiments, the etching gas used for isotropic dry etching of single-crystal silicon includes, in this embodiment, at least sulfur hexafluoride (SF6). SF6 ionizes into a plasma containing fluorine radicals under RF excitation. These fluorine radicals chemically react with single-crystal silicon to generate volatile silicon tetrafluoride (SiF4), thereby removing the silicon. SF6 exhibits a high etching rate for single-crystal silicon and good etching selectivity for mask materials such as silicon dioxide and silicon nitride, making it suitable for etching high aspect ratio trenches.

[0048] Alternatively, in some embodiments, the etching gas may also include oxygen (O2) and carbon tetrafluoride (CF4).

[0049] Specifically, adding oxygen can regulate the etching morphology. Oxygen reacts with silicon etching products and fluorocarbons in the plasma generated during etching, promoting the generation of active fluorine radicals, thereby increasing the etching rate to some extent. Furthermore, the addition of oxygen forms a thin silicon oxide passivation layer on the sidewall of the trench. This passivation layer suppresses the lateral etching rate, thus regulating the sidewall profile of the first segment K11. By precisely controlling the oxygen flow rate ratio, the lateral expansion and sidewall tilt angle of the first segment K11 can be adjusted, making the profile of the first segment of the heart-shaped trench more symmetrical.

[0050] Furthermore, carbon tetrafluoride optimizes the etching selectivity. As a fluorine-containing gas, carbon tetrafluoride can dissociate in plasma to generate fluorine radicals, which can replenish the active species required for the etching reaction. Simultaneously, carbon tetrafluoride can form a fluoropolymer deposition layer on the mask surface and trench sidewalls. This deposition layer enhances the protection of the mask layer and sidewalls, improves the etching selectivity, slows down the mask layer consumption rate, and ensures the integrity of the mask layer during long-term etching.

[0051] Optionally, in some implementations, the etching step can be divided into two stages, namely a first stage and a second stage.

[0052] The first stage lasts for 10 seconds, the reaction chamber pressure is 80 mTorr, the bias power is 0 W, the bias pulse mode is pulsed (duty cycle is 25%), the gas flow rate is: carbon tetrafluoride 180 sccm, oxygen 50 sccm, sulfur hexafluoride 40 sccm, sulfur hexafluoride in the special channel 100 sccm, and the etching temperature is 30°C for the cathode, 70°C for the dome, and 70°C for the chamber wall.

[0053] The second stage lasts for 30 seconds, with a reaction chamber pressure of 80 mTorr, a bias power of 0 W, a bias pulse mode of continuous wave (CW), a source power of 1200 W, a coil power of 25%, and gas flow rates of: carbon tetrafluoride 180 sccm, oxygen 50 sccm, sulfur hexafluoride 40 sccm, and sulfur hexafluoride in the special channel 100 sccm. The etching temperatures are: cathode 30°C, dome 70°C, and chamber wall 70°C.

[0054] It should be noted that the total time for the first and second stages is 40 seconds. The above process parameters are for illustrative purposes only. Those skilled in the art can make appropriate adjustments to the above parameters according to the specific etching equipment and target trench size, for example, by extending the total time of the first and second stages to 60 seconds, 90 seconds or longer, to obtain the desired etching depth and heart-shaped trench.

[0055] Optionally, in some embodiments, after isotropic dry etching of single-crystal silicon to form trenches of a predetermined shape, with the mask layer as a mask, the etching method further includes: removing the mask layer.

[0056] Specifically, the mask layer can be removed using one or more of the following methods in combination: wet etching, dry etching, and chemical mechanical polishing. After removing the mask layer, only the trenched single-crystal silicon is retained for subsequent use.

[0057] Based on the same inventive concept, this invention also provides a single-crystal silicon with trenches, such as... Figure 6 As shown, Figure 6This is a schematic diagram of a trenched monocrystalline silicon structure provided by an embodiment of the present invention. The trenched monocrystalline silicon is formed by the etching method for monocrystalline silicon provided in any embodiment of the present invention. The monocrystalline silicon includes a first surface S1 and a second surface S2 opposite to each other, and a trench K1 is provided on the first surface S1. The trench K1 includes a first sub-segment K11 and a second sub-segment K12 sequentially moving away from the first surface; along the direction away from the first surface, the width of the first sub-segment K11 gradually increases, and the width of the second sub-segment K12 gradually decreases; wherein, the minimum width of the first sub-segment K11 is greater than the width of the opening. The trenched monocrystalline silicon of this embodiment is formed by the etching method for monocrystalline silicon provided in any embodiment of the present invention and has the same beneficial effects, which will not be repeated here.

[0058] Based on the same inventive concept, the present invention also provides a semiconductor device, such as... Figure 7 As shown, Figure 7 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention. The semiconductor device includes a trenched monocrystalline silicon as provided in any embodiment of the present invention. The trenched monocrystalline silicon forms a well region 21, a source N+ region 26, and a P+ implantation region 27, and the trenched monocrystalline silicon is N-type, that is, it also has an N-type drift region. The semiconductor device also includes a gate 23, a source 25, and a drain 29. The gate 23 is located in the trench. The source 23 is located on the surface of the monocrystalline silicon corresponding to the trench, that is, the first surface S1. The drain 29 is located on the second surface S2. The semiconductor device also includes a gate oxide layer 24 and a passivation layer 25. Similar to conventional semiconductor devices, the difference lies in the shape of the trench. In this embodiment, the trench is a heart-shaped trench with a shape that is wider at the top and narrower at the bottom, that is, a larger opening, which is more conducive to the filling of the gate material. This can optimize the electric field distribution at the bottom of the trench and avoid breakdown; it can also increase the surface area of ​​the trench sidewalls, enhance the gate's control over the channel, and reduce the on-resistance.

[0059] For example, the source N+ region 26 may correspond to a portion of the first sub-segment. The well region 21 may correspond to another portion of the first sub-segment and the second sub-segment.

[0060] It should be noted that the semiconductor device is only one application example of the trenched monocrystalline silicon provided in the embodiments of the present invention, and the trenched monocrystalline silicon can also be applied in other fields.

[0061] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0062] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for etching single-crystal silicon, characterized in that, include: Provide monocrystalline silicon; A mask layer is formed on one side of the monocrystalline silicon, the mask layer having at least one opening that exposes the surface of the monocrystalline silicon; Using the mask layer as a mask, isotropic dry etching is performed on the single crystal silicon to form trenches of a predetermined shape; wherein the ratio of the depth of the trench to the width of the opening is greater than or equal to 4; the trench includes a first sub-segment and a second sub-segment that are sequentially moved away from the mask layer; along the direction away from the mask layer, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein the minimum width of the first sub-segment is greater than the width of the opening.

2. The etching method for single-crystal silicon according to claim 1, characterized in that, The provision of monocrystalline silicon includes: providing monocrystalline silicon with a crystal orientation of (110); The sidewall of the first sub-segment is defined by the (111) crystal plane in the monocrystalline silicon.

3. The etching method for single-crystal silicon according to claim 1, characterized in that, Forming a mask layer on one side of the single-crystal silicon includes: A mask material layer and a photolithography material layer are sequentially formed on one side of the single-crystal silicon. Pattern the photolithography material layer; Using the patterned photolithography material layer as a mask, the mask material layer is patterned to form the mask layer.

4. The etching method for single-crystal silicon according to claim 3, characterized in that, The material of the mask layer includes SiO2.

5. The etching method for single-crystal silicon according to claim 1 or 3, characterized in that, The thickness of the mask layer is greater than or equal to 20,000 angstroms.

6. The etching method for single-crystal silicon according to claim 1, characterized in that, The depth of the second sub-segment is greater than or equal to three times the depth of the first sub-segment.

7. The etching method for single-crystal silicon according to claim 1, characterized in that, The etching gas used for isotropic dry etching of the single-crystal silicon includes SF6.

8. The etching method for single-crystal silicon according to claim 7, characterized in that, The etching gas also includes O2 and CF4.

9. A type of single-crystal silicon with trenches, characterized in that, The single-crystal silicon with trenches is formed by the etching method of single-crystal silicon according to any one of claims 1-8; the single-crystal silicon includes opposing first and second surfaces, the first surface is provided with the trenches, the trenches include a first sub-segment and a second sub-segment that are sequentially moved away from the first surface; along the direction away from the first surface, the width of the first sub-segment gradually increases, and the width of the second sub-segment gradually decreases; wherein, the minimum width of the first sub-segment is greater than the width of the opening.

10. A semiconductor device, characterized in that, The semiconductor device includes: The single-crystal silicon with trenches as described in claim 9; The gate is located within the trench; The source electrode is located on one side of the single-crystal silicon corresponding to the trench; The drain is located on the other side of the single-crystal silicon.

Images