3C-SiC composite epitaxial structure based on 4H-SiC and device structure

Abstract

The invention provides a 3C-SiC composite epitaxial structure and device structure based on 4H-SiC, and the composite epitaxial structure comprises a 4H-SiC substrate, an N-type doped epitaxial layer, a P-type doped buried layer, a carrier tunneling region, and a 3C-SiC epitaxial layer. The N-type doped epitaxial layer is arranged on the 4H-SiC substrate; the 3C-SiC epitaxial layer is subjected to secondary epitaxy or bonded on the surface of the N-type doped epitaxial layer; a carrier tunneling region is formed on a contact interface layer of the 3C-SiC epitaxial layer and the N-type doped epitaxial layer; and the P-type doped buried layer ions are implanted into the upper region of the N-type doped epitaxial layer. The structure can effectively solve the problems that in the prior art, when 4H-SiC serves as a substrate to prepare a SiC-MOS device, improvement of interface state density and channel electron mobility is limited, the conduction capacity of the device is poor, and the electrical performance and the long-term reliability are poor. The composite epitaxial structure and the device structure are high in device conduction capability and good in electrical performance and long-term reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a 3C-SiC composite epitaxial structure and a device structure based on 4H-SiC. Background Art

[0002] In the actual design, manufacture and application of power devices, GaN, SiC and Ga 2 O 3 Wide bandgap semiconductor materials can provide a much higher voltage resistance per unit thickness than silicon, but there are various problems in the basic structure and process manufacturing construction of power devices, and they also require a lot of special or high-temperature process processing equipment.

[0003] For example, silicon carbide (SiC) MOSFET devices have always had gate oxide interface states and various reliability issues related to them. SiC materials have many crystal forms, such as 3C-SiC, 4H-SiC and 6H-SiC. Among them, 4H-SiC is the main SiC crystal form used in the preparation of SiC devices due to its wide bandgap and high critical breakdown field strength. However, there are some problems in SiC-MOS devices prepared by 4H-SiC that need to be solved: 1. The existing 4H-SiC MOSFET gate oxide interface quality optimization technology still has limited effects on improving the interface state density and channel electron mobility.

[0004] 2. After 3C-SiC and 4H-SiC are heteroepitaxially grown or bonded together, an electron potential well and potential barrier will be formed at the interface, making it difficult for electrons to flow between 3C-SiC and 4H-SiC, and the conduction ability of the device is very poor.

[0005] 3. Existing technical solutions have limited protection effects on the bottom and corner oxides of the gate trench, especially under extreme electrical stress conditions such as avalanche breakdown or short circuit, the gate dielectric layer is easily damaged.

[0006] 4. Since the diffusion coefficient of impurity elements in SiC materials is extremely low, the doping of SiC materials can often only be achieved through high-temperature ion implantation to form a PN shallow junction. It is difficult to achieve deep junction implantation and high-temperature push junction of P-type doping like Si. Simply increasing the energy of ion implantation will cause damage to the lattice structure of SiC, affecting the electrical performance and long-term reliability of the device.

[0007] 5. 3C-SiC and 4H-SiC heteroepitaxial growth and bonding technology; Ga 2 O 3 3C-SiC heteroepitaxial technology and Ga 2 O 3As 4H-SiC heteroepitaxial technology is not yet mature, there are a large number of lattice defects at the heteroepitaxial / bonding interface; when the device is in the blocking state, these interface layer defects generate electron-hole pairs under the action of a strong electric field, resulting in an increase in the leakage current of the device.

[0008] Based on this, the present invention provides a new 3C-SiC composite epitaxial structure and device structure based on 4H-SiC. Summary of the invention

[0009] Based on the above description, the present invention provides a 3C-SiC composite epitaxial structure and device structure based on 4H-SiC to solve the problems in the prior art of using 4H-SiC as a substrate to prepare SiC-MOS devices, such as limited improvement in interface state density and channel electron mobility, poor device conduction capability, and poor electrical performance and long-term reliability.

[0010] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides a 3C-SiC composite epitaxial structure based on 4H-SiC, comprising: a 4H-SiC substrate, an N-type doped epitaxial layer, a P-type doped buried layer, a carrier tunneling region and a 3C-SiC epitaxial layer; The N-type doped epitaxial layer is disposed on the 4H-SiC substrate; The 3C-SiC epitaxial layer is secondary epitaxially grown or bonded to the surface of the N-type doped epitaxial layer; The contact interface layer between the 3C-SiC epitaxial layer and the N-type doped epitaxial layer forms the carrier tunneling region; The P-type doped buried layer is ion implanted into the upper region of the N-type doped epitaxial layer.

[0011] Based on the above technical solution, the present invention can also be improved as follows.

[0012] Furthermore, the 4H-SiC substrate is an N-type doped 4H-SiC layer; and the 3C-SiC epitaxial layer is an N-type doped 3C-SiC layer.

[0013] Furthermore, the N-type doped epitaxial layer is an N-type doped 4H-SiC layer or an N-type doped Ga 2 O 3 layer.

[0014] Furthermore, the carrier tunneling region is an N-type doped carrier tunneling region.

[0015] Furthermore, the 3C-SiC composite epitaxial structure based on 4H-SiC also includes a P epitaxial buried layer; The P epitaxial buried layer is arranged on the surface of the N-type doped epitaxial layer and between the N-type doped epitaxial layer and the 3C-SiC epitaxial layer.

[0016] Furthermore, the P-type doped buried layer is provided in plurality; and the plurality of P-type doped buried layers are distributed at intervals in the N-type doped epitaxial layer.

[0017] In a second aspect, the present invention further provides a device structure, characterized in that the device structure comprises: a 3C-SiC composite epitaxial structure based on 4H-SiC as described in the first aspect, a P-type doped connection region, a P+ region, an N+ region, a P-well region, a gate, a source and a drain; The P-type doped connection region is connected to the P-type doped buried layer in the 3C-SiC composite epitaxial structure based on 4H-SiC; The P+ region is provided on the 3C-SiC composite epitaxial structure based on 4H-SiC, and the P+ region is in contact and connected with the P-type doped connection region at least in one cross section; The gate is arranged on the upper part of the 3C-SiC epitaxial layer in the 3C-SiC composite epitaxial structure based on 4H-SiC; The P-well region and the N+ region are respectively provided on both sides of the gate in a superimposed manner; the P-well region is located in the upper surface area of ​​the 3C-SiC epitaxial layer, and the N+ region is located on the side of the P-well region away from the substrate of the 3C-SiC composite epitaxial structure based on 4H-SiC; The gate is disposed at a middle position between the P-well region and the N+ region; The source electrode is arranged on the top of the N+ region and the P+ region; The drain is arranged at the bottom of the 4H-SiC based 3C-SiC composite epitaxial structure.

[0018] Based on the above technical solution, the present invention can also be improved as follows.

[0019] Further, the P+ region is contact-connected with the P epitaxial buried layer of the 3C-SiC composite epitaxial structure based on 4H-SiC; Alternatively, the device structure further includes a P-type doped contact region, wherein the P-type doped contact region is disposed around and at the bottom of the gate and is in contact with and connected to the P-type doped buried layer.

[0020] Further, the gate is a trench gate, and the trench gate is arranged at a middle position between the N+ region and the P-well region, and is arranged in the 3C-SiC epitaxial layer of the 3C-SiC composite epitaxial structure based on 4H-SiC; Alternatively, the gate is a planar gate, and a bottom of the planar gate is connected to both the P-well region and the N+ region.

[0021] Furthermore, the device structure also includes a half-enclosed P-type connection layer; The half-enclosed P-type connection layer vertically penetrates the N+ region, P-well region, 3C-SiC epitaxial layer and carrier tunneling region of the 3C-SiC composite epitaxial structure based on 4H-SiC to the P epitaxial buried layer.

[0022] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: The 3C-SiC composite epitaxial structure and device structure based on 4H-SiC provided by the present invention have the following beneficial effects compared with the prior art: The 3C-SiC composite epitaxial structure based on 4H-SiC includes an N-type doped 4H-SiC substrate, an N-type doped epitaxial layer above the 4H-SiC substrate, an N-type doped 3C-SiC epitaxial layer above the N-type epitaxial layer, an epitaxial interface layer naturally generated between the N-type doped epitaxial layer and the 3C-SiC, an N-type doped carrier tunneling region penetrating a portion of the epitaxial interface layer, and a P-type doped buried layer below the N-type doped carrier tunneling region.

[0023] (1) The composite epitaxial structure composed of 3C-SiC and 4H-SiC has a relatively narrow bandgap width at the top of the 3C-SiC, which means that the channel electron mobility of the power device based on 3C-SiC is higher, the threshold stability of the device is higher, and the device can achieve lower on-resistance and higher switching frequency. This alleviates the problem that the existing 4H-SiC MOSFET gate oxide interface quality optimization technology is still limited in improving the interface state density and channel electron mobility.

[0024] (2) In the epitaxial interface layer formed by 3C-SiC and N-type doped epitaxial layer, a high doping concentration N-type region is selectively injected to form a carrier tunneling zone. The high concentration of doping makes the width of the electron potential barrier and electron potential well near the epitaxial interface thinner, and electrons can tunnel through the potential barrier and potential well that they could not pass through before, thereby enhancing the tunneling effect of electrons and reducing the on-resistance of the device. This solves the problem that after 3C-SiC and 4H-SiC are heteroepitaxially grown or bonded together, electron potential wells and potential barriers are formed at the interface, making it difficult for electrons to flow between 3C-SiC and 4H-SiC, and the on-resistance of the device is very poor.

[0025] (3) A P-type doped buried layer is provided below the carrier tunneling region, which can shield the excessive drain potential from passing through the carrier tunneling layer, thereby reducing the electric field strength of the gate oxide in the 3C-SiC epitaxial layer, thereby protecting the gate oxide of the power device. This solves the problem that the existing technical solutions have limited protection effects on the bottom and corner oxides of the gate trench, especially the gate dielectric layer is easily damaged under extreme electrical stress conditions such as avalanche breakdown or short circuit.

[0026] (4) The P-type doped buried layer is formed during the epitaxial growth process, avoiding the need for high-energy implantation after the epitaxy is fully formed, thus reducing damage to the epitaxial layer lattice. This solves the problem that due to the extremely low diffusion coefficient of impurity elements in SiC materials, the doping of SiC materials can only be done through high-temperature ion implantation to form a PN shallow junction, and it is difficult to achieve deep junction implantation and high-temperature push-junction of P-type doping like Si. Increasing the energy of ion implantation blindly will damage the lattice structure of SiC, affecting the electrical performance and long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic structural diagram of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Example 1 of the present invention; Figure 2 A schematic diagram of the structure of a device provided in Embodiment 2 of the present invention; Figure 3 and Figure 4 Two grounding methods and structural diagrams of P-type doped buried layers provided in Embodiment 2 of the present invention; Figure 5 and Figure 6 A schematic diagram of the distribution of multiple P-type doped buried layers in the composite epitaxial structure provided in Example 3 of the present invention; Figure 7 A schematic structural diagram of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Example 4 of the present invention; Figure 8 A schematic structural diagram of a corresponding device structure provided in Embodiment 4 of the present invention; Fig. 9 A schematic structural diagram of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Example 5 of the present invention; Fig.10 A schematic diagram of the structure of a device provided in Example 6 of the present invention; Fig.11 A schematic diagram of the structure of a device provided in Example 7 of the present invention; Fig.12 A schematic diagram of the structure of a device provided in Example 8 of the present invention; Fig.13A schematic diagram of the structure of a device provided in Example 9 of the present invention; Fig.14 and Fig.15 A schematic diagram of the structure of a device provided in Embodiment 10 of the present invention; Fig.16 A schematic diagram of the structure of a device provided in Embodiment 11 of the present invention; Fig.17 A schematic structural diagram of a device structure provided in Embodiment 12 of the present invention; Figures 18 to 26 A cell layout diagram provided in Example 13 of the present invention; Fig. 27 and 28 A cross-sectional view of a cellular layout provided in Example 13 of the present invention; Fig.29 A schematic diagram of the structure of a device provided in Embodiment 14 of the present invention; Fig.30 A schematic diagram of the preparation process of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Example 15 of the present invention; In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. 4H-SiC substrate; 2. N-type doped epitaxial layer; 3. P-type doped buried layer; 4. Carrier tunneling region; 5. 3C-SiC epitaxial layer; 6. P-type doped connection region; 7. P-type doped connection region; 8. P+ region; 9. N+ region; 10. P-well region; 11. P epitaxial buried layer; 12. Deep P+ source; 13. Half-enclosed P-type connection layer; 14. Gate; 15. Source; 16. Drain. DETAILED DESCRIPTION

[0028] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0029] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0030] Example 1 like Figure 1 As shown, this embodiment provides an integrated structure based on a multi-material composite substrate, such as Figure 1 As shown, it includes: a 4H-SiC substrate 1, an N-type doped epitaxial layer 2, a P-type doped buried layer 3, a carrier tunneling region 4 and a 3C-SiC epitaxial layer 5.

[0031] The N-type doped epitaxial layer 2 is disposed on the 4H-SiC substrate 1 .

[0032] The 4H-SiC substrate 1 is an N-type doped 4H-SiC layer; the N-type doped epitaxial layer 2 is an N-type doped 4H-SiC layer or an N-type doped Ga 2 O 3 In this embodiment, a 4H-SiC layer is used as the N-type doped epitaxial layer 2 as a specific example for introduction.

[0033] The 3C-SiC epitaxial layer 5 is secondary epitaxially grown or bonded to the surface of the N-type doped 4H-SiC epitaxial layer.

[0034] The 3C-SiC epitaxial layer 5 is an N-type doped 3C-SiC layer.

[0035] That is, the 3C-SiC epitaxial layer 5 is located at the top of the structure, which has the following effect: the 3C-SiC at the top has a relatively narrow bandgap width, which means that the channel electron mobility of the power device prepared based on 3C-SiC is higher, the threshold stability of the device is higher, and the device can achieve lower on-resistance and higher switching frequency.

[0036] A carrier tunneling region 4 is formed at the contact interface layer between the 3C-SiC epitaxial layer 5 and the N-type doped epitaxial layer 2 ; and ions of the P-type doped buried layer 3 are implanted into the upper region of the N-type doped epitaxial layer 2 .

[0037] The carrier tunneling region 4 is an N-type doped carrier tunneling region.

[0038] It should be noted that the contact interface layer is naturally generated between the two epitaxial materials, rather than being intentionally set. Figure 1 As shown, the N-type doped carrier tunneling region 4 penetrates part of the epitaxial interface layer.

[0039] Specifically, a high-doping concentration N-type region (carrier tunneling region 4) is selectively injected into the 3C-SiC and 4H-SiC epitaxial interface layers. The high-concentration doping makes the width of the electron potential barrier and the electron potential well near the epitaxial interface thinner. Electrons can tunnel through the potential barriers and potential wells that they could not pass through originally, thereby enhancing the tunneling effect of electrons and reducing the on-resistance of the device.

[0040] Specifically, a P-type doped buried layer 3 is arranged below the carrier tunneling region 4. The P-type doped buried layer 3 can shield the excessive drain 16 potential from passing through the carrier tunneling layer, thereby reducing the electric field strength of the gate 14 oxide in the 3C-SiC epitaxial layer 5, thereby protecting the gate 14 oxide of the power device.

[0041] This embodiment provides two grounding methods and structural diagrams of the P-type doped buried layer 3. Figure 3 and Figure 4 The two device interfaces shown are used for Figure 2 The device structure interface in the device realizes the grounding of the P+ doped buried layer.

[0042] The P-type buried layer is formed during the epitaxial growth process, which avoids the need for high-energy injection after the epitaxy is fully formed, thereby reducing damage to the epitaxial layer lattice.

[0043] Example 2 like Figure 2 As shown, this embodiment provides a device structure, including: a 3C-SiC composite epitaxial structure based on 4H-SiC as in Example 1, a P-type doped connection region 6, a P+ region 8, an N+ region 9, a P-well region 10, a gate 14, a source 15 and a drain 16.

[0044] The P-type doped connection region 6 is provided in the P-type doped buried layer 3 in the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0045] The P+ region 8 is disposed on the 3C-SiC composite epitaxial structure based on 4H-SiC, and the P+ region 8 is in contact and connected with the P-type doped connection region 6 at least in one cross section.

[0046] In this embodiment, the gate 14 is a trench gate, and the gate 14 is disposed on the upper portion of the 3C-SiC epitaxial layer 5 in the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0047] A P-well region 10 and an N+ region 9 are respectively provided on both sides of the gate 14. The P-well region 10 is located in the upper surface area of ​​the 3C-SiC epitaxial layer 5, and the N+ region 9 is located on the side of the P-well region 10 away from the substrate in the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0048] The gate 14 further includes a P-type doped grounding region 7 , which is disposed around and at the bottom of the gate 14 and is in contact with the P-type doped buried layer 3 .

[0049] It should be noted that: in actual operation, the structural interface that can conduct current ( Figure 2 The device cross section in the figure), and the device interface that cannot conduct current ( Figure 3 The cross section in the device can be freely combined to control the distribution of current in the device, thereby enhancing the extreme stress reliability of the device.

[0050] The source 15 is disposed on top of the N+ region 9 and the P+ region 8 .

[0051] The drain 16 is disposed at the bottom of the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0052] Example 3 Based on Example 1, the difference from Example 1 is that: In this embodiment, a plurality of P-type doped buried layers are provided; the plurality of P-type doped buried layers are distributed in the N-type doped epitaxial layer at intervals. The plurality here refers to 2 or more.

[0053] Specifically, Figure 5 As shown, there are two P-type doped buried layers 3 in 4H-SiC, one above and one below; Figure 6 As shown, there are three P-type doped buried layers 3 in 4H-SiC, one on top and two on the bottom, the upper one is located in the middle area, and the two on the bottom are located on both sides respectively; more than one layer of P-type doped buried layer can be set in 4H-SiC, the advantage of which is that better electric field shielding effect can be achieved; and the P-type doped buried layers between different layers can adopt a staggered distribution or a completely different distribution.

[0054] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0055] Example 4 Based on Example 1, the difference from Example 1 is that: In this embodiment, if Figure 7 As shown, the 3C-SiC composite epitaxial structure based on 4H-SiC further includes a P epitaxial buried layer 11; the P epitaxial buried layer 11 is arranged on the surface of the N-type doped epitaxial layer and between the N-type doped epitaxial layer and the 3C-SiC epitaxial layer.

[0056] Specifically, Figure 7 As shown, a sandwich epitaxy of N-type 4H-SiC, P-type 4H-SiC, and N-type 3C-SiC can be formed on the surface of 4H-SiC by epitaxy / injection. The P epitaxial buried layer can not only shield the drain potential and enhance the reliability of the gate oxide like the P-type doped buried layer, but also shield the leakage current caused by defects in the interface layer of 3C-SiC and 4H-SiC in the blocking state, thereby reducing the power consumption of the device under blocking conditions.

[0057] In addition, the P epitaxial buried layer 11 can also serve as the P-type doped connection region in Embodiment 2, such as Figure 8 shown.

[0058] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0059] Example 5 Based on Example 1, the difference from Example 1 is that: 3C-SiC and 4H-SiC in epitaxial materials can be replaced by other semiconductor materials, such as Fig. 9As shown, for example, 4H-SiC is replaced with Ga, which has a stronger pressure resistance. 2 O 3 Material.

[0060] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0061] Example 6 Based on Example 2, the difference from Example 2 is that: In this embodiment, the gate 14 is a planar gate. Fig.10 As shown, the bottom of the planar gate is connected to both the P-well region and the N+ region.

[0062] The power device based on the composite epitaxial wafer can be a planar gate MOSFET, IGBT or other device structures. That is, a composite epitaxial structure proposed in this patent can be used to prepare various existing semiconductor device structures.

[0063] For the rest of the same structures, please refer to the introduction of Example 2 and will not be repeated here.

[0064] Example 7 Based on Example 2, the difference from Example 2 is that: In this embodiment, Fig.11 As shown, in the device structure, a deep P+ source 12 is constructed above the P+ region. The deep P+ source 12 can be formed by a source auxiliary trench. The advantage of this is that the source contact area is increased and the on-resistance of the device is reduced.

[0065] For the rest of the same structures, please refer to the introduction of Example 2 and will not be repeated here.

[0066] Example 8 Based on Example 2 and Example 7, the difference from Example 7 is that: In this embodiment, Fig.12 As shown, the material filled in the source auxiliary trench can be replaced by the insulating medium with the source metal. The advantage of this is that the energy of P+ source ion implantation can be reduced and the damage to the crystal lattice can be reduced.

[0067] For the rest of the same structures, please refer to the introduction of Example 2 and will not be repeated here.

[0068] Example 9 Based on Example 2 and Example 8, the difference from Example 8 is that: In this embodiment, Fig.13 As shown, the source metal in the auxiliary trench can contact the N-type doped 3C-SiC to form a Schottky diode, thereby improving the third quadrant freewheeling characteristics of the device.

[0069] For the rest of the same structures, please refer to the introduction of Example 2 and will not be repeated here.

[0070] Example 10 Based on Example 2, the difference from Example 2 is that: In this embodiment, Fig.14 As shown, a half-wrapped P-type connection layer 13 can be introduced at one of the corners of the trench, and the half-wrapped P-type buried layer 13 needs to wrap one side of the trench gate; the half-wrapped P-type connection layer 13 short-circuits the P-type doped buried layer and the source to achieve grounding. The half-wrapped P-type connection layer 13 can not only provide better protection for the trench gate oxide layer, but also reduce the cell size of the device.

[0071] The half-wrapped P-type connection layer 13 is not completely continuous, but is periodically distributed. Fig.15 shown.

[0072] For the rest of the same structures, please refer to the introduction of Example 2 and will not be repeated here.

[0073] Embodiment 11 Based on Example 2, the difference from Example 2 is that: In this embodiment, Fig.16 As shown, the carrier tunneling region 4 and the groove of the device do not need to appear correspondingly in the vertical direction, which means that the epitaxial structure of this patent has lower requirements on the device preparation process and a greater design margin.

[0074] For the rest of the same structures, please refer to the introduction of Example 2 and will not be repeated here.

[0075] Example 12 Based on Example 1, the difference from Example 1 is that: In this embodiment, Fig.17 As shown, the carrier tunneling region 4 may not be continuous, but may be periodically and discontinuously distributed. The advantage of this is that the current distribution can be dispersed. The top view is shown in FIG. Fig.17 shown.

[0076] It should be noted that the carrier tunneling region, the P-type doped buried layer, and the P-type doped connection region may be distributed discontinuously in space.

[0077] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0078] Embodiment 13 Based on Example 2, the difference from Example 2 is that: In this embodiment, the cell layout can be square cells, strip cells and hexagonal cells, and the corresponding examples are as follows: Figures 18 to 26 As shown, the screenshot of side A is as follows Fig. 27 As shown, the screenshot of side B is as follows Fig.28 shown.

[0079] Embodiment 14 Based on Example 2 and Example 7, the difference from Example 2 is that: In this embodiment, Fig.29 As shown, the area of ​​the P-type doped connection region can be adjusted, and it is only necessary to ensure that any P-type doped buried layer is in contact with at least one P-type doped connection region, and the P-type doped connection region is in contact with at least one deep P+ source.

[0080] Embodiment 15 In order to facilitate the understanding of the 3C-SiC composite epitaxial structure based on 4H-SiC provided in Example 1, Fig.30 As shown, this embodiment provides a preparation method thereof: Step S1: preparing a 4H-SiC substrate; Step S2: growing a 4H-SiC epitaxial layer on a 4H-SiC substrate; Step S3: ion implantation in the 4H-SiC epitaxial layer to form a P-type doped buried layer; Step S4: forming an N-type doped 3C-SiC epitaxial layer on the surface of the 4H-SiC epitaxial layer by secondary epitaxy / bonding; Step S5: selectively implanting a high-doping concentration N-type region into the 3C-SiC and 4H-SiC epitaxial interface layers to form a carrier tunneling region.

[0081] That is, the 3C-SiC composite epitaxial structure based on 4H-SiC provided in Example 1 is obtained.

[0082] In summary, the composite epitaxial structures and corresponding manufacturing methods, as well as the corresponding device structures provided in the above-mentioned embodiments 1 to 15 all have the following technical effects: (1) The composite epitaxial structure composed of 3C-SiC and 4H-SiC has a relatively narrow bandgap width at the top of the 3C-SiC, which means that the channel electron mobility of the power device based on 3C-SiC is higher, the threshold stability of the device is higher, and the device can achieve lower on-resistance and higher switching frequency. This alleviates the problem that the existing 4H-SiC MOSFET gate oxide interface quality optimization technology is still limited in improving the interface state density and channel electron mobility.

[0083] (2) In the epitaxial interface layer formed by 3C-SiC and N-type doped epitaxial layer, a high doping concentration N-type region is selectively injected to form a carrier tunneling zone. The high concentration of doping makes the width of the electron potential barrier and electron potential well near the epitaxial interface thinner, and electrons can tunnel through the potential barrier and potential well that they could not pass through before, thereby enhancing the tunneling effect of electrons and reducing the on-resistance of the device. This solves the problem that after 3C-SiC and 4H-SiC are heteroepitaxially grown or bonded together, electron potential wells and potential barriers are formed at the interface, making it difficult for electrons to flow between 3C-SiC and 4H-SiC, and the on-resistance of the device is very poor.

[0084] (3) A P-type doped buried layer is provided below the carrier tunneling region, which can shield the excessive drain potential from passing through the carrier tunneling layer, thereby reducing the electric field strength of the gate oxide in the 3C-SiC epitaxial layer, thereby protecting the gate oxide of the power device. This solves the problem that the existing technical solutions have limited protection effects on the bottom and corner oxides of the gate trench, especially the gate dielectric layer is easily damaged under extreme electrical stress conditions such as avalanche breakdown or short circuit.

[0085] (4) The P-type doped buried layer is formed during the epitaxial growth process, avoiding the need for high-energy implantation after the epitaxy is fully formed, thus reducing damage to the epitaxial layer lattice. This solves the problem that due to the extremely low diffusion coefficient of impurity elements in SiC materials, the doping of SiC materials can only be done through high-temperature ion implantation to form a PN shallow junction, and it is difficult to achieve deep junction implantation and high-temperature push-junction of P-type doping like Si. Increasing the energy of ion implantation blindly will damage the lattice structure of SiC, affecting the electrical performance and long-term reliability of the device.

[0086] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3C-SiC composite epitaxial structure based on 4H-SiC, characterized in that: include: 4H-SiC substrate, N-type doped epitaxial layer, P-type doped buried layer, carrier tunneling region and 3C-SiC epitaxial layer; The N-type doped epitaxial layer is disposed on the 4H-SiC substrate; The 3C-SiC epitaxial layer is secondary epitaxially grown or bonded to the surface of the N-type doped epitaxial layer; The contact interface layer between the 3C-SiC epitaxial layer and the N-type doped epitaxial layer forms the carrier tunneling region; The P-type doped buried layer is ion implanted into the upper region of the N-type doped epitaxial layer.

2. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 1, characterized in that: The 4H-SiC substrate is an N-type doped 4H-SiC layer; and the 3C-SiC epitaxial layer is an N-type doped 3C-SiC layer.

3. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 2, characterized in that: The N-type doped epitaxial layer is an N-type doped 4H-SiC layer or an N-type doped Ga2O3 layer.

4. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 3, characterized in that: The carrier tunneling region is an N-type doped carrier tunneling region.

5. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 4, characterized in that: The 3C-SiC composite epitaxial structure based on 4H-SiC further includes a P epitaxial buried layer; The P epitaxial buried layer is arranged on the surface of the N-type doped epitaxial layer and between the N-type doped epitaxial layer and the 3C-SiC epitaxial layer.

6. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 1, characterized in that: The P-type doped buried layer is provided in plurality; the plurality of P-type doped buried layers are distributed at intervals in the N-type doped epitaxial layer.

7. A device structure, characterized in that: The device structure comprises: a 3C-SiC composite epitaxial structure based on 4H-SiC according to any one of claims 1 to 6, a P-type doped connection region, a P+ region, an N+ region, a P-well region, a gate, a source and a drain; The P-type doped connection region is provided in a P-type doped buried layer in the 3C-SiC composite epitaxial structure based on 4H-SiC; The P+ region is provided on the 3C-SiC composite epitaxial structure based on 4H-SiC, and the P+ region is in contact and connected with the P-type doped connection region at least in one cross section; The gate is arranged on the upper part of the 3C-SiC epitaxial layer in the 3C-SiC composite epitaxial structure based on 4H-SiC; The P-well region and the N+ region are respectively provided on both sides of the gate in a superimposed manner; the P-well region is located in the upper surface area of ​​the 3C-SiC epitaxial layer, and the N+ region is located on the side of the P-well region away from the substrate of the 3C-SiC composite epitaxial structure based on 4H-SiC; The source electrode is arranged on the top of the N+ region and the P+ region; The drain is arranged at the bottom of the 4H-SiC based 3C-SiC composite epitaxial structure.

8. The device structure according to claim 7, characterized in that: The P+ region is in contact with the P epitaxial buried layer of the 3C-SiC composite epitaxial structure based on 4H-SiC; Alternatively, the device structure further includes a P-type doped contact region, wherein the P-type doped contact region is disposed around and at the bottom of the gate and is in contact with and connected to the P-type doped buried layer.

9. The device structure according to claim 7, characterized in that: The gate is a trench gate, and the trench gate is arranged at a middle position between the N+ region and the P-well region, and is arranged in the 3C-SiC epitaxial layer of the 3C-SiC composite epitaxial structure based on 4H-SiC; Alternatively, the gate is a planar gate, and a bottom of the planar gate is connected to both the P-well region and the N+ region.

10. The device structure according to claim 7, characterized in that: The device structure also includes a half-wrapped P-type connection layer; The half-enclosed P-type connection layer vertically penetrates the N+ region, P-well region, 3C-SiC epitaxial layer and carrier tunneling region of the 3C-SiC composite epitaxial structure based on 4H-SiC to the P epitaxial buried layer.

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