Semiconductor structure and method of fabricating the same

Abstract

Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. The method comprises: providing a functional layer, the top surface of the functional layer having a groove; forming a filling layer, the filling layer being filled in at least the groove, the filling layer being doped with target ions; and performing first annealing treatment on the filling layer. The method can improve the filling effect and the top surface profile of the filling layer, thereby improving the quality of the filling layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor technology, the size of semiconductor devices is constantly decreasing, while the aspect ratio (AR) of structures such as gaps and holes is further increasing. For example, the aspect ratio of related structures in 32nm process is usually greater than 10:1. When depositing films within these structures, the quality of the resulting films is relatively poor. Summary of the Invention

[0003] This application provides a semiconductor structure and a method for fabricating the same.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, including:

[0005] A functional layer is provided, the top surface of which has grooves;

[0006] A filling layer is formed, the filling layer at least filling the trench, and the filling layer is doped with target ions; and

[0007] The filler layer is subjected to a first annealing process.

[0008] In some possible implementations, forming the filler layer further includes:

[0009] The filling layer is formed by a deposition process, the deposition process including a first deposition and a second deposition, wherein the first deposition and / or the second deposition includes the introduction of a gas containing the target ions.

[0010] In some possible implementations, the deposition process further includes a third deposition, and forming the filler layer by the deposition process further includes:

[0011] A first film layer is formed by the first deposition, and the first film layer at least covers the sidewalls and bottom wall of the trench;

[0012] A second film layer is formed by the second deposition, the second film layer covering the top surface of the first film layer and filling the trench;

[0013] A third film layer is formed by the third deposition, the third film layer covers the second film layer, and the third film layer, the second film layer and the first film layer form the filling layer;

[0014] The third deposition includes introducing a gas containing the target ions.

[0015] In some possible implementations, a second annealing process is performed after at least one of the first deposition and the second deposition.

[0016] In some possible implementations, the method further includes:

[0017] The filling layer is planarized.

[0018] In some possible implementations, the target ion includes boron ions, and the filling layer is made of silicon oxide.

[0019] In some possible implementations, the precursor for the first deposition and / or the second deposition comprises ethyl silicate and an oxygen-containing gas, wherein the gas containing the target ion comprises borane.

[0020] In some possible implementations, the functional layer includes a substrate, the top surface of which forms the trench.

[0021] In some possible implementations, the functional layer includes a dielectric layer and a conductive layer disposed on the dielectric layer;

[0022] The trench is formed within the conductive layer, and the trench exposes the top surface of the dielectric layer.

[0023] Secondly, embodiments of this application provide a semiconductor structure, including:

[0024] A functional layer, the top surface of which has grooves;

[0025] A filling layer, which at least fills the trench, is formed by doping the filling layer with target ions and undergoing a first annealing treatment. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0027] Figure 1 This is a diagram illustrating the film deposition process.

[0028] Figure 2 A schematic diagram of a cavity;

[0029] Figure 3 This is a schematic diagram of the gap;

[0030] Figure 4 A flowchart illustrating the method for fabricating the semiconductor structure provided in this application;

[0031] Figure 5 A schematic diagram of the functional layer provided in this application;

[0032] Figure 6 Another schematic diagram of the functional layer provided in this application;

[0033] Figure 7 This is a schematic diagram showing the filling layer after it has been formed, as provided in this application.

[0034] Figure 8 This is a partial schematic diagram of the filling layer provided in this application.

[0035] Explanation of reference numerals in the attached figures:

[0036] 11-film layer;

[0037] 12-Void;

[0038] 13- Gap;

[0039] 20-Functional layer;

[0040] 21-Groove;

[0041] 22-Substrate;

[0042] 23-Dielectric layering;

[0043] 24-Conductive layering;

[0044] 30 - Filler layer.

[0045] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0047] See related technologies. Figures 1 to 3 The upper end of the trench is usually at a right angle, and the filling speed is relatively fast when the membrane layer 11 fills the trench. The upper end of the trench is often blocked first, and the membrane layer 11 inside the trench forms gaps 13 (Seam) or voids 12 (Void), making it difficult to form a good filling. The flatness of the top surface of the membrane layer 11 outside the trench is poor, and its quality is poor.

[0048] The semiconductor structure fabrication method provided in this application improves the filling ability of the filling layer in the trench by doping the filling layer with target ions, so that the filling layer is reflowed under the promotion of the target ions during the first annealing process, thereby reducing the gaps or voids in the filling layer in the trench and improving the filling effect; and / or, reducing the height difference of the filling layer, improving the flatness of the top surface of the filling layer, improving the morphology of the filling layer, and thus improving the quality of the filling layer.

[0049] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0050] See Figure 4 This application provides a method for fabricating a semiconductor structure, which specifically includes the following steps:

[0051] In step S100, a functional layer is provided, the top surface of which has grooves.

[0052] See Figure 5 and Figure 6 The functional layer 20 can be a single layer or a stack of layers, and the trench 21 is formed on the top surface of the functional layer 20, wherein the top surface of the functional layer 20 is the upper surface of the functional layer 20. In some possible examples, the bottom of the trench 21 is located within the functional layer 20, that is, the trench 21 does not penetrate the functional layer 20. In other possible examples, the trench 21 may penetrate the functional layer 20.

[0053] Taking a plane perpendicular to the extension direction of the trench 21 as a cross-section, the cross-section of the trench 21 can be rectangular, trapezoidal, etc., and the depth-to-width ratio of the trench 21 can be greater than or equal to 10. Multiple trenches 21 can be present, spaced apart from each other. The embodiments of this application do not limit the structure of the functional layer 20, nor the shape or number of the trenches 21.

[0054] In some possible implementations, such as Figure 5As shown, the functional layer 20 includes a substrate 22, with a trench 21 formed on the top surface of the substrate 22. The substrate 22 can be a semiconductor substrate, and its material includes, but is not limited to, silicon, germanium, silicon germanide, arsenic germanide, silicon on insulator (SOI), and germanium on insulator (GOI). The trench 21 can be a trench in shallow trench isolation (STI), and the trench 21 is subsequently filled with insulating material.

[0055] In some other possible implementations, such as Figure 6 As shown, the functional layer 20 includes a dielectric layer 23 and a conductive layer 24 disposed on the dielectric layer 23. A trench 21 is formed within the conductive layer 24, exposing the top surface of the dielectric layer 23. The dielectric layer 23 is made of an insulating material, while the conductive layer 24 can be made of metal. The trench 21 penetrates the conductive layer 24 and extends to the dielectric layer 23, exposing the surface of the dielectric layer 23 within the trench 21.

[0056] In step S200, a filling layer is formed, which at least fills the trench, and the filling layer is doped with target ions.

[0057] See Figure 6 and Figure 7 The filler layer 30 can be deposited and formed, and the filler layer 30 at least fills the trench 21; in other words, the filler layer 30 can at least fill a portion of the trench 21. For example, the filler layer 30 fills the bottom of the trench 21, that is, the top surface of the filler layer 30 is lower than the top surface of the functional layer 20. Another example is that the filler layer 30 fills the trench 21, that is, the top surface of the filler layer 30 is flush with the top surface of the functional layer 20. Yet another example is that the filler layer 30 completely fills the trench 21 and covers the functional layer 20, with the top surface of the filler layer 30 higher than the top surface of the functional layer 20.

[0058] The filling layer 30 is doped with target ions, which are non-metallic elements and have minimal impact on the electrical properties of the semiconductor structure. The target ions are related to the material of the filling layer 30; for example, the target ions include boron ions, and the material of the filling layer 30 includes silicon oxide. Utilizing the target ions can improve the filling capacity and / or surface morphology of the filling layer 30.

[0059] It is understood that the position of the target ions within the filling layer 30 is not limited. For example, the filling layer 30 adjacent to the walls of trench 21 may be doped with target ions, while the filling layer 30 outside trench 21 may not be doped with target ions. Another example is that the filling layer 30 adjacent to the walls of trench 21 may not be doped with target ions, while the filling layer 30 outside trench 21 may be doped with target ions. Yet another example is that the entire filling layer 30 may be relatively uniformly doped with target ions. The walls of trench 21 include the trench 21 and / or its bottom wall.

[0060] In some possible implementations, the target ions are doped during the formation of the filling layer 30, for example, by forming the filling layer 30 through a deposition process, during which a gas containing the target ions is introduced throughout or part of the deposition of the filling layer 30, the gas dissociates to form a plasma of the target ions, and is doped into the filling layer 30 as the filling layer 30 is deposited.

[0061] In some other possible implementations, the target ions are implanted after the filling layer 30 is formed. For example, after the filling layer 30 is formed, ion implantation is performed on the filling layer 30 to dope the target ions into the filling layer 30.

[0062] In step S300, the fill layer undergoes a first annealing process.

[0063] During the first annealing treatment of the filler layer 30, the target ions can lower the glass reflow temperature of the filler layer 30, enabling the filler layer 30 to reflow, thereby improving the filling effect of the trench 21 of the filler layer 30 and / or the surface profile of the filler layer 30. The temperature of the first annealing treatment is 800℃ to 1200℃, for example, 1100℃.

[0064] It is understandable that when the filling layer 30 in the trench 21 is doped with target ions, the first annealing treatment can promote the reflow of the filling layer 30 in the trench 21, improve the filling ability of the filling layer 30 in the trench 21, reduce the gaps or voids in the filling layer 30 in the trench 21, and improve the filling effect.

[0065] It is also understandable that when the filling layer 30 outside the trench 21 is doped with target ions, the first annealing treatment can promote the reflow of the filling layer 30 outside the trench 21, reduce the height difference of the filling layer 30, improve the flatness of the top surface of the filling layer 30, and improve the morphology of the filling layer 30.

[0066] In the semiconductor structure fabrication method of this application embodiment, the top surface of the functional layer 20 has a trench 21, and the formed filling layer 30 fills at least the trench 21. The filling layer 30 is doped with target ions, and the filling layer 30 undergoes a first annealing treatment. In this way, during the first annealing treatment, the target ions lower the glass reflow temperature of the filling layer 30, allowing the filling layer 30 to achieve a glass circuit at a lower temperature. This can improve the filling ability of the filling layer 30 to fill the trench 21, reduce gaps or voids in the filling layer 30 within the trench 21, and improve the filling effect; and / or, reduce the height difference of the filling layer 30, improve the flatness of the top surface of the filling layer 30, improve the morphology of the filling layer 30, and thus improve the quality of the filling layer 30.

[0067] In some possible implementations, forming the filler layer 30 includes: forming the filler layer through a deposition process, the deposition process including a first deposition and a second deposition, wherein the first deposition and the second deposition include the introduction of a gas containing target ions. The filler layer formed by the first deposition and the second deposition can fill the trench 21. This allows for control of the deposition rate, adjusting the deposition rate according to the formation location to improve efficiency; and also allows for the doping of target ions into the filler layer 30 at different locations as needed.

[0068] For example, a gas containing target ions is introduced during the first deposition, causing the film formed by the first deposition to be doped with target ions. Also for example, a gas containing target ions is introduced during the second deposition, causing the film formed by the second deposition to be doped with target ions. Still for example, a gas containing target ions is introduced during both the first and second depositions, causing the film formed by the first and second depositions to be doped with target ions.

[0069] In the first deposition process, a gas containing target ions is introduced, and the first film layer is doped with the target ions. The first film layer is then reflowed under the first annealing treatment, which reduces gaps in the filler layer 30 and improves the filling effect. Similarly, in the second deposition process, a gas containing target ions is introduced, and the second film layer is doped with the target ions. The second film layer is then reflowed under the first annealing treatment, which reduces voids in the filler layer 30 and improves the filling effect.

[0070] In some possible implementations, the deposition process further includes a third deposition, and the formation of the filling layer 30 by the deposition process further includes: forming a first film layer by a first deposition, the first film layer at least covering the sidewalls and bottom wall of the trench; forming a second film layer by a second deposition, the second film layer covering the top surface of the first film layer and filling the trench; forming a third film layer by a third deposition, the third film layer covering the second film layer, the third film layer, the second film layer and the first film layer forming the filling layer 30, wherein the third deposition includes the introduction of a gas containing target ions.

[0071] In this process, the first deposition forms the first film layer. The deposition rate of the first deposition is relatively low, and the flow rate of the corresponding gas (e.g., precursor) is also low. That is, the first deposition is a low-flow, low-velocity deposition to achieve a uniform base layer. The first film layer is of approximately uniform thickness, around 800 angstroms.

[0072] The second deposition forms a second film layer. The deposition rate of the second deposition is relatively low, and the corresponding gas flow rate is increased. That is, the second deposition is a high-flow-rate, low-velocity deposition to facilitate rapid filling. The top surface of the second film layer is higher than the top surface of the functional layer 20.

[0073] The third deposition forms a third film layer. The deposition rate of the third deposition is relatively high, and the corresponding gas flow rate is increased, that is, the third deposition is a high-flow-rate, high-speed deposition to facilitate rapid deposition. The third film layer, the second film layer, and the first film layer form a filling layer 30.

[0074] The third deposition involves introducing a gas containing target ions. The third film layer outside trench 21 is doped with target ions, and the third film layer itself is also doped with target ions. During the first annealing treatment, the third film layer is reflowed, which can reduce the height difference at the top surface of the filler layer 30 (see...). Figure 8 As shown at point H in the middle, it improves the contour, reduces the height difference of the filler layer 30, increases the flatness of the top surface of the filler layer 30, and improves the morphology of the filler layer 30, thereby improving the quality of the filler layer 30.

[0075] It is understandable that a gas containing target ions is introduced during the first, second, and third deposition processes. The target ions are distributed throughout the entire filling layer 30, which can improve the filling effect and the contour of the filling layer 30, resulting in better performance of the filling layer 30.

[0076] In some possible implementations, the method further includes planarizing the filler layer 30. For example, chemical mechanical polishing (CMP) is used to polish the filler layer 30, resulting in a flat surface on the top surface of the filler layer 30. The target ions can improve the height difference of the top surface of the filler layer 30 before polishing, which is beneficial for polishing the filler layer 30.

[0077] In some possible implementations, a second annealing process is performed after at least one of the first and second depositions. For example, a second annealing process is performed after both the first and second depositions, or after either the first or second deposition. The second annealing process is performed after deposition in which a gas containing the target ions is introduced.

[0078] In this process, the precursors for both the first and / or second depositions include tetraethyl orthosilicate (TEOS) and oxygen-containing gas, while the gas containing target ions includes borane. The deposition may be, for example, plasma-enhanced chemical vapor deposition (PECVD), where the plasma density is high. The precursors and the gas containing target ions collide and decompose with excited high-energy electrons to form plasma.

[0079] This application provides a semiconductor structure, see embodiments thereof. Figures 5 to 7 The semiconductor structure includes a functional layer 20 and a filling layer 30. The top surface of the functional layer 20 has a trench 21. The filling layer 30 fills at least the trench 21. The filling layer 30 is doped with target ions and formed after a first annealing process.

[0080] The functional layer 20 can be a single layer or a stack of layers, and the trench 21 is formed on the top surface of the functional layer 20, such as... Figure 5 and Figure 6 As shown, the top surface of functional layer 20 is the upper surface of functional layer 20. In some possible examples, the bottom of trench 21 is located within functional layer 20, that is, trench 21 does not penetrate functional layer 20. In other possible examples, trench 21 may penetrate functional layer 20.

[0081] Taking a plane perpendicular to the extension direction of the trench 21 as a cross-section, the cross-section of the trench 21 can be rectangular, trapezoidal, etc., and the depth-to-width ratio of the trench 21 can be greater than or equal to 10. Multiple trenches 21 can be present, spaced apart from each other. The embodiments of this application do not limit the structure of the functional layer 20, nor the shape or number of the trenches 21.

[0082] In some possible implementations, such as Figure 5 As shown, the functional layer 20 includes a substrate 22, and a trench 21 is formed on the top surface of the substrate 22. The substrate 22 can be a semiconductor substrate, and the material of the substrate 22 includes, but is not limited to, silicon, germanium, silicon germanide, arsenic germanide, silicon-on-insulator, and germanium-on-insulator. The trench 21 can be a trench in a shallow trench isolation system, and the trench 21 is subsequently filled with insulating material.

[0083] In some other possible implementations, such as Figure 6 As shown, the functional layer 20 includes a dielectric layer 23 and a conductive layer 24 disposed on the dielectric layer 23. A trench 21 is formed within the conductive layer 24, exposing the top surface of the dielectric layer 23. The dielectric layer 23 is made of an insulating material, while the conductive layer 24 can be made of metal. The trench 21 penetrates the conductive layer 24 and extends to the dielectric layer 23, exposing the surface of the dielectric layer 23 within the trench 21.

[0084] The filler layer 30 fills at least within the trench 21. For example, the filler layer 30 fills the bottom of the trench 21, meaning the top surface of the filler layer 30 is lower than the top surface of the functional layer 20. Alternatively, the filler layer 30 fills the trench 21, meaning the top surface of the filler layer 30 is flush with the top surface of the functional layer 20. Yet another example is that the filler layer 30 completely fills the trench 21 and covers the functional layer 20, with the top surface of the filler layer 30 higher than the top surface of the functional layer 20.

[0085] The filling layer 30 is doped with target ions, which are non-metallic elements and have minimal impact on the electrical properties of the semiconductor structure. The target ions are related to the material of the filling layer 30; for example, the target ions include boron ions, and the material of the filling layer 30 includes silicon oxide. Utilizing the target ions can improve the filling capacity and / or surface morphology of the filling layer 30.

[0086] It is understood that the location of the target ions within the filling layer is not limited. For example, the filling layer 30 adjacent to the wall of trench 21 may be doped with target ions, while the filling layer 30 outside trench 21 may not be doped with target ions. Another example is that the filling layer 30 adjacent to the wall of trench 21 may not be doped with target ions, while the filling layer 30 outside trench 21 may be doped with target ions. Yet another example is that the entire filling layer 30 may be relatively uniformly doped with target ions. The wall of trench 21 includes the trench 21 and / or its bottom wall.

[0087] When the filling layer 30 within the trench 21 is doped with target ions, a first annealing treatment is performed. The target ions can promote the reflow of the filling layer 30 within the trench 21, improve the filling capacity of the filling layer 30 in the trench 21, reduce gaps or voids in the filling layer 30 within the trench 21, and improve the filling effect. When the filling layer 30 outside the trench 21 is doped with target ions, a first annealing treatment is performed. The target ions can promote the reflow of the filling layer 30 outside the trench 21, reduce the height difference of the filling layer 30, improve the flatness of the top surface of the filling layer 30, and improve the morphology of the filling layer 30.

[0088] In the semiconductor structure fabrication method of this application embodiment, the top surface of the functional layer 20 has a trench 21, and a filling layer 30 is formed to fill the trench 21. The filling layer 30 is doped with target ions and formed through a first annealing process. In this way, the target ions lower the glass reflow temperature of the filling layer 30, so that the filling layer 30 can achieve a glass circuit at a lower temperature, which can improve the filling ability of the filling layer 30 to fill the trench 21, reduce the gaps or voids in the filling layer 30 in the trench 21, and improve the filling effect; and / or, reduce the height difference of the filling layer 30, improve the flatness of the top surface of the filling layer 30, improve the morphology of the filling layer 30, and thus improve the quality of the filling layer 30.

[0089] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0090] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0091] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A functional layer is provided, the top surface of which has grooves; A filling layer is formed, the filling layer at least filling the trench, and the filling layer is doped with target ions; as well as The filler layer is subjected to a first annealing process.

2. The manufacturing method according to claim 1, characterized in that, Forming the filling layer further includes: The filling layer is formed by a deposition process, the deposition process including a first deposition and a second deposition, wherein the first deposition or the second deposition includes the introduction of a gas containing the target ions.

3. The manufacturing method according to claim 2, characterized in that, The deposition process further includes a third deposition, and forming the filler layer by the deposition process further includes: A first film layer is formed by the first deposition, and the first film layer at least covers the sidewalls and bottom wall of the trench; A second film layer is formed by the second deposition, the second film layer covering the top surface of the first film layer and filling the trench; A third film layer is formed by the third deposition, the third film layer covers the second film layer, and the third film layer, the second film layer and the first film layer form the filling layer; The third deposition includes introducing a gas containing the target ions.

4. The manufacturing method according to claim 3, characterized in that, A second annealing process is performed after at least one of the first deposition and the second deposition.

5. The manufacturing method according to claim 1, characterized in that, The method further includes: The filling layer is planarized.

6. The manufacturing method according to any one of claims 2-5, characterized in that, The target ion includes boron ions, and the filling layer is made of silicon oxide.

7. The manufacturing method according to claim 6, characterized in that, The precursor for the first or second deposition includes ethyl silicate and an oxygen-containing gas, wherein the gas containing the target ion includes borane.

8. The manufacturing method according to any one of claims 1-5, characterized in that, The functional layer includes a substrate, and the trench is formed on the top surface of the substrate.

9. The manufacturing method according to any one of claims 1-5, characterized in that, The functional layer includes a dielectric layer and a conductive layer disposed on the dielectric layer; The trench is formed within the conductive layer, and the trench exposes the top surface of the dielectric layer.

10. A semiconductor structure, characterized in that, include: A functional layer, the top surface of which has grooves; A filling layer, which at least fills the trench, is formed by doping the filling layer with target ions and undergoing a first annealing treatment.

Images