A method for manufacturing a semiconductor structure

Abstract

The application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, forming a buffer layer on the substrate, forming a patterned hard mask layer on the buffer layer, wherein the patterned hard mask layer has a first opening and a first step part which circumferentially surrounds the first opening, the thickness of the hard mask layer at the first step part is smaller than the thickness of the hard mask layer which is located on the side of the first step part away from the first opening, forming a second opening which penetrates through the buffer layer by a first etching process with the hard mask layer as a mask, wherein the second opening is located in position corresponding to the first opening, performing local thermal oxidation on the substrate of the inner wall of the second opening to form an oxidation layer, and performing planarization on the upper surface of the oxidation layer and the hard mask layer by a CMP process. The technical scheme of the application can effectively reduce the generation of scratches in the CMP process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for fabricating a semiconductor structure. Background Technology

[0002] Low-voltage IGBT (Insulated Gate Bipolar Transistor) devices typically employ a planar LOCOS (Local Oxidation of Silicon) structure, while high-voltage IGBT devices typically employ a trench LOCOS structure. The trench LOCOS structure effectively improves the device's breakdown voltage and increases device density.

[0003] Because the LOCOS process produces a bird's beak, and the impact of the beak on subsequent processes is significant, CMP (Chemical Motion Processing) is used for planarization. However, the hard mask layer (such as a silicon nitride layer) protrudes much higher than other areas at the beak location, which can cause the hard mask layer to peel off during CMP polishing, resulting in severe scratches.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, the present invention provides a method for fabricating a semiconductor structure, comprising: A substrate is provided, on which a buffer layer is formed; A patterned hard mask layer is formed on the buffer layer, wherein the patterned hard mask layer has a first opening and a first step portion surrounding the first opening in the circumferential direction, and the thickness of the hard mask layer at the first step portion is less than the thickness of the hard mask layer located on the side of the first step portion away from the first opening. Using the hard mask layer as a mask, a second opening penetrating the buffer layer is formed by a first etching process, wherein the second opening corresponds to the position of the first opening; The substrate on the inner wall of the second opening is subjected to local thermal oxidation to form an oxide layer; The upper surfaces of the oxide layer and the hard mask layer are planarized using a CMP process.

[0007] For example, forming a patterned hard mask layer on the buffer layer includes: A hard mask layer is formed on the buffer layer, and a photoresist layer is formed on the hard mask layer; A third opening and a second step located at the circumferential edge of the third opening are formed on the photoresist layer by photolithography, wherein the third opening corresponds to the position of the first opening, and the thickness of the photoresist layer at the second step is less than the thickness of the photoresist layer on the side of the second step away from the third opening. Using the photoresist layer as a mask, the hard mask layer is etched through a second etching process to form a patterned hard mask layer.

[0008] For example, the photomask used in the photolithography process is provided with a sub-resolution auxiliary pattern, which is used to form a second exposure area surrounding the first exposure area around the first exposure area corresponding to the third opening position. The second exposure area corresponds to the second step position, and the exposure light intensity at the second exposure area is less than the exposure light intensity at the first exposure area.

[0009] For example, the light intensity at the second exposure area is 40%-60% of the light intensity at the first exposure area.

[0010] For example, in the photolithography process, different masks are used to expose the position on the photoresist layer corresponding to the third opening and the position on the photoresist layer corresponding to the second step, respectively.

[0011] For example, the second etching process is an anisotropic dry etching process.

[0012] For example, the hard mask layer is a silicon nitride layer.

[0013] For example, the hard mask layer is formed on the buffer layer by an LPCVD process.

[0014] For example, the bottom of the second opening is below the lower surface of the buffer layer.

[0015] For example, the substrate is a silicon substrate; The buffer layer is formed on the substrate by an ISSG process or a thermal oxidation process.

[0016] According to the semiconductor structure fabrication method of the present invention, a first opening and a first step portion surrounding the first opening are formed on the hard mask layer. The thickness of the hard mask layer at the first step portion is less than the thickness of the hard mask layer on the side of the first step portion away from the first opening. Therefore, when the substrate on the inner wall of the second opening is subjected to local thermal oxidation, the height of the hard mask layer protrusion at the beak can be effectively reduced, and excessive warping of the hard mask layer at the beak portion can be avoided. In addition, the risk of peeling off the hard mask layer in the CMP process can be effectively reduced, and the generation of scratches can be reduced. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention. In the drawings, Figures 1A-1D These are cross-sectional schematic diagrams of the structures corresponding to each step of the semiconductor structure fabrication method in related technologies; Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application; Figures 3A-3G This is a cross-sectional schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of this application; Figure 4 This is a schematic diagram of the first and second exposure areas formed by the photomask; Figure 5 For along Figure 4 A schematic diagram of light intensity changes along the red line.

[0018] Explanation of reference numerals in the attached figures: 10 - Substrate, 20 - Buffer layer, 30 - Hard mask layer, 40 - Opening, 50 - Oxide layer; 100 - Substrate, 200 - Buffer layer, 300 - Hard mask layer, 310 - First opening, 320 - First step, 400 - Photoresist layer, 410 - Third opening, 420 - Second step, 500 - Second opening, 600 - Oxide layer, 710 - First exposure area, 720 - Second exposure area. Detailed Implementation

[0019] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0020] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0022] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0025] See attached document Figures 1A-1D An exemplary method for fabricating semiconductor structures in related technologies is provided. This fabrication method includes the following steps: First, see appendix Figure 1A A substrate 10 is provided, and a buffer layer 20 is formed on the substrate 10 by a process such as thermal oxidation, and then a hard mask layer 30 is formed on the buffer layer 20 by a deposition process such as CVD (Chemical Vapor Deposition).

[0026] Then, see appendix. Figure 1B An opening 40 is formed through the hard mask layer 30 and the buffer layer 20 by photolithography and etching processes. For example, the opening 40 may extend into the substrate 10.

[0027] Then, see appendix. Figure 1C The substrate 10 on the inner wall of the opening 40 is locally thermally oxidized to form an oxide layer 50. In this step, a bird's beak is formed at the edge of the opening 40. Figure 1C The protrusion of the hard mask layer 30 at point A is much higher than at other locations.

[0028] Then, see appendix. Figure 1D The upper surfaces of the oxide layer 50 and the hard mask layer 30 are planarized using a CMP process. During this process, because the protrusion of the hard mask layer 30 at the beak position is much higher than other positions, the protruding hard mask layer 30 will be subjected to greater stress during CMP polishing, which can easily lead to the hard mask layer 30 peeling off and producing severe scratches, especially arc scratches, during polishing.

[0029] The following is a reference to the appendix. Figure 2 An exemplary method for fabricating a semiconductor structure according to an embodiment of this application will be described, the method comprising the following steps: S10: Provide a substrate and form a buffer layer on the substrate.

[0030] S20: A patterned hard mask layer is formed on the buffer layer, wherein the patterned hard mask layer has a first opening and a first step portion surrounding the first opening in the circumferential direction, and the thickness of the hard mask layer at the first step portion is less than the thickness of the hard mask layer located on the side of the first step portion away from the first opening.

[0031] S30: Using a hard mask layer as a mask, a second opening penetrating the buffer layer is formed through a first etching process, wherein the second opening corresponds to the position of the first opening.

[0032] S40: Local thermal oxidation of the substrate on the inner wall of the second opening is performed to form an oxide layer.

[0033] S50: The upper surfaces of the oxide layer and hard mask layer are planarized using the CMP process.

[0034] According to the semiconductor structure fabrication method of the present application embodiment, a first opening and a first step portion surrounding the first opening are formed on the hard mask layer. The thickness of the hard mask layer at the first step portion is less than the thickness of the hard mask layer located on the side of the first step portion away from the first opening. Therefore, when the substrate on the inner wall of the second opening is subjected to local thermal oxidation, the height of the hard mask layer protrusion at the bird's beak can be effectively reduced, and excessive warping of the hard mask layer at the bird's beak can be avoided. In addition, the risk of peeling off the hard mask layer in the CMP process can be effectively reduced, and the generation of scratches can be reduced.

[0035] The following is a reference to the appendix. Figures 3A-3G , Figure 4 , Figure 5 A method for fabricating a semiconductor structure according to an embodiment of this application (i.e., steps S10-S50 described above) will be described in detail.

[0036] In step S10, see Appendix Figure 3A A substrate 100 is provided, and a buffer layer 200 is formed on the substrate 100.

[0037] In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 may also be a substrate of other suitable materials that can be locally thermally oxidized to form an oxide layer 600.

[0038] The buffer layer 200 serves as a transition layer, providing stress buffering between the substrate 100 and the hard mask layer 300, and improving the stress mismatch problem between the substrate 100 and the hard mask layer 300. In this embodiment, the buffer layer 200 is a silicon oxide layer, formed on the substrate 100 by ISSG (In Situ Steam Generation) or thermal oxidation processes. The buffer layer 200 formed by these processes has good quality and small thickness, and can effectively buffer the stress in the subsequently formed hard mask layer 300.

[0039] The ISSG process uses oxygen mixed with a small amount of hydrogen as the reaction atmosphere. Under high temperature and low pressure, a large number of oxygen free radicals with strong oxidizing properties are generated, resulting in fewer defects in the oxide film obtained from the reaction and a lower interface state density.

[0040] In step S20, see Appendix Figures 3B-3DA patterned hard mask layer 300 is formed on the buffer layer 200. The patterned hard mask layer 300 has a first opening 310 and a first step portion 320 circumferentially surrounding the first opening 310. The thickness of the hard mask layer 300 at the first step portion 320 is less than the thickness of the hard mask layer 300 located on the side of the first step portion 320 away from the first opening 310; that is, the thickness of the hard mask layer 300 at the first step portion 320 is less than the thickness of the hard mask layer 300 where no step portion or opening is formed. It should be noted that the first opening 310 is an opening that penetrates the hard mask layer 300.

[0041] Specifically, in step S20, firstly, see Appendix Figure 3B A hard mask layer 300 is formed on the buffer layer 200, and a photoresist layer 400 is formed on the hard mask layer 300.

[0042] In this embodiment, the hard mask layer 300 is a silicon nitride layer, but it can also be any other suitable hard mask material known to those skilled in the art. The hard mask layer 300 can be formed on the buffer layer 200 using a deposition process such as CVD. For example, the hard mask layer 300 is formed on the buffer layer 200 using LPCVD (Low Pressure Chemical Vapor Deposition). The LPCVD process can reduce the stress in the hard mask layer 300 by adjusting process parameters such as the ratio of reactant gases and the pressure in the reaction chamber, thereby reducing the thickness of the buffer layer 200. In other words, a thinner buffer layer 200 can effectively buffer the stress in the hard mask layer 300. In some embodiments, the hard mask layer 300 can also be formed on the buffer layer 200 using PECVD (Plasma Enhanced Chemical Vapor Deposition). After the hard mask layer 300 is formed, a photoresist layer 400 can be formed on the hard mask layer 300 by spin coating.

[0043] Then, see appendix. Figure 3CA third opening 410 and a second step 420 located at the circumferential edge of the third opening 410 are formed on the photoresist layer 400 using a photolithography process. The third opening 410 penetrates the photoresist layer 400 and corresponds in position to the subsequently formed first opening 310. The second step 420 circumferentially surrounds the third opening 410. The thickness of the photoresist layer 400 at the second step 420 is less than the thickness of the photoresist layer 400 on the side of the second step 420 away from the third opening 410; that is, the thickness of the photoresist layer 400 at the second step 420 is less than the thickness of the photoresist layer 400 where the step and opening are not formed, and also less than the thickness of the initially formed photoresist layer 400. The photolithography process includes exposure, development, and other photolithography steps.

[0044] In this embodiment, the photomask used in the photolithography process is equipped with a sub-resolution assistant feature (SRAF). A photomask, also known as a photomask, is a core tool in the integrated circuit (IC) manufacturing process. It consists of an opaque light-blocking film (usually a chromium layer) forming a specific pattern structure on a transparent substrate (such as glass or quartz). The main function of the photomask is to transfer the designed circuit pattern onto the wafer through the exposure process. The sub-resolution assistant feature refers to the tiny pattern added to the photomask. Its size is smaller than the resolution of the photolithography machine, and therefore it does not form an actual pattern on the photoresist after exposure, but it can affect the light intensity at the main pattern location. See Appendix. Figure 4 Appendix Figure 5 In this embodiment, the sub-resolution auxiliary pattern is used to form a second exposure region 720 surrounding the first exposure region 710, which corresponds to the position of the third opening 410. The second exposure region 720 corresponds to the position of the second step portion 420. The exposure light intensity at the second exposure region 720 is less than that at the first exposure region 710. The photoresist layer 400 of the first exposure region 710 is fully exposed, while the photoresist layer 400 of the second exposure region 720 is partially exposed. Thus, after exposure and development, the first exposure region 710 forms the third opening 410, and after exposure and development, the second exposure region 720 forms the second step portion 420. Both the first exposure region 710 and the second exposure region 720 are exposure regions formed on the photoresist when exposure is performed using a mask. The first exposure region 710 is formed by light transmission from the main pattern area (transparent area) on the mask, and the second exposure region 720 is formed by light transmission from the sub-resolution auxiliary pattern. For example, the exposure intensity at the second exposure area 720 is 40%-60% of the exposure intensity at the first exposure area 710.

[0045] In other embodiments, during the photolithography process, different masks can be used to expose the positions on the photoresist layer 400 corresponding to the third opening 410 and the positions on the photoresist layer 400 corresponding to the second step portion 420, respectively. That is, one mask is first used to expose the position on the photoresist layer 400 corresponding to the third opening 410 for the first time, and then another mask is used to expose the position on the photoresist layer 400 corresponding to the second step portion 420 for the second time. The light intensity of the second exposure is less than that of the first exposure, so that the photoresist layer 400 at the third opening 410 is fully exposed, and the photoresist layer 400 at the second step portion 420 is partially exposed. Subsequently, after development, the third opening 410 and the second step portion 420 surrounding the third opening 410 are formed.

[0046] Then, see appendix. Figure 3D Using the photoresist layer 400 as a mask, the hard mask layer 300 is etched through a second etching process to form a patterned hard mask layer 300. Since the photoresist layer 400 has a third opening 410 and a second step portion 420 located at the circumferential edge of the third opening 410, the thickness of the photoresist layer 400 at the second step portion 420 is less than the thickness of the photoresist layer 400 located on the side of the second step portion 420 away from the third opening 410. Therefore, when the hard mask layer 300 is etched using the photoresist layer 400 as a mask, the photoresist layer 400 at the second step portion 420 will be exhausted before the first opening 310, corresponding to the position of the third opening 410, penetrates the hard mask layer 300. This results in the first opening 310 penetrating the hard mask layer 300, and the hard mask layer 300 around the first opening 310 is also partially etched, forming a first step portion 320 circumferentially surrounding the first opening 310. The thickness of the hard mask layer 300 at the first step portion 320 is less than the thickness of the hard mask layer 300 on the side of the first step portion 320 away from the first opening 310. That is, the thickness of the hard mask layer 300 at the first step portion 320 is less than the thickness of the hard mask layer 300 where no step portion or opening is formed. For example, the thickness of the hard mask layer 300 at the first step portion 320 is 40%-60% of the thickness of the hard mask layer 300 on the side of the first step portion 320 away from the first opening 310. It should be noted that the thickness of the photoresist layer 400 at the second step portion 420 needs to be set such that the photoresist layer 400 at the second step portion 420 is exhausted before the first opening 310 penetrating the hard mask layer 300 is formed in the second etching process. For example, the second etching process is an anisotropic dry etching process, which includes, but is not limited to, reactive ion etching (RIE) and inductively coupled plasma (ICP) etching processes.

[0047] For example, after the patterned hard mask layer 300 is formed, the photoresist layer 400 can be removed, for example, by a wet stripping process. In some embodiments, a separate stripping process may not be performed, and subsequent steps may be performed directly.

[0048] In step S30, see Appendix Figure 3E Using a hard mask layer 300 as a mask, a second opening 500 penetrating the buffer layer 200 is formed through a first etching process, wherein the second opening 500 corresponds to the position of the first opening 310. For example, the first etching process can be an anisotropic dry etching process.

[0049] In this embodiment, the bottom of the second opening 500 is lower than the lower surface of the buffer layer 200, and the second opening 500 extends into the substrate 100, thereby increasing the depth of the subsequently formed oxide layer 600 in the substrate 100, which is beneficial for subsequent processes. In some other embodiments, the second opening 500 may only penetrate the buffer layer 200, exposing the upper surface of the substrate 100.

[0050] In step S40, see Appendix Figure 3F The substrate 100 on the inner wall of the second opening 500 is locally thermally oxidized to form an oxide layer 600.

[0051] Localized thermal oxidation refers to oxidizing the substrate 100 on the inner wall of the second opening 500 using water vapor and oxygen at high temperature (or through other suitable thermal oxidation methods) with a hard mask layer 300 and a buffer layer 200 as masks, to form an oxide layer 600. A portion of the oxide layer 600 is located on the substrate 100, and a portion protrudes from the upper surface of the substrate 100. In this embodiment, both the oxide layer 600 and the buffer layer 200 are silicon oxide layers.

[0052] Since a first step portion 320 is formed around the first opening 310 of the hard mask layer 300 in a circumferential direction, the thickness of the hard mask layer 300 at the first step portion 320 (that is, the thickness of the hard mask layer 300 at the bird's beak formed by thermal oxidation) is thinner than the thickness of the hard mask layer 300 at other locations. Therefore, the height of the protrusion of the hard mask layer 300 at the bird's beak can be effectively reduced, and the hard mask layer 300 at the bird's beak can be prevented from excessively warping. In turn, the risk of peeling off the hard mask layer 300 in the subsequent CMP process can be effectively reduced, and the generation of scratches can be reduced.

[0053] For example, in some embodiments, when the hard mask layer 300 is a silicon nitride layer, the preparation method further includes removing the silicon oxynitride layer on the upper surface of the hard mask layer 300 before step S50. When the hard mask layer 300 is a silicon nitride layer, its upper surface will also be oxidized to a certain extent in step S40 to form a silicon oxynitride layer. Before step S50, this silicon oxynitride layer can be removed to improve the polishing effect of the CMP process in step S50. For example, the silicon oxynitride layer on the upper surface of the hard mask layer 300 can be removed by a wet cleaning process. In some embodiments, when the thickness of the silicon oxynitride layer on the upper surface of the hard mask layer 300 is extremely thin and its impact on the CMP process is minimal, the silicon oxynitride layer on the upper surface of the hard mask layer 300 may not be removed separately, but the CMP process can be performed directly to remove it.

[0054] In step S50, see Appendix Figure 3G The upper surfaces of the oxide layer 600 and the hard mask layer 300 are planarized using a CMP process. That is, the upper surfaces of the oxide layer 600 and the hard mask layer 300 are ground using a CMP process until their overall flatness meets a preset requirement. For example, in step S50, the upper surfaces of the oxide layer 600 and the hard mask layer 300 are ground to be flush using a CMP process.

[0055] For example, after step S50, the remaining hard mask layer 300 can be removed by a process such as wet etching.

[0056] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0057] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0058] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0059] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0060] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0061] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a buffer layer is formed; A patterned hard mask layer is formed on the buffer layer, wherein the patterned hard mask layer has a first opening and a first step portion surrounding the first opening in the circumferential direction, and the thickness of the hard mask layer at the first step portion is less than the thickness of the hard mask layer located on the side of the first step portion away from the first opening. Using the hard mask layer as a mask, a second opening penetrating the buffer layer is formed by a first etching process, wherein the second opening corresponds to the position of the first opening; The substrate on the inner wall of the second opening is subjected to local thermal oxidation to form an oxide layer; The upper surfaces of the oxide layer and the hard mask layer are planarized using a CMP process.

2. The preparation method according to claim 1, characterized in that, A patterned hard mask layer is formed on the buffer layer, including: A hard mask layer is formed on the buffer layer, and a photoresist layer is formed on the hard mask layer; A third opening and a second step located at the circumferential edge of the third opening are formed on the photoresist layer by photolithography, wherein the third opening corresponds to the position of the first opening, and the thickness of the photoresist layer at the second step is less than the thickness of the photoresist layer on the side of the second step away from the third opening. Using the photoresist layer as a mask, the hard mask layer is etched through a second etching process to form a patterned hard mask layer.

3. The preparation method according to claim 2, characterized in that, The photomask used in the photolithography process is provided with a sub-resolution auxiliary pattern. The sub-resolution auxiliary pattern is used to form a second exposure area around the first exposure area corresponding to the third opening position. The second exposure area corresponds to the second step position. The exposure light intensity at the second exposure area is less than the exposure light intensity at the first exposure area.

4. The preparation method according to claim 3, characterized in that, The light intensity at the second exposure area is 40%-60% of the light intensity at the first exposure area.

5. The preparation method according to claim 2, characterized in that, In the photolithography process, different photomasks are used to expose the positions on the photoresist layer corresponding to the third opening and the positions on the photoresist layer corresponding to the second step.

6. The preparation method according to claim 2, characterized in that, The second etching process is an anisotropic dry etching process.

7. The preparation method according to claim 2, characterized in that, The hard mask layer is a silicon nitride layer.

8. The preparation method according to claim 7, characterized in that, The hard mask layer is formed on the buffer layer using an LPCVD process.

9. The preparation method according to claim 1, characterized in that, The bottom of the second opening is below the lower surface of the buffer layer.

10. The preparation method according to claim 1, characterized in that, The substrate is a silicon substrate; The buffer layer is formed on the substrate by an ISSG process or a thermal oxidation process.

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