Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, a dielectric layer is formed on the substrate, and the dielectric layer is formed with an opening; the substrate is inverted and immersed in an acid etching solution for etching, the size of the upper part of the opening is increased by adjusting the immersion depth and the residence time, and the upper part of the opening is formed with an inverted trapezoidal profile; a smooth repair layer is deposited on the sidewall surface of the dielectric layer under a first condition to smooth the sidewall surface of the inverted trapezoidal profile; a first film layer is sequentially deposited in the opening; a chemical mechanical polishing removes the conductive layer and the seed layer in the inverted trapezoidal profile, and removes the dielectric layer covering the inverted trapezoidal profile, and a metal interconnection structure is formed in the polished dielectric layer. The aspect ratio of the upper part of the opening is reduced, which is beneficial to inhibit the first film layer from forming a overhanging structure at the top of the opening, so that the material can be prevented from prematurely plugging at the top of the opening when filling the material in the opening, the cavity defect is improved, and the reliability and the process yield of the device are improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor manufacturing processes, the feature size of integrated circuits continues to shrink. Especially after entering the 28nm and below technology nodes, the aspect ratio of metal interconnect structures increases. In trenches or vias with high aspect ratios, copper filling processes face severe challenges.

[0003] Currently, metal interconnect structures are typically formed using the damascus process. However, in the damascus process, plating voids are a significant factor affecting chip yield and reliability. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems in the existing technology.

[0005] To achieve the above objectives, in a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0006] A substrate is provided, on which a dielectric layer is formed, and the dielectric layer has openings;

[0007] The substrate is inverted and the dielectric layer is immersed in an acidic etching solution for etching. By adjusting the immersion depth and dwell time, the size of the upper part of the opening is increased so that the upper part of the opening forms an inverted trapezoidal profile.

[0008] Under the first condition, a smoothing repair layer is deposited on the sidewall surface of the medium layer to smooth the sidewall surface of the inverted trapezoidal profile;

[0009] Deposit a first film layer into the opening;

[0010] Chemical mechanical polishing is performed to remove the first film layer within the inverted trapezoidal contour and to remove the dielectric layer covering the inverted trapezoidal contour.

[0011] In one embodiment, the step of inverting the substrate and immersing the dielectric layer in an acidic etching solution for etching includes:

[0012] The substrate is inverted, and the immersion depth of the dielectric layer in the acidic etching solution is controlled by a stepper motor to increase in a stepwise manner, with each depth remaining for a preset duration.

[0013] In one embodiment, the step depth of each step is 50 angstroms to 100 angstroms; the dwell time at each depth is 5 seconds to 100 seconds; the step-by-step increment is 4 to 10 times; and the acidic etching solution is a hydrofluoric acid solution.

[0014] In one embodiment, after the dielectric layer is etched by immersing it in an acidic etching solution, the surface of the inverted trapezoidal contour is formed with an uneven structure.

[0015] After depositing the smoothing repair layer, the smoothing repair layer covers the inverted trapezoidal contour, filling and smoothing the uneven structure of the surface of the inverted trapezoidal contour.

[0016] In one embodiment, a metal interconnect layer is formed in the dielectric layer, and the opening exposes at least a portion of the surface of the metal interconnect layer; a precursor gas for depositing the smoothing repair layer has a higher adsorption capacity for the dielectric layer than for the metal interconnect layer, and the smoothing repair layer is selectively grown on the dielectric layer.

[0017] In one embodiment, the first conditions include: deposition temperature of 100℃-400℃, precursor gas flow rate of 100sccm-1000sccm, radio frequency power of 200W-1000W, radio frequency duration of 2s-10s, cavity pressure of 2Torr-10Torr, and deposition cycle number of 2-10 times.

[0018] In one embodiment, the precursor gas of the smoothing repair layer is bis(tert-butylamino)silane; the thickness of the smoothing repair layer is 1 nm-10 nm.

[0019] In one embodiment, the top surface of the dielectric layer is covered by a hard mask layer, which is immersed in an acidic etching solution along with the dielectric layer. The acidic etching solution has a low etching ratio for the hard mask layer.

[0020] After depositing a smooth repair layer on the sidewall surface of the dielectric layer, the hard mask layer is etched away.

[0021] In one embodiment, the initial depth-to-width ratio of the opening is 5:1 to 20:1;

[0022] After the upper part of the opening forms an inverted trapezoidal outline, the width of the top opening of the inverted trapezoidal outline is greater than the width of the lower part of the opening.

[0023] Secondly, this application provides a semiconductor structure, which is fabricated using the semiconductor structure fabrication method described in the first aspect.

[0024] The semiconductor structure and its fabrication method of this application have the following unexpected effects: the dielectric layer is etched by immersing the inverted substrate in an acidic etching solution. By adjusting the immersion depth and dwell time, the size of the upper part of the opening is increased, and the upper part of the opening forms an inverted trapezoidal profile, thereby reducing the aspect ratio of the upper part of the opening. This helps to suppress the formation of a protruding structure of the first film layer at the top of the opening. This can suppress the premature sealing of the top of the opening when filling the opening with material, which helps to improve void defects and thus improve the reliability of the device and the process yield. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0027] Figure 2 This is a schematic diagram of a dielectric layer with an opening provided in one embodiment;

[0028] Figure 3 This is a schematic diagram of the structure after the substrate is immersed in an acidic etching solution, as provided in one embodiment.

[0029] Figure 4 This is a schematic diagram of the structure after the upper part of the opening is formed into an inverted trapezoidal outline, as provided in one embodiment;

[0030] Figure 5 This is a schematic diagram of the structure after etching away the hard mask layer in one embodiment;

[0031] Figure 6 This is a schematic diagram of the structure after the smooth repair layer is formed in one embodiment;

[0032] Figure 7 This is a schematic diagram of the structure after the barrier layer and seed layer are formed in one embodiment;

[0033] Figure 8 This is a schematic diagram of the structure after the conductive layer is formed in one embodiment;

[0034] Figure 9 This is a schematic diagram of the structure after chemical mechanical polishing to form a metal interconnect structure in one embodiment.

[0035] Explanation of reference numerals in the attached figures:

[0036] 31. Dielectric layer; 32. Opening; 32a. Inverted trapezoidal profile; 33. Smoothing repair layer; 34. Barrier layer; 35. Seed layer; 36. Conductive layer; 37. Metal interconnect structure; 38. Metal interconnect layer; 39. Hard mask layer. Detailed Implementation

[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] In traditional copper interconnect manufacturing processes, trenches are first etched into the dielectric layer, followed by the deposition of a copper barrier / seed layer using Physical Vapor Deposition (PVD), and finally, an electrochemical plating (ECP) layer is used to fill the conductive copper layer. However, due to the high directionality of PVD, copper atoms are difficult to deposit uniformly at the bottom and sidewalls of high aspect ratio openings. Instead, a thicker deposition layer tends to form at the top corners of the opening, creating a so-called overhang structure. This overhang structure leads to a severe pinch-off effect during subsequent electrochemical plating, where copper growth at the top of the opening is much faster than at the bottom. Before the bottom is fully filled, the top closes, creating voids within the interconnect structure. These voids not only reduce the electromigration (EM) lifetime of the copper interconnect but also significantly decrease chip yield, hindering the development of advanced process technologies.

[0041] In related solutions, the shape retention of the seed layer is improved by optimizing the parameters of the physical vapor deposition process, and the filling profile is adjusted by using reverse pulse electroplating technology. However, for high aspect ratio structures with an aspect ratio greater than 5:1, the above methods are still difficult to completely eliminate void defects, and are often accompanied by problems such as narrow process windows, high costs, or adverse effects on subsequent processes.

[0042] Therefore, there is an urgent need in the field for a manufacturing method that can effectively reduce void defects in high aspect ratio metal interconnect structures in order to improve device reliability and process yield.

[0043] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0044] Step S101: Provide a substrate, on which a dielectric layer 31 is formed, and an opening 32 is formed in the dielectric layer 31.

[0045] Step S102: Invert the substrate and immerse the dielectric layer 31 in an acidic etching solution for etching. By adjusting the immersion depth and dwell time, increase the size of the upper part of the opening 32 so that the upper part of the opening 32 forms an inverted trapezoidal profile 32a.

[0046] Step S103: Under the first condition, a smoothing repair layer 33 is deposited on the sidewall surface of the dielectric layer 31 to smooth the sidewall surface of the inverted trapezoidal profile 32a.

[0047] Step S104: Deposit the first film layer into the opening 32.

[0048] Step S105: Perform chemical mechanical polishing to remove the first film layer within the inverted trapezoidal contour 32a and remove the dielectric layer 31 covering the inverted trapezoidal contour 32a.

[0049] In the above-mentioned semiconductor structure fabrication method, the dielectric layer 31 is immersed in an acidic etching solution and etched by inverting the substrate. By adjusting the immersion depth and dwell time, the size of the upper part of the opening 32 is increased, and the upper part of the opening 32 forms an inverted trapezoidal contour 32a, thereby reducing the aspect ratio of the upper part of the opening 32. This helps to suppress the formation of a protruding structure of the first film layer at the top of the opening, thereby suppressing the material from prematurely sealing the top of the opening 32 when filling the opening with material. This makes the filling process more complete, which helps to improve void defects and thus improve the reliability of the device and the process yield.

[0050] Below, in conjunction with reference Figures 2-9 The process of fabricating the semiconductor structure in this embodiment will be further explained.

[0051] In step S101, the substrate (not shown in the figure) may be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0052] It is understood that the substrate provided in this embodiment has undergone multiple previous processes before forming the dielectric layer 31, and one or more stacked semiconductor device layers can be formed in or on the substrate. Each semiconductor device layer can contain a variety of semiconductor devices and a variety of metal interconnects. The semiconductor devices may include at least one of metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, resistors, inductors, diodes, and optical devices.

[0053] In this embodiment, a dielectric layer 31 is formed on the substrate. The material of the dielectric layer 31 includes, but is not limited to, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride, and its dielectric constant (k value) is less than 3.0 to reduce interconnect delay.

[0054] Reference Figure 2An opening 32 is formed in the dielectric layer 31, and the opening 32 can penetrate the dielectric layer 31. For example, the opening 32 for copper interconnect can be formed in the dielectric layer 31 using photolithography and etching processes, and the opening 32 has a high aspect ratio. For example, the aspect ratio of the opening 32 is greater than 5:1. In some embodiments, the initial aspect ratio of the opening 32 is 5:1 to 20:1; the initial aspect ratio of the opening 32 is 8:1 to 10:1; for example, the initial aspect ratio of the opening 32 can be 5:1, 8:1, 10:1, 12:1, 15:1, 18:1 or 20:1.

[0055] In this embodiment, the formation process of the opening 32 includes: coating photoresist on the dielectric layer 31, forming a pattern through exposure and development, then performing dry etching using fluorocarbon-based plasma to transfer the pattern to the dielectric layer 31, and finally removing the photoresist and performing wet cleaning. The opening 32 can be a through-hole with equal width at the top and bottom, or the opening 32 can be a first opening 32 and a second opening 32 connected sequentially from top to bottom, that is, the opening 32 is a stepped hole, with the width of the lower first opening 32 being greater than the width of the upper second opening 32.

[0056] In this embodiment, a metal interconnect layer 38 is formed in the dielectric layer 31, and the opening 32 exposes at least a portion of the surface of the metal interconnect layer 38.

[0057] In step S102, refer to Figure 3 , Figure 4 The substrate is inverted, with the dielectric layer 31 facing the acidic etchant. A stepper motor controls the dielectric layer 31 to be immersed in the acidic etchant in a stepped manner, gradually increasing the immersion depth and controlling the immersion etching time at each depth. The etching amount of the dielectric layer 31 on the sidewalls of the opening 32 decreases from top to bottom, thereby forming an inverted trapezoidal profile 32a on the upper part of the opening 32. The width of the top opening 32 of the inverted trapezoidal profile 32a is increased compared to before etching, while the lower part of the opening 32 (the area not etched by the acidic etchant) retains its initial width.

[0058] After the dielectric layer 31 is immersed in the acid etching solution in a stepwise manner, the surface of the inverted trapezoidal contour 32a formed has a concave-convex structure, that is, the surface of the inverted trapezoidal contour 32a is rough.

[0059] In step S103, refer to Figure 6A plasma-enhanced atomic layer deposition (PEALD) process is used to selectively deposit an oxide layer on the sidewall surface of the dielectric layer 31 as a smoothing repair layer 33. After depositing the smoothing repair layer 33, it covers the inverted trapezoidal contour 32a, filling and smoothing the uneven structure on the surface of the inverted trapezoidal contour 32a. The smoothing repair layer 33 repairs the rough morphology of the etched inverted trapezoidal contour 32a, forming a smooth surface layer on the surface of the inverted trapezoidal contour 32a, providing a high-quality interface for the subsequent deposition of the seed layer 35 and the conductive layer 36, which is beneficial for further improving the filling defects.

[0060] In step S104, refer to Figure 7 The first film layer is deposited on the surface of the dielectric layer 31 and inside the opening 32 using a physical vapor deposition process.

[0061] In this embodiment, taking the damascus process as an example, the first film layer may include a barrier layer 34 (not shown in the figure) and a seed layer 35 deposited sequentially. The seed layer 35 covers the bottom wall and sidewalls (including the inverted trapezoidal profile 32a) of the opening 32 and the top surface of the dielectric layer 31. The barrier layer 34 may be a single-layer or multi-layer structure, and the material of the barrier layer 34 may include at least one of tantalum or tantalum nitride, titanium or titanium nitride; the seed layer 35 may be a copper seed layer.

[0062] Since the upper part of the opening 32 has formed an inverted trapezoidal profile 32a, the overhang phenomenon at the upper part of the opening 32 is suppressed during the physical vapor deposition process, and copper atoms can be uniformly deposited to the bottom of the opening 32.

[0063] It is understood that the method of this application can also be applied to other filling processes involving high aspect ratio through holes or trenches.

[0064] In step S105, refer to Figure 9 Chemical mechanical polishing (CMP) is used to planarize the inverted trapezoidal profile 32a, remove the first film layer within the inverted trapezoidal profile 32a, such as the seed layer 35 and / or the barrier layer 34, and remove the dielectric layer 31 covering the inverted trapezoidal profile 32a, while retaining the first film layer within the opening 32 portion below the inverted trapezoidal profile 32a.

[0065] Taking the damascus process as an example, after depositing the first film layer into the opening 32 in step S104, an electrochemical electroplating process is used to deposit conductive material into the opening 32 to fill the conductive layer 36, achieving void-free copper filling. It can be understood that after etching with an acidic etching solution, the width of the upper part of the opening 32 increases, reducing the difficulty of filling the opening 32 and thus preventing the conductive material filling the opening 32 from sealing prematurely, achieving void-free filling. Even if voids still exist in the formed conductive layer 36, the increased width of the upper part of the opening 32 can reduce the size of the voids. Furthermore, in this embodiment, the conductive layer 36 is deposited first, followed by chemical mechanical polishing. During the chemical mechanical polishing process, void defects can be ground away, ensuring that the formed metal interconnect structure 37 is free of void defects, making the manufacturing process more controllable and thus improving product yield.

[0066] Alternatively, after removing the first film layer within the inverted trapezoidal contour 32a and the dielectric layer 31 covering the inverted trapezoidal contour 32a in step S105, an electrochemical electroplating process can be used to fill the opening 32 with conductive material to form a conductive layer 36. In this way, removing the dielectric layer 31 covering the inverted trapezoidal contour 32a reduces the height and aspect ratio of the opening 32, further reducing the difficulty of filling the opening 32. This not only improves void filling but also saves on conductive material deposition, reducing production costs. This is beneficial for improving void defects in the metal interconnect structure 37, resulting in a more uniform current density distribution in the metal interconnect structure 37, avoiding localized current concentration and Joule heating effects, thereby improving electromigration lifetime.

[0067] In some embodiments, step S102 involves inverting the substrate and immersing the dielectric layer 31 in an acidic etching solution for etching. This includes: inverting the substrate and controlling the immersion depth of the dielectric layer 31 in the acidic etching solution to increase in a stepwise manner using a stepper motor, with each depth remaining for a preset duration. In this embodiment, after etching, the inverted trapezoidal contour 32a at the top of the opening 32 is a stepped contour with a decreasing width from top to bottom.

[0068] Furthermore, the acidic etching solution used is a hydrofluoric acid solution with a concentration of 500:1 to 1000:1, such as 500:1, 600:1, 700:1, 800:1, 900:1, or 1000:1. The step depth of each step is 50-100 angstroms; the dwell time at each depth is 5-100 seconds; and the number of steps is 4-10.

[0069] For example, each step size is 50 angstroms. (See reference...) Figure 3 , Figure 4The dielectric layer 31 can be immersed in hydrofluoric acid solution by stepping motor to a depth of 50 angstroms, and the dielectric layer 31 can remain at this depth for 50 seconds; then, the dielectric layer 31 can be immersed in hydrofluoric acid solution to a depth of 100 angstroms, and the dielectric layer 31 can remain at this depth for 50 seconds; the dielectric layer 31 can be immersed in hydrofluoric acid solution to a depth of 150 angstroms, and the dielectric layer 31 can remain at this depth for 50 seconds; the dielectric layer 31 can be immersed in hydrofluoric acid solution to a depth of 200 angstroms, and the dielectric layer 31 can remain at this depth for 50 seconds.

[0070] It is understandable that the step depth, dwell time, and number of steps of each step can be flexibly adjusted according to the thickness and material of the medium layer 31 and the depth-to-width ratio of the opening 32.

[0071] Through the above controls, refer to Figure 3 , Figure 4 The upper sidewall of opening 32 is etched with hydrofluoric acid solution, with the etching amount decreasing from top to bottom, thus forming an inverted trapezoidal profile 32a at the top of opening 32. Taking four immersions as an example, the dielectric layer 31 in the 0-50 angstrom region at the top of the inverted trapezoidal profile 32a is etched with the largest amount (approximately 5nm-8nm) on both sides. The etching amount decreases from top to bottom in the 50-100 angstrom region (approximately 4nm-6nm), the etching amount in the 100-150 angstrom region is approximately 2nm-4nm, and the etching amount in the 150-120 angstrom region is approximately 0.5nm-2.5nm. Ultimately, the width of the top opening 32 of the inverted trapezoidal profile 32a is larger than before etching, while the opening 32 below the inverted trapezoidal profile 32a retains its original profile. After the inverted trapezoidal profile 32a is formed at the top of opening 32, the width of the top opening 32 of the inverted trapezoidal profile 32a is greater than the initial width of the lower part of opening 32.

[0072] In some embodiments, the precursor gas for depositing the smoothing repair layer 33 in step S103 has a higher adsorption capacity for the dielectric layer 31 than for the metal interconnect layer 38, and the smoothing repair layer 33 is selectively grown on the dielectric layer 31. The smoothing repair layer 33 grows only on the sidewalls of the dielectric layer 31 and not on the surface of the metal interconnect layer 38 exposed at the bottom of the opening 32, so that the subsequent seed layer 35 and conductive layer 36 can directly form a low-resistance ohmic contact with the bottom metal interconnect layer 38, without the contact resistance increasing or the electroplating filling failing due to the additional insulating layer.

[0073] In some embodiments, the first conditions in step S103 include: a deposition temperature of 100℃-400℃, such as 100℃, 150℃, 180℃, 200℃, 250℃, 300℃, 350℃, or 400℃; a precursor gas flow rate of 100sccm-1000sccm, such as 100, 200, 400, 500, 700sccm, 800sccm, 900sccm, or 1000sccm; a radio frequency power of 200W-1000W, such as 200W, 300W, 400W, 500W, 600W, 700W, 800W, 900W, or 1000W; a radio frequency duration of 2s-10s; a cavity pressure of 2torr-10torr; and 2-10 deposition cycles.

[0074] Among them, reference Figure 6 The precursor gas for the smooth repair layer 33 is bis(tert-butylamino)silane (SiH2[NH(C4H9)]2, 2NTE); the thickness of the smooth repair layer 33 is 1nm-10nm. In this embodiment, plasma-enhanced atomic layer deposition can be used to form the smooth repair layer 33 on the surface of the dielectric layer 31 on the sidewall of the opening 32 after 2-10 PEALD cycles.

[0075] By depositing a smooth repair layer 33 using PEALD, the smooth repair layer 33 not only fills and covers the uneven structure of the surface of the inverted trapezoidal contour 32a, but also forms smoother rounded corners at the sharp protruding edges, making the originally sharp stepped edges rounded, reducing the surface roughness of the sidewalls, and making them smoother than after etching, thereby providing an improved interface for the subsequent deposition of the seed layer 35 and the conductive layer 36.

[0076] In some embodiments, refer to Figure 2 The top surface of the dielectric layer 31 is covered by a hard mask layer 39. In this embodiment, the hard mask layer 39 is a mask formed by patterning and etching the dielectric layer 31 to form the opening 32. When the dielectric layer 31 is immersed in an acidic etching solution for etching, the hard mask layer 39 and the dielectric layer 31 are immersed together in the acidic etching solution, and the acidic etching solution has a low etching ratio for the hard mask layer 39.

[0077] After step S102, where a smooth repair layer 33 is deposited on the sidewall surface of the dielectric layer 31, and before step S103, where the smooth repair layer 33 is deposited, refer to... Figure 5 Step S100: Etch to remove the hard mask layer 39.

[0078] In this embodiment, the top surface of the dielectric layer 31 on the substrate provided in step S101 is covered by a hard mask layer 39. The hard mask layer 39 is a mask used for pattern transfer during the etching process of the dielectric layer 31 to form the opening 32. The hard mask layer 39 can be a titanium nitride layer. In step S102, when the substrate is inverted and immersed in the acidic etching solution, the hard mask layer 39 and the dielectric layer 31 are immersed together in the acidic etching solution. Since the acidic etching solution has a low etching ratio for the hard mask layer 39, the hard mask layer 39 does not change significantly during the etching process. Thus, the top of the dielectric layer 31 is shielded and covered by the hard mask layer 39.

[0079] This allows the hydrofluoric acid solution to etch only the exposed sidewalls of the dielectric layer 31, without directly contacting and etching the top surface of the dielectric layer 31. Thus, the protection of the hard mask layer 39 helps control the critical dimensions of the top surface of the dielectric layer 31, preventing excessive enlargement due to the isotropic etching of the hydrofluoric acid solution.

[0080] Reference Figure 5 In step S102, the dielectric layer 31 is immersed in an acidic etching solution to etch it, forming an inverted trapezoidal contour 32a on the upper part of the opening 32. Then, the substrate is inverted and immersed in a 5%-20% hydrogen peroxide (H2O2) solution. The immersion depth is controlled by a stepper motor to ensure that the hard mask layer 39 is completely immersed in the hydrogen peroxide solution for 3-10 minutes to completely remove the hard mask layer 39 and expose the top surface of the dielectric layer 31. After removing the hard mask layer 39, step S103 is performed to deposit a smooth repair layer 33 on the sidewall surface of the dielectric layer 31.

[0081] In one embodiment, this embodiment provides a method for fabricating a semiconductor structure, including the following steps:

[0082] Step S201: Refer to Figure 2 A substrate is provided, on which a dielectric layer 31 is formed. The top surface of the dielectric layer 31 is covered by a hard mask layer 39. The dielectric layer 31 has an opening 32 with an aspect ratio of 5:1 to 10:1. A metal interconnect layer 38 is formed in the substrate, and the opening 32 exposes at least a portion of the surface of the metal interconnect layer 38. The hard mask layer 39 is used to form the opening 32. In this embodiment, the hard mask layer 39 is formed on the top surface of the dielectric layer 31 and defines a mask pattern. The dielectric layer 31 is etched according to the hard mask layer 39 until at least a portion of the top surface of the metal interconnect layer 38 is exposed, and then the etching stops to form the opening 32.

[0083] Step S202: Refer to Figure 3 , Figure 4The substrate is inverted, and the dielectric layer 31 and the hard mask layer 39 are immersed together in a hydrofluoric acid solution with a concentration of 500:1 to 1000:1. The immersion depth of the dielectric layer 31 in the hydrofluoric acid solution is controlled stepwise by a stepper motor to increase the size of the upper part of the opening 32 and form an inverted trapezoidal profile 32a on the upper part of the opening 32. The step depth of each step is 50 angstroms to 100 angstroms, and each depth is held for 5s to 100s. The stepwise increase is performed 4 to 10 times.

[0084] In each step, the size of the opening 32 increases by 1.5nm-2nm. In this embodiment, the step depth of each step is 50 angstroms. The substrate is immersed in hydrofluoric acid solution four times, reaching depths of 50 angstroms, 100 angstroms, 150 angstroms, and 200 angstroms respectively, and remaining at each depth for 50 seconds. After the step etching, approximately 6nm of the dielectric layer 31 on both sides of the top 0-50 angstroms of the opening 32 is removed, approximately 4.5nm of the dielectric layer 31 on both sides of the top 50-100 angstroms of the opening 32 is removed, approximately 3nm of the dielectric layer 31 on both sides of the top 100-150 angstroms of the opening 32 is removed, and approximately 1.5nm of the dielectric layer 31 on both sides of the top 150-200 angstroms of the opening 32 is removed. The sidewall of the upper part of the opening 32 has an inverted trapezoidal contour 32a, which is a step-shaped contour with a decreasing width from top to bottom (from the top of the dielectric layer 31 towards the substrate).

[0085] Step S203: Refer to Figure 8 The substrate is inverted and immersed in a 5%-20% hydrogen peroxide solution. The immersion depth is controlled by a stepper motor so that the hard mask layer 39 is completely immersed in the hydrogen peroxide solution for 3-10 minutes to completely remove the hard mask layer 39 and expose the top surface of the dielectric layer 31.

[0086] Step S204: Refer to Figure 6 Using bis(tert-butylamino)silane as a precursor, the deposition temperature is 100℃-400℃, the flow rate of the precursor gas is 100sccm-1000sccm, the radio frequency power is 200W-1000W, the radio frequency action time is 2s-10s, and the chamber pressure is 2Torr-10Torr. Plasma-enhanced atomic layer deposition is performed for 2-10 cycles to deposit a smooth repair layer 33 on the sidewall surface of the dielectric layer 31 to smooth the sidewall surface of the inverted trapezoidal contour 32a. The thickness of the smooth repair layer 33 is 1nm-10nm.

[0087] In this embodiment, bis(tert-butylamino)silane selectively does not adsorb onto the metal interconnect layer 38 exposed at the bottom of the opening 32. This is because the metal interconnect layer 38 (typically copper) lacks the active sites (such as hydroxyl-OH groups) required for chemisorption of bis(tert-butylamino)silane. Therefore, bis(tert-butylamino)silane only nucleates and grows on the sidewall surface of the dielectric layer 31, avoiding the introduction of an insulating layer on the surface of the metal interconnect layer 38. This ensures that the subsequent seed layer 35 and conductive layer 36 maintain a low-resistance ohmic contact with the bottom metal interconnect layer 38. Bis(tert-butylamino)silane selectively adsorbs onto the surface of the dielectric layer 31, forming a smooth repair layer 33 on the sidewall surface of the opening 32. The smooth repair layer 33 covers the inverted trapezoidal profile 32a and the sidewall of the opening 32 below the inverted trapezoidal profile 32a.

[0088] The smoothing repair layer 33 fills the uneven structure of the surface of the inverted trapezoidal contour 32a and rounds the raised edges of the sharp stepped corners of the inverted trapezoidal contour 32a. Finally, the jagged rough contour originally formed by the etching of hydrofluoric acid solution on the sidewall is filled and smoothed by the inverted trapezoidal contour 32a, making the sidewall surface of the inverted trapezoidal contour 32a smoother.

[0089] Step S205: A barrier layer 34 and a seed layer 35 are sequentially deposited in the opening 32 using a physical vapor deposition process, and a conductive layer 36 is filled into the opening 32 using an electroplating process.

[0090] Reference Figure 7 A physical vapor deposition (PVD) process is used to deposit a barrier layer 34 on the inner wall surface and bottom of the opening 32. The barrier layer 34 may include tantalum or tantalum nitride, and its thickness is 50 to 150 angstroms. This barrier layer is used to prevent copper atoms from diffusing into the dielectric layer 31. Continuing with the PVD process, a seed layer 35 is deposited on the inner wall surface and bottom of the opening 32. The seed layer 35 has a thickness of 500 to 1000 angstroms and is used to provide a plating surface for subsequent electroplating processes. In this embodiment, the seed layer 35 is a copper seed layer.

[0091] Reference Figure 8 Since the upper part of the opening 32 has formed an inverted trapezoidal profile 32a, and the sidewall surface is relatively smooth after being repaired by the smoothing repair layer 33, the width of the top opening 32 of the inverted trapezoidal profile 32a is greater than that of the lower part, making it easier for the particles of physical vapor deposition to directly reach the bottom of the opening 32, and reducing the excessive deposition at the top corner. Therefore, the barrier layer 34 and the seed layer 35 will not form a protruding structure at the top of the opening 32.

[0092] An electrochemical electroplating process is used to electroplat copper into the opening 32 to form a conductive layer 36. During the electroplating process, the copper grows uniformly from the bottom of the opening 32 upwards, avoiding premature closure of the top (pinch-off effect), thereby achieving void-free filling in the opening 32.

[0093] Step S206: Perform chemical mechanical polishing to remove the conductive layer 36 and seed layer 35 within the inverted trapezoidal contour 32a, and remove the dielectric layer 31 covering the inverted trapezoidal contour 32a, forming a metal interconnect structure 37 in the dielectric layer 31 retained by polishing.

[0094] Reference Figure 9 A chemical mechanical polishing (CMP) process is used to planarize the substrate surface, first removing excess conductive film layers outside the top opening 32 of the inverted trapezoidal contour 32a. Polishing continues, removing the conductive layer 36, seed layer 35, and barrier layer 34 within the region of the inverted trapezoidal contour 32a, as well as the dielectric layer 31 constituting the inverted trapezoidal contour 32a. The polishing endpoint is located below the inverted trapezoidal contour 32a. After polishing, the conductive layer 36, seed layer 35, and barrier layer 34 inside the opening 32 are retained, forming a metal interconnect structure 37. A smoothing repair layer 33 is disposed between the barrier layer 34 and the dielectric layer 31 of the metal interconnect structure 37, and there are no voids or defects inside the metal interconnect structure 37.

[0095] It should be understood that although the steps in the flowchart are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages within other steps.

[0096] According to an exemplary embodiment, the semiconductor structure is fabricated using the method described in the above embodiment. (Refer to...) Figure 9 The semiconductor structure includes a substrate on which a dielectric layer 31 is disposed. The dielectric layer 31 is made of materials including, but not limited to, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride, and has a dielectric constant (k-value) less than 3.0 to reduce interconnect delay. The dielectric layer 31 has an opening 32, in which a metal interconnect structure 37 is disposed. The metal interconnect structure 37 includes a barrier layer 34, a seed layer 35, and a conductive layer 36. The barrier layer 34 covers the bottom and sidewalls of the opening 32. The barrier layer 34 can be a single-layer or multi-layer structure, and its material includes at least one of tantalum or tantalum nitride, titanium or titanium nitride. The seed layer 35 covers the inner surface of the barrier layer 34 and can be a copper seed layer. The conductive layer 36 covers the seed layer 35 and fills the unfilled area of ​​the opening 32.

[0097] Among them, reference Figure 9A smoothing repair layer 33 is provided between the barrier layer 34 and the dielectric layer 31. The smoothing repair layer 33 is an oxide layer deposited by plasma-enhanced atomic layer deposition process. The material may include silicon oxide. The thickness of the smoothing repair layer 33 is 1nm-10nm.

[0098] Scanning electron microscopy (SEM) was used to observe the cross-section of the chemically mechanically polished structure. The results showed that the conductive layer 36 within the opening 32 was densely filled without any visible voids or pits, and the seed layer 35 had no overhang at the top of the opening 32. This embodiment reduces the defect density of the metal interconnect structure 37 and improves product yield.

[0099] The semiconductor structure in this embodiment can be Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash EPROM, Ferroelectric Random Access Memory (FeRAM), Magnetic Random-Access Memory (MRAM), or other types of memory.

[0100] The semiconductor structure and its fabrication method of this application have the following unexpected effects: the dielectric layer is etched by immersing the inverted substrate in an acidic etching solution. By adjusting the immersion depth and dwell time, the size of the upper part of the opening is increased, and the upper part of the opening forms an inverted trapezoidal profile, thereby reducing the aspect ratio of the upper part of the opening. This helps to suppress the formation of a protruding structure of the first film layer at the top of the opening. This can suppress the premature sealing of the top of the opening when filling the opening with material, which helps to improve void defects and thus improve the reliability of the device and the process yield.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a dielectric layer is formed, and the dielectric layer has openings; The substrate is inverted and the dielectric layer is immersed in an acidic etching solution for etching. By adjusting the immersion depth and dwell time, the size of the upper part of the opening is increased so that the upper part of the opening forms an inverted trapezoidal profile. Under the first condition, a smoothing repair layer is deposited on the sidewall surface of the medium layer to smooth the sidewall surface of the inverted trapezoidal profile; Deposit a first film layer into the opening; Chemical mechanical polishing is performed to remove the first film layer within the inverted trapezoidal contour and to remove the dielectric layer covering the inverted trapezoidal contour.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The step of inverting the substrate and immersing the dielectric layer in an acidic etching solution for etching includes: The substrate is inverted, and the immersion depth of the dielectric layer in the acidic etching solution is controlled by a stepper motor to increase in a stepwise manner, with each depth remaining for a preset duration.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The step depth of each step is 50-100 angstroms; the dwell time at each depth is 5-100 seconds; the step-by-step increment is 4-10 times; the acidic etching solution is hydrofluoric acid solution.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, After the dielectric layer is immersed in an acidic etching solution for etching, the surface of the inverted trapezoidal contour has a concave-convex structure. After depositing the smoothing repair layer, the smoothing repair layer covers the inverted trapezoidal contour, filling and smoothing the uneven structure of the surface of the inverted trapezoidal contour.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, A metal interconnect layer is formed in the dielectric layer, and the opening exposes at least a portion of the surface of the metal interconnect layer; The precursor gas for depositing the smooth repair layer has a higher adsorption capacity on the dielectric layer than on the metal interconnect layer, and the smooth repair layer is selectively grown on the dielectric layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The first conditions include: deposition temperature of 100℃-400℃, precursor gas flow rate of 100sccm-1000sccm, radio frequency power of 200W-1000W, radio frequency duration of 2s-10s, cavity pressure of 2Torr-10Torr; and deposition cycle number of 2-10 times.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The precursor gas for the smoothing repair layer is bis(tert-butylamino)silane; the thickness of the smoothing repair layer is 1 nm-10 nm.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The top surface of the dielectric layer is covered by a hard mask layer, and the hard mask layer and the dielectric layer are immersed together in an acidic etching solution, which has a low etching ratio for the hard mask layer. After depositing a smooth repair layer on the sidewall surface of the dielectric layer, the hard mask layer is etched away.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The initial depth-to-width ratio of the opening is 5:1 to 20:1; After the upper part of the opening forms an inverted trapezoidal outline, the width of the top opening of the inverted trapezoidal outline is greater than the width of the lower part of the opening.

10. A semiconductor structure, characterized in that, It is prepared by the method of fabricating the semiconductor structure as described in any one of claims 1-9.

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