Multi-chip integrated package structure based on multi-layer glass substrate and method of preparing package

Abstract

The application belongs to the technical field of semiconductor packaging, and particularly relates to a multi-chip integrated packaging structure based on a multi-layer glass substrate and a packaging method, which comprises the following steps: collecting surface reference mark coordinate data of each layer of glass substrates, dividing a reference candidate area and determining a reference anchor area, selecting a positioning sampling point to calculate a coordinate deviation, executing a differential positioning correction strategy, generating a first generation of positioning results, constructing second generation of positioning results through symmetrical compensation and weight enhancement, and verifying through an iterative optimization and a comprehensive judgment function; generating an initial integrated structure by sequentially assembling each chip based on the optimized positioning results, constructing a packaging structure after coplanarity calibration and local functional microstructure connectivity verification, and performing real-time correction according to the local residual stress and temperature gradient verification results; and the application realizes the interlaminar positioning effect of the multi-layer glass substrate stack through the reference anchor area selection technology based on the position dispersion evaluation and the two-generation positioning result iterative optimization technology.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically to a multi-chip integrated packaging structure based on a multilayer glass substrate and a method for its fabrication. Background Technology

[0002] As semiconductor devices develop towards higher integration, higher density interconnects, and heterogeneous integration, traditional packaging solutions based on silicon interposers and organic substrates (such as BT and ABF substrates) are gradually becoming unable to meet the comprehensive requirements of high-performance computing chips, artificial intelligence accelerator chips, and RF front-end modules for interconnect density, signal integrity, and cost control.

[0003] However, existing technologies for realizing multi-chip integrated packaging structures and their fabrication methods based on multilayer glass substrates are mainly limited by the high hardness and brittleness of the glass material itself, which makes the sidewalls of through-hole processing rough and the forming of high aspect ratio through-holes difficult. The mismatch of thermal expansion coefficients between the glass substrate and the metal wiring layer and dielectric layer leads to the accumulation of warping in multilayer stacking, making it difficult to guarantee the alignment accuracy between layers. In addition, there are a series of interconnected core technical bottlenecks, such as the difference in thickness and interconnect spacing of different functional chips, insufficient high-frequency signal crosstalk suppression capability, and the low thermal conductivity of the glass substrate itself, which makes it difficult to dissipate local hot spots in time. As a result, in practical applications, it is difficult to simultaneously ensure the continuous improvement of through-hole interconnect density, multilayer wiring density and multi-chip integration, as well as the overall reliability of the packaging structure (resistance to stress cracking, resistance to interface delamination), dimensional flatness stability, high-frequency signal integrity and heat dissipation efficiency, thus affecting the overall performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a multi-chip integrated packaging structure and a packaging method based on a multilayer glass substrate. This addresses a series of interconnected issues in the prior art, such as the mismatch in thermal expansion coefficients between the glass substrate and the metal wiring layer and dielectric layer leading to accumulated warping of multiple layers, difficulty in ensuring interlayer alignment accuracy, differences in thickness and interconnect spacing between different functional chips, insufficient suppression of high-frequency signal crosstalk, and difficulty in timely dissipation of local hot spots due to the low thermal conductivity of the glass substrate itself.

[0005] Multi-chip integrated packaging structures based on multilayer glass substrates include:

[0006] A multilayer glass substrate stack is formed by stacking multiple glass substrates sequentially along the thickness direction, and the interlayer electrical connection between adjacent glass substrates is achieved through a glass through-hole interconnection structure.

[0007] A gradient transition layer is disposed on the inner wall of the glass via and at the contact interface between the glass substrate and the adjacent metal wiring layer and dielectric layer. The gradient transition layer is composed of multiple sub-layers stacked sequentially along the radial or thickness direction. The volume fraction of the metal phase and the coefficient of thermal expansion of each sub-layer are continuously transitioned from the glass substrate side to the metal wiring layer side along the stacking direction.

[0008] A multi-chip integrated layer is composed of multiple chips mounted on the surface of a multilayer glass substrate stack, and the height difference between each chip does not exceed the coplanarity threshold.

[0009] A local grounding shielding ring microstructure is integrated along the boundaries of each chip functional area in the metal wiring layer of the multilayer glass substrate stack, and is connected to the reference ground plane through the glass via interconnect structure.

[0010] The localized thermally conductive microstructure consists of a vertical copper pillar and horizontal thermally conductive fins. The vertical copper pillar extends through the thickness direction of the multilayer glass substrate and its bottom end contacts the heat dissipation pad on the back of the chip in the multi-chip integrated layer, while its top end connects to the heat dissipation copper cladding area of ​​the top layer of the package. The horizontal thermally conductive fins are disposed at the top of the vertical copper pillar and extend radially in all directions.

[0011] The method for fabricating and packaging a multi-chip integrated packaging structure based on a multilayer glass substrate includes the following steps: using an optical positioning sensor to collect the position coordinate data of local reference marks on the surface of each layer of glass substrate, dividing the total single-layer glass substrate surface into multiple reference candidate regions according to spatial distribution, calculating the position dispersion of each candidate region, and determining the reference anchoring region, randomly selecting multiple alignment sampling points according to the determined reference anchoring region, calculating the coordinate deviation between the sampling points and the target position, classifying the current sampling points according to the calculation results, executing an alignment correction strategy according to the divided state, collecting interlayer position data after each execution of the alignment correction strategy, generating a first-generation alignment result after all sampling points have been processed, performing symmetric compensation and weight enhancement processing on the results after each alignment correction in the first-generation alignment result, constructing a second-generation alignment result based on the enhanced processing result, optimizing the alignment result by iterating the first-generation alignment result and the second-generation alignment result, and determining whether the optimization of the alignment result is completed by constructing an alignment comprehensive judgment function;

[0012] Based on the optimized alignment results, multiple chips to be integrated are set, and the target placement positions are determined according to the reference network. Each chip is then placed sequentially according to the alignment sequence. After all chips to be integrated are placed, an initial integrated structure is generated. The initial integrated structure is then subjected to coplanarity calibration and local functional microstructure connectivity verification. Once the local functional microstructure connectivity verification is passed, a multi-layer glass substrate multi-chip integrated packaging structure is constructed. The constructed packaging structure is then subjected to local area verification, and the packaging structure is corrected in real time based on the verification results of the local structure.

[0013] Preferably, the step of classifying the current sampling point into states based on the calculation results is as follows:

[0014] Calculate the coordinate deviation between the sampling point and the target position. And set a lower limit for the coordinate deviation threshold. Upper limit The calculated coordinate deviation between the sampling point and the target position is compared with a set coordinate deviation threshold. Based on the comparison result, the current sampling point is classified into states, specifically:

[0015] If the comparison results satisfy the formula If the current sampling point is marked as a stable alignment point, it means that the current sampling point has not shifted in the global reference coordinate system. No alignment correction is performed, the current sampling point is marked as a stable alignment point, and the process of the next sampling point is directly started.

[0016] If the comparison results satisfy the formula If the current sampling point is marked as the alignment point to be observed, it means that the degree of offset of the current sampling point cannot be directly determined. Alignment correction is temporarily suspended until all other sampling points have been processed. A second alignment assessment is then performed on the alignment point to be observed based on the overall alignment results. If the second assessment still cannot determine the correction direction, the current position is maintained.

[0017] If the comparison results satisfy the formula If the position shift occurs, it indicates that the current sampling point has shifted, and the alignment correction strategy will be executed.

[0018] Preferably, the alignment correction strategy is implemented as follows:

[0019] Calculate the directional deviation component of the position offset and Based on the calculated directional deviation components, the correction direction is determined, and thus:

[0020] like The deviation components of the direction satisfy the formula Then along Perform an expansion operation in the positive direction;

[0021] like The deviation components of the direction satisfy the formula Then along The contraction operation is performed in the negative direction;

[0022] like The deviation components of the direction satisfy the formula Then along Perform an expansion operation in the positive direction;

[0023] like The deviation components of the direction satisfy the formula Then along The contraction operation is performed in the negative direction.

[0024] Preferably, the symmetric compensation and weight enhancement processing is performed on the results after each alignment correction in the first-generation alignment results, as follows:

[0025] Set the central symmetry axis of the reference anchoring area The reference anchoring area is divided into two parts according to the set axis of symmetry, including: the first part of the reference anchoring area. and the second part of the reference anchoring area. ;

[0026] The first part of the reference anchoring area Inner reference marker The second part mapped to the reference anchoring area And the mapping position is Similarly, the second part of the reference anchoring area The reference marker points are mapped to the first part of the reference anchoring area. ;

[0027] Set sampling points Corresponding mirror sampling points And calculate the symmetric compensation amount. Through position weight coefficient By enhancing the symmetric compensation amount, we have:

[0028] ;

[0029] in, This represents the calculated symmetry compensation amount. This represents the set position weight coefficient. This represents the enhanced symmetry compensation amount.

[0030] Preferably, the first-generation alignment results and the second-generation alignment results are as follows:

[0031] If we set iteration conditions for the first-generation alignment results, then we have:

[0032] The first-generation alignment result's baseline network coverage integrity index is better than the integrity baseline value corresponding to the baseline anchoring region. If it does not meet the requirement, then... Re-execute the correction strategy to generate a new round of first-generation alignment results until the iteration conditions are met;

[0033] If we set iterative conditions for the second-generation alignment results, then we have:

[0034] Calculate the residual alignment error of the second-generation alignment results Simultaneously calculate the residual error corresponding to the first generation. ,pass Verify all sampling points in the second-generation alignment results; if any do not meet the requirements... For sampling points that meet the conditions, the sampling points are then readjusted for results that do not meet the conditions. Then re-execute the weight enhancement process until the iteration conditions are met;

[0035] If we set the iteration stopping condition, then we have:

[0036] If all first-generation alignment results can find corresponding second-generation alignment results that satisfy the iteration conditions, then the set of all current second-generation alignment results that satisfy the conditions is taken as the alignment result for which optimization is completed.

[0037] Preferably, the step of determining whether the optimization of the alignment result is complete by constructing an alignment synthesis judgment function is as follows:

[0038] Calculate the representative index of the benchmark respectively Benchmark network coverage integrity index And the residual alignment error index C, and construct an alignment comprehensive judgment function. ,in, , , This represents the weighting coefficient, and the set weighting coefficient values ​​satisfy the formula. , This indicates the output result of the positional synthesis judgment function;

[0039] Set the alignment and comprehensive judgment threshold The set comprehensive judgment threshold is compared with the output of the alignment comprehensive judgment function. Based on the comparison result, it is determined whether the alignment result optimization is complete. Therefore:

[0040] If the comparison results satisfy the formula If the current alignment result is true, it means that the reference network is stable, the coverage is complete, and the residual error meets the requirements. The current alignment result will be output as the final valid result.

[0041] If the comparison results satisfy the formula This indicates that the current alignment result does not meet the accuracy requirements, and further adjustments are made based on the sub-thresholds. , , To determine the reasons for not meeting the standards, we can consider the following:

[0042] If the benchmark representative index If the standard is not met, the coordinate data of the benchmark marker location will be re-collected; if the benchmark network coverage integrity index is not met... If the target is not met, adjust the relevant parameters in the alignment correction strategy and reprocess; if the residual alignment error index If the standard is not met, readjustment will be made. Perform weight augmentation processing until the optimized result satisfies... until.

[0043] Preferably, the coplanarity calibration is performed as follows:

[0044] Based on the optimized alignment results, set The thickness of the chip to be integrated is Interconnection spacing is The mounting target position is determined based on the reference network, and each chip is mounted sequentially according to the alignment sequence. After all the chips to be integrated are mounted, an initial integrated structure is generated. Furthermore, the mounting position of each chip in the initial integrated structure is directly determined by the second-generation alignment result mapped by the reference sampling point number corresponding to the current chip.

[0045] For the generated initial integrated structure, arbitrarily select three height points and detect the height difference between any two points. ;

[0046] Set coplanarity calibration threshold The set coplanarity calibration threshold is compared with the calculated height difference, and coplanarity calibration is performed based on the comparison results. Then:

[0047] If the height difference between any two points does not exceed the coplanarity calibration threshold If the initial integration structure passes the coplanarity calibration, it can proceed directly to connectivity verification without re-mounting.

[0048] If the height difference between any two points exceeds the coplanarity calibration threshold, then three points are selected again for detection;

[0049] If consecutive tests fail to meet the coplanarity condition, the coplanarity calibration of the current initial integrated structure is deemed unsuccessful.

[0050] Preferably, the connectivity verification of the local functional microstructures is specifically as follows:

[0051] The initial integrated structure is divided into multiple adjacent regions. One region is randomly selected as the initial verification region. At the same time, the adjacent regions of the initial verification region are located, the local functional microstructure boundaries of the initial verification region and its adjacent regions are determined, and the gap metric between two adjacent boundaries is calculated. ;

[0052] Set connectivity threshold The set connectivity threshold is compared with the calculated gap metric, and connectivity verification is performed based on the comparison results. Specifically:

[0053] If the comparison results satisfy the formula If the connection is true, it indicates that the local functional microstructure between the two regions is connected. The current adjacent region is marked as a verified connected region, and the current adjacent region is used as a new initial verification region. The connectivity verification is then performed on its adjacent regions until all regions have been verified.

[0054] If the comparison results satisfy the formula If the structure between the two regions is not connected, record the current disconnection event and count the cumulative number of disconnections.

[0055] After all regions have been traversed, the cumulative number of disconnections is compared with the set threshold for the number of disconnections. Then:

[0056] If the cumulative number of disconnections exceeds the threshold, it means that the connectivity verification of the current initial integrated structure has failed. The corresponding local functional microstructures will be re-embedded and the verification process will be re-executed.

[0057] If the cumulative number of disconnections does not exceed the threshold, it means that the connectivity verification of the current initial integrated structure has passed, and a multi-layer glass substrate multi-chip integrated packaging structure is constructed based on the current initial integrated structure.

[0058] Preferably, the real-time correction of the encapsulation structure based on the verification results of the local structure is as follows:

[0059] For the constructed encapsulation structure, the encapsulation structure is divided into: Each structural element is analyzed, and the local residual stress index of each structural element is calculated sequentially. and local temperature gradient index At the same time, a local residual stress threshold is set for each structural unit. and local temperature gradient threshold And construct a modified trigger determination function. ,in, The output of the modified trigger function is used to determine whether to perform the modification, specifically:

[0060] If the output of the modified trigger determination function satisfies the formula If the result is negative, it means that the local residual stress and local temperature gradient of the current structural unit have not exceeded the corresponding threshold, no correction is needed, and the current structural unit is skipped and the verification of the next structural unit is directly entered.

[0061] If the output of the modified trigger determination function satisfies the formula If so, only stress correction will be performed;

[0062] If the output of the modified trigger determination function satisfies the formula If so, only heat dissipation correction will be performed;

[0063] If the output of the modified trigger determination function satisfies the formula Then stress correction and heat dissipation correction are performed sequentially, with stress correction performed first and heat dissipation correction performed later.

[0064] Compared with the prior art, the present invention has the following beneficial effects:

[0065] 1. This invention achieves the interlayer alignment effect of multilayer glass substrates by adopting a benchmark anchoring region selection technology based on position dispersion evaluation and an iterative optimization technology based on two generations of alignment results. This effectively solves the problem in the prior art that the mismatch of thermal expansion coefficients between the glass substrate and the metal wiring layer leads to the accumulation of warping in multilayer stacking and the difficulty in ensuring the interlayer alignment accuracy.

[0066] 2. This invention achieves a smooth transition of thermal expansion coefficients and reduces interface stress concentration between the glass substrate and the metal wiring layer by adopting a gradient transition layer material composition technology that continuously transitions from silicon oxide-based ceramic phase to metal-based composite structure. This effectively solves the problem of interface peeling and microcrack propagation caused by abrupt changes in thermal expansion coefficients in the prior art.

[0067] 3. This invention achieves consistent integration of heterogeneous chips with different thicknesses and interconnect spacing by adopting a multi-chip precision mounting and integration technology based on coplanarity calibration and region-by-region verification of local functional microstructure connectivity. This effectively solves the problem that the coplanarity of the integrated structure is difficult to guarantee due to the differences in the thickness and interconnect spacing of multiple chips in the prior art.

[0068] 4. This invention achieves effective isolation of transverse crosstalk electromagnetic fields between chips and suppression of high-frequency radiation interference by adopting local grounding shielding ring electromagnetic suppression technology that integrates in situ along the boundaries of each chip's functional area and connects to the reference ground plane with low impedance via glass through-holes. This effectively solves the problem of insufficient high-frequency signal crosstalk suppression capability in existing multi-chip integrated packaging structures.

[0069] 5. This invention utilizes a three-dimensional dendritic topology configuration with a combination of vertical copper pillar arrays and transverse thermally conductive fins to create a local thermally conductive microstructure. It also employs a dynamic compensation technology for the density of the thermally conductive microstructure triggered by a local temperature gradient index. This achieves the effect of coordinated heat dissipation of the vertical dominant thermal pathway and the transverse auxiliary diffusion pathway, as well as timely dissipation of local hot spots. This effectively solves the problem in the prior art where the low thermal conductivity of the glass substrate itself makes it difficult to dissipate local hot spots in a timely manner. Attached Figure Description

[0070] Figure 1 This is a schematic diagram of the composition of the multi-chip integrated packaging structure based on a multilayer glass substrate according to the present invention.

[0071] Figure 2 This is a schematic diagram of the overall method steps for fabricating and packaging a multi-chip integrated packaging structure based on a multilayer glass substrate according to the present invention. Detailed Implementation

[0072] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0073] Example 1

[0074] Reference Figure 1 As one embodiment of the present invention, a multi-chip integrated packaging structure based on a multilayer glass substrate is provided, comprising:

[0075] A multilayer glass substrate stack is formed by stacking multiple glass substrates sequentially along the thickness direction, and the interlayer electrical connection between adjacent glass substrates is achieved through a glass through-hole interconnection structure.

[0076] A gradient transition layer is disposed on the inner wall of the glass via and at the interface between the glass substrate and the adjacent metal wiring layer and dielectric layer. The gradient transition layer is composed of multiple sub-layers stacked sequentially along the radial or thickness direction. The volume fraction of the metal phase and the coefficient of thermal expansion of each sub-layer are continuously transitioned from the glass substrate side to the metal wiring layer side along the stacking direction.

[0077] A multi-chip integrated layer is composed of multiple chips mounted on the surface of a multilayer glass substrate stack, and the height difference between each chip does not exceed the coplanarity threshold.

[0078] A local grounding shielding ring microstructure is integrated along the boundaries of each chip functional area in the metal wiring layer of a multilayer glass substrate stack, and is connected to the reference ground plane through the glass via interconnect structure.

[0079] The localized thermally conductive microstructure consists of a vertical copper pillar and horizontal thermally conductive fins. The vertical copper pillar extends through the thickness direction of the multilayer glass substrate and its bottom end contacts the heat dissipation pad on the back of the chip in the multi-chip integrated layer, while its top end connects to the heat dissipation copper cladding area of ​​the top layer of the package. The horizontal thermally conductive fins are located at the top of the vertical copper pillar and extend outwards.

[0080] The aperture range of the glass through-hole interconnect structure is: The aspect ratio is The inner wall of the glass through-hole is formed by laser-induced etching, and the sidewall roughness is no greater than [value missing]. The glass vias are filled with a conductive metallic material, made of copper or tungsten. This conductive metallic material is bonded to the glass substrate via a seed layer, which is either a titanium / copper composite layer or a chromium / copper composite layer, with a thickness of [missing information]. The seed layer is formed on the inner wall of the glass via by physical vapor deposition or chemical plating. The gradient transition layer covers the inner wall of the glass via and the seed layer, or the gradient transition layer also serves as the adhesion promotion layer of the seed layer. When the glass via interconnect structure between adjacent glass substrates achieves interlayer electrical connection, the glass via interconnect structure between the upper and lower glass substrates achieves alignment connection through metal pads located at the interlayer interface or direct copper-copper bonding.

[0081] Reference Figure 2 Furthermore, a method for fabricating and packaging a multi-chip integrated packaging structure based on a multilayer glass substrate is provided, including the following steps:

[0082] S1: Determination of the reference anchoring region based on positional dispersion and adaptive iterative alignment optimization of sampling points.

[0083] Specifically, the determination of the reference anchoring region based on positional dispersion and the adaptive iterative alignment optimization of sampling points involve fabricating a gradient transition layer at the inner wall of the glass via and the contact interface of the glass substrate. Based on the pre-calibrated mapping relationship established between the local reference marks on the surface of each glass substrate layer and the global reference coordinate system, the alignment of the multilayer glass substrate stack is achieved. Iterative optimization is then performed based on the alignment results. The specific implementation is as follows:

[0084] Using optical positioning sensors, position coordinate data of local reference marks on the surface of each glass substrate are collected, and based on the collected position coordinate data, a reference representativeness assessment is performed, specifically as follows:

[0085] The total area is The surface of a single-layer glass substrate is divided into spatial distributions as follows: There are several baseline candidate regions, and the area of ​​each candidate region satisfies... ,in, Indicates the first One benchmark candidate region, This indicates the total number of baseline candidate regions.

[0086] The location dispersion of each candidate region is calculated and used as a representative evaluation index for that candidate region. The candidate region with the smallest location dispersion is then selected as the benchmark anchor region from all candidate regions. Specifically:

[0087] For the Within each candidate region For each reference marker point, the centroid coordinates and the positional dispersion of the candidate region are calculated sequentially. Then:

[0088] , ;

[0089] ;

[0090] in, Indicates the first The centroid coordinates within each candidate region Indicates the first The location dispersion of each candidate region;

[0091] If we select the candidate region with the smallest location dispersion from all candidate regions as the reference anchor region, then we have:

[0092] ;

[0093] in, This indicates the defined reference anchorage area.

[0094] It should be noted that the selection criteria for the benchmark anchoring area are as follows: the relative positional relationship of the benchmark marker points in the candidate area with the smallest positional dispersion is relatively stable, which can provide a more reliable reference basis for subsequent inter-layer alignment calculations and reduce the transmission of overall alignment error caused by local benchmark point offset.

[0095] Furthermore, based on the determined benchmark anchoring area, for the stress risk locations adjacent to the glass-through-via (TGV) interconnect structures in the current area, random selection is made. Each pair of sampling points (numbered) The coordinates are ), and compare the selected sampling points with the pre-calibrated target positions in the global reference coordinate system. Perform coordinate deviation comparison and execute differential adjustments based on the comparison results, as detailed below:

[0096] Set the lower limit of the coordinate deviation threshold Upper limit The specific values ​​are set by the implementers based on the actual application scenario, and the coordinate deviation between the sampling point and the target position is calculated. Therefore:

[0097] ;

[0098] in, Indicates the first The coordinates of each sampling point Indicates the set target location. This represents the coordinate deviation between the calculated sampling point and the target position.

[0099] The calculated coordinate deviation between the sampling point and the target position is compared with a set coordinate deviation threshold. Based on the comparison result, the current sampling point is classified into states, specifically:

[0100] If the comparison results satisfy the formula If the current sampling point is marked as a stable alignment point, it means that the current sampling point has not shifted in the global reference coordinate system. No alignment correction is performed, the current sampling point is marked as a stable alignment point, and the process of the next sampling point is directly started.

[0101] If the comparison results satisfy the formula If the current sampling point is marked as the alignment point to be observed, it means that the degree of offset of the current sampling point cannot be directly determined. The current sampling point is marked as the alignment point to be observed, and the alignment correction is not performed for the time being. After all other sampling points have been processed, the alignment point to be observed is re-judged based on the overall alignment result. If the second judgment result still cannot determine the correction direction, the current position is kept unchanged.

[0102] If the comparison results satisfy the formula This indicates that the current sampling point has shifted position, and an alignment correction strategy is executed, as follows:

[0103] Calculating the directional deviation component of the position offset, we have:

[0104] , ;

[0105] in, Indicates the first The coordinates of each sampling point Indicates the set target location. express directional deviation component, express The deviation component of direction.

[0106] Based on the calculated directional deviation components, the correction direction is determined, and thus:

[0107] like The deviation components of the direction satisfy the formula Then along Perform an expansion operation in the positive direction;

[0108] like The deviation components of the direction satisfy the formula Then along The contraction operation is performed in the negative direction;

[0109] like The deviation components of the direction satisfy the formula Then along Perform an expansion operation in the positive direction;

[0110] like The deviation components of the direction satisfy the formula Then along The contraction operation is performed in the negative direction.

[0111] It also collects inter-layer position data after each execution of the alignment correction strategy, and generates the first-generation alignment result after all sampling points have been processed. Then we have:

[0112]

[0113] The first-generation alignment result consists of all intermediate results generated after the correction strategy is implemented, arranged according to the sampling point selection order. The sampling points for the correction are... Stable alignment site .

[0114] For the first-generation alignment results, symmetry compensation and weight enhancement processing are performed on the results after each alignment correction in the first-generation alignment results. Based on the enhanced results, a second-generation alignment result is constructed. At the same time, by iterating through the first-generation and second-generation alignment results, the alignment results are optimized, thereby realizing the interlayer alignment of the multilayer glass substrate. The specific implementation is as follows:

[0115] Set the central symmetry axis of the reference anchoring area Dividing the reference anchoring area into two parts according to the set axis of symmetry, we have:

[0116] ;

[0117] in, This indicates the first part of the reference anchoring area. This represents the second part of the reference anchorage area.

[0118] Based on the partitioned parts, a symmetric mapping transformation is performed, as follows:

[0119] The first part of the reference anchoring area Inner reference marker The second part mapped to the reference anchoring area And the mapping position is Similarly, the second part of the reference anchoring area The reference marker points are mapped to the first part of the reference anchoring area. ;

[0120] Set sampling points Corresponding mirror sampling points The symmetrical compensation amount is:

[0121] ;

[0122] in, This represents the calculated symmetry compensation amount.

[0123] After completing the symmetric mapping, the compensated result is weighted by using position weight coefficients. (Set by the implementers based on the actual baseline marker distribution density) The symmetry compensation amount is enhanced, specifically as follows:

[0124] ;

[0125] in, This represents the calculated symmetry compensation amount. This represents the set position weight coefficient. This represents the enhanced symmetry compensation amount;

[0126] In addition, key reference points located around the via-glass (TGV) interconnect structure and at the edge of the multilayer contact interface were taken. Take the rest , by all Constitutes the second generation of alignment results .

[0127] Based on the generated second-generation alignment results, the alignment results are optimized by iterating with the first-generation alignment results, as follows:

[0128] The iteration conditions are set for the first-generation alignment results, specifically as follows:

[0129] The baseline network coverage integrity index of the first-generation alignment results Better than the integrity benchmark value corresponding to the benchmark anchoring area ;

[0130] If not satisfied, let Re-execute the correction strategy to generate a new round of first-generation alignment results until the iteration conditions are met.

[0131] The iteration conditions for the second-generation alignment results are set as follows:

[0132] Calculating the residual alignment error of the second-generation alignment result, we have:

[0133] ;

[0134] Simultaneous calculation of the residual error corresponding to the first generation ,pass Verify all sampling points in the second-generation alignment results; if any do not meet the requirements... For sampling points that meet the conditions, the sampling points are then readjusted for results that do not meet the conditions. Then re-execute the weight enhancement process until the iteration conditions are met.

[0135] Set the iteration stopping condition as follows:

[0136] If all first-generation alignment results can find corresponding second-generation alignment results that satisfy the iteration conditions, then the set of all current second-generation alignment results that satisfy the conditions is taken as the alignment result for which optimization is completed.

[0137] Furthermore, based on the optimized alignment results, benchmark representativeness indices are calculated respectively. Benchmark network coverage integrity index ,in, This indicates the total number of bitwise connection paths. This represents the number of effective paths and the residual alignment error index C= And based on the calculation results, a positional comprehensive judgment function is constructed, specifically as follows:

[0138] ;

[0139] in, Indicates the benchmark representativeness index used in the calculation. This represents the baseline network coverage integrity index used in the calculation. This represents the calculated residual alignment error index. , , This represents the weighting coefficient, which is set by the implementer based on the actual application scenario, and the set weighting coefficient value satisfies the formula. , This represents the output result of the positional synthesis judgment function.

[0140] It should be noted that the weighting coefficients in this technical solution are set according to the following principles:

[0141] For application scenarios where baseline stability is the primary objective. A larger value should be chosen; for application scenarios where coverage integrity is the primary objective, A larger value should be chosen; for applications where residual error control is the primary objective, The larger value should be taken; for scenarios that take all three into account, the weight coefficients should be taken to the same value.

[0142] Set the alignment and comprehensive judgment threshold The set comprehensive judgment threshold is then compared with the output of the alignment comprehensive judgment function. Based on the comparison result, it is determined whether the alignment result optimization is complete, as follows:

[0143] If the comparison results satisfy the formula If the current alignment result is true, it means that the reference network is stable, the coverage is complete, and the residual error meets the requirements. The current alignment result will be output as the final valid result.

[0144] If the comparison results satisfy the formula This indicates that the current alignment result does not meet the accuracy requirements, and further adjustments are made based on the sub-thresholds. , , To determine the reasons for not meeting the standards, we can consider the following:

[0145] If the benchmark representative index If the standard is not met, the coordinate data of the benchmark marker location will be re-collected; if the benchmark network coverage integrity index is not met... If the target is not met, adjust the relevant parameters in the alignment correction strategy and reprocess; if the residual alignment error index If the standard is not met, readjustment will be made. Perform weight augmentation processing until the optimized result satisfies... until.

[0146] It should be noted that the calculation of the baseline network coverage integrity index in the comprehensive judgment function is used to evaluate whether the alignment connection paths between each glass substrate layer are effectively connected, thereby verifying the coverage integrity of the baseline network. Specifically:

[0147] Connectivity detection is performed on the paired connection paths, the endpoints and intermediate nodes of each connection path are extracted, the extracted results are marked as connected regions, and each path is judged to meet the integrity condition of effective end-to-end connectivity without breakage. Paths that meet the condition are counted as valid paths, and the ratio of the number of valid paths to the total number of paths is calculated, which is the baseline network coverage integrity index.

[0148] The calculation of the residual alignment error index in the comprehensive judgment function is used to measure the degree of residual deviation between each sampling point and the target position after the second-generation alignment result is applied. Specifically:

[0149] Select the corrected position of each sampling point and its corresponding target position, calculate the residual deviation of each sampling point, and use the average value of the residual deviations of all sampling points as the residual alignment error index.

[0150] S2: Real-time correction of multi-chip integrated packaging based on local stress regulation and thermal diffusion enhancement.

[0151] Specifically, the real-time correction of multi-chip integrated packaging based on local stress regulation and enhanced thermal diffusion involves precise multi-chip mounting and integration, simultaneous embedding of local grounding shielding ring microstructures and local thermally conductive microstructures, based on optimized multi-layer alignment results, and real-time correction of the integrated package structure. The specific implementation is as follows:

[0152] Based on the optimized alignment results, set The thickness of the chip to be integrated is Interconnection spacing is Based on the reference network, the target placement positions are determined, and the chips are sequentially placed according to the alignment sequence. Then:

[0153] ;

[0154] After all the chips to be integrated are mounted, an initial integrated structure is generated. The mounting position of each chip in the initial integrated structure is directly determined by the second-generation alignment result mapped by the reference sampling point number corresponding to the current chip.

[0155] Furthermore, for the generated initial integrated structure, coplanarity calibration is used to ensure the high consistency of each chip, and the local functional microstructure connectivity of the calibrated structure is verified, as follows:

[0156] For the generated initial integrated structure, arbitrarily select three height points and detect the height difference between any two points, then we have:

[0157] ;

[0158] in, express , The height difference between two points is used for coplanarity calibration, specifically:

[0159] Set coplanarity calibration threshold The set coplanarity calibration threshold is compared with the calculated height difference, and coplanarity calibration is performed based on the comparison results, specifically as follows:

[0160] If the height difference between any two points does not exceed the coplanarity calibration threshold If the initial integration structure passes the coplanarity calibration, it can proceed directly to connectivity verification without re-mounting.

[0161] If the height difference between any two points exceeds the coplanarity calibration threshold, then three points are selected again for detection;

[0162] If consecutive tests fail to meet the coplanarity condition, the coplanarity calibration of the current initial integrated structure is deemed unsuccessful.

[0163] It should be noted that in cases where coplanarity calibration fails, forced pressing is not performed directly on the current initial integrated structure; instead, the structure is re-attached.

[0164] Furthermore, the connectivity verification of local functional microstructures is performed on the initial integrated structure after coplanarity calibration is passed. Connectivity verification is conducted through region-by-region traversal detection, as follows:

[0165] The initial integrated structure is divided into multiple adjacent regions. One region is randomly selected as the initial verification region. Simultaneously, the adjacent regions of the initial verification region are located, and the local functional microstructure boundaries of the initial verification region and its adjacent regions are determined. The gap metric between two adjacent boundaries is then calculated. Therefore:

[0166] ;

[0167] in, This represents the gap metric between two adjacent boundaries, used for connectivity verification, specifically:

[0168] Set connectivity threshold The set connectivity threshold is compared with the calculated gap metric, and connectivity verification is performed based on the comparison results. Specifically:

[0169] If the comparison results satisfy the formula If the connection is true, it indicates that the local functional microstructure between the two regions is connected. The current adjacent region is marked as a verified connected region, and the current adjacent region is used as a new initial verification region. The above verification process is continued to be performed on its adjacent regions until all regions have been verified.

[0170] If the comparison results satisfy the formula If the structure between the two regions is not connected, record the current disconnection event and count the cumulative number of disconnections.

[0171] After all regions have been traversed, the cumulative number of disconnections is compared with the set threshold for the number of disconnections. Then:

[0172] If the cumulative number of disconnections exceeds the threshold, it means that the connectivity verification of the current initial integrated structure has failed. The corresponding local functional microstructures will be re-embedded and the verification process will be re-executed.

[0173] If the cumulative number of disconnections does not exceed the threshold, it means that the connectivity verification of the current initial integrated structure has passed, and a multi-layer glass substrate multi-chip integrated packaging structure is constructed based on the current initial integrated structure.

[0174] Furthermore, real-time correction of the constructed multi-layer glass substrate multi-chip integrated packaging structure involves performing local area verification on the constructed packaging structure and making real-time corrections to the packaging structure based on the verification results of the local structure. The specific implementation is as follows:

[0175] For the constructed encapsulation structure, the encapsulation structure is divided into: Given several structural elements, and calculating the local residual stress and local temperature gradient indices for each element sequentially, we have:

[0176] ;

[0177] ;

[0178] in, This represents the calculated local residual stress index. Indices representing the calculated local temperature gradient;

[0179] Simultaneously, a local residual stress threshold is set for each structural unit. and local temperature gradient threshold And by constructing a modified trigger determination function, we have:

[0180] ;

[0181] in, The output of the modified trigger function is used to determine whether to perform the modification, specifically:

[0182] If the output of the modified trigger determination function satisfies the formula If the result is negative, it means that the local residual stress and local temperature gradient of the current structural unit have not exceeded the corresponding threshold, no correction is needed, and the current structural unit is skipped and the verification of the next structural unit is directly entered.

[0183] If the output of the modified trigger determination function satisfies the formula If so, only stress correction will be performed;

[0184] If the output of the modified trigger determination function satisfies the formula If so, only heat dissipation correction will be performed;

[0185] If the output of the modified trigger determination function satisfies the formula Then stress correction and heat dissipation correction are performed sequentially, with the order being stress correction first and then heat dissipation correction.

[0186] It should be noted that the determination of the execution order in this embodiment has a clear physical basis, specifically as follows:

[0187] After stress correction is completed, the structural morphology of the area tends to be stable, and the heat dissipation correction method has a more reliable basis for execution. If heat dissipation correction is performed first, the correction range may deviate because the structural morphology has not yet stabilized.

[0188] Furthermore, stress correction involves increasing the thickness and number of gradient transition layers at the corresponding locations of structural units with abnormal local residual stress parameters. The gradient transition layer is composed of… Each sublayer is sequentially stacked along the radial direction (inner wall of the glass through-hole) or the thickness direction (contact interface), with each sublayer having a uniform thickness and a single layer thickness of [missing information]. The total thickness of the gradient transition layer is Volume fraction of metallic phase in each sublayer Numbering along sub-layers ( If it changes according to a linear law, then:

[0189] ;

[0190] in, This represents the lower limit of the metal phase volume fraction in the sublayer closest to the glass matrix. The upper limit of the metal phase volume fraction of the sublayer closest to the copper fill layer or metal wiring layer;

[0191] In addition, the thermal expansion coefficient of each sublayer According to the mixing law For linear changes, we have:

[0192] ;

[0193] in, The coefficient of thermal expansion of the glass matrix is ​​. is the coefficient of thermal expansion of the metallic phase.

[0194] It should be noted that the gradient transition layer reduces the coefficient of thermal expansion along the thickness direction from... linear transition to Eliminate interfacial stress concentration caused by abrupt changes in the coefficient of thermal expansion between the glass substrate and the metal wiring layer;

[0195] The material gradient of the gradient transition layer has a clearly defined composition in this embodiment, specifically:

[0196] The sublayer near the glass substrate is dominated by a silica-based ceramic phase, with a metallic phase (copper or tungsten) uniformly distributed in the ceramic matrix in a particle-dispersed form. The volume fraction of the metallic phase is... from (Usually starting at 5% to 15%); following the sub-layer numbering As the ceramic phase increases, the volume fraction of the metallic phase increases linearly, while the proportion of the ceramic phase decreases linearly. This continues until the sublayer near the copper filler layer or metal wiring layer reaches a certain volume fraction. (Usually 85% to 95%), the current side layer has a continuous metallic phase as the matrix and a ceramic phase dispersed in the form of particles.

[0197] For structural elements that only undergo stress correction, the thickness and number of sub-layers of the gradient transition layer are increased at the corresponding location of the current structural element, specifically as follows:

[0198] Increasing the thickness of the gradient transition layer results in:

[0199] ;

[0200] in, This refers to the incremental thickness of the gradient transition layer that needs to be added to the current structural unit. The stress-thickness compensation coefficient is determined in advance by the implementers through process experiments. This represents the difference between the residual stress of the current structural unit and the threshold value.

[0201] Increase the number of sub-layers to It is in the original Based on the sub-layer, add on the side of the copper fill layer / metal wiring layer. Each sublayer (the volume fraction of the metallic phase in the additional sublayer is determined by outward interpolation following the original linear gradient law), so that the total thickness of the gradient transition layer at the current local location is... Increase to Without altering the original gradient law, the stress dispersion capability at that location is enhanced until all structural units with local residual stress anomalies have completed the above processing, indicating that the stress correction of the current encapsulation structure is complete.

[0202] Heat dissipation correction is based on structural units with abnormal local temperature gradient indicators, which increases the density of local heat-conducting microstructures at the corresponding locations of the current structural unit.

[0203] The localized thermally conductive microstructure in this embodiment has a clearly defined topological shape, specifically:

[0204] The localized thermally conductive microstructure adopts a three-dimensional dendritic topology combining a vertical copper pillar array with horizontal thermally conductive fins. Each thermally conductive microstructure unit consists of a vertical copper pillar trunk and multiple horizontal thermally conductive fins radiating outwards from its top. The vertical copper pillar trunk runs through the thickness direction of the glass substrate, with its bottom end in direct contact with the heat dissipation pad on the back of the chip and its top end connected to the heat dissipation copper-clad area on the top layer of the package, forming a vertical low thermal resistance path from the chip heat source to the outside of the package. The horizontal thermally conductive fins radiate horizontally from the top of the vertical copper pillar trunk, with a typical number of 4 to 8 fins. Each fin is evenly arranged along the circumference, with a rectangular cross-section. The ratio of fin length to width is controlled between 3:1 and 5:1 to maximize the horizontal thermal contact area within a limited footprint. The horizontal thermally conductive fins are embedded in the low thermal conductivity filling medium of the chip gap layer, utilizing the expanded contact area between the fins and the filling medium to conduct heat laterally to adjacent heat dissipation areas, thereby simultaneously achieving coordinated heat dissipation of the vertical dominant thermal path and the horizontal auxiliary diffusion path.

[0205] In addition, a specified gap is maintained between the ends of the transverse heat-conducting fins of adjacent heat-conducting microstructure units. This gap is no greater than half the thermal diffusion length of the filling medium to ensure that transverse heat flow can be continuously transferred between adjacent microstructure units and to avoid the heat flow island effect.

[0206] For structural units that only perform heat dissipation correction, increasing the density of local heat-conducting microstructures at the corresponding location of the current structural unit results in:

[0207] ;

[0208] in, The density increment needs to be added to the local thermally conductive microstructure of the current structural unit. The temperature gradient-density compensation coefficient is determined in advance by the implementers through heat dissipation simulation or measured data. This represents the difference between the current structural unit's local temperature gradient index and the threshold value.

[0209] And increase the number of thermally conductive microstructures to It is to uniformly supplement within the current structural unit. Each localized thermally conductive microstructure unit increases the density of the thermally conductive microstructure in the current region from the original density. To enhance the heat dissipation capability of the local hot spot, rather than simply reducing the chip's functional density, the correction process ensures that it does not affect the multi-chip integration. The correction is completed when all structural units with abnormal local temperature gradients have completed heat dissipation correction.

[0210] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of protection claimed by the present invention.

Claims

1. A multi-chip integrated packaging structure based on a multilayer glass substrate, characterized in that, include: A multilayer glass substrate stack is formed by stacking multiple glass substrates sequentially along the thickness direction, and the interlayer electrical connection between adjacent glass substrates is achieved through a glass through-hole interconnection structure. A gradient transition layer is disposed on the inner wall of the glass via and at the contact interface between the glass substrate and the adjacent metal wiring layer and dielectric layer. The gradient transition layer is composed of multiple sub-layers stacked sequentially along the radial or thickness direction. The volume fraction of the metal phase and the coefficient of thermal expansion of each sub-layer are continuously transitioned from the glass substrate side to the metal wiring layer side along the stacking direction. A multi-chip integrated layer is composed of multiple chips mounted on the surface of a multilayer glass substrate stack, and the height difference between each chip does not exceed the coplanarity threshold. A local grounding shielding ring microstructure is integrated along the boundaries of each chip functional area in the metal wiring layer of the multilayer glass substrate stack, and is connected to the reference ground plane through the glass via interconnect structure. The localized thermally conductive microstructure consists of a vertical copper pillar and horizontal thermally conductive fins. The vertical copper pillar extends through the thickness direction of the multilayer glass substrate and its bottom end contacts the heat dissipation pad on the back of the chip in the multi-chip integrated layer, while its top end connects to the heat dissipation copper cladding area of ​​the top layer of the package. The horizontal thermally conductive fins are disposed at the top of the vertical copper pillar and extend radially in all directions.

2. A method for fabricating and packaging a multi-chip integrated packaging structure based on a multilayer glass substrate, characterized in that: Includes the following steps: Using optical positioning sensors, position coordinate data of local reference marks on the surface of each glass substrate are collected. The total surface of a single-layer glass substrate is divided into multiple reference candidate regions according to spatial distribution. The position dispersion of each candidate region is calculated, and the reference anchoring region is determined. Based on the determined reference anchoring region, multiple alignment sampling points are randomly selected, and the coordinate deviation between the sampling points and the target position is calculated. The current sampling point is divided into states according to the calculation results. An alignment correction strategy is executed according to the divided states. Interlayer position data after each execution of the alignment correction strategy is collected. After all sampling points are processed, the first-generation alignment result is generated. Symmetric compensation and weight enhancement processing are performed on the results after each alignment correction in the first-generation alignment result. The second-generation alignment result is constructed based on the enhanced results. The alignment result is optimized by iterating through the first-generation and second-generation alignment results. The optimization of the alignment result is determined by constructing an alignment comprehensive judgment function. Based on the optimized alignment results, multiple chips to be integrated are set, and the target placement positions are determined according to the reference network. Each chip is then placed sequentially according to the alignment sequence. After all chips to be integrated are placed, an initial integrated structure is generated. The initial integrated structure is then subjected to coplanarity calibration and local functional microstructure connectivity verification. Once the local functional microstructure connectivity verification is passed, a multi-layer glass substrate multi-chip integrated packaging structure is constructed. The constructed packaging structure is then subjected to local area verification, and the packaging structure is corrected in real time based on the verification results of the local structure.

3. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The state division of the current sampling point based on the calculation results is as follows: Calculate the coordinate deviation between the sampling point and the target position. And set a lower limit for the coordinate deviation threshold. Upper limit The calculated coordinate deviation between the sampling point and the target position is compared with a set coordinate deviation threshold. Based on the comparison result, the current sampling point is classified into states, specifically: If the comparison results satisfy the formula If the current sampling point is marked as a stable alignment point, it means that the current sampling point has not shifted in the global reference coordinate system. No alignment correction is performed, the current sampling point is marked as a stable alignment point, and the process of the next sampling point is directly started. If the comparison results satisfy the formula If the current sampling point is marked as the alignment point to be observed, it means that the degree of offset of the current sampling point cannot be directly determined. Alignment correction is temporarily suspended until all other sampling points have been processed. A second alignment assessment is then performed on the alignment point to be observed based on the overall alignment results. If the second assessment still cannot determine the correction direction, the current position is maintained. If the comparison results satisfy the formula If the position of the current sampling point is offset, then the alignment correction strategy will be executed.

4. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 3, characterized in that: The specific implementation of the alignment correction strategy is as follows: Calculate the directional deviation component of the position offset and Based on the calculated directional deviation components, the correction direction is determined, and thus: like The deviation components of the direction satisfy the formula Then along Perform an expansion operation in the positive direction; like The deviation components of the direction satisfy the formula Then along The contraction operation is performed in the negative direction; like The deviation components of the direction satisfy the formula Then along Perform an expansion operation in the positive direction; like The deviation components of the direction satisfy the formula Then along The contraction operation is performed in the negative direction.

5. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The symmetric compensation and weight enhancement processing of the results after each alignment correction in the first-generation alignment results is as follows: Set the central symmetry axis of the reference anchoring area The reference anchoring area is divided into two parts according to the set axis of symmetry, including: the first part of the reference anchoring area. and the second part of the reference anchoring area. ; The first part of the reference anchoring area Inner reference marker The second part mapped to the reference anchoring area And the mapping position is Similarly, the second part of the reference anchoring area The reference marker points are mapped to the first part of the reference anchoring area. ; Set sampling points Corresponding mirror sampling points And calculate the symmetric compensation amount. Through position weight coefficient By enhancing the symmetric compensation amount, we have: ； in, This represents the calculated symmetry compensation amount. This represents the set position weight coefficient. This represents the enhanced symmetry compensation amount.

6. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The specific results of the first and second generation alignments are as follows: If we set iteration conditions for the first-generation alignment results, then we have: The first-generation alignment result's baseline network coverage integrity index is better than the integrity baseline value corresponding to the baseline anchoring region. If it does not meet the requirement, then... Re-execute the correction strategy to generate a new round of first-generation alignment results until the iteration conditions are met; If we set iterative conditions for the second-generation alignment results, then we have: Calculate the residual alignment error of the second-generation alignment results Simultaneously calculate the residual error corresponding to the first generation. ,pass Verify all sampling points in the second-generation alignment results; if any do not meet the requirements... For sampling points that meet the conditions, the sampling points are then readjusted for results that do not meet the conditions. Then re-execute the weight enhancement process until the iteration conditions are met; If we set the iteration stopping condition, then we have: If all first-generation alignment results can find corresponding second-generation alignment results that satisfy the iteration conditions, then the set of all current second-generation alignment results that satisfy the conditions is taken as the alignment result for which optimization is completed.

7. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The process of determining whether the alignment result optimization is complete by constructing an alignment synthesis judgment function is as follows: Calculate the representative index of the benchmark respectively Benchmark network coverage integrity index And the residual alignment error index C, and construct an alignment comprehensive judgment function. ,in, , , This represents the weighting coefficient, and the set weighting coefficient values ​​satisfy the formula. , This indicates the output result of the positional synthesis judgment function; Set the alignment and comprehensive judgment threshold The set comprehensive judgment threshold is compared with the output of the alignment comprehensive judgment function. Based on the comparison result, it is determined whether the alignment result optimization is complete. Therefore: If the comparison results satisfy the formula If the current alignment result is true, it means that the reference network is stable, the coverage is complete, and the residual error meets the requirements. The current alignment result will be output as the final valid result. If the comparison results satisfy the formula This indicates that the current alignment result does not meet the accuracy requirements, and further adjustments are made based on the sub-thresholds. , , To determine the reasons for not meeting the standards, we can consider the following: If the benchmark representative index If the standard is not met, the coordinate data of the benchmark marker location will be re-collected; if the benchmark network coverage integrity index is not met... If the target is not met, adjust the relevant parameters in the alignment correction strategy and reprocess; if the residual alignment error index If the standard is not met, readjustment will be made. Perform weight augmentation processing until the optimized result satisfies... until.

8. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The coplanarity calibration is performed as follows: Based on the optimized alignment results, set The thickness of the chip to be integrated is Interconnection spacing is The mounting target position is determined based on the reference network, and each chip is mounted sequentially according to the alignment sequence. After all the chips to be integrated are mounted, an initial integrated structure is generated. Furthermore, the mounting position of each chip in the initial integrated structure is directly determined by the second-generation alignment result mapped by the reference sampling point number corresponding to the current chip. For the generated initial integrated structure, arbitrarily select three height points and detect the height difference between any two points. ; Set coplanarity calibration threshold The set coplanarity calibration threshold is compared with the calculated height difference, and coplanarity calibration is performed based on the comparison results. Then: If the height difference between any two points does not exceed the coplanarity calibration threshold If the initial integration structure passes the coplanarity calibration, it can proceed directly to connectivity verification without re-mounting. If the height difference between any two points exceeds the coplanarity calibration threshold, then three points are selected again for detection; If consecutive tests fail to meet the coplanarity condition, the coplanarity calibration of the current initial integrated structure is deemed unsuccessful.

9. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The verification of the connectivity of the local functional microstructures is as follows: The initial integrated structure is divided into multiple adjacent regions. One region is randomly selected as the initial verification region. At the same time, the adjacent regions of the initial verification region are located, the local functional microstructure boundaries of the initial verification region and its adjacent regions are determined, and the gap metric between two adjacent boundaries is calculated. ; Set connectivity threshold The set connectivity threshold is compared with the calculated gap metric, and connectivity verification is performed based on the comparison results. Specifically: If the comparison results satisfy the formula If the connection is true, it indicates that the local functional microstructure between the two regions is connected. The current adjacent region is marked as a verified connected region, and the current adjacent region is used as a new initial verification region. The connectivity verification is then performed on its adjacent regions until all regions have been verified. If the comparison results satisfy the formula If the structure between the two regions is not connected, record the current disconnection event and count the cumulative number of disconnections. After all regions have been traversed, the cumulative number of disconnections is compared with the set threshold for the number of disconnections. Then: If the cumulative number of disconnections exceeds the threshold, it means that the connectivity verification of the current initial integrated structure has failed. The corresponding local functional microstructures will be re-embedded and the verification process will be re-executed. If the cumulative number of disconnections does not exceed the threshold, it means that the connectivity verification of the current initial integrated structure has passed, and a multi-layer glass substrate multi-chip integrated packaging structure is constructed based on the current initial integrated structure.

10. The fabrication and packaging method of the multi-chip integrated packaging structure based on a multilayer glass substrate as described in claim 2, characterized in that: The real-time correction of the encapsulation structure based on the verification results of the local structure is as follows: For the constructed encapsulation structure, the encapsulation structure is divided into: Each structural element is analyzed, and the local residual stress index of each structural element is calculated sequentially. and local temperature gradient index At the same time, a local residual stress threshold is set for each structural unit. and local temperature gradient threshold And construct a modified trigger determination function. ,in, The output of the modified trigger function is used to determine whether to perform the modification, specifically: If the output of the modified trigger determination function satisfies the formula If the result is negative, it means that the local residual stress and local temperature gradient of the current structural unit have not exceeded the corresponding threshold, no correction is needed, and the current structural unit is skipped and the verification of the next structural unit is directly entered. If the output of the modified trigger determination function satisfies the formula If so, only stress correction will be performed; If the output of the modified trigger determination function satisfies the formula If so, only heat dissipation correction will be performed; If the output of the modified trigger determination function satisfies the formula Then stress correction and heat dissipation correction are performed sequentially, with stress correction performed first and heat dissipation correction performed later.

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